Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4336

1

T1

10

T3

4

T4

28

auto[1]

2182

1

T1

2

T3

6

T4

22

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	212	1			T1	4		T4	4		T70	2
auto[134217728:268435455]	206	1			T4	2		T24	2		T173	2
auto[268435456:402653183]	210	1			T1	2		T70	2		T181	2
auto[402653184:536870911]	212	1			T4	2		T30	2		T173	2
auto[536870912:671088639]	196	1			T1	2		T4	2		T177	4
auto[671088640:805306367]	244	1			T26	2		T45	2		T7	4
auto[805306368:939524095]	206	1			T15	2		T45	2		T189	2
auto[939524096:1073741823]	196	1			T58	2		T45	2		T43	2
auto[1073741824:1207959551]	194	1			T15	2		T6	2		T164	2
auto[1207959552:1342177279]	214	1			T173	2		T98	2		T164	2
auto[1342177280:1476395007]	210	1			T4	4		T24	2		T182	2
auto[1476395008:1610612735]	190	1			T3	2		T4	4		T26	4
auto[1610612736:1744830463]	206	1			T6	2		T59	2		T163	2
auto[1744830464:1879048191]	204	1			T4	2		T24	4		T177	2
auto[1879048192:2013265919]	182	1			T3	2		T4	6		T31	2
auto[2013265920:2147483647]	188	1			T3	2		T7	4		T21	2
auto[2147483648:2281701375]	186	1			T3	2		T31	2		T121	2
auto[2281701376:2415919103]	202	1			T4	2		T30	2		T31	2
auto[2415919104:2550136831]	222	1			T15	2		T24	2		T42	2
auto[2550136832:2684354559]	206	1			T4	2		T15	2		T58	2
auto[2684354560:2818572287]	238	1			T4	2		T24	2		T42	4
auto[2818572288:2952790015]	218	1			T24	2		T177	2		T6	2
auto[2952790016:3087007743]	216	1			T5	2		T173	4		T177	2
auto[3087007744:3221225471]	200	1			T70	2		T20	2		T7	2
auto[3221225472:3355443199]	176	1			T70	2		T64	2		T59	2
auto[3355443200:3489660927]	196	1			T1	2		T4	2		T31	4
auto[3489660928:3623878655]	188	1			T4	2		T5	2		T70	2
auto[3623878656:3758096383]	208	1			T4	4		T177	2		T131	2
auto[3758096384:3892314111]	194	1			T4	4		T24	2		T64	2
auto[3892314112:4026531839]	178	1			T1	2		T4	2		T173	4
auto[4026531840:4160749567]	212	1			T4	2		T26	2		T7	4
auto[4160749568:4294967295]	208	1			T3	2		T4	2		T58	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	156	1			T1	4		T4	2		T70	2
auto[0:134217727]	auto[1]	56	1			T4	2		T42	2		T58	2
auto[134217728:268435455]	auto[0]	136	1			T24	2		T173	2		T26	2
auto[134217728:268435455]	auto[1]	70	1			T4	2		T58	2		T7	4
auto[268435456:402653183]	auto[0]	150	1			T1	2		T70	2		T106	2
auto[268435456:402653183]	auto[1]	60	1			T181	2		T53	2		T89	2
auto[402653184:536870911]	auto[0]	130	1			T4	2		T173	2		T58	2
auto[402653184:536870911]	auto[1]	82	1			T30	2		T176	2		T6	2
auto[536870912:671088639]	auto[0]	134	1			T1	2		T4	2		T177	4
auto[536870912:671088639]	auto[1]	62	1			T7	4		T67	2		T60	2
auto[671088640:805306367]	auto[0]	156	1			T26	2		T45	2		T7	4
auto[671088640:805306367]	auto[1]	88	1			T8	2		T73	4		T359	2
auto[805306368:939524095]	auto[0]	156	1			T45	2		T7	6		T82	2
auto[805306368:939524095]	auto[1]	50	1			T15	2		T189	2		T7	2
auto[939524096:1073741823]	auto[0]	148	1			T45	2		T43	2		T7	4
auto[939524096:1073741823]	auto[1]	48	1			T58	2		T407	2		T218	2
auto[1073741824:1207959551]	auto[0]	154	1			T15	2		T6	2		T164	2
auto[1073741824:1207959551]	auto[1]	40	1			T264	2		T77	2		T409	2
auto[1207959552:1342177279]	auto[0]	136	1			T173	2		T164	2		T82	2
auto[1207959552:1342177279]	auto[1]	78	1			T98	2		T86	2		T211	2
auto[1342177280:1476395007]	auto[0]	134	1			T4	4		T43	2		T7	2
auto[1342177280:1476395007]	auto[1]	76	1			T24	2		T182	2		T131	2
auto[1476395008:1610612735]	auto[0]	126	1			T4	2		T26	2		T6	2
auto[1476395008:1610612735]	auto[1]	64	1			T3	2		T4	2		T26	2
auto[1610612736:1744830463]	auto[0]	150	1			T6	2		T59	2		T163	2
auto[1610612736:1744830463]	auto[1]	56	1			T22	2		T89	2		T35	2
auto[1744830464:1879048191]	auto[0]	124	1			T4	2		T177	2		T86	2
auto[1744830464:1879048191]	auto[1]	80	1			T24	4		T164	2		T46	2
auto[1879048192:2013265919]	auto[0]	106	1			T4	4		T31	2		T59	2
auto[1879048192:2013265919]	auto[1]	76	1			T3	2		T4	2		T131	2
auto[2013265920:2147483647]	auto[0]	138	1			T3	2		T7	2		T21	2
auto[2013265920:2147483647]	auto[1]	50	1			T7	2		T180	2		T74	2
auto[2147483648:2281701375]	auto[0]	128	1			T31	2		T121	2		T59	4
auto[2147483648:2281701375]	auto[1]	58	1			T3	2		T7	2		T340	2
auto[2281701376:2415919103]	auto[0]	128	1			T4	2		T31	2		T173	2
auto[2281701376:2415919103]	auto[1]	74	1			T30	2		T182	2		T7	2
auto[2415919104:2550136831]	auto[0]	164	1			T15	2		T24	2		T7	4
auto[2415919104:2550136831]	auto[1]	58	1			T42	2		T106	2		T60	2
auto[2550136832:2684354559]	auto[0]	132	1			T15	2		T121	2		T20	2
auto[2550136832:2684354559]	auto[1]	74	1			T4	2		T58	2		T67	2
auto[2684354560:2818572287]	auto[0]	156	1			T121	2		T164	2		T7	2
auto[2684354560:2818572287]	auto[1]	82	1			T4	2		T24	2		T42	4
auto[2818572288:2952790015]	auto[0]	142	1			T24	2		T177	2		T6	2
auto[2818572288:2952790015]	auto[1]	76	1			T22	2		T249	2		T123	2
auto[2952790016:3087007743]	auto[0]	142	1			T173	4		T177	2		T6	2
auto[2952790016:3087007743]	auto[1]	74	1			T5	2		T181	2		T91	2
auto[3087007744:3221225471]	auto[0]	128	1			T70	2		T20	2		T278	2
auto[3087007744:3221225471]	auto[1]	72	1			T7	2		T179	2		T73	2
auto[3221225472:3355443199]	auto[0]	118	1			T70	2		T64	2		T7	4
auto[3221225472:3355443199]	auto[1]	58	1			T59	2		T163	2		T218	2
auto[3355443200:3489660927]	auto[0]	132	1			T1	2		T4	2		T31	2
auto[3355443200:3489660927]	auto[1]	64	1			T31	2		T67	2		T180	2
auto[3489660928:3623878655]	auto[0]	106	1			T70	2		T24	2		T182	2
auto[3489660928:3623878655]	auto[1]	82	1			T4	2		T5	2		T182	2
auto[3623878656:3758096383]	auto[0]	122	1			T4	2		T74	2		T94	2
auto[3623878656:3758096383]	auto[1]	86	1			T4	2		T177	2		T131	2
auto[3758096384:3892314111]	auto[0]	132	1			T24	2		T64	2		T132	2
auto[3758096384:3892314111]	auto[1]	62	1			T4	4		T46	2		T340	2
auto[3892314112:4026531839]	auto[0]	114	1			T4	2		T173	4		T42	2
auto[3892314112:4026531839]	auto[1]	64	1			T1	2		T67	2		T88	2
auto[4026531840:4160749567]	auto[0]	120	1			T26	2		T7	4		T8	2
auto[4026531840:4160749567]	auto[1]	92	1			T4	2		T50	2		T53	2
auto[4160749568:4294967295]	auto[0]	138	1			T3	2		T4	2		T58	2
auto[4160749568:4294967295]	auto[1]	70	1			T177	2		T132	2		T62	2