Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2886

1

T1

6

T3

5

T4

25

auto[1]

319

1

T106

9

T121

9

T131

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T4	2		T58	1		T177	2
auto[134217728:268435455]	111	1			T3	1		T4	2		T31	1
auto[268435456:402653183]	92	1			T4	1		T24	1		T185	1
auto[402653184:536870911]	98	1			T1	1		T3	1		T4	1
auto[536870912:671088639]	103	1			T4	3		T26	1		T98	1
auto[671088640:805306367]	110	1			T1	2		T4	2		T31	1
auto[805306368:939524095]	108	1			T70	1		T24	1		T131	2
auto[939524096:1073741823]	113	1			T26	1		T182	1		T21	1
auto[1073741824:1207959551]	101	1			T173	1		T177	1		T45	1
auto[1207959552:1342177279]	107	1			T1	1		T3	1		T15	1
auto[1342177280:1476395007]	93	1			T26	1		T106	1		T121	1
auto[1476395008:1610612735]	97	1			T4	2		T182	1		T106	1
auto[1610612736:1744830463]	101	1			T4	2		T15	1		T24	1
auto[1744830464:1879048191]	85	1			T3	1		T4	1		T6	1
auto[1879048192:2013265919]	98	1			T4	1		T24	1		T177	1
auto[2013265920:2147483647]	99	1			T106	1		T64	1		T59	1
auto[2147483648:2281701375]	115	1			T177	1		T106	1		T131	1
auto[2281701376:2415919103]	97	1			T15	1		T173	1		T42	1
auto[2415919104:2550136831]	86	1			T45	1		T106	1		T20	1
auto[2550136832:2684354559]	86	1			T4	1		T58	1		T131	2
auto[2684354560:2818572287]	96	1			T4	1		T173	1		T58	1
auto[2818572288:2952790015]	101	1			T4	1		T31	1		T70	1
auto[2952790016:3087007743]	106	1			T4	1		T31	1		T24	1
auto[3087007744:3221225471]	89	1			T70	1		T173	1		T7	1
auto[3221225472:3355443199]	94	1			T24	1		T42	2		T182	1
auto[3355443200:3489660927]	93	1			T4	1		T26	1		T106	2
auto[3489660928:3623878655]	97	1			T1	1		T173	1		T58	1
auto[3623878656:3758096383]	109	1			T176	1		T58	1		T6	1
auto[3758096384:3892314111]	117	1			T4	1		T26	1		T177	1
auto[3892314112:4026531839]	106	1			T3	1		T182	1		T131	2
auto[4026531840:4160749567]	97	1			T4	1		T15	1		T30	1
auto[4160749568:4294967295]	106	1			T1	1		T4	1		T173	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	89	1			T4	2		T58	1		T177	2
auto[0:134217727]	auto[1]	5	1			T132	1		T379	1		T399	1
auto[134217728:268435455]	auto[0]	97	1			T3	1		T4	2		T31	1
auto[134217728:268435455]	auto[1]	14	1			T121	1		T211	1		T377	1
auto[268435456:402653183]	auto[0]	80	1			T4	1		T24	1		T185	1
auto[268435456:402653183]	auto[1]	12	1			T121	1		T263	1		T227	1
auto[402653184:536870911]	auto[0]	87	1			T1	1		T3	1		T4	1
auto[402653184:536870911]	auto[1]	11	1			T106	1		T131	1		T227	1
auto[536870912:671088639]	auto[0]	94	1			T4	3		T26	1		T98	1
auto[536870912:671088639]	auto[1]	9	1			T132	1		T180	1		T379	1
auto[671088640:805306367]	auto[0]	101	1			T1	2		T4	2		T31	1
auto[671088640:805306367]	auto[1]	9	1			T257	2		T398	1		T399	2
auto[805306368:939524095]	auto[0]	99	1			T70	1		T24	1		T131	1
auto[805306368:939524095]	auto[1]	9	1			T131	1		T379	1		T239	1
auto[939524096:1073741823]	auto[0]	103	1			T26	1		T182	1		T21	1
auto[939524096:1073741823]	auto[1]	10	1			T396	2		T287	1		T230	1
auto[1073741824:1207959551]	auto[0]	92	1			T173	1		T177	1		T45	1
auto[1073741824:1207959551]	auto[1]	9	1			T401	1		T287	1		T230	1
auto[1207959552:1342177279]	auto[0]	99	1			T1	1		T3	1		T15	1
auto[1207959552:1342177279]	auto[1]	8	1			T131	1		T227	1		T236	1
auto[1342177280:1476395007]	auto[0]	83	1			T26	1		T106	1		T20	1
auto[1342177280:1476395007]	auto[1]	10	1			T121	1		T353	1		T239	1
auto[1476395008:1610612735]	auto[0]	88	1			T4	2		T182	1		T131	1
auto[1476395008:1610612735]	auto[1]	9	1			T106	1		T82	2		T232	1
auto[1610612736:1744830463]	auto[0]	95	1			T4	2		T15	1		T24	1
auto[1610612736:1744830463]	auto[1]	6	1			T131	1		T313	1		T398	1
auto[1744830464:1879048191]	auto[0]	76	1			T3	1		T4	1		T6	1
auto[1744830464:1879048191]	auto[1]	9	1			T131	1		T227	1		T230	2
auto[1879048192:2013265919]	auto[0]	88	1			T4	1		T24	1		T177	1
auto[1879048192:2013265919]	auto[1]	10	1			T106	1		T227	1		T236	1
auto[2013265920:2147483647]	auto[0]	86	1			T64	1		T59	1		T67	1
auto[2013265920:2147483647]	auto[1]	13	1			T106	1		T353	1		T239	1
auto[2147483648:2281701375]	auto[0]	108	1			T177	1		T106	1		T164	1
auto[2147483648:2281701375]	auto[1]	7	1			T131	1		T227	1		T257	1
auto[2281701376:2415919103]	auto[0]	87	1			T15	1		T173	1		T42	1
auto[2281701376:2415919103]	auto[1]	10	1			T106	1		T121	1		T132	1
auto[2415919104:2550136831]	auto[0]	79	1			T45	1		T20	1		T7	1
auto[2415919104:2550136831]	auto[1]	7	1			T106	1		T122	1		T257	1
auto[2550136832:2684354559]	auto[0]	75	1			T4	1		T58	1		T131	1
auto[2550136832:2684354559]	auto[1]	11	1			T131	1		T227	1		T379	1
auto[2684354560:2818572287]	auto[0]	84	1			T4	1		T173	1		T58	1
auto[2684354560:2818572287]	auto[1]	12	1			T121	1		T122	3		T273	1
auto[2818572288:2952790015]	auto[0]	86	1			T4	1		T31	1		T70	1
auto[2818572288:2952790015]	auto[1]	15	1			T131	1		T263	1		T313	1
auto[2952790016:3087007743]	auto[0]	98	1			T4	1		T31	1		T24	1
auto[2952790016:3087007743]	auto[1]	8	1			T132	1		T227	1		T279	1
auto[3087007744:3221225471]	auto[0]	83	1			T70	1		T173	1		T7	1
auto[3087007744:3221225471]	auto[1]	6	1			T263	1		T353	1		T236	1
auto[3221225472:3355443199]	auto[0]	86	1			T24	1		T42	2		T182	1
auto[3221225472:3355443199]	auto[1]	8	1			T106	1		T121	1		T82	1
auto[3355443200:3489660927]	auto[0]	81	1			T4	1		T26	1		T106	1
auto[3355443200:3489660927]	auto[1]	12	1			T106	1		T180	1		T313	1
auto[3489660928:3623878655]	auto[0]	93	1			T1	1		T173	1		T58	1
auto[3489660928:3623878655]	auto[1]	4	1			T313	2		T279	1		T262	1
auto[3623878656:3758096383]	auto[0]	99	1			T176	1		T58	1		T6	1
auto[3623878656:3758096383]	auto[1]	10	1			T131	1		T313	1		T227	1
auto[3758096384:3892314111]	auto[0]	96	1			T4	1		T26	1		T177	1
auto[3758096384:3892314111]	auto[1]	21	1			T121	1		T131	2		T82	1
auto[3892314112:4026531839]	auto[0]	97	1			T3	1		T182	1		T64	1
auto[3892314112:4026531839]	auto[1]	9	1			T131	2		T180	1		T227	1
auto[4026531840:4160749567]	auto[0]	82	1			T4	1		T15	1		T30	1
auto[4026531840:4160749567]	auto[1]	15	1			T121	2		T131	1		T132	1
auto[4160749568:4294967295]	auto[0]	95	1			T1	1		T4	1		T173	2
auto[4160749568:4294967295]	auto[1]	11	1			T106	1		T279	1		T257	2