Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1532

1

T1

6

T3

1

T4

8

auto[1]

1726

1

T3

4

T4

17

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T3	1		T4	1		T31	1
auto[134217728:268435455]	94	1			T4	1		T24	1		T6	1
auto[268435456:402653183]	100	1			T15	2		T45	1		T182	1
auto[402653184:536870911]	97	1			T70	1		T24	1		T58	1
auto[536870912:671088639]	100	1			T59	1		T7	1		T67	1
auto[671088640:805306367]	103	1			T3	2		T5	1		T30	1
auto[805306368:939524095]	123	1			T4	1		T24	3		T26	1
auto[939524096:1073741823]	104	1			T1	1		T4	1		T70	1
auto[1073741824:1207959551]	96	1			T4	1		T42	1		T7	1
auto[1207959552:1342177279]	122	1			T1	1		T5	1		T24	1
auto[1342177280:1476395007]	93	1			T4	1		T164	1		T7	2
auto[1476395008:1610612735]	97	1			T4	1		T26	1		T182	1
auto[1610612736:1744830463]	111	1			T3	1		T4	1		T70	1
auto[1744830464:1879048191]	110	1			T4	2		T15	1		T24	1
auto[1879048192:2013265919]	85	1			T31	1		T173	1		T106	1
auto[2013265920:2147483647]	87	1			T4	1		T30	1		T31	1
auto[2147483648:2281701375]	116	1			T4	1		T20	1		T59	1
auto[2281701376:2415919103]	107	1			T1	1		T3	1		T4	1
auto[2415919104:2550136831]	92	1			T4	1		T177	1		T185	1
auto[2550136832:2684354559]	109	1			T4	1		T31	1		T173	1
auto[2684354560:2818572287]	107	1			T70	1		T6	1		T182	1
auto[2818572288:2952790015]	79	1			T1	1		T31	1		T173	1
auto[2952790016:3087007743]	108	1			T173	1		T58	1		T106	1
auto[3087007744:3221225471]	117	1			T4	2		T42	1		T7	2
auto[3221225472:3355443199]	96	1			T1	1		T26	1		T176	1
auto[3355443200:3489660927]	102	1			T4	1		T15	1		T42	1
auto[3489660928:3623878655]	111	1			T1	1		T4	1		T24	1
auto[3623878656:3758096383]	93	1			T24	1		T173	1		T59	1
auto[3758096384:3892314111]	111	1			T4	3		T70	1		T42	1
auto[3892314112:4026531839]	78	1			T4	2		T173	1		T177	2
auto[4026531840:4160749567]	113	1			T4	1		T58	1		T45	1
auto[4160749568:4294967295]	92	1			T6	1		T59	1		T164	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T173	1		T164	1		T7	1
auto[0:134217727]	auto[1]	58	1			T3	1		T4	1		T31	1
auto[134217728:268435455]	auto[0]	39	1			T6	1		T215	1		T402	1
auto[134217728:268435455]	auto[1]	55	1			T4	1		T24	1		T131	1
auto[268435456:402653183]	auto[0]	43	1			T15	2		T45	1		T106	1
auto[268435456:402653183]	auto[1]	57	1			T182	1		T189	1		T7	1
auto[402653184:536870911]	auto[0]	42	1			T24	1		T43	1		T46	1
auto[402653184:536870911]	auto[1]	55	1			T70	1		T58	1		T7	2
auto[536870912:671088639]	auto[0]	41	1			T7	1		T54	1		T73	2
auto[536870912:671088639]	auto[1]	59	1			T59	1		T67	1		T180	1
auto[671088640:805306367]	auto[0]	51	1			T3	1		T177	1		T8	1
auto[671088640:805306367]	auto[1]	52	1			T3	1		T5	1		T30	1
auto[805306368:939524095]	auto[0]	57	1			T4	1		T24	2		T26	1
auto[805306368:939524095]	auto[1]	66	1			T24	1		T7	1		T86	1
auto[939524096:1073741823]	auto[0]	45	1			T1	1		T164	1		T241	1
auto[939524096:1073741823]	auto[1]	59	1			T4	1		T70	1		T98	1
auto[1073741824:1207959551]	auto[0]	50	1			T74	1		T193	1		T313	1
auto[1073741824:1207959551]	auto[1]	46	1			T4	1		T42	1		T7	1
auto[1207959552:1342177279]	auto[0]	65	1			T1	1		T177	1		T182	1
auto[1207959552:1342177279]	auto[1]	57	1			T5	1		T24	1		T45	1
auto[1342177280:1476395007]	auto[0]	44	1			T164	1		T7	1		T50	1
auto[1342177280:1476395007]	auto[1]	49	1			T4	1		T7	1		T74	1
auto[1476395008:1610612735]	auto[0]	43	1			T4	1		T26	1		T132	1
auto[1476395008:1610612735]	auto[1]	54	1			T182	1		T7	1		T74	1
auto[1610612736:1744830463]	auto[0]	50	1			T4	1		T42	1		T8	1
auto[1610612736:1744830463]	auto[1]	61	1			T3	1		T70	1		T26	1
auto[1744830464:1879048191]	auto[0]	48	1			T4	1		T15	1		T24	1
auto[1744830464:1879048191]	auto[1]	62	1			T4	1		T177	1		T131	1
auto[1879048192:2013265919]	auto[0]	43	1			T173	1		T131	1		T215	1
auto[1879048192:2013265919]	auto[1]	42	1			T31	1		T106	1		T59	1
auto[2013265920:2147483647]	auto[0]	49	1			T4	1		T173	1		T58	2
auto[2013265920:2147483647]	auto[1]	38	1			T30	1		T31	1		T43	1
auto[2147483648:2281701375]	auto[0]	52	1			T59	1		T7	1		T54	2
auto[2147483648:2281701375]	auto[1]	64	1			T4	1		T20	1		T7	1
auto[2281701376:2415919103]	auto[0]	59	1			T1	1		T6	1		T215	1
auto[2281701376:2415919103]	auto[1]	48	1			T3	1		T4	1		T58	1
auto[2415919104:2550136831]	auto[0]	41	1			T185	1		T59	1		T7	1
auto[2415919104:2550136831]	auto[1]	51	1			T4	1		T177	1		T7	2
auto[2550136832:2684354559]	auto[0]	48	1			T4	1		T173	1		T177	1
auto[2550136832:2684354559]	auto[1]	61	1			T31	1		T182	1		T121	1
auto[2684354560:2818572287]	auto[0]	47	1			T6	1		T182	1		T7	1
auto[2684354560:2818572287]	auto[1]	60	1			T70	1		T121	1		T163	1
auto[2818572288:2952790015]	auto[0]	37	1			T1	1		T215	1		T74	1
auto[2818572288:2952790015]	auto[1]	42	1			T31	1		T173	1		T163	1
auto[2952790016:3087007743]	auto[0]	42	1			T173	1		T58	1		T86	1
auto[2952790016:3087007743]	auto[1]	66	1			T106	1		T121	1		T64	1
auto[3087007744:3221225471]	auto[0]	57	1			T7	2		T21	1		T392	1
auto[3087007744:3221225471]	auto[1]	60	1			T4	2		T42	1		T82	1
auto[3221225472:3355443199]	auto[0]	51	1			T1	1		T182	1		T131	1
auto[3221225472:3355443199]	auto[1]	45	1			T26	1		T176	1		T67	1
auto[3355443200:3489660927]	auto[0]	55	1			T15	1		T6	1		T45	1
auto[3355443200:3489660927]	auto[1]	47	1			T4	1		T42	1		T58	1
auto[3489660928:3623878655]	auto[0]	60	1			T1	1		T24	1		T26	1
auto[3489660928:3623878655]	auto[1]	51	1			T4	1		T98	1		T131	1
auto[3623878656:3758096383]	auto[0]	47	1			T24	1		T173	1		T392	1
auto[3623878656:3758096383]	auto[1]	46	1			T59	1		T7	1		T86	1
auto[3758096384:3892314111]	auto[0]	52	1			T4	1		T42	1		T20	1
auto[3758096384:3892314111]	auto[1]	59	1			T4	2		T70	1		T121	1
auto[3892314112:4026531839]	auto[0]	37	1			T177	1		T6	1		T20	1
auto[3892314112:4026531839]	auto[1]	41	1			T4	2		T173	1		T177	1
auto[4026531840:4160749567]	auto[0]	45	1			T4	1		T58	1		T45	1
auto[4026531840:4160749567]	auto[1]	68	1			T106	1		T121	1		T20	1
auto[4160749568:4294967295]	auto[0]	45	1			T6	1		T59	1		T8	1
auto[4160749568:4294967295]	auto[1]	47	1			T164	1		T7	1		T132	1