Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 99.00 98.07 98.43 97.67 98.93 98.41 91.17


Total test records in report: 1078
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T1004 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3171186233 May 14 04:24:03 PM PDT 24 May 14 04:24:06 PM PDT 24 7990382 ps
T1005 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1086421995 May 14 04:23:45 PM PDT 24 May 14 04:23:52 PM PDT 24 557838160 ps
T1006 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1828874815 May 14 04:23:37 PM PDT 24 May 14 04:23:43 PM PDT 24 75495630 ps
T1007 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2064260587 May 14 04:23:37 PM PDT 24 May 14 04:23:42 PM PDT 24 24695187 ps
T1008 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1886533157 May 14 04:23:43 PM PDT 24 May 14 04:23:50 PM PDT 24 99061888 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2251752412 May 14 04:24:02 PM PDT 24 May 14 04:24:06 PM PDT 24 28304216 ps
T1010 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4145956531 May 14 04:23:51 PM PDT 24 May 14 04:23:57 PM PDT 24 86491192 ps
T1011 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2435032939 May 14 04:23:38 PM PDT 24 May 14 04:23:51 PM PDT 24 819793975 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2178881725 May 14 04:23:26 PM PDT 24 May 14 04:23:47 PM PDT 24 1791210631 ps
T1013 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1073403087 May 14 04:23:21 PM PDT 24 May 14 04:23:26 PM PDT 24 111966037 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2749113073 May 14 04:23:25 PM PDT 24 May 14 04:23:35 PM PDT 24 278323831 ps
T1015 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.861826487 May 14 04:23:27 PM PDT 24 May 14 04:23:33 PM PDT 24 12925977 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4136822309 May 14 04:23:23 PM PDT 24 May 14 04:23:28 PM PDT 24 45280657 ps
T1017 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4134342084 May 14 04:23:40 PM PDT 24 May 14 04:23:47 PM PDT 24 60925857 ps
T1018 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2589464897 May 14 04:23:29 PM PDT 24 May 14 04:23:36 PM PDT 24 87254395 ps
T1019 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3155630972 May 14 04:23:31 PM PDT 24 May 14 04:23:39 PM PDT 24 61702963 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3129677639 May 14 04:23:31 PM PDT 24 May 14 04:23:38 PM PDT 24 350447391 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3362530521 May 14 04:23:53 PM PDT 24 May 14 04:24:00 PM PDT 24 467697228 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4278888547 May 14 04:23:38 PM PDT 24 May 14 04:23:44 PM PDT 24 153537620 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3078383317 May 14 04:23:27 PM PDT 24 May 14 04:23:39 PM PDT 24 841369076 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.839096621 May 14 04:23:28 PM PDT 24 May 14 04:23:35 PM PDT 24 54695127 ps
T1025 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4278222092 May 14 04:23:58 PM PDT 24 May 14 04:24:05 PM PDT 24 97466204 ps
T1026 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1046370127 May 14 04:23:26 PM PDT 24 May 14 04:23:33 PM PDT 24 1190600811 ps
T154 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.872760442 May 14 04:23:36 PM PDT 24 May 14 04:23:47 PM PDT 24 336273514 ps
T1027 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2797133900 May 14 04:23:28 PM PDT 24 May 14 04:23:42 PM PDT 24 1193914134 ps
T1028 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1377694201 May 14 04:24:01 PM PDT 24 May 14 04:24:04 PM PDT 24 164258874 ps
T1029 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1158947807 May 14 04:23:37 PM PDT 24 May 14 04:23:43 PM PDT 24 237744131 ps
T1030 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4230916229 May 14 04:23:18 PM PDT 24 May 14 04:23:23 PM PDT 24 300980584 ps
T1031 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4068163289 May 14 04:23:30 PM PDT 24 May 14 04:23:36 PM PDT 24 251681480 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2894958949 May 14 04:23:46 PM PDT 24 May 14 04:23:50 PM PDT 24 24217851 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2112465681 May 14 04:23:41 PM PDT 24 May 14 04:23:46 PM PDT 24 25150853 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2733668596 May 14 04:23:31 PM PDT 24 May 14 04:23:40 PM PDT 24 1109549649 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.112909341 May 14 04:23:36 PM PDT 24 May 14 04:23:44 PM PDT 24 79068043 ps
T1036 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.498259874 May 14 04:23:51 PM PDT 24 May 14 04:23:54 PM PDT 24 160616501 ps
T1037 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.184249950 May 14 04:23:29 PM PDT 24 May 14 04:23:36 PM PDT 24 22237916 ps
T1038 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4050350777 May 14 04:23:52 PM PDT 24 May 14 04:24:04 PM PDT 24 363763355 ps
T1039 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1850242210 May 14 04:23:31 PM PDT 24 May 14 04:23:41 PM PDT 24 80448138 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.222642657 May 14 04:23:43 PM PDT 24 May 14 04:23:48 PM PDT 24 21933289 ps
T1041 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.407008037 May 14 04:24:08 PM PDT 24 May 14 04:24:15 PM PDT 24 88040596 ps
T1042 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3532266927 May 14 04:23:51 PM PDT 24 May 14 04:23:55 PM PDT 24 536866083 ps
T1043 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3616799949 May 14 04:23:31 PM PDT 24 May 14 04:23:42 PM PDT 24 39420732 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3586627834 May 14 04:23:48 PM PDT 24 May 14 04:23:51 PM PDT 24 86605073 ps
T1045 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.855827354 May 14 04:23:48 PM PDT 24 May 14 04:23:52 PM PDT 24 124226323 ps
T1046 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.171240177 May 14 04:23:49 PM PDT 24 May 14 04:23:52 PM PDT 24 12608308 ps
T1047 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4005698175 May 14 04:23:50 PM PDT 24 May 14 04:23:54 PM PDT 24 14717102 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2163372448 May 14 04:23:29 PM PDT 24 May 14 04:23:36 PM PDT 24 26635376 ps
T1049 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.905115326 May 14 04:23:29 PM PDT 24 May 14 04:23:35 PM PDT 24 94670375 ps
T1050 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3338696551 May 14 04:23:30 PM PDT 24 May 14 04:23:38 PM PDT 24 47692449 ps
T152 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3715755683 May 14 04:23:44 PM PDT 24 May 14 04:23:55 PM PDT 24 496512178 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2152822639 May 14 04:23:49 PM PDT 24 May 14 04:23:56 PM PDT 24 208696981 ps
T1052 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3912851265 May 14 04:23:32 PM PDT 24 May 14 04:23:39 PM PDT 24 10185844 ps
T1053 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1717000584 May 14 04:23:27 PM PDT 24 May 14 04:23:34 PM PDT 24 64206123 ps
T1054 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3524643369 May 14 04:23:43 PM PDT 24 May 14 04:23:48 PM PDT 24 116767844 ps
T1055 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2885660869 May 14 04:23:36 PM PDT 24 May 14 04:23:42 PM PDT 24 15140282 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2357691307 May 14 04:23:31 PM PDT 24 May 14 04:23:40 PM PDT 24 494835885 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1769858997 May 14 04:23:44 PM PDT 24 May 14 04:23:48 PM PDT 24 26746104 ps
T1058 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3382002530 May 14 04:24:10 PM PDT 24 May 14 04:24:21 PM PDT 24 8684155 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.709034566 May 14 04:23:25 PM PDT 24 May 14 04:23:32 PM PDT 24 32865898 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1043379956 May 14 04:23:26 PM PDT 24 May 14 04:23:33 PM PDT 24 365215039 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2736635590 May 14 04:24:04 PM PDT 24 May 14 04:24:08 PM PDT 24 10267642 ps
T1062 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1092693835 May 14 04:24:01 PM PDT 24 May 14 04:24:07 PM PDT 24 122348103 ps
T1063 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1844390901 May 14 04:23:31 PM PDT 24 May 14 04:23:38 PM PDT 24 48980502 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3828160703 May 14 04:23:49 PM PDT 24 May 14 04:23:52 PM PDT 24 34340522 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.643615390 May 14 04:23:24 PM PDT 24 May 14 04:23:30 PM PDT 24 165809926 ps
T1066 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.937813547 May 14 04:23:50 PM PDT 24 May 14 04:23:53 PM PDT 24 12289104 ps
T1067 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4172168542 May 14 04:24:00 PM PDT 24 May 14 04:24:03 PM PDT 24 60640433 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2058994286 May 14 04:23:53 PM PDT 24 May 14 04:23:59 PM PDT 24 119210011 ps
T1069 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1613854018 May 14 04:23:30 PM PDT 24 May 14 04:23:43 PM PDT 24 207858558 ps
T1070 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.176369088 May 14 04:23:30 PM PDT 24 May 14 04:23:36 PM PDT 24 12585810 ps
T1071 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1565077035 May 14 04:24:01 PM PDT 24 May 14 04:24:04 PM PDT 24 148868725 ps
T159 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2433523758 May 14 04:23:58 PM PDT 24 May 14 04:24:03 PM PDT 24 542715931 ps
T1072 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.510789008 May 14 04:23:27 PM PDT 24 May 14 04:23:33 PM PDT 24 62948573 ps
T1073 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3741195880 May 14 04:23:44 PM PDT 24 May 14 04:23:50 PM PDT 24 29319762 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3863105220 May 14 04:23:59 PM PDT 24 May 14 04:24:07 PM PDT 24 123877505 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3804412407 May 14 04:23:19 PM PDT 24 May 14 04:23:28 PM PDT 24 345636549 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.997184673 May 14 04:23:53 PM PDT 24 May 14 04:23:57 PM PDT 24 96203579 ps
T1077 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1367206848 May 14 04:23:41 PM PDT 24 May 14 04:23:46 PM PDT 24 11762438 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.569222709 May 14 04:23:27 PM PDT 24 May 14 04:23:34 PM PDT 24 59441529 ps

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.380480060
Short name T4
Test name
Test status
Simulation time 10305901031 ps
CPU time 46.86 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:55 PM PDT 24
Peak memory 222636 kb
Host smart-45b72c66-1308-4fa7-ae6a-9fdcfa882237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380480060 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.380480060
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1554805212
Short name T7
Test name
Test status
Simulation time 5535107342 ps
CPU time 46.65 seconds
Started May 14 02:20:16 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 217048 kb
Host smart-74e3d941-923c-4fd3-9971-fddfb8fc5602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554805212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1554805212
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1579865470
Short name T9
Test name
Test status
Simulation time 1076759520 ps
CPU time 12.32 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:25 PM PDT 24
Peak memory 235092 kb
Host smart-cb6dd283-6607-4a0e-a875-494c49ec9061
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579865470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1579865470
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4134831144
Short name T59
Test name
Test status
Simulation time 2351941457 ps
CPU time 21.68 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:19 PM PDT 24
Peak memory 220816 kb
Host smart-74444066-05f6-495e-8309-eb610fbfb854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134831144 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4134831144
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.856955207
Short name T6
Test name
Test status
Simulation time 55869639 ps
CPU time 2.76 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:12 PM PDT 24
Peak memory 222876 kb
Host smart-b9e0a32d-1645-4499-ac52-ac33d06607ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856955207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.856955207
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1812822542
Short name T123
Test name
Test status
Simulation time 2534877488 ps
CPU time 29.76 seconds
Started May 14 02:21:26 PM PDT 24
Finished May 14 02:21:57 PM PDT 24
Peak memory 215280 kb
Host smart-0d88158e-bea8-4050-963c-e8a94b78f616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812822542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1812822542
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3431030276
Short name T53
Test name
Test status
Simulation time 519158840 ps
CPU time 14.27 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 214780 kb
Host smart-c6028c54-8bef-4165-9bf9-3537f45aa59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431030276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3431030276
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4047610518
Short name T131
Test name
Test status
Simulation time 1301532425 ps
CPU time 68.65 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:26:05 PM PDT 24
Peak memory 222444 kb
Host smart-ca896f51-9827-4056-b473-1de354e560ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047610518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4047610518
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2868893081
Short name T76
Test name
Test status
Simulation time 2202565834 ps
CPU time 27.7 seconds
Started May 14 02:20:25 PM PDT 24
Finished May 14 02:20:54 PM PDT 24
Peak memory 222620 kb
Host smart-c6dba849-a175-42ce-acf2-4e79099909ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868893081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2868893081
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2595644580
Short name T1
Test name
Test status
Simulation time 133685641 ps
CPU time 2.06 seconds
Started May 14 02:19:54 PM PDT 24
Finished May 14 02:19:57 PM PDT 24
Peak memory 222568 kb
Host smart-a55c4bbd-b613-4d70-bebb-a6ec49a9e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595644580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2595644580
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2342428368
Short name T103
Test name
Test status
Simulation time 287720969 ps
CPU time 3.52 seconds
Started May 14 04:23:39 PM PDT 24
Finished May 14 04:23:47 PM PDT 24
Peak memory 220416 kb
Host smart-5cfe6098-b3af-4ab6-8020-8a9e0392ce06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342428368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2342428368
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.583674551
Short name T227
Test name
Test status
Simulation time 3320611439 ps
CPU time 91.69 seconds
Started May 14 02:20:56 PM PDT 24
Finished May 14 02:22:29 PM PDT 24
Peak memory 215852 kb
Host smart-9b524164-3729-49cb-ba91-c6e50aadda57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583674551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.583674551
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.578888497
Short name T44
Test name
Test status
Simulation time 13214299837 ps
CPU time 295.14 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:30:17 PM PDT 24
Peak memory 217216 kb
Host smart-4ca029fb-f73d-457f-b960-f147209003f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578888497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.578888497
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.660389649
Short name T20
Test name
Test status
Simulation time 56379873 ps
CPU time 3.29 seconds
Started May 14 02:27:04 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 222576 kb
Host smart-12e3c176-b557-4507-8895-17d1bd3635f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660389649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.660389649
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1024781057
Short name T399
Test name
Test status
Simulation time 3978161890 ps
CPU time 48.62 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:27:19 PM PDT 24
Peak memory 215216 kb
Host smart-51e51f0a-cbfe-4ca8-8bdf-6fb91b65dbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024781057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1024781057
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1392983477
Short name T108
Test name
Test status
Simulation time 163824286 ps
CPU time 7.3 seconds
Started May 14 04:23:53 PM PDT 24
Finished May 14 04:24:02 PM PDT 24
Peak memory 220420 kb
Host smart-952bf8b8-75fa-42bc-8450-b2f5cec76194
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392983477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1392983477
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.670211232
Short name T121
Test name
Test status
Simulation time 7346975941 ps
CPU time 102.78 seconds
Started May 14 02:21:52 PM PDT 24
Finished May 14 02:23:36 PM PDT 24
Peak memory 215344 kb
Host smart-f10bd873-7eda-4886-b5ad-dcc86881cb8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670211232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.670211232
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3751454931
Short name T74
Test name
Test status
Simulation time 1076800048 ps
CPU time 28.3 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:25:16 PM PDT 24
Peak memory 222308 kb
Host smart-04c78fcb-e0d1-40bf-beed-01a7ab92780c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751454931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3751454931
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3386501972
Short name T33
Test name
Test status
Simulation time 235334094 ps
CPU time 2.09 seconds
Started May 14 02:26:12 PM PDT 24
Finished May 14 02:26:15 PM PDT 24
Peak memory 210176 kb
Host smart-ec4d55b7-f168-4e52-bef4-1cc16a4e07a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386501972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3386501972
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2745248665
Short name T77
Test name
Test status
Simulation time 306918437 ps
CPU time 21.44 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:29 PM PDT 24
Peak memory 222592 kb
Host smart-adc7c3e8-f7ef-4ee1-abf2-cba400f74788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745248665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2745248665
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1458799425
Short name T200
Test name
Test status
Simulation time 687520465 ps
CPU time 5.36 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:31 PM PDT 24
Peak memory 209812 kb
Host smart-c94bd164-2881-4414-850a-482b6fdd7a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458799425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1458799425
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1935361019
Short name T752
Test name
Test status
Simulation time 105683695 ps
CPU time 6.29 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:16 PM PDT 24
Peak memory 215168 kb
Host smart-6c573e1a-590a-4371-974d-7b5800a9bf05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935361019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1935361019
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3732347109
Short name T26
Test name
Test status
Simulation time 163401000 ps
CPU time 4.2 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:08 PM PDT 24
Peak memory 218584 kb
Host smart-cead7588-4c5c-4032-ad9c-bc54a5321abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732347109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3732347109
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.530438243
Short name T37
Test name
Test status
Simulation time 405999387 ps
CPU time 3.92 seconds
Started May 14 02:24:46 PM PDT 24
Finished May 14 02:24:51 PM PDT 24
Peak memory 210136 kb
Host smart-c3c9c62b-2ff3-4175-b631-42c559ff1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530438243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.530438243
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2014314761
Short name T257
Test name
Test status
Simulation time 921513072 ps
CPU time 13.63 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:54 PM PDT 24
Peak memory 214720 kb
Host smart-fe4c0e20-511e-40e3-8385-de31d6ef2ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014314761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2014314761
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.302759008
Short name T133
Test name
Test status
Simulation time 187212415 ps
CPU time 4.27 seconds
Started May 14 02:20:39 PM PDT 24
Finished May 14 02:20:44 PM PDT 24
Peak memory 218272 kb
Host smart-f958ed53-3462-4b48-b05b-d6fb16263898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302759008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.302759008
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1327299218
Short name T400
Test name
Test status
Simulation time 521944122 ps
CPU time 14.68 seconds
Started May 14 02:20:40 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 215536 kb
Host smart-544b9344-8413-4808-bc3f-40fb03027883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327299218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1327299218
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.405470946
Short name T141
Test name
Test status
Simulation time 260334412 ps
CPU time 7.04 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 214068 kb
Host smart-046d9f3a-ac26-4749-ad62-c4fa6a7cd0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405470946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
405470946
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4049768868
Short name T22
Test name
Test status
Simulation time 162759973 ps
CPU time 3.05 seconds
Started May 14 02:25:49 PM PDT 24
Finished May 14 02:25:54 PM PDT 24
Peak memory 221124 kb
Host smart-744620d2-c660-499c-93cc-5a8ca906c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049768868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4049768868
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.981091048
Short name T218
Test name
Test status
Simulation time 1263236272 ps
CPU time 13.89 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:38 PM PDT 24
Peak memory 216756 kb
Host smart-f5e467bc-544e-49e2-99a0-83f0fdd91758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981091048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.981091048
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.588553452
Short name T168
Test name
Test status
Simulation time 1366517075 ps
CPU time 51.79 seconds
Started May 14 02:20:03 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 216716 kb
Host smart-cac6b04d-6509-40ce-9957-235a43c54f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588553452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.588553452
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3795213892
Short name T79
Test name
Test status
Simulation time 495404017 ps
CPU time 14.29 seconds
Started May 14 02:27:44 PM PDT 24
Finished May 14 02:28:00 PM PDT 24
Peak memory 221684 kb
Host smart-937a12ac-0258-4ceb-b3b3-a148b4d8b0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795213892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3795213892
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3278210837
Short name T96
Test name
Test status
Simulation time 38852367 ps
CPU time 0.89 seconds
Started May 14 02:20:59 PM PDT 24
Finished May 14 02:21:01 PM PDT 24
Peak memory 205896 kb
Host smart-0472524b-c1c9-4d87-b186-964b542d7305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278210837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3278210837
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2120980411
Short name T406
Test name
Test status
Simulation time 179179109 ps
CPU time 9.16 seconds
Started May 14 02:25:38 PM PDT 24
Finished May 14 02:25:48 PM PDT 24
Peak memory 214848 kb
Host smart-00073351-76e9-4812-8ff4-82f9d393c891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120980411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2120980411
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3319379734
Short name T113
Test name
Test status
Simulation time 2007254229 ps
CPU time 21.11 seconds
Started May 14 02:20:26 PM PDT 24
Finished May 14 02:20:47 PM PDT 24
Peak memory 222620 kb
Host smart-a5e25197-3f8d-488b-a231-b4543d44a3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319379734 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3319379734
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2818083710
Short name T220
Test name
Test status
Simulation time 42608041 ps
CPU time 2.41 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:09 PM PDT 24
Peak memory 219844 kb
Host smart-8075c0a9-d15e-4081-b1f9-f44b89c6d60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818083710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2818083710
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.596546660
Short name T211
Test name
Test status
Simulation time 1009098068 ps
CPU time 5.36 seconds
Started May 14 02:25:48 PM PDT 24
Finished May 14 02:25:54 PM PDT 24
Peak memory 214356 kb
Host smart-4a4c2731-2cbe-43cc-967b-44d928c29c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596546660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.596546660
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1387331013
Short name T12
Test name
Test status
Simulation time 605299757 ps
CPU time 17.53 seconds
Started May 14 02:26:05 PM PDT 24
Finished May 14 02:26:24 PM PDT 24
Peak memory 209020 kb
Host smart-5bcf6ef9-a69b-474a-a00d-f91d016a41e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387331013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1387331013
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3602570972
Short name T157
Test name
Test status
Simulation time 127798969 ps
CPU time 5.5 seconds
Started May 14 04:23:39 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 214020 kb
Host smart-095a8260-7163-4f1b-a32e-6f69ed76bdb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602570972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3602570972
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4036296022
Short name T92
Test name
Test status
Simulation time 170562198 ps
CPU time 3.99 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:32 PM PDT 24
Peak memory 208548 kb
Host smart-8618bc47-e884-4bec-b981-e3dd919a0393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036296022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4036296022
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3322268585
Short name T49
Test name
Test status
Simulation time 70414903 ps
CPU time 2.91 seconds
Started May 14 02:21:49 PM PDT 24
Finished May 14 02:21:54 PM PDT 24
Peak memory 216056 kb
Host smart-7a69b7bf-ff0c-416a-9db9-ece7b49af332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322268585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3322268585
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3336453317
Short name T205
Test name
Test status
Simulation time 1492912295 ps
CPU time 14.51 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 221120 kb
Host smart-a75ae3af-8a3f-442e-99ee-cc356ad547dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336453317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3336453317
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4044344823
Short name T336
Test name
Test status
Simulation time 459699242 ps
CPU time 6.9 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:27 PM PDT 24
Peak memory 214252 kb
Host smart-1893e349-5f1b-43b0-97a7-82421eda3acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044344823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4044344823
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3817735157
Short name T169
Test name
Test status
Simulation time 5063392461 ps
CPU time 50.61 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:26:43 PM PDT 24
Peak memory 222552 kb
Host smart-991ace75-bbd4-4030-8e37-816edcadd867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817735157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3817735157
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4204501913
Short name T143
Test name
Test status
Simulation time 96780388 ps
CPU time 3.21 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 214232 kb
Host smart-7ccdca97-d603-458c-b905-c8d84a3f141e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204501913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4204501913
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.41376874
Short name T23
Test name
Test status
Simulation time 89951268 ps
CPU time 3.35 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:07 PM PDT 24
Peak memory 221560 kb
Host smart-7ca0b289-455c-4b45-857e-992922a33f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41376874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.41376874
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3330328337
Short name T137
Test name
Test status
Simulation time 659543776 ps
CPU time 4.49 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 218268 kb
Host smart-9d5bc4c6-b181-4755-b418-77ef13113708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330328337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3330328337
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3225063483
Short name T224
Test name
Test status
Simulation time 66348563 ps
CPU time 2.65 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:35 PM PDT 24
Peak memory 214692 kb
Host smart-3747dd16-58d0-4f5b-9c3b-ab5e007f364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225063483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3225063483
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3561978438
Short name T82
Test name
Test status
Simulation time 944433465 ps
CPU time 13.9 seconds
Started May 14 02:25:38 PM PDT 24
Finished May 14 02:25:53 PM PDT 24
Peak memory 214364 kb
Host smart-a8ebed3f-b056-4622-b8fc-1b6ad7a92f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561978438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3561978438
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1882105534
Short name T355
Test name
Test status
Simulation time 337598314 ps
CPU time 3.29 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 222364 kb
Host smart-15728c65-de32-4181-b885-ded4d880ad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882105534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1882105534
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.17923438
Short name T348
Test name
Test status
Simulation time 3244118542 ps
CPU time 62.08 seconds
Started May 14 02:26:18 PM PDT 24
Finished May 14 02:27:22 PM PDT 24
Peak memory 222684 kb
Host smart-a614b114-0b6b-4112-8274-df60fe567213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17923438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.17923438
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3377638045
Short name T61
Test name
Test status
Simulation time 427547288 ps
CPU time 2.84 seconds
Started May 14 02:25:58 PM PDT 24
Finished May 14 02:26:01 PM PDT 24
Peak memory 210044 kb
Host smart-14a6006d-b323-4a7d-9f1e-5d614bdc5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377638045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3377638045
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3039307643
Short name T151
Test name
Test status
Simulation time 886499708 ps
CPU time 4.94 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 213936 kb
Host smart-86200b7b-81af-474e-9bb7-317c07c7cf7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039307643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3039307643
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.159954875
Short name T147
Test name
Test status
Simulation time 215635121 ps
CPU time 2.84 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:40 PM PDT 24
Peak memory 214032 kb
Host smart-a5659385-8f10-4f5d-a6e4-79f2276168e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159954875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
159954875
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4072590379
Short name T138
Test name
Test status
Simulation time 41211545 ps
CPU time 3.21 seconds
Started May 14 02:26:43 PM PDT 24
Finished May 14 02:26:48 PM PDT 24
Peak memory 218248 kb
Host smart-2b763910-75f5-4252-935c-8411ec66b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072590379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4072590379
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3677967214
Short name T671
Test name
Test status
Simulation time 53784462 ps
CPU time 1.9 seconds
Started May 14 02:21:09 PM PDT 24
Finished May 14 02:21:12 PM PDT 24
Peak memory 214248 kb
Host smart-0df87f32-2b2b-4167-a884-6bf1018c592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677967214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3677967214
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3606428584
Short name T279
Test name
Test status
Simulation time 206415714 ps
CPU time 4.03 seconds
Started May 14 02:21:53 PM PDT 24
Finished May 14 02:21:59 PM PDT 24
Peak memory 214424 kb
Host smart-c57986d5-36e5-4292-bdf3-58d68382ac03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606428584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3606428584
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3044179478
Short name T278
Test name
Test status
Simulation time 74769211 ps
CPU time 3.22 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:12 PM PDT 24
Peak memory 214316 kb
Host smart-2c0e0295-0b55-4742-8385-4eb548d60b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044179478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3044179478
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.505628449
Short name T292
Test name
Test status
Simulation time 673160050 ps
CPU time 30.87 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:26:13 PM PDT 24
Peak memory 222420 kb
Host smart-d2203fd2-c40b-48f2-998a-42d4ec77924e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505628449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.505628449
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3301252117
Short name T865
Test name
Test status
Simulation time 394820450 ps
CPU time 4.3 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:25:58 PM PDT 24
Peak memory 222692 kb
Host smart-03ac0dcd-2648-4336-8406-e7874abd9f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301252117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3301252117
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2538904845
Short name T264
Test name
Test status
Simulation time 1217860866 ps
CPU time 6.12 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:26:37 PM PDT 24
Peak memory 222444 kb
Host smart-57f74a20-3ccf-4861-a659-b514cd99aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538904845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2538904845
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.541208371
Short name T3
Test name
Test status
Simulation time 581962815 ps
CPU time 4.02 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:10 PM PDT 24
Peak memory 209036 kb
Host smart-a91f0768-a5c9-4003-9799-d04e2d467c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541208371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.541208371
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.561185701
Short name T134
Test name
Test status
Simulation time 100858251 ps
CPU time 3.62 seconds
Started May 14 02:21:26 PM PDT 24
Finished May 14 02:21:31 PM PDT 24
Peak memory 222764 kb
Host smart-ec5a0d48-0e81-432d-9b00-c0423fe6878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561185701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.561185701
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2886755500
Short name T140
Test name
Test status
Simulation time 90077632 ps
CPU time 3.18 seconds
Started May 14 02:22:06 PM PDT 24
Finished May 14 02:22:09 PM PDT 24
Peak memory 222624 kb
Host smart-f7000864-01fe-4017-9572-50cec9464715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886755500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2886755500
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.712796690
Short name T136
Test name
Test status
Simulation time 123900700 ps
CPU time 5.23 seconds
Started May 14 02:25:59 PM PDT 24
Finished May 14 02:26:04 PM PDT 24
Peak memory 218036 kb
Host smart-d5850aae-82dc-4263-9760-ae951eb81412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712796690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.712796690
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.866879675
Short name T139
Test name
Test status
Simulation time 200471504 ps
CPU time 2.43 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:20:45 PM PDT 24
Peak memory 217464 kb
Host smart-3a92e7f8-f7fc-4c32-be9e-62ff59ea5cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866879675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.866879675
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3926049740
Short name T135
Test name
Test status
Simulation time 226217294 ps
CPU time 4.03 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:39 PM PDT 24
Peak memory 218300 kb
Host smart-5e8867a6-e611-4d01-bc92-74e5fa05de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926049740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3926049740
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3124192013
Short name T311
Test name
Test status
Simulation time 1895747269 ps
CPU time 24.72 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:26 PM PDT 24
Peak memory 208192 kb
Host smart-dad88357-fe35-4b16-a0a3-fb4632ebec0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124192013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3124192013
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.140201874
Short name T191
Test name
Test status
Simulation time 100079731 ps
CPU time 1.82 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:28 PM PDT 24
Peak memory 214268 kb
Host smart-64ec0d94-53a7-4bdf-be70-e5958fa814c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140201874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.140201874
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3278836832
Short name T249
Test name
Test status
Simulation time 149225683 ps
CPU time 2.2 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:42 PM PDT 24
Peak memory 214548 kb
Host smart-e7e01a40-42ea-4e3c-acd9-b652908ee6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278836832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3278836832
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1870502965
Short name T395
Test name
Test status
Simulation time 313421261 ps
CPU time 2.43 seconds
Started May 14 02:21:36 PM PDT 24
Finished May 14 02:21:39 PM PDT 24
Peak memory 210264 kb
Host smart-a2239c20-3be4-4219-be02-bf3565767504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870502965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1870502965
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3124219398
Short name T410
Test name
Test status
Simulation time 379096439 ps
CPU time 9.64 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:25:42 PM PDT 24
Peak memory 215324 kb
Host smart-6c382140-a340-4692-8787-383687fc17ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124219398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3124219398
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2428531017
Short name T19
Test name
Test status
Simulation time 177465417 ps
CPU time 7.48 seconds
Started May 14 02:26:40 PM PDT 24
Finished May 14 02:26:50 PM PDT 24
Peak memory 214432 kb
Host smart-85adabae-99f2-4c9b-b32e-e0ce9ff99639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428531017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2428531017
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.872760442
Short name T154
Test name
Test status
Simulation time 336273514 ps
CPU time 6.83 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:47 PM PDT 24
Peak memory 214152 kb
Host smart-05c8761a-cf3e-4646-9830-55b4dab030d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872760442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.872760442
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1053689713
Short name T158
Test name
Test status
Simulation time 128168978 ps
CPU time 4.11 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205768 kb
Host smart-2c28aa23-e363-4648-a67b-b74279a31745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053689713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1053689713
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2789679785
Short name T156
Test name
Test status
Simulation time 401680041 ps
CPU time 6.18 seconds
Started May 14 04:24:04 PM PDT 24
Finished May 14 04:24:14 PM PDT 24
Peak memory 214036 kb
Host smart-f2793c85-1a3e-401a-b494-23f039f4505f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789679785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2789679785
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3523436642
Short name T153
Test name
Test status
Simulation time 37707202 ps
CPU time 1.86 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 209836 kb
Host smart-8109d565-031e-4fa0-bbfa-02b77f918fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523436642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3523436642
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1069051739
Short name T40
Test name
Test status
Simulation time 1619928223 ps
CPU time 9.99 seconds
Started May 14 02:20:02 PM PDT 24
Finished May 14 02:20:13 PM PDT 24
Peak memory 237912 kb
Host smart-217c6606-531d-4453-be73-f514f1a003b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069051739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1069051739
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.407074631
Short name T373
Test name
Test status
Simulation time 202416689 ps
CPU time 2.65 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:02 PM PDT 24
Peak memory 214056 kb
Host smart-7d35c2a0-e06a-4453-b02f-0b1383b38164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407074631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.407074631
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.962304673
Short name T297
Test name
Test status
Simulation time 166830787 ps
CPU time 4.55 seconds
Started May 14 02:19:28 PM PDT 24
Finished May 14 02:19:33 PM PDT 24
Peak memory 214380 kb
Host smart-7d297526-4c76-4c5e-970e-46eaa38fa428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962304673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.962304673
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1347745279
Short name T144
Test name
Test status
Simulation time 1448393411 ps
CPU time 22.16 seconds
Started May 14 02:19:46 PM PDT 24
Finished May 14 02:20:09 PM PDT 24
Peak memory 222596 kb
Host smart-c3d73f60-06c5-491b-8609-7cdc9b3135fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347745279 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1347745279
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1402723987
Short name T356
Test name
Test status
Simulation time 280853329 ps
CPU time 8.55 seconds
Started May 14 02:21:02 PM PDT 24
Finished May 14 02:21:12 PM PDT 24
Peak memory 221480 kb
Host smart-f62f700c-a321-4749-bda6-3c0af9352563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402723987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1402723987
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4047692486
Short name T332
Test name
Test status
Simulation time 76582200 ps
CPU time 3.48 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:14 PM PDT 24
Peak memory 218476 kb
Host smart-9792a4f5-8cf3-464d-9205-fc8f99cab128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047692486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4047692486
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3135184375
Short name T180
Test name
Test status
Simulation time 34804799 ps
CPU time 2.59 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:28 PM PDT 24
Peak memory 214644 kb
Host smart-e4d36ab6-b748-4b2a-b038-0bad82d5c295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135184375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3135184375
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4061171328
Short name T324
Test name
Test status
Simulation time 766358943 ps
CPU time 4.47 seconds
Started May 14 02:21:26 PM PDT 24
Finished May 14 02:21:31 PM PDT 24
Peak memory 221416 kb
Host smart-1ec984b9-08ed-41c6-b702-8649ece8b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061171328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4061171328
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2291665982
Short name T285
Test name
Test status
Simulation time 71102721 ps
CPU time 2.13 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:43 PM PDT 24
Peak memory 214516 kb
Host smart-42383f1a-2675-4449-905c-303cec73c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291665982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2291665982
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4158112126
Short name T230
Test name
Test status
Simulation time 324896953 ps
CPU time 13.9 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:22:00 PM PDT 24
Peak memory 215392 kb
Host smart-d4b360da-4dc5-44e1-af79-182c53929c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158112126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4158112126
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.716710405
Short name T706
Test name
Test status
Simulation time 219134740 ps
CPU time 2.51 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 214332 kb
Host smart-fb0a3201-f0a0-486a-9958-089221e92523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716710405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.716710405
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2996693887
Short name T268
Test name
Test status
Simulation time 363395355 ps
CPU time 4.85 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 206812 kb
Host smart-d2e08064-bd3a-46e3-9ba5-a693f9ca2fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996693887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2996693887
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2178191963
Short name T315
Test name
Test status
Simulation time 294238781 ps
CPU time 3.73 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:22:02 PM PDT 24
Peak memory 209956 kb
Host smart-333e1865-fae2-485a-8740-6c3cb2bce25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178191963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2178191963
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.235015422
Short name T287
Test name
Test status
Simulation time 407991731 ps
CPU time 5.18 seconds
Started May 14 02:25:09 PM PDT 24
Finished May 14 02:25:15 PM PDT 24
Peak memory 214960 kb
Host smart-7c4102bd-3ed5-4753-b41a-9d2745c3b0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235015422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.235015422
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2229605626
Short name T245
Test name
Test status
Simulation time 397628743 ps
CPU time 4.64 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:14 PM PDT 24
Peak memory 214336 kb
Host smart-6ab59bb8-ad8f-42dc-b85c-050e6efc779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229605626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2229605626
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2875137332
Short name T858
Test name
Test status
Simulation time 1478949632 ps
CPU time 16.06 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:26:01 PM PDT 24
Peak memory 222672 kb
Host smart-22a869ef-d336-41aa-8653-408f87c902fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875137332 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2875137332
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.945257869
Short name T78
Test name
Test status
Simulation time 2535571389 ps
CPU time 18.47 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:26 PM PDT 24
Peak memory 222416 kb
Host smart-52239b59-431f-4c30-8a75-cf6455dd9873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945257869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.945257869
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2478247667
Short name T69
Test name
Test status
Simulation time 193061971 ps
CPU time 6.95 seconds
Started May 14 02:26:26 PM PDT 24
Finished May 14 02:26:35 PM PDT 24
Peak memory 220376 kb
Host smart-81bae6bf-7145-424d-99fc-9981629bdd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478247667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2478247667
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.586111121
Short name T361
Test name
Test status
Simulation time 386777994 ps
CPU time 5.68 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:45 PM PDT 24
Peak memory 222700 kb
Host smart-71fa8969-0e1b-49be-a9a9-08973edeca04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586111121 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.586111121
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3334506485
Short name T208
Test name
Test status
Simulation time 349353665 ps
CPU time 17.16 seconds
Started May 14 02:26:55 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 215180 kb
Host smart-6693ac7d-231b-40d8-8a70-f9285185aba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334506485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3334506485
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3597662128
Short name T346
Test name
Test status
Simulation time 308450654 ps
CPU time 16.66 seconds
Started May 14 02:27:04 PM PDT 24
Finished May 14 02:27:24 PM PDT 24
Peak memory 214280 kb
Host smart-5a6eba34-a7fa-45ec-b5cb-5ac2375cd135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597662128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3597662128
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3364448084
Short name T349
Test name
Test status
Simulation time 6912813115 ps
CPU time 54.56 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:28:33 PM PDT 24
Peak memory 216188 kb
Host smart-388c5941-0d57-4cbd-bbb9-ae9e5a978e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364448084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3364448084
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2241585415
Short name T68
Test name
Test status
Simulation time 115228835 ps
CPU time 3.79 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:50 PM PDT 24
Peak memory 217624 kb
Host smart-b3fac687-7f4f-4aaa-a255-ab605aaffc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241585415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2241585415
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.486056930
Short name T984
Test name
Test status
Simulation time 274620010 ps
CPU time 4.56 seconds
Started May 14 04:23:17 PM PDT 24
Finished May 14 04:23:24 PM PDT 24
Peak memory 205892 kb
Host smart-c9bd9aef-053c-4302-92e5-dba675941bf2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486056930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.486056930
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1830013502
Short name T142
Test name
Test status
Simulation time 1038384380 ps
CPU time 12.47 seconds
Started May 14 04:23:22 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 205760 kb
Host smart-d806f910-4732-489e-9000-7b68fdecd31f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830013502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
830013502
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4230916229
Short name T1030
Test name
Test status
Simulation time 300980584 ps
CPU time 1.24 seconds
Started May 14 04:23:18 PM PDT 24
Finished May 14 04:23:23 PM PDT 24
Peak memory 205836 kb
Host smart-501d61d1-70b0-4761-9338-35f7d67b1f29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230916229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
230916229
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3725972954
Short name T971
Test name
Test status
Simulation time 151283244 ps
CPU time 1.51 seconds
Started May 14 04:23:23 PM PDT 24
Finished May 14 04:23:29 PM PDT 24
Peak memory 214100 kb
Host smart-90c526ef-599b-4192-94d4-7dc19934ce3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725972954 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3725972954
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2729248584
Short name T928
Test name
Test status
Simulation time 25753310 ps
CPU time 1.2 seconds
Started May 14 04:23:19 PM PDT 24
Finished May 14 04:23:24 PM PDT 24
Peak memory 205884 kb
Host smart-392c86dd-3872-42aa-8936-d8098a6530ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729248584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2729248584
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4136822309
Short name T1016
Test name
Test status
Simulation time 45280657 ps
CPU time 0.7 seconds
Started May 14 04:23:23 PM PDT 24
Finished May 14 04:23:28 PM PDT 24
Peak memory 205564 kb
Host smart-850224f6-8bd4-4376-8634-ce4a8a551228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136822309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4136822309
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1723354336
Short name T982
Test name
Test status
Simulation time 242016898 ps
CPU time 2.91 seconds
Started May 14 04:23:22 PM PDT 24
Finished May 14 04:23:29 PM PDT 24
Peak memory 205996 kb
Host smart-986d278d-d523-4427-82a1-26b128e8cfef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723354336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1723354336
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2733668596
Short name T1034
Test name
Test status
Simulation time 1109549649 ps
CPU time 2.77 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:40 PM PDT 24
Peak memory 214352 kb
Host smart-4174c85f-0f07-4739-b900-162f0cee4a05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733668596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2733668596
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3366489234
Short name T1001
Test name
Test status
Simulation time 105037937 ps
CPU time 3.63 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 214436 kb
Host smart-598a2a39-0655-4952-860a-d4e32e6d39a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366489234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3366489234
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3833996467
Short name T989
Test name
Test status
Simulation time 505476348 ps
CPU time 3.34 seconds
Started May 14 04:23:21 PM PDT 24
Finished May 14 04:23:29 PM PDT 24
Peak memory 214048 kb
Host smart-0e78625b-735d-4a72-8bbe-82c63af8ac36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833996467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3833996467
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3804412407
Short name T1075
Test name
Test status
Simulation time 345636549 ps
CPU time 4.85 seconds
Started May 14 04:23:19 PM PDT 24
Finished May 14 04:23:28 PM PDT 24
Peak memory 206124 kb
Host smart-a4e65517-8da6-426c-a83e-3e527558a5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804412407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3804412407
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1510429807
Short name T936
Test name
Test status
Simulation time 1139627979 ps
CPU time 6.12 seconds
Started May 14 04:23:23 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 205796 kb
Host smart-41ed0807-6752-40d1-a8a4-c1859e29c2d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510429807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
510429807
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2178881725
Short name T1012
Test name
Test status
Simulation time 1791210631 ps
CPU time 15.98 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:47 PM PDT 24
Peak memory 205948 kb
Host smart-8d29c720-72b7-41e9-b3c9-72e98950f1d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178881725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
178881725
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1073403087
Short name T1013
Test name
Test status
Simulation time 111966037 ps
CPU time 0.95 seconds
Started May 14 04:23:21 PM PDT 24
Finished May 14 04:23:26 PM PDT 24
Peak memory 205696 kb
Host smart-6bc40364-2ffa-4cde-8f84-d5940464373b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073403087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
073403087
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.493125374
Short name T945
Test name
Test status
Simulation time 205005545 ps
CPU time 2.18 seconds
Started May 14 04:23:20 PM PDT 24
Finished May 14 04:23:27 PM PDT 24
Peak memory 214116 kb
Host smart-787a0664-d935-4a5e-8934-f161e7b5e3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493125374 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.493125374
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.258069370
Short name T130
Test name
Test status
Simulation time 30655501 ps
CPU time 1.09 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:29 PM PDT 24
Peak memory 205808 kb
Host smart-7489475e-2c18-4677-a48c-d6fbd405b1a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258069370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.258069370
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.278830357
Short name T981
Test name
Test status
Simulation time 14510204 ps
CPU time 0.92 seconds
Started May 14 04:23:20 PM PDT 24
Finished May 14 04:23:25 PM PDT 24
Peak memory 205744 kb
Host smart-ab0e2949-5eff-431c-988a-830c9969a756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278830357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.278830357
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2921677630
Short name T973
Test name
Test status
Simulation time 84844101 ps
CPU time 2.41 seconds
Started May 14 04:23:19 PM PDT 24
Finished May 14 04:23:26 PM PDT 24
Peak memory 214072 kb
Host smart-6f4bba75-2ba3-49da-9938-b4b2a5489faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921677630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2921677630
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.946297000
Short name T947
Test name
Test status
Simulation time 652496074 ps
CPU time 5.1 seconds
Started May 14 04:23:18 PM PDT 24
Finished May 14 04:23:26 PM PDT 24
Peak memory 214448 kb
Host smart-bda92119-e8f6-41ea-b455-ec93c718f7a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946297000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.946297000
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4032629404
Short name T998
Test name
Test status
Simulation time 764536934 ps
CPU time 8.06 seconds
Started May 14 04:23:21 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 214508 kb
Host smart-5cfd3d1e-9e24-4aaf-a10e-aea67d86d459
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032629404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4032629404
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.792096396
Short name T951
Test name
Test status
Simulation time 131079822 ps
CPU time 1.76 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:30 PM PDT 24
Peak memory 214044 kb
Host smart-83d5ffba-885e-4886-a243-eecdf0a5c0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792096396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.792096396
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.435901897
Short name T920
Test name
Test status
Simulation time 792288330 ps
CPU time 2.25 seconds
Started May 14 04:23:40 PM PDT 24
Finished May 14 04:23:47 PM PDT 24
Peak memory 214108 kb
Host smart-298eee2c-9464-49c3-9cfb-510b69889ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435901897 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.435901897
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2064260587
Short name T1007
Test name
Test status
Simulation time 24695187 ps
CPU time 1.12 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 205768 kb
Host smart-725ff051-63d6-4150-8491-91a072af66ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064260587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2064260587
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1769858997
Short name T1057
Test name
Test status
Simulation time 26746104 ps
CPU time 0.89 seconds
Started May 14 04:23:44 PM PDT 24
Finished May 14 04:23:48 PM PDT 24
Peak memory 205752 kb
Host smart-005e3af0-0f5b-4d64-9ce5-a6266253a224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769858997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1769858997
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1725746462
Short name T128
Test name
Test status
Simulation time 84181807 ps
CPU time 2.3 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 205704 kb
Host smart-9f4f6d0e-f59b-473b-b009-adc015aee31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725746462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1725746462
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.679450613
Short name T102
Test name
Test status
Simulation time 114000020 ps
CPU time 1.97 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 214444 kb
Host smart-b1ef3fd6-0976-4a45-8275-f91b756eee16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679450613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.679450613
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1850242210
Short name T1039
Test name
Test status
Simulation time 80448138 ps
CPU time 4.69 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 214428 kb
Host smart-86f6c2d8-991e-4dde-b342-7dbd267b3ee4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850242210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1850242210
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3741195880
Short name T1073
Test name
Test status
Simulation time 29319762 ps
CPU time 2.04 seconds
Started May 14 04:23:44 PM PDT 24
Finished May 14 04:23:50 PM PDT 24
Peak memory 214048 kb
Host smart-f2b2d4cd-6291-48c8-8145-6d01e18b6a28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741195880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3741195880
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.634028327
Short name T146
Test name
Test status
Simulation time 84137930 ps
CPU time 3.32 seconds
Started May 14 04:23:43 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214052 kb
Host smart-66b078c6-1485-43ff-8609-0e5c60ae9d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634028327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.634028327
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3616799949
Short name T1043
Test name
Test status
Simulation time 39420732 ps
CPU time 1.54 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 214176 kb
Host smart-655f62bc-16e7-4d9b-b954-28980d839b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616799949 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3616799949
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.278198982
Short name T127
Test name
Test status
Simulation time 136026828 ps
CPU time 1.3 seconds
Started May 14 04:23:44 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 205784 kb
Host smart-ab9acf04-a994-4efd-bd43-6a19993563df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278198982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.278198982
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4005698175
Short name T1047
Test name
Test status
Simulation time 14717102 ps
CPU time 0.95 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205704 kb
Host smart-334db15b-7dd9-477e-a6c4-e35a58fa2f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005698175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4005698175
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3218456913
Short name T999
Test name
Test status
Simulation time 46078378 ps
CPU time 1.6 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 205956 kb
Host smart-892c0501-2a58-41c0-9274-cb266b3e0704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218456913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3218456913
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2067561367
Short name T111
Test name
Test status
Simulation time 306420997 ps
CPU time 1.79 seconds
Started May 14 04:23:38 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 214288 kb
Host smart-54daceb0-3f0f-4d14-9578-85c63021ebfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067561367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2067561367
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2898428321
Short name T104
Test name
Test status
Simulation time 159675521 ps
CPU time 7.05 seconds
Started May 14 04:23:43 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 214420 kb
Host smart-d7e509e2-a470-4870-9ac5-f10ec99ecc00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898428321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2898428321
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3430361693
Short name T931
Test name
Test status
Simulation time 290346649 ps
CPU time 3.29 seconds
Started May 14 04:23:32 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 213984 kb
Host smart-1fe2300c-ca25-485b-a3f5-ac19fc2265ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430361693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3430361693
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3715755683
Short name T152
Test name
Test status
Simulation time 496512178 ps
CPU time 7.34 seconds
Started May 14 04:23:44 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 216468 kb
Host smart-8c545b16-f594-47f5-b206-629a842a1cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715755683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3715755683
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1973942568
Short name T145
Test name
Test status
Simulation time 207157042 ps
CPU time 1.67 seconds
Started May 14 04:23:46 PM PDT 24
Finished May 14 04:23:50 PM PDT 24
Peak memory 214156 kb
Host smart-0d860704-b434-4ba7-8c9d-06a3ab287cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973942568 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1973942568
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.688761579
Short name T994
Test name
Test status
Simulation time 19613694 ps
CPU time 0.93 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205636 kb
Host smart-6e791265-6f2c-4396-bd81-48740f8b212b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688761579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.688761579
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.222642657
Short name T1040
Test name
Test status
Simulation time 21933289 ps
CPU time 0.8 seconds
Started May 14 04:23:43 PM PDT 24
Finished May 14 04:23:48 PM PDT 24
Peak memory 205608 kb
Host smart-035540d9-d46a-41f3-a59f-b14ca6534f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222642657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.222642657
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4278888547
Short name T1022
Test name
Test status
Simulation time 153537620 ps
CPU time 1.58 seconds
Started May 14 04:23:38 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 205896 kb
Host smart-4c8a51e8-255c-4ce4-b33d-044e90ee5ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278888547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4278888547
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3491907613
Short name T943
Test name
Test status
Simulation time 183082402 ps
CPU time 3.03 seconds
Started May 14 04:23:44 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214448 kb
Host smart-66296e19-8189-4e5b-8d95-a3329360fa3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491907613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3491907613
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4050732908
Short name T993
Test name
Test status
Simulation time 328896885 ps
CPU time 8.87 seconds
Started May 14 04:23:52 PM PDT 24
Finished May 14 04:24:03 PM PDT 24
Peak memory 214596 kb
Host smart-71e4c337-6786-4454-abab-e5c41b81ed14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050732908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4050732908
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1038756528
Short name T977
Test name
Test status
Simulation time 74803280 ps
CPU time 2.06 seconds
Started May 14 04:23:42 PM PDT 24
Finished May 14 04:23:48 PM PDT 24
Peak memory 214016 kb
Host smart-6354f9b3-fd13-46b8-8acc-cd59406c0079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038756528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1038756528
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1235515153
Short name T914
Test name
Test status
Simulation time 496659916 ps
CPU time 3.84 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:45 PM PDT 24
Peak memory 205724 kb
Host smart-5fde5b2e-75c3-4baa-96f2-bafa531ccd5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235515153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1235515153
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2209614
Short name T924
Test name
Test status
Simulation time 19838800 ps
CPU time 1.35 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:01 PM PDT 24
Peak memory 214208 kb
Host smart-d0cd7a4b-4d0d-474c-93e3-5b360be70fbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209614 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2209614
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2112465681
Short name T1033
Test name
Test status
Simulation time 25150853 ps
CPU time 0.97 seconds
Started May 14 04:23:41 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205824 kb
Host smart-f270e446-da7b-48cf-b616-ce9b4818866a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112465681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2112465681
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.444233238
Short name T963
Test name
Test status
Simulation time 17402135 ps
CPU time 0.83 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205448 kb
Host smart-4bdab96c-15e8-4a4a-8ae7-6c177d7a9b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444233238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.444233238
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3738867349
Short name T960
Test name
Test status
Simulation time 178339181 ps
CPU time 2.96 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:09 PM PDT 24
Peak memory 205948 kb
Host smart-cb416760-d6d1-43ec-ba0f-3c62ba1b534b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738867349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3738867349
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2058994286
Short name T1068
Test name
Test status
Simulation time 119210011 ps
CPU time 3.25 seconds
Started May 14 04:23:53 PM PDT 24
Finished May 14 04:23:59 PM PDT 24
Peak memory 214400 kb
Host smart-c3824cb0-1ce4-43b7-aba7-c84b9948ec5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058994286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2058994286
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3863105220
Short name T1074
Test name
Test status
Simulation time 123877505 ps
CPU time 5.48 seconds
Started May 14 04:23:59 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 214276 kb
Host smart-eeb46bdb-8d29-4ef7-8527-bf4c77bc4a60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863105220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3863105220
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.997184673
Short name T1076
Test name
Test status
Simulation time 96203579 ps
CPU time 2.26 seconds
Started May 14 04:23:53 PM PDT 24
Finished May 14 04:23:57 PM PDT 24
Peak memory 214132 kb
Host smart-0e74451f-055c-40c4-8751-9cb0376df5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997184673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.997184673
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4134342084
Short name T1017
Test name
Test status
Simulation time 60925857 ps
CPU time 2.39 seconds
Started May 14 04:23:40 PM PDT 24
Finished May 14 04:23:47 PM PDT 24
Peak memory 219624 kb
Host smart-9feb4bed-ca59-4adc-a6ca-7d0f0af2f8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134342084 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4134342084
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4161276799
Short name T935
Test name
Test status
Simulation time 52100696 ps
CPU time 1.04 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 205756 kb
Host smart-5d53db3e-8044-49b4-83e6-0a11265d4fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161276799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4161276799
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4275047840
Short name T955
Test name
Test status
Simulation time 14584460 ps
CPU time 0.83 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:53 PM PDT 24
Peak memory 205448 kb
Host smart-ae951602-dafe-4c30-913f-2a31034c9c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275047840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4275047840
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1204900905
Short name T124
Test name
Test status
Simulation time 25559770 ps
CPU time 1.71 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 205760 kb
Host smart-075d5efd-1abe-4905-b3b1-4f3f41008ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204900905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1204900905
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1086421995
Short name T1005
Test name
Test status
Simulation time 557838160 ps
CPU time 4.19 seconds
Started May 14 04:23:45 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 214348 kb
Host smart-80c5802f-ae50-4956-b301-305db443dd0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086421995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1086421995
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4278222092
Short name T1025
Test name
Test status
Simulation time 97466204 ps
CPU time 5.38 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:05 PM PDT 24
Peak memory 214364 kb
Host smart-f66e70a0-4de3-4b81-ab56-df9bcab35ce9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278222092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4278222092
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.855827354
Short name T1045
Test name
Test status
Simulation time 124226323 ps
CPU time 2.4 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 214164 kb
Host smart-a5c68849-3ec6-40f3-8fd4-9d9ad92d7cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855827354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.855827354
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.593042790
Short name T148
Test name
Test status
Simulation time 146101731 ps
CPU time 5.77 seconds
Started May 14 04:23:39 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 214128 kb
Host smart-40729740-3cce-4d47-a513-45c372bfa459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593042790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.593042790
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3828160703
Short name T1064
Test name
Test status
Simulation time 34340522 ps
CPU time 1.21 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 205916 kb
Host smart-2f35c312-1c39-499e-a6ac-8d93f64339ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828160703 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3828160703
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2885660869
Short name T1055
Test name
Test status
Simulation time 15140282 ps
CPU time 1.29 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 205820 kb
Host smart-d597c2f0-fdc0-49c5-9402-f14e4c32a1d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885660869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2885660869
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.57203642
Short name T991
Test name
Test status
Simulation time 10373498 ps
CPU time 0.77 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 205608 kb
Host smart-0ecd65b9-da85-4f0d-94b3-77f5e5b9e616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57203642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.57203642
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.421189510
Short name T126
Test name
Test status
Simulation time 85230516 ps
CPU time 2.67 seconds
Started May 14 04:24:00 PM PDT 24
Finished May 14 04:24:05 PM PDT 24
Peak memory 205844 kb
Host smart-7f37ed61-5958-4450-a570-81ab5e1f768e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421189510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.421189510
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1158947807
Short name T1029
Test name
Test status
Simulation time 237744131 ps
CPU time 1.9 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 214400 kb
Host smart-9c660c1d-fe7c-4fb2-bffb-040ed74f4baa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158947807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1158947807
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2915291016
Short name T970
Test name
Test status
Simulation time 792539815 ps
CPU time 2.06 seconds
Started May 14 04:23:53 PM PDT 24
Finished May 14 04:23:57 PM PDT 24
Peak memory 215424 kb
Host smart-d51643b8-ef72-494e-90a0-52ee8156f232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915291016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2915291016
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3586627834
Short name T1044
Test name
Test status
Simulation time 86605073 ps
CPU time 1.45 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214172 kb
Host smart-0dab15d2-6382-417a-910b-65bb7e8b3ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586627834 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3586627834
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3120306630
Short name T966
Test name
Test status
Simulation time 10169074 ps
CPU time 1.03 seconds
Started May 14 04:23:52 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 205888 kb
Host smart-37dba19d-e5f4-4226-8f1c-fb3401c1e657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120306630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3120306630
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2228676561
Short name T952
Test name
Test status
Simulation time 11802780 ps
CPU time 0.92 seconds
Started May 14 04:23:35 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 205512 kb
Host smart-bfef2b62-0513-446d-a541-f6f6e3b01435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228676561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2228676561
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2195878980
Short name T968
Test name
Test status
Simulation time 189834859 ps
CPU time 2.44 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:56 PM PDT 24
Peak memory 205972 kb
Host smart-90643bd5-410c-4b4b-9b2f-a69a9eb4d777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195878980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2195878980
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3532266927
Short name T1042
Test name
Test status
Simulation time 536866083 ps
CPU time 2.47 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 214380 kb
Host smart-8fc42118-bc77-4e07-be8f-1b8641496f99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532266927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3532266927
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4145956531
Short name T1010
Test name
Test status
Simulation time 86491192 ps
CPU time 3.86 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:57 PM PDT 24
Peak memory 214340 kb
Host smart-1ab0379e-1c59-454a-b44c-ab4b6de273eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145956531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4145956531
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1828874815
Short name T1006
Test name
Test status
Simulation time 75495630 ps
CPU time 2.18 seconds
Started May 14 04:23:37 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 215392 kb
Host smart-0385aa1e-182b-4e85-a4a4-5a8e88ce744b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828874815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1828874815
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1681351108
Short name T150
Test name
Test status
Simulation time 145758262 ps
CPU time 3.75 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 214008 kb
Host smart-20620816-a8fe-4457-b75d-ead266d68e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681351108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1681351108
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.440460639
Short name T976
Test name
Test status
Simulation time 54786359 ps
CPU time 1.66 seconds
Started May 14 04:23:54 PM PDT 24
Finished May 14 04:23:57 PM PDT 24
Peak memory 214016 kb
Host smart-e1adf953-2a41-449d-8aaf-7ebd9e9eec1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440460639 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.440460639
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.498259874
Short name T1036
Test name
Test status
Simulation time 160616501 ps
CPU time 0.91 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205576 kb
Host smart-1b8374a4-fd6d-4c11-bee0-a5885f47579d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498259874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.498259874
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.452796259
Short name T912
Test name
Test status
Simulation time 17170461 ps
CPU time 0.75 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 205604 kb
Host smart-5b9561a8-4bcf-45a8-9c2e-5427bf96ddae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452796259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.452796259
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3362530521
Short name T1021
Test name
Test status
Simulation time 467697228 ps
CPU time 4.87 seconds
Started May 14 04:23:53 PM PDT 24
Finished May 14 04:24:00 PM PDT 24
Peak memory 205896 kb
Host smart-0de83891-3518-49dd-bc23-860611005f8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362530521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3362530521
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4102732488
Short name T112
Test name
Test status
Simulation time 67431047 ps
CPU time 1.75 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 214340 kb
Host smart-eb90481c-3820-440d-b6e6-e564683eedf8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102732488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4102732488
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4050350777
Short name T1038
Test name
Test status
Simulation time 363763355 ps
CPU time 9.49 seconds
Started May 14 04:23:52 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 214464 kb
Host smart-541e7d22-27d5-40f4-ab65-feff5fd82a45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050350777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4050350777
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.891280933
Short name T958
Test name
Test status
Simulation time 410022038 ps
CPU time 4.34 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 216092 kb
Host smart-3684ae52-2a43-4fc3-8180-8f93f1ad012f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891280933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.891280933
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.778667639
Short name T937
Test name
Test status
Simulation time 198355157 ps
CPU time 1.67 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:01 PM PDT 24
Peak memory 214064 kb
Host smart-f67d4aad-d9d5-4cd7-9c3b-73f84891ea84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778667639 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.778667639
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.4172168542
Short name T1067
Test name
Test status
Simulation time 60640433 ps
CPU time 0.97 seconds
Started May 14 04:24:00 PM PDT 24
Finished May 14 04:24:03 PM PDT 24
Peak memory 205740 kb
Host smart-5d2ac213-3cba-4390-a42b-bba2a98cd73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172168542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.4172168542
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2183900577
Short name T911
Test name
Test status
Simulation time 24238170 ps
CPU time 0.81 seconds
Started May 14 04:23:54 PM PDT 24
Finished May 14 04:23:57 PM PDT 24
Peak memory 205516 kb
Host smart-89ffbc56-a03d-4780-aaef-4a133b37491d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183900577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2183900577
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1886533157
Short name T1008
Test name
Test status
Simulation time 99061888 ps
CPU time 2.8 seconds
Started May 14 04:23:43 PM PDT 24
Finished May 14 04:23:50 PM PDT 24
Peak memory 205932 kb
Host smart-c1620cab-6127-443b-bf41-24f9f8a7062d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886533157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1886533157
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2584053571
Short name T944
Test name
Test status
Simulation time 138465672 ps
CPU time 3.61 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:56 PM PDT 24
Peak memory 214212 kb
Host smart-d334cad7-1361-4a49-81aa-318b4225231b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584053571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2584053571
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3011773456
Short name T910
Test name
Test status
Simulation time 61137600 ps
CPU time 2.1 seconds
Started May 14 04:23:38 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 214064 kb
Host smart-6cc26149-6bee-42a3-b096-700af06d99b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011773456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3011773456
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2433523758
Short name T159
Test name
Test status
Simulation time 542715931 ps
CPU time 3.57 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:03 PM PDT 24
Peak memory 213972 kb
Host smart-152a6c9d-cbdc-4ade-be28-64782f3ccbcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433523758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2433523758
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3524643369
Short name T1054
Test name
Test status
Simulation time 116767844 ps
CPU time 1.53 seconds
Started May 14 04:23:43 PM PDT 24
Finished May 14 04:23:48 PM PDT 24
Peak memory 214196 kb
Host smart-7aaae485-a642-498b-9546-748dcfa8d644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524643369 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3524643369
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2042021722
Short name T932
Test name
Test status
Simulation time 40211940 ps
CPU time 1.14 seconds
Started May 14 04:24:05 PM PDT 24
Finished May 14 04:24:09 PM PDT 24
Peak memory 205812 kb
Host smart-f4dc53e5-136f-437c-b474-0dd527568c9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042021722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2042021722
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2736635590
Short name T1061
Test name
Test status
Simulation time 10267642 ps
CPU time 0.77 seconds
Started May 14 04:24:04 PM PDT 24
Finished May 14 04:24:08 PM PDT 24
Peak memory 205328 kb
Host smart-4b8e0a47-d254-4013-aac4-66e67f362398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736635590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2736635590
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3663259555
Short name T166
Test name
Test status
Simulation time 799100331 ps
CPU time 4.51 seconds
Started May 14 04:24:02 PM PDT 24
Finished May 14 04:24:09 PM PDT 24
Peak memory 205728 kb
Host smart-ac776b27-0f30-420d-8b4f-54b0f493694f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663259555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3663259555
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1092693835
Short name T1062
Test name
Test status
Simulation time 122348103 ps
CPU time 4.15 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 214368 kb
Host smart-78f6a370-65b4-4845-9f44-fe6bfe94ef7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092693835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1092693835
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2601497127
Short name T990
Test name
Test status
Simulation time 185525622 ps
CPU time 5.19 seconds
Started May 14 04:24:07 PM PDT 24
Finished May 14 04:24:18 PM PDT 24
Peak memory 214360 kb
Host smart-4b8ce3eb-58a7-4d04-853f-68dfee6d9a2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601497127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2601497127
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.407008037
Short name T1041
Test name
Test status
Simulation time 88040596 ps
CPU time 2.26 seconds
Started May 14 04:24:08 PM PDT 24
Finished May 14 04:24:15 PM PDT 24
Peak memory 213756 kb
Host smart-c4f16a5c-822b-4b2b-8798-b6f310a03bde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407008037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.407008037
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3078383317
Short name T1023
Test name
Test status
Simulation time 841369076 ps
CPU time 7.23 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 205836 kb
Host smart-e128bdb5-db92-4923-a6a4-785d7f4e8323
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078383317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
078383317
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2797133900
Short name T1027
Test name
Test status
Simulation time 1193914134 ps
CPU time 8.68 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 205912 kb
Host smart-c3951120-d974-4e1f-bc70-de71631ee95b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797133900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
797133900
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2251752412
Short name T1009
Test name
Test status
Simulation time 28304216 ps
CPU time 1.09 seconds
Started May 14 04:24:02 PM PDT 24
Finished May 14 04:24:06 PM PDT 24
Peak memory 205876 kb
Host smart-82b5960e-fd5a-4171-9409-558f0f45c2c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251752412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
251752412
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.643615390
Short name T1065
Test name
Test status
Simulation time 165809926 ps
CPU time 1.38 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:30 PM PDT 24
Peak memory 205872 kb
Host smart-7ba271c3-12ea-4505-9816-6258d7148ccc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643615390 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.643615390
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.510789008
Short name T1072
Test name
Test status
Simulation time 62948573 ps
CPU time 0.89 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 205652 kb
Host smart-20ddcbab-e9a9-47f4-a472-799fcac0395c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510789008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.510789008
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.176369088
Short name T1070
Test name
Test status
Simulation time 12585810 ps
CPU time 0.74 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205568 kb
Host smart-1f444bf2-c240-4ac6-906d-3addc33d08c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176369088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.176369088
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3668507330
Short name T129
Test name
Test status
Simulation time 32908264 ps
CPU time 1.83 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 205908 kb
Host smart-e4cfaab9-487b-4ed5-a551-d0fc56d967dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668507330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3668507330
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2357691307
Short name T1056
Test name
Test status
Simulation time 494835885 ps
CPU time 3.05 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:40 PM PDT 24
Peak memory 214376 kb
Host smart-ecc14ec8-1fba-4a28-ad8f-f9655e5bfcfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357691307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2357691307
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3107593780
Short name T110
Test name
Test status
Simulation time 377606926 ps
CPU time 7.17 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 214352 kb
Host smart-a1121fec-6c88-434a-a3fc-f443f4aabd58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107593780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3107593780
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2705792459
Short name T954
Test name
Test status
Simulation time 250645266 ps
CPU time 2.86 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 222272 kb
Host smart-70811ec8-853a-4f52-bc53-bc7f0929b07b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705792459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2705792459
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3058354011
Short name T962
Test name
Test status
Simulation time 44250874 ps
CPU time 0.8 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 205568 kb
Host smart-24e0ff6c-c1f5-4a93-871f-55bdaab90d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058354011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3058354011
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.34247737
Short name T978
Test name
Test status
Simulation time 8751214 ps
CPU time 0.78 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:01 PM PDT 24
Peak memory 205236 kb
Host smart-f2da073d-0f21-4b14-b50c-e4eb53cc65e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.34247737
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1824978528
Short name T918
Test name
Test status
Simulation time 13682424 ps
CPU time 0.73 seconds
Started May 14 04:23:52 PM PDT 24
Finished May 14 04:23:55 PM PDT 24
Peak memory 205584 kb
Host smart-c81a9e2e-29ad-4449-bf8d-1e59b15be156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824978528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1824978528
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1931675770
Short name T974
Test name
Test status
Simulation time 26636361 ps
CPU time 0.8 seconds
Started May 14 04:23:41 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205580 kb
Host smart-4af1fe4f-4060-42ac-989b-d45c42654120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931675770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1931675770
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1565077035
Short name T1071
Test name
Test status
Simulation time 148868725 ps
CPU time 0.78 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 205540 kb
Host smart-6d9663d2-aaaa-4ab9-a061-5f7255d63889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565077035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1565077035
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.582495532
Short name T948
Test name
Test status
Simulation time 15213653 ps
CPU time 0.71 seconds
Started May 14 04:23:58 PM PDT 24
Finished May 14 04:24:01 PM PDT 24
Peak memory 205308 kb
Host smart-265081e9-5e70-4bce-8a36-79ce8bc8955a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582495532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.582495532
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1488776601
Short name T967
Test name
Test status
Simulation time 10808483 ps
CPU time 0.76 seconds
Started May 14 04:23:42 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205580 kb
Host smart-0f9fb499-82f9-4a3a-9dfe-e0a26d264e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488776601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1488776601
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3282254358
Short name T929
Test name
Test status
Simulation time 14167642 ps
CPU time 0.72 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:06 PM PDT 24
Peak memory 205252 kb
Host smart-b7ae7b22-6089-4e98-b0da-68f0fee3a057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282254358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3282254358
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2713883089
Short name T923
Test name
Test status
Simulation time 41129177 ps
CPU time 0.88 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 205516 kb
Host smart-f60101a9-bdd9-4367-806d-29ac98a206de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713883089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2713883089
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1377694201
Short name T1028
Test name
Test status
Simulation time 164258874 ps
CPU time 0.92 seconds
Started May 14 04:24:01 PM PDT 24
Finished May 14 04:24:04 PM PDT 24
Peak memory 205556 kb
Host smart-77087abd-f5ca-45a2-a69d-820433413c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377694201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1377694201
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2749113073
Short name T1014
Test name
Test status
Simulation time 278323831 ps
CPU time 5.33 seconds
Started May 14 04:23:25 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205688 kb
Host smart-be11450a-113f-4730-b587-5691f7a8fa46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749113073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
749113073
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3803985347
Short name T972
Test name
Test status
Simulation time 1558097251 ps
CPU time 12.47 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 205960 kb
Host smart-32b49bcc-2b80-44d4-8e6c-965c3af472ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803985347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
803985347
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4068163289
Short name T1031
Test name
Test status
Simulation time 251681480 ps
CPU time 0.9 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205564 kb
Host smart-08d5fe2e-2adf-4780-9415-c6e4d21a4cc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068163289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
068163289
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1758542595
Short name T922
Test name
Test status
Simulation time 47644625 ps
CPU time 2.15 seconds
Started May 14 04:23:35 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 214112 kb
Host smart-7c33e1ca-ffa5-4f6e-9771-da17e4c35650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758542595 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1758542595
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3152770205
Short name T934
Test name
Test status
Simulation time 46548859 ps
CPU time 1.48 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205824 kb
Host smart-cb9e7ed3-be78-4dfd-9c41-594a380003c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152770205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3152770205
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2163372448
Short name T1048
Test name
Test status
Simulation time 26635376 ps
CPU time 0.79 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205588 kb
Host smart-ef0cf229-7784-419b-907c-4c7ab11365aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163372448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2163372448
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.709034566
Short name T1059
Test name
Test status
Simulation time 32865898 ps
CPU time 2.33 seconds
Started May 14 04:23:25 PM PDT 24
Finished May 14 04:23:32 PM PDT 24
Peak memory 205900 kb
Host smart-57a261f1-8fb7-4f9f-ba55-91f425d5b64d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709034566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.709034566
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1046370127
Short name T1026
Test name
Test status
Simulation time 1190600811 ps
CPU time 2.36 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 214404 kb
Host smart-13c0e22d-8ad9-496a-94af-f2539dc88133
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046370127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1046370127
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.372603184
Short name T946
Test name
Test status
Simulation time 1656836729 ps
CPU time 10.27 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 214464 kb
Host smart-cc269cb4-3441-47eb-aa5d-42d0f434d0a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372603184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.372603184
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3715223523
Short name T995
Test name
Test status
Simulation time 22618294 ps
CPU time 1.73 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214080 kb
Host smart-7e9f5576-e169-42f0-aacd-23544457ddee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715223523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3715223523
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.112909341
Short name T1035
Test name
Test status
Simulation time 79068043 ps
CPU time 3.29 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:44 PM PDT 24
Peak memory 205812 kb
Host smart-5d6f25fd-29be-45f8-89a0-6a81a53abb00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112909341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
112909341
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1367206848
Short name T1077
Test name
Test status
Simulation time 11762438 ps
CPU time 0.72 seconds
Started May 14 04:23:41 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205508 kb
Host smart-fd3d9892-8340-48e1-b09a-a10fd78c5237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367206848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1367206848
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4192774733
Short name T980
Test name
Test status
Simulation time 7176389 ps
CPU time 0.67 seconds
Started May 14 04:24:07 PM PDT 24
Finished May 14 04:24:12 PM PDT 24
Peak memory 205612 kb
Host smart-6c3f3c2c-bc6a-4dfa-bbeb-b166aef3f92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192774733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4192774733
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2442547224
Short name T979
Test name
Test status
Simulation time 32175589 ps
CPU time 0.72 seconds
Started May 14 04:23:42 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205500 kb
Host smart-6d4c915b-0a49-4dba-99fd-dcf908fb7241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442547224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2442547224
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1668771021
Short name T925
Test name
Test status
Simulation time 86483666 ps
CPU time 0.91 seconds
Started May 14 04:23:59 PM PDT 24
Finished May 14 04:24:02 PM PDT 24
Peak memory 205524 kb
Host smart-f0be05c5-c502-4bcb-8c20-79dd079e73ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668771021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1668771021
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3171186233
Short name T1004
Test name
Test status
Simulation time 7990382 ps
CPU time 0.77 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:06 PM PDT 24
Peak memory 205328 kb
Host smart-c614980d-5541-466e-b834-c234c9810edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171186233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3171186233
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1226981996
Short name T933
Test name
Test status
Simulation time 48295496 ps
CPU time 0.9 seconds
Started May 14 04:23:46 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 205524 kb
Host smart-e3c62d6a-cbd4-47f9-8057-21ef94b3a849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226981996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1226981996
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1303005362
Short name T950
Test name
Test status
Simulation time 49577157 ps
CPU time 0.73 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 205508 kb
Host smart-13de2665-a97a-4f35-8a77-d31371134005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303005362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1303005362
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2550235097
Short name T915
Test name
Test status
Simulation time 31469968 ps
CPU time 0.83 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:53 PM PDT 24
Peak memory 205508 kb
Host smart-a9e8bb7a-77ff-468c-920d-14b66246061b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550235097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2550235097
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.937813547
Short name T1066
Test name
Test status
Simulation time 12289104 ps
CPU time 0.87 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:53 PM PDT 24
Peak memory 205532 kb
Host smart-c99fa5f3-2074-4ab1-bc7c-160143d5488b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937813547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.937813547
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2766087189
Short name T919
Test name
Test status
Simulation time 35949058 ps
CPU time 0.72 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 205588 kb
Host smart-452f75e5-03c8-4da8-a536-b1b2bedc5f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766087189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2766087189
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4069751098
Short name T961
Test name
Test status
Simulation time 1650715308 ps
CPU time 8.12 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:46 PM PDT 24
Peak memory 205836 kb
Host smart-1b131a0b-8531-4c07-8c1a-9312256d9f4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069751098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
069751098
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.487203494
Short name T921
Test name
Test status
Simulation time 265544952 ps
CPU time 6.57 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205724 kb
Host smart-1b905168-7679-46cf-9179-6d820734feed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487203494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.487203494
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1273793524
Short name T956
Test name
Test status
Simulation time 54312505 ps
CPU time 1.36 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:32 PM PDT 24
Peak memory 205728 kb
Host smart-6c0f0d36-c490-4b86-8c41-898b0622bb12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273793524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
273793524
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.905115326
Short name T1049
Test name
Test status
Simulation time 94670375 ps
CPU time 1.12 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205896 kb
Host smart-30cbd3f9-5eea-4720-bbcd-0f3b27386007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905115326 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.905115326
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.569222709
Short name T1078
Test name
Test status
Simulation time 59441529 ps
CPU time 1.23 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 205816 kb
Host smart-a115b4f8-d71b-4ee3-8202-cf0f3a2544fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569222709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.569222709
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.861826487
Short name T1015
Test name
Test status
Simulation time 12925977 ps
CPU time 0.7 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 205572 kb
Host smart-572bf50f-c891-4d5d-9464-a743cd87bea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861826487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.861826487
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1726588128
Short name T953
Test name
Test status
Simulation time 407725671 ps
CPU time 3.57 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 205812 kb
Host smart-015ea3a0-b148-4f62-8ddf-3564546d675f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726588128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1726588128
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3129677639
Short name T1020
Test name
Test status
Simulation time 350447391 ps
CPU time 2.15 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 214292 kb
Host smart-98cc71f6-22d5-4e34-87cd-b9e68f8a0799
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129677639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3129677639
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1106057102
Short name T1003
Test name
Test status
Simulation time 257269561 ps
CPU time 5.66 seconds
Started May 14 04:23:24 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 214292 kb
Host smart-e1b8b4e6-e63d-4f40-8922-8c86a4ab471d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106057102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1106057102
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2578885931
Short name T913
Test name
Test status
Simulation time 73139177 ps
CPU time 2.2 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 215000 kb
Host smart-4bb2e1b3-6990-4b57-9f20-e652e316415c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578885931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2578885931
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3452218678
Short name T949
Test name
Test status
Simulation time 15386576 ps
CPU time 0.68 seconds
Started May 14 04:23:59 PM PDT 24
Finished May 14 04:24:01 PM PDT 24
Peak memory 205632 kb
Host smart-6f683295-d5dd-4e13-ac4c-3c767c83abc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452218678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3452218678
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3751856464
Short name T964
Test name
Test status
Simulation time 35659228 ps
CPU time 0.8 seconds
Started May 14 04:24:06 PM PDT 24
Finished May 14 04:24:12 PM PDT 24
Peak memory 205556 kb
Host smart-023adb27-aeb2-4688-bb45-7806677dcf7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751856464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3751856464
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1973218254
Short name T942
Test name
Test status
Simulation time 36655974 ps
CPU time 0.75 seconds
Started May 14 04:23:51 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205656 kb
Host smart-1c207933-e2bd-4fbd-b7c3-bbbf1b0d1e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973218254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1973218254
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2809376893
Short name T927
Test name
Test status
Simulation time 12269094 ps
CPU time 0.84 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 205676 kb
Host smart-554cfa01-97dd-41ac-b79a-034c27d21c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809376893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2809376893
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3382002530
Short name T1058
Test name
Test status
Simulation time 8684155 ps
CPU time 0.8 seconds
Started May 14 04:24:10 PM PDT 24
Finished May 14 04:24:21 PM PDT 24
Peak memory 205556 kb
Host smart-a8b48387-5b72-4358-8495-eadb68efe545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382002530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3382002530
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3920750179
Short name T917
Test name
Test status
Simulation time 8575396 ps
CPU time 0.85 seconds
Started May 14 04:24:03 PM PDT 24
Finished May 14 04:24:07 PM PDT 24
Peak memory 205620 kb
Host smart-98c0715f-8a49-498f-9caa-10d0b53f0ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920750179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3920750179
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.171240177
Short name T1046
Test name
Test status
Simulation time 12608308 ps
CPU time 0.69 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 205552 kb
Host smart-8e6f264a-afe2-448e-9ce8-7c8ca9dce23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171240177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.171240177
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3359577857
Short name T957
Test name
Test status
Simulation time 14809996 ps
CPU time 0.71 seconds
Started May 14 04:24:09 PM PDT 24
Finished May 14 04:24:16 PM PDT 24
Peak memory 205612 kb
Host smart-fc442e79-77a1-4a7e-b947-2676a8c53612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359577857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3359577857
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.929069929
Short name T926
Test name
Test status
Simulation time 8305209 ps
CPU time 0.79 seconds
Started May 14 04:24:08 PM PDT 24
Finished May 14 04:24:14 PM PDT 24
Peak memory 205632 kb
Host smart-81f1d34e-cc8e-42c1-9d73-aeed72a1dcca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929069929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.929069929
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2087370723
Short name T992
Test name
Test status
Simulation time 46843667 ps
CPU time 0.8 seconds
Started May 14 04:23:50 PM PDT 24
Finished May 14 04:23:54 PM PDT 24
Peak memory 205580 kb
Host smart-8d8d3cd2-f94e-455a-b7b0-0501219b7d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087370723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2087370723
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.999789460
Short name T1000
Test name
Test status
Simulation time 117916742 ps
CPU time 1.49 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:32 PM PDT 24
Peak memory 214204 kb
Host smart-b22af355-7c95-4184-bb6d-d2e61ed30e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999789460 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.999789460
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2589464897
Short name T1018
Test name
Test status
Simulation time 87254395 ps
CPU time 1.45 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205884 kb
Host smart-a922d227-6066-42f4-a114-54dfcb29b14b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589464897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2589464897
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.124769086
Short name T959
Test name
Test status
Simulation time 90045413 ps
CPU time 0.8 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 205524 kb
Host smart-23936900-4b1e-4fbc-b04a-0d8b90075686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124769086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.124769086
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1043379956
Short name T1060
Test name
Test status
Simulation time 365215039 ps
CPU time 2.34 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:33 PM PDT 24
Peak memory 214100 kb
Host smart-3dae1b7f-c482-4fca-b61f-c0dcb42c1d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043379956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1043379956
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4220006039
Short name T107
Test name
Test status
Simulation time 181119058 ps
CPU time 2.6 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 219124 kb
Host smart-995c9fec-f91d-4f31-a576-70f4416d6a23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220006039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4220006039
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1220663644
Short name T985
Test name
Test status
Simulation time 2137741436 ps
CPU time 15.58 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 214388 kb
Host smart-6149cb70-6cff-471e-b8be-5b45a9a96929
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220663644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1220663644
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2767402721
Short name T983
Test name
Test status
Simulation time 151694333 ps
CPU time 2.18 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:42 PM PDT 24
Peak memory 214076 kb
Host smart-56da00ed-ffd2-4cfc-9e31-d436a4b995a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767402721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2767402721
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2208048228
Short name T916
Test name
Test status
Simulation time 107359378 ps
CPU time 1.46 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:32 PM PDT 24
Peak memory 216624 kb
Host smart-adaca1d4-e213-4b2b-a31e-503f4327639b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208048228 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2208048228
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1184573433
Short name T965
Test name
Test status
Simulation time 23161279 ps
CPU time 0.96 seconds
Started May 14 04:23:35 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 205736 kb
Host smart-fc44db67-e4eb-467a-8b2e-69b005272b64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184573433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1184573433
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2319991814
Short name T1002
Test name
Test status
Simulation time 38173146 ps
CPU time 0.79 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 205576 kb
Host smart-21afa6ec-5ab0-44f0-ac67-8363850934c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319991814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2319991814
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.839096621
Short name T1024
Test name
Test status
Simulation time 54695127 ps
CPU time 1.78 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205832 kb
Host smart-44f012a0-8b79-4728-ba9c-38572fb0de58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839096621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.839096621
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1717000584
Short name T1053
Test name
Test status
Simulation time 64206123 ps
CPU time 2.19 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 214344 kb
Host smart-e8a3d94d-99b8-4d04-91c9-0d248bb9b91f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717000584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1717000584
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2885089406
Short name T986
Test name
Test status
Simulation time 417625341 ps
CPU time 8.59 seconds
Started May 14 04:23:26 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 214440 kb
Host smart-4d1557cb-49f4-46d7-8e47-4396715259ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885089406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2885089406
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3764720611
Short name T997
Test name
Test status
Simulation time 68876804 ps
CPU time 1.56 seconds
Started May 14 04:23:27 PM PDT 24
Finished May 14 04:23:34 PM PDT 24
Peak memory 214076 kb
Host smart-04473e4b-f2a6-417d-8785-9b7ac0bcb7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764720611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3764720611
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2435032939
Short name T1011
Test name
Test status
Simulation time 819793975 ps
CPU time 9.01 seconds
Started May 14 04:23:38 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214156 kb
Host smart-ebc2f811-6897-447d-b877-e90e5a93c94e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435032939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2435032939
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3338696551
Short name T1050
Test name
Test status
Simulation time 47692449 ps
CPU time 2.41 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 217836 kb
Host smart-3d48de5c-3224-40f1-ac5e-2a7220fe41d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338696551 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3338696551
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3912851265
Short name T1052
Test name
Test status
Simulation time 10185844 ps
CPU time 0.96 seconds
Started May 14 04:23:32 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 205784 kb
Host smart-7409d738-4a84-4f4d-baed-b1c1443ec8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912851265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3912851265
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4072812003
Short name T940
Test name
Test status
Simulation time 22852950 ps
CPU time 0.74 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205588 kb
Host smart-e92ebace-b2e7-4404-8073-8b83a2da0347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072812003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4072812003
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3375212604
Short name T939
Test name
Test status
Simulation time 443592844 ps
CPU time 2.17 seconds
Started May 14 04:23:33 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 205820 kb
Host smart-82440b58-b8fd-4307-8afb-e1a29fe32a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375212604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3375212604
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2904943230
Short name T988
Test name
Test status
Simulation time 314067506 ps
CPU time 2.27 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:37 PM PDT 24
Peak memory 214428 kb
Host smart-89d2b48a-f21b-430b-b9a1-a1b1ebb6955f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904943230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2904943230
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2546197511
Short name T109
Test name
Test status
Simulation time 3411135794 ps
CPU time 11.27 seconds
Started May 14 04:23:32 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 214460 kb
Host smart-3c3d1bf3-456e-4de7-b67b-f7ae4c85db46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546197511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2546197511
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2396475272
Short name T996
Test name
Test status
Simulation time 472729398 ps
CPU time 3.55 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 222304 kb
Host smart-23ab9d2d-7288-4c18-bfb0-194c4cdfecc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396475272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2396475272
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2712669906
Short name T372
Test name
Test status
Simulation time 351476511 ps
CPU time 2.83 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 214048 kb
Host smart-3376a1b7-ea94-41c0-b3e8-865b21958f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712669906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2712669906
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3317830964
Short name T938
Test name
Test status
Simulation time 117855838 ps
CPU time 1.72 seconds
Started May 14 04:23:48 PM PDT 24
Finished May 14 04:23:52 PM PDT 24
Peak memory 214128 kb
Host smart-5a251bc2-1cb0-4321-a480-e401d6578409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317830964 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3317830964
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1305253642
Short name T125
Test name
Test status
Simulation time 48252540 ps
CPU time 1.07 seconds
Started May 14 04:23:46 PM PDT 24
Finished May 14 04:23:49 PM PDT 24
Peak memory 205828 kb
Host smart-d56cd0de-1c5b-4b9b-85c5-79444ef5cdbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305253642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1305253642
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1060720330
Short name T941
Test name
Test status
Simulation time 15514053 ps
CPU time 0.74 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 205588 kb
Host smart-c4f79b13-84c8-4319-b685-869d5faa45d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060720330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1060720330
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1360293921
Short name T930
Test name
Test status
Simulation time 36044187 ps
CPU time 1.52 seconds
Started May 14 04:23:28 PM PDT 24
Finished May 14 04:23:35 PM PDT 24
Peak memory 205852 kb
Host smart-8dfaf218-84ea-4872-b8d3-b03d23e3ecda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360293921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1360293921
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2468756810
Short name T975
Test name
Test status
Simulation time 76505820 ps
CPU time 2.54 seconds
Started May 14 04:23:45 PM PDT 24
Finished May 14 04:23:51 PM PDT 24
Peak memory 214376 kb
Host smart-11b64596-d500-422b-a92f-52e6ea27e91f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468756810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2468756810
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1613854018
Short name T1069
Test name
Test status
Simulation time 207858558 ps
CPU time 7.06 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:43 PM PDT 24
Peak memory 220536 kb
Host smart-61608440-b88e-4c88-b4c6-e9deb6d9a066
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613854018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1613854018
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.557447148
Short name T969
Test name
Test status
Simulation time 39783434 ps
CPU time 2.37 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:37 PM PDT 24
Peak memory 214048 kb
Host smart-40528c7f-aad2-4b4f-9e69-06aa0e8fe450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557447148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.557447148
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3155630972
Short name T1019
Test name
Test status
Simulation time 61702963 ps
CPU time 1.63 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 214092 kb
Host smart-6ee85a72-fcaa-4c02-87fe-b9c4f08f70b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155630972 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3155630972
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1844390901
Short name T1063
Test name
Test status
Simulation time 48980502 ps
CPU time 1.19 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:38 PM PDT 24
Peak memory 205796 kb
Host smart-556ffdc4-69c6-4db8-8962-0be170221d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844390901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1844390901
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3993033685
Short name T987
Test name
Test status
Simulation time 15000747 ps
CPU time 0.77 seconds
Started May 14 04:23:36 PM PDT 24
Finished May 14 04:23:41 PM PDT 24
Peak memory 205520 kb
Host smart-3e56114e-e7e8-4e35-8c8d-b4fb8fa14d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993033685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3993033685
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2894958949
Short name T1032
Test name
Test status
Simulation time 24217851 ps
CPU time 1.4 seconds
Started May 14 04:23:46 PM PDT 24
Finished May 14 04:23:50 PM PDT 24
Peak memory 205848 kb
Host smart-fcc7fc13-7e69-4509-a4ee-8f3d6c5cbc9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894958949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2894958949
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3094111041
Short name T105
Test name
Test status
Simulation time 240534573 ps
CPU time 2.43 seconds
Started May 14 04:23:31 PM PDT 24
Finished May 14 04:23:39 PM PDT 24
Peak memory 214320 kb
Host smart-3ef449bd-d5ce-43d3-9915-7f9caaf2f106
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094111041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3094111041
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2152822639
Short name T1051
Test name
Test status
Simulation time 208696981 ps
CPU time 5.15 seconds
Started May 14 04:23:49 PM PDT 24
Finished May 14 04:23:56 PM PDT 24
Peak memory 220200 kb
Host smart-145f0ef6-e1c0-4acb-8b6f-2dab5776b176
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152822639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2152822639
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.184249950
Short name T1037
Test name
Test status
Simulation time 22237916 ps
CPU time 1.38 seconds
Started May 14 04:23:29 PM PDT 24
Finished May 14 04:23:36 PM PDT 24
Peak memory 213988 kb
Host smart-a11ca149-c37b-40b2-86aa-e05c19a39822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184249950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.184249950
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3376931152
Short name T160
Test name
Test status
Simulation time 133165721 ps
CPU time 4.93 seconds
Started May 14 04:23:30 PM PDT 24
Finished May 14 04:23:40 PM PDT 24
Peak memory 213960 kb
Host smart-f75caaa8-8fbc-47bf-b88d-8ebaef267b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376931152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3376931152
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1024528114
Short name T829
Test name
Test status
Simulation time 37948291 ps
CPU time 0.83 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:28 PM PDT 24
Peak memory 205988 kb
Host smart-801e912f-3851-4a79-886a-12e9df41b6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024528114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1024528114
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3967323794
Short name T122
Test name
Test status
Simulation time 2496652188 ps
CPU time 103.29 seconds
Started May 14 02:19:19 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 215192 kb
Host smart-c6cbd7db-235d-48e6-8338-281632eb175d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967323794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3967323794
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1778491552
Short name T791
Test name
Test status
Simulation time 84775690 ps
CPU time 3.61 seconds
Started May 14 02:19:28 PM PDT 24
Finished May 14 02:19:32 PM PDT 24
Peak memory 214320 kb
Host smart-e971ee8c-193a-471a-bf1f-ef0a4838a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778491552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1778491552
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2353467776
Short name T85
Test name
Test status
Simulation time 181775430 ps
CPU time 5.27 seconds
Started May 14 02:19:26 PM PDT 24
Finished May 14 02:19:32 PM PDT 24
Peak memory 208228 kb
Host smart-1dd27b66-65a9-494e-9471-6bf7c0e08f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353467776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2353467776
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2876571915
Short name T507
Test name
Test status
Simulation time 84964321 ps
CPU time 2.45 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:31 PM PDT 24
Peak memory 212716 kb
Host smart-f17c7b04-5b8b-45be-b851-99f5bc309699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876571915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2876571915
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1969320674
Short name T634
Test name
Test status
Simulation time 68196897 ps
CPU time 2.95 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:30 PM PDT 24
Peak memory 220192 kb
Host smart-27511ad3-c063-4860-9f3d-0ea12741841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969320674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1969320674
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1928178882
Short name T670
Test name
Test status
Simulation time 143755484 ps
CPU time 2.55 seconds
Started May 14 02:19:18 PM PDT 24
Finished May 14 02:19:22 PM PDT 24
Peak memory 209984 kb
Host smart-1a6e60ec-944a-4fe3-967c-650b0bf01fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928178882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1928178882
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2417896897
Short name T10
Test name
Test status
Simulation time 483745661 ps
CPU time 7.02 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:35 PM PDT 24
Peak memory 233452 kb
Host smart-91b49739-14a5-448d-8f6c-4dfecb6b270a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417896897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2417896897
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2273721234
Short name T848
Test name
Test status
Simulation time 209936128 ps
CPU time 2.85 seconds
Started May 14 02:19:18 PM PDT 24
Finished May 14 02:19:21 PM PDT 24
Peak memory 208892 kb
Host smart-c4d0bd7a-fcf3-43e6-81ad-52df9a5949e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273721234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2273721234
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3161617715
Short name T630
Test name
Test status
Simulation time 518709546 ps
CPU time 4.47 seconds
Started May 14 02:19:18 PM PDT 24
Finished May 14 02:19:23 PM PDT 24
Peak memory 206928 kb
Host smart-a3ada950-78de-43ee-b41e-3ddaa324a67d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161617715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3161617715
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1167468204
Short name T750
Test name
Test status
Simulation time 138263961 ps
CPU time 2.84 seconds
Started May 14 02:19:17 PM PDT 24
Finished May 14 02:19:20 PM PDT 24
Peak memory 208528 kb
Host smart-1c37f17b-9854-48e4-9b00-9360ff61568c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167468204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1167468204
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.186462988
Short name T386
Test name
Test status
Simulation time 179049723 ps
CPU time 2.48 seconds
Started May 14 02:19:17 PM PDT 24
Finished May 14 02:19:20 PM PDT 24
Peak memory 208684 kb
Host smart-f35c3164-0e3c-4c75-a01d-b6475ca12283
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186462988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.186462988
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3471300582
Short name T163
Test name
Test status
Simulation time 150582734 ps
CPU time 4.88 seconds
Started May 14 02:19:26 PM PDT 24
Finished May 14 02:19:31 PM PDT 24
Peak memory 218148 kb
Host smart-a94b2973-65cf-4246-a933-f81639b70086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471300582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3471300582
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.764541142
Short name T740
Test name
Test status
Simulation time 2976016887 ps
CPU time 28.15 seconds
Started May 14 02:19:17 PM PDT 24
Finished May 14 02:19:46 PM PDT 24
Peak memory 208516 kb
Host smart-2783156a-446d-49be-b783-f5dc5bc3a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764541142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.764541142
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4169587425
Short name T199
Test name
Test status
Simulation time 4510944124 ps
CPU time 47.35 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:20:15 PM PDT 24
Peak memory 216368 kb
Host smart-0fde2ed5-f1b4-4653-b46a-d3f4a3b9cefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169587425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4169587425
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1787723764
Short name T563
Test name
Test status
Simulation time 45082323 ps
CPU time 1.53 seconds
Started May 14 02:19:25 PM PDT 24
Finished May 14 02:19:27 PM PDT 24
Peak memory 209624 kb
Host smart-47957738-ba4e-40fb-861f-954cc623b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787723764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1787723764
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4015952368
Short name T541
Test name
Test status
Simulation time 206558372 ps
CPU time 0.82 seconds
Started May 14 02:19:45 PM PDT 24
Finished May 14 02:19:47 PM PDT 24
Peak memory 206028 kb
Host smart-3206a88d-4d78-4d66-be0a-13e09bda3f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015952368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4015952368
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3957181160
Short name T795
Test name
Test status
Simulation time 62071380 ps
CPU time 2.73 seconds
Started May 14 02:19:36 PM PDT 24
Finished May 14 02:19:40 PM PDT 24
Peak memory 214332 kb
Host smart-ad5f2b74-a097-485e-827a-8da204558384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957181160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3957181160
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3518721033
Short name T831
Test name
Test status
Simulation time 344707749 ps
CPU time 3.03 seconds
Started May 14 02:19:37 PM PDT 24
Finished May 14 02:19:41 PM PDT 24
Peak memory 218384 kb
Host smart-dc458f4b-977a-49f5-9c32-f4acc00dc1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518721033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3518721033
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4012245632
Short name T261
Test name
Test status
Simulation time 296184642 ps
CPU time 3.5 seconds
Started May 14 02:19:38 PM PDT 24
Finished May 14 02:19:42 PM PDT 24
Peak memory 214272 kb
Host smart-2dea3b94-8194-4bdc-a95f-cdd8b709544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012245632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4012245632
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1869320541
Short name T782
Test name
Test status
Simulation time 272708189 ps
CPU time 1.85 seconds
Started May 14 02:19:35 PM PDT 24
Finished May 14 02:19:38 PM PDT 24
Peak memory 220508 kb
Host smart-017e21da-7291-40da-b201-f4e023f1e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869320541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1869320541
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.587504211
Short name T588
Test name
Test status
Simulation time 194824624 ps
CPU time 4.03 seconds
Started May 14 02:19:36 PM PDT 24
Finished May 14 02:19:41 PM PDT 24
Peak memory 207588 kb
Host smart-6adf4a4a-1517-43a2-9e26-95952559249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587504211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.587504211
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1295836091
Short name T812
Test name
Test status
Simulation time 1227237768 ps
CPU time 10.1 seconds
Started May 14 02:19:40 PM PDT 24
Finished May 14 02:19:50 PM PDT 24
Peak memory 208732 kb
Host smart-c2a23cb1-e67c-4272-97d4-86259963ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295836091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1295836091
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1182956633
Short name T11
Test name
Test status
Simulation time 1461631342 ps
CPU time 10.7 seconds
Started May 14 02:19:44 PM PDT 24
Finished May 14 02:19:56 PM PDT 24
Peak memory 234728 kb
Host smart-569f2d57-654a-467c-95d4-e2b3a0b88e54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182956633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1182956633
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3945015483
Short name T652
Test name
Test status
Simulation time 143403309 ps
CPU time 6.04 seconds
Started May 14 02:19:26 PM PDT 24
Finished May 14 02:19:32 PM PDT 24
Peak memory 206916 kb
Host smart-bed47a97-762f-40c5-adf2-8c171804f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945015483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3945015483
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3476647539
Short name T520
Test name
Test status
Simulation time 598715963 ps
CPU time 7.48 seconds
Started May 14 02:19:35 PM PDT 24
Finished May 14 02:19:43 PM PDT 24
Peak memory 208132 kb
Host smart-cec04b1f-2279-4b64-8fe6-de22d4bf58eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476647539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3476647539
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3846372276
Short name T527
Test name
Test status
Simulation time 507177982 ps
CPU time 3.79 seconds
Started May 14 02:19:26 PM PDT 24
Finished May 14 02:19:30 PM PDT 24
Peak memory 208600 kb
Host smart-3ff739ec-ff6c-4e05-a48c-22e7a74ced23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846372276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3846372276
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3491257434
Short name T688
Test name
Test status
Simulation time 781589091 ps
CPU time 2.95 seconds
Started May 14 02:19:41 PM PDT 24
Finished May 14 02:19:45 PM PDT 24
Peak memory 208032 kb
Host smart-4530df7e-aebd-44b7-b0d8-76c2812a4269
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491257434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3491257434
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3650567724
Short name T422
Test name
Test status
Simulation time 226971799 ps
CPU time 3.72 seconds
Started May 14 02:19:38 PM PDT 24
Finished May 14 02:19:42 PM PDT 24
Peak memory 215900 kb
Host smart-75de04c9-ee03-4603-b5f8-1df2157b969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650567724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3650567724
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.200042125
Short name T728
Test name
Test status
Simulation time 318023041 ps
CPU time 3.21 seconds
Started May 14 02:19:27 PM PDT 24
Finished May 14 02:19:31 PM PDT 24
Peak memory 208296 kb
Host smart-478e6f40-fc68-447f-9785-775507c5bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200042125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.200042125
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1407093809
Short name T194
Test name
Test status
Simulation time 11964203305 ps
CPU time 144.43 seconds
Started May 14 02:19:47 PM PDT 24
Finished May 14 02:22:12 PM PDT 24
Peak memory 216544 kb
Host smart-7feb49ac-a16c-4f14-bb7c-cf77ae5ad0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407093809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1407093809
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3990090314
Short name T796
Test name
Test status
Simulation time 415151632 ps
CPU time 6.42 seconds
Started May 14 02:19:39 PM PDT 24
Finished May 14 02:19:45 PM PDT 24
Peak memory 218208 kb
Host smart-5a226143-13e1-4896-bb1c-c2ef1bfb3b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990090314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3990090314
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4033153163
Short name T366
Test name
Test status
Simulation time 350731970 ps
CPU time 9.61 seconds
Started May 14 02:19:44 PM PDT 24
Finished May 14 02:19:55 PM PDT 24
Peak memory 211008 kb
Host smart-826ee78b-e5a2-402e-9f06-a0ce6e054160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033153163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4033153163
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1051925649
Short name T374
Test name
Test status
Simulation time 34447028 ps
CPU time 2.71 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:06 PM PDT 24
Peak memory 214420 kb
Host smart-09b33203-b68a-472e-b6d7-1e574c4f69c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051925649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1051925649
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1368667621
Short name T574
Test name
Test status
Simulation time 72626085 ps
CPU time 3.65 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:06 PM PDT 24
Peak memory 209924 kb
Host smart-9dc24cc2-7eb6-42cf-979d-61fe584fc7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368667621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1368667621
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2891353408
Short name T319
Test name
Test status
Simulation time 871147043 ps
CPU time 6.85 seconds
Started May 14 02:21:03 PM PDT 24
Finished May 14 02:21:11 PM PDT 24
Peak memory 214324 kb
Host smart-21acb44f-a399-45ea-8881-adf9bf394f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891353408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2891353408
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1134545657
Short name T604
Test name
Test status
Simulation time 61599705 ps
CPU time 3.21 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:04 PM PDT 24
Peak memory 214588 kb
Host smart-d0570758-feaf-43b4-a388-47a7550a23b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134545657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1134545657
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2660218962
Short name T603
Test name
Test status
Simulation time 231692172 ps
CPU time 5.47 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:08 PM PDT 24
Peak memory 209516 kb
Host smart-4dba0201-ec4e-4431-be25-db5a0f6d6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660218962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2660218962
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3914812666
Short name T599
Test name
Test status
Simulation time 109013272 ps
CPU time 4.53 seconds
Started May 14 02:20:59 PM PDT 24
Finished May 14 02:21:04 PM PDT 24
Peak memory 214324 kb
Host smart-2a16ac40-d3d2-4a79-824a-bc6e65e64cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914812666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3914812666
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2876109048
Short name T178
Test name
Test status
Simulation time 451342494 ps
CPU time 6.51 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:08 PM PDT 24
Peak memory 206904 kb
Host smart-fb3724f5-51e6-4990-9909-99d649dd71d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876109048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2876109048
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.636587994
Short name T625
Test name
Test status
Simulation time 3289622489 ps
CPU time 47.62 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 209044 kb
Host smart-939a21eb-352a-4ea9-9997-571d34fdfd19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636587994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.636587994
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.589079252
Short name T849
Test name
Test status
Simulation time 90676126 ps
CPU time 3.26 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:05 PM PDT 24
Peak memory 206908 kb
Host smart-fc624997-c008-4231-817a-b89662775171
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589079252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.589079252
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3892048810
Short name T565
Test name
Test status
Simulation time 240779460 ps
CPU time 4.92 seconds
Started May 14 02:21:03 PM PDT 24
Finished May 14 02:21:09 PM PDT 24
Peak memory 208588 kb
Host smart-75f64d59-b0eb-40cb-8fae-49b786a2374c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892048810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3892048810
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2663959452
Short name T902
Test name
Test status
Simulation time 119588584 ps
CPU time 3.59 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:05 PM PDT 24
Peak memory 209864 kb
Host smart-2759c3ad-984f-47ad-bddc-c9279d1e3227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663959452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2663959452
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2530350242
Short name T436
Test name
Test status
Simulation time 38408442 ps
CPU time 1.74 seconds
Started May 14 02:21:02 PM PDT 24
Finished May 14 02:21:05 PM PDT 24
Peak memory 206848 kb
Host smart-eeedf810-dd5e-4f10-b6eb-11dcca5ff7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530350242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2530350242
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.748078025
Short name T388
Test name
Test status
Simulation time 1437295182 ps
CPU time 11.44 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:14 PM PDT 24
Peak memory 214308 kb
Host smart-6530d52e-d32c-4d32-963e-0c15a784f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748078025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.748078025
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.699523074
Short name T539
Test name
Test status
Simulation time 62841385 ps
CPU time 1.99 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 209888 kb
Host smart-24e33ffc-d522-43c6-b2a9-6e2e4a588673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699523074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.699523074
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2611804248
Short name T97
Test name
Test status
Simulation time 11369003 ps
CPU time 0.78 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:13 PM PDT 24
Peak memory 205904 kb
Host smart-1e072e3a-f096-4e30-bba7-70ff7f093055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611804248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2611804248
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3162879607
Short name T106
Test name
Test status
Simulation time 812957526 ps
CPU time 43.41 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:54 PM PDT 24
Peak memory 215212 kb
Host smart-0585f666-9e35-408d-a364-5302d0cdc33e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162879607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3162879607
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2315100501
Short name T624
Test name
Test status
Simulation time 90643268 ps
CPU time 3.27 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:16 PM PDT 24
Peak memory 210024 kb
Host smart-1d8ad2b2-ddee-45a3-9334-15fe1e8aa2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315100501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2315100501
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.735114048
Short name T93
Test name
Test status
Simulation time 121408776 ps
CPU time 5.61 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:17 PM PDT 24
Peak memory 214248 kb
Host smart-46acf201-fa84-47b1-b5b0-1bc29b4e7b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735114048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.735114048
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2130724737
Short name T660
Test name
Test status
Simulation time 144855448 ps
CPU time 3.38 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:16 PM PDT 24
Peak memory 210052 kb
Host smart-011512e7-0e6d-49d0-8bbc-12bf748803b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130724737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2130724737
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1369185627
Short name T275
Test name
Test status
Simulation time 468054005 ps
CPU time 5 seconds
Started May 14 02:21:12 PM PDT 24
Finished May 14 02:21:18 PM PDT 24
Peak memory 210508 kb
Host smart-21593389-a4c8-4fc9-8070-21cbb40546d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369185627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1369185627
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3072937690
Short name T842
Test name
Test status
Simulation time 293297587 ps
CPU time 5.17 seconds
Started May 14 02:21:03 PM PDT 24
Finished May 14 02:21:09 PM PDT 24
Peak memory 208396 kb
Host smart-82c475e2-c42a-46d1-a0fd-b8b2f8fc9cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072937690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3072937690
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.318947942
Short name T295
Test name
Test status
Simulation time 94315556 ps
CPU time 2.74 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:04 PM PDT 24
Peak memory 208512 kb
Host smart-97ee6435-18a6-4ac6-b0f0-fe5efd492ade
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318947942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.318947942
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4063925896
Short name T2
Test name
Test status
Simulation time 2035360058 ps
CPU time 14.57 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:16 PM PDT 24
Peak memory 208800 kb
Host smart-24fb9d6e-4d1e-433a-8ab6-069881d07e8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063925896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4063925896
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2431365182
Short name T686
Test name
Test status
Simulation time 98062206 ps
CPU time 4.15 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:15 PM PDT 24
Peak memory 209176 kb
Host smart-2a709244-219c-4608-85a9-3fdccc8bfe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431365182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2431365182
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3863203476
Short name T183
Test name
Test status
Simulation time 383523048 ps
CPU time 4.58 seconds
Started May 14 02:21:02 PM PDT 24
Finished May 14 02:21:08 PM PDT 24
Peak memory 207996 kb
Host smart-50976afc-493d-410a-b711-f44aab36021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863203476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3863203476
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1826592770
Short name T885
Test name
Test status
Simulation time 4716590962 ps
CPU time 28.31 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:39 PM PDT 24
Peak memory 215672 kb
Host smart-7891ef60-7668-4b6d-928c-2f5ae8a69798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826592770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1826592770
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3419207769
Short name T598
Test name
Test status
Simulation time 770774125 ps
CPU time 5.38 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:17 PM PDT 24
Peak memory 214332 kb
Host smart-008dfdcb-c486-4a76-83a7-5e5cc33b4bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419207769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3419207769
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1783988668
Short name T65
Test name
Test status
Simulation time 66868677 ps
CPU time 2.82 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:16 PM PDT 24
Peak memory 210148 kb
Host smart-d8e3c5ab-86a8-4946-9117-e150eacd43c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783988668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1783988668
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.864914012
Short name T431
Test name
Test status
Simulation time 42028970 ps
CPU time 0.8 seconds
Started May 14 02:21:23 PM PDT 24
Finished May 14 02:21:24 PM PDT 24
Peak memory 205976 kb
Host smart-63dec299-640d-41af-ae08-c4731063a944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864914012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.864914012
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3949328296
Short name T492
Test name
Test status
Simulation time 222847181 ps
CPU time 2.71 seconds
Started May 14 02:21:27 PM PDT 24
Finished May 14 02:21:31 PM PDT 24
Peak memory 209716 kb
Host smart-722d037e-baf7-403a-ba59-b2b7dfa61637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949328296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3949328296
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1298316444
Short name T540
Test name
Test status
Simulation time 66530662 ps
CPU time 4.76 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:30 PM PDT 24
Peak memory 214376 kb
Host smart-7d7d379a-bdea-44a5-adfb-aff144a87142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298316444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1298316444
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1522265674
Short name T864
Test name
Test status
Simulation time 153726661 ps
CPU time 4.2 seconds
Started May 14 02:21:27 PM PDT 24
Finished May 14 02:21:32 PM PDT 24
Peak memory 220520 kb
Host smart-919a9dc2-5bb3-44c6-bf24-aa13df1714d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522265674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1522265674
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2985506658
Short name T631
Test name
Test status
Simulation time 368442232 ps
CPU time 4.19 seconds
Started May 14 02:21:12 PM PDT 24
Finished May 14 02:21:18 PM PDT 24
Peak memory 208040 kb
Host smart-fe2f1b94-9f21-4ae2-a9c6-c7278543744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985506658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2985506658
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1244088602
Short name T446
Test name
Test status
Simulation time 588976526 ps
CPU time 4.53 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:17 PM PDT 24
Peak memory 206912 kb
Host smart-6955a527-a927-40c3-9b9c-2c71120ac934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244088602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1244088602
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2563133984
Short name T383
Test name
Test status
Simulation time 211442217 ps
CPU time 2.98 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:15 PM PDT 24
Peak memory 206896 kb
Host smart-5de04291-6939-4801-8183-50dd0a4812c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563133984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2563133984
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1216637523
Short name T188
Test name
Test status
Simulation time 156722763 ps
CPU time 4.76 seconds
Started May 14 02:21:11 PM PDT 24
Finished May 14 02:21:17 PM PDT 24
Peak memory 208052 kb
Host smart-3ddaf378-bb97-4270-8a5f-6ecdb3198318
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216637523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1216637523
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1943895462
Short name T832
Test name
Test status
Simulation time 144434959 ps
CPU time 2.94 seconds
Started May 14 02:21:10 PM PDT 24
Finished May 14 02:21:13 PM PDT 24
Peak memory 206720 kb
Host smart-8d9f3bd4-7193-4bc0-be85-95db3a09830e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943895462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1943895462
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1195160656
Short name T359
Test name
Test status
Simulation time 203210232 ps
CPU time 3.44 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:28 PM PDT 24
Peak memory 208748 kb
Host smart-3dc27a52-1f54-4ec6-8175-4f251b026c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195160656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1195160656
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3377735491
Short name T14
Test name
Test status
Simulation time 322228901 ps
CPU time 3.83 seconds
Started May 14 02:21:13 PM PDT 24
Finished May 14 02:21:18 PM PDT 24
Peak memory 208100 kb
Host smart-6986492d-983a-4bb6-b548-8ababe031ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377735491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3377735491
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3849466349
Short name T694
Test name
Test status
Simulation time 1755598519 ps
CPU time 26.1 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:52 PM PDT 24
Peak memory 214264 kb
Host smart-a51dbe75-13db-42c2-ac81-403db09d121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849466349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3849466349
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3886226876
Short name T701
Test name
Test status
Simulation time 306998950 ps
CPU time 9.63 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:35 PM PDT 24
Peak memory 211092 kb
Host smart-ed813393-3b27-42a8-9dbe-267abc90bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886226876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3886226876
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3902926812
Short name T707
Test name
Test status
Simulation time 11717608 ps
CPU time 0.79 seconds
Started May 14 02:21:28 PM PDT 24
Finished May 14 02:21:29 PM PDT 24
Peak memory 205984 kb
Host smart-d04c472a-b0a0-4c3c-b2b6-e908f04593ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902926812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3902926812
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3443040504
Short name T398
Test name
Test status
Simulation time 2353122582 ps
CPU time 113.76 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:23:18 PM PDT 24
Peak memory 214432 kb
Host smart-7e4706cd-ec89-4c43-8323-71561a92bdad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443040504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3443040504
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.458885218
Short name T555
Test name
Test status
Simulation time 36932678 ps
CPU time 2.1 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:29 PM PDT 24
Peak memory 207180 kb
Host smart-ff287c42-5c0d-4bba-866c-fa524ecb027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458885218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.458885218
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3426145735
Short name T329
Test name
Test status
Simulation time 585685338 ps
CPU time 6.22 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:32 PM PDT 24
Peak memory 222576 kb
Host smart-f6273ca7-0acc-44d1-b003-bd9a4b05f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426145735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3426145735
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2665429379
Short name T207
Test name
Test status
Simulation time 1396914801 ps
CPU time 21.53 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:46 PM PDT 24
Peak memory 222508 kb
Host smart-43370770-d11e-46d1-8ac2-fe95664c0d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665429379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2665429379
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2272020442
Short name T259
Test name
Test status
Simulation time 689189791 ps
CPU time 4.03 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:30 PM PDT 24
Peak memory 208224 kb
Host smart-2696b807-73ab-49f8-9cae-16c54f9738c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272020442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2272020442
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1703211181
Short name T715
Test name
Test status
Simulation time 57884904 ps
CPU time 2.95 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:29 PM PDT 24
Peak memory 208812 kb
Host smart-2c21c357-ac48-4a5a-b112-adf3e5ab528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703211181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1703211181
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1468404268
Short name T879
Test name
Test status
Simulation time 71096494 ps
CPU time 1.76 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:27 PM PDT 24
Peak memory 206964 kb
Host smart-1b8b00a0-a7d6-4ade-bb59-48e2176f6584
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468404268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1468404268
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.635592328
Short name T335
Test name
Test status
Simulation time 183581151 ps
CPU time 5.95 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:32 PM PDT 24
Peak memory 208644 kb
Host smart-eff92ce5-f1bc-4a8b-90fa-4eca885fed51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635592328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.635592328
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1261719070
Short name T593
Test name
Test status
Simulation time 42876325 ps
CPU time 2.48 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:28 PM PDT 24
Peak memory 207392 kb
Host smart-7ec274c1-52a7-402f-865d-ff87916f61e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261719070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1261719070
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2502351177
Short name T548
Test name
Test status
Simulation time 345487196 ps
CPU time 4.79 seconds
Started May 14 02:21:28 PM PDT 24
Finished May 14 02:21:33 PM PDT 24
Peak memory 209572 kb
Host smart-25a595a7-b19a-4082-9675-8cec72a3d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502351177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2502351177
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.151411349
Short name T478
Test name
Test status
Simulation time 29963692 ps
CPU time 2.13 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:28 PM PDT 24
Peak memory 206804 kb
Host smart-9d09357d-e621-4590-b598-598f482c92f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151411349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.151411349
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4053845780
Short name T233
Test name
Test status
Simulation time 207813378 ps
CPU time 2.72 seconds
Started May 14 02:21:26 PM PDT 24
Finished May 14 02:21:30 PM PDT 24
Peak memory 218568 kb
Host smart-bc9cec37-7c98-4a93-ae20-167ea84e2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053845780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4053845780
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2152897099
Short name T572
Test name
Test status
Simulation time 135768545 ps
CPU time 1.82 seconds
Started May 14 02:21:24 PM PDT 24
Finished May 14 02:21:26 PM PDT 24
Peak memory 208808 kb
Host smart-9649f23e-b449-4e4e-a7eb-ef7e0d4ac797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152897099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2152897099
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3574036591
Short name T737
Test name
Test status
Simulation time 21021775 ps
CPU time 0.74 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:41 PM PDT 24
Peak memory 205924 kb
Host smart-353a0e1f-f418-4467-81ca-db7c2c20e46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574036591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3574036591
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2253993756
Short name T871
Test name
Test status
Simulation time 51508615 ps
CPU time 3.85 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:43 PM PDT 24
Peak memory 214332 kb
Host smart-f4241798-98cb-4004-a080-a9503f340795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253993756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2253993756
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.604981185
Short name T490
Test name
Test status
Simulation time 77265813 ps
CPU time 3.24 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:42 PM PDT 24
Peak memory 221032 kb
Host smart-b2b8e7ea-0e33-42e8-a6bd-28ed0f6f1c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604981185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.604981185
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2550152006
Short name T258
Test name
Test status
Simulation time 5739303098 ps
CPU time 37.68 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:22:17 PM PDT 24
Peak memory 214304 kb
Host smart-71a56789-517a-4ca6-bc3d-f07b2b513550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550152006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2550152006
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.124751389
Short name T530
Test name
Test status
Simulation time 38689030 ps
CPU time 2.16 seconds
Started May 14 02:21:40 PM PDT 24
Finished May 14 02:21:43 PM PDT 24
Peak memory 214180 kb
Host smart-07698627-29f4-42c5-bdab-a55628977553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124751389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.124751389
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4024619095
Short name T62
Test name
Test status
Simulation time 229219477 ps
CPU time 3.99 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 218964 kb
Host smart-46a6517e-985c-497c-9e50-d47ac3bdef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024619095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4024619095
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4140992899
Short name T537
Test name
Test status
Simulation time 371869110 ps
CPU time 4.53 seconds
Started May 14 02:21:40 PM PDT 24
Finished May 14 02:21:46 PM PDT 24
Peak memory 207612 kb
Host smart-768cdd9f-edf6-4094-b263-ac7521dcbcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140992899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4140992899
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.17210957
Short name T904
Test name
Test status
Simulation time 68096248 ps
CPU time 2.93 seconds
Started May 14 02:21:41 PM PDT 24
Finished May 14 02:21:45 PM PDT 24
Peak memory 208192 kb
Host smart-691c16fa-767b-4f68-8a2c-1e150099c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17210957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.17210957
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3143331613
Short name T384
Test name
Test status
Simulation time 109555998 ps
CPU time 2.88 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:43 PM PDT 24
Peak memory 206900 kb
Host smart-81ae731d-e806-4ada-9972-aa179eafd7db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143331613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3143331613
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2273540311
Short name T439
Test name
Test status
Simulation time 248120789 ps
CPU time 6.86 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:48 PM PDT 24
Peak memory 208192 kb
Host smart-c3a80b7e-44de-4299-a62d-1ccb30f32f59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273540311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2273540311
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.355261773
Short name T851
Test name
Test status
Simulation time 81454001 ps
CPU time 1.9 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:40 PM PDT 24
Peak memory 206988 kb
Host smart-6e780177-88eb-42aa-91eb-960b2db207af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355261773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.355261773
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.323252709
Short name T837
Test name
Test status
Simulation time 119459647 ps
CPU time 2.51 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:41 PM PDT 24
Peak memory 209396 kb
Host smart-4f89e40e-3b87-4a9a-9abe-dea6cad81d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323252709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.323252709
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3645267477
Short name T491
Test name
Test status
Simulation time 514616221 ps
CPU time 9.28 seconds
Started May 14 02:21:25 PM PDT 24
Finished May 14 02:21:36 PM PDT 24
Peak memory 208808 kb
Host smart-bc85e8ef-cd68-4ec2-b7b4-481b88cefc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645267477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3645267477
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1486012157
Short name T296
Test name
Test status
Simulation time 3032433720 ps
CPU time 18.41 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:59 PM PDT 24
Peak memory 220904 kb
Host smart-c365b47e-da2a-4ce3-9b5f-1e1b7247dc53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486012157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1486012157
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3473266129
Short name T340
Test name
Test status
Simulation time 2309695250 ps
CPU time 17.07 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:57 PM PDT 24
Peak memory 207812 kb
Host smart-484d62dc-3d0f-4a14-a9d7-bd625a46f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473266129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3473266129
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.636079784
Short name T419
Test name
Test status
Simulation time 18207783 ps
CPU time 0.76 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:40 PM PDT 24
Peak memory 205972 kb
Host smart-d5ad0187-99df-4be2-a5f5-2fe824619eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636079784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.636079784
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.203339110
Short name T404
Test name
Test status
Simulation time 85776984 ps
CPU time 3.85 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:45 PM PDT 24
Peak memory 215312 kb
Host smart-8fe0a858-67cb-405d-8aa7-e40bb35425a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203339110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.203339110
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3593049890
Short name T582
Test name
Test status
Simulation time 489059843 ps
CPU time 2.77 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 210356 kb
Host smart-6fae810a-5fd4-4c69-9d99-c0030a0f1f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593049890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3593049890
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2300419225
Short name T708
Test name
Test status
Simulation time 42426257 ps
CPU time 1.84 seconds
Started May 14 02:21:36 PM PDT 24
Finished May 14 02:21:39 PM PDT 24
Peak memory 218284 kb
Host smart-228edfaf-669a-4df3-95e6-01b83927e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300419225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2300419225
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.269103364
Short name T225
Test name
Test status
Simulation time 54083762 ps
CPU time 2.93 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 214356 kb
Host smart-5fa38d55-affd-47e0-8eb7-be7bb371df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269103364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.269103364
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1931428582
Short name T626
Test name
Test status
Simulation time 617611349 ps
CPU time 6.89 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:47 PM PDT 24
Peak memory 214296 kb
Host smart-5cae6c35-3789-4eed-96b4-cf5c6d4858a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931428582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1931428582
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3803339997
Short name T330
Test name
Test status
Simulation time 353139988 ps
CPU time 4.77 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 218268 kb
Host smart-8b88de4e-0376-442d-939e-670cfedad4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803339997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3803339997
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1526576218
Short name T580
Test name
Test status
Simulation time 116181820 ps
CPU time 3.77 seconds
Started May 14 02:21:41 PM PDT 24
Finished May 14 02:21:46 PM PDT 24
Peak memory 208936 kb
Host smart-2ed1276c-f63d-4da1-89ca-5a64f48f3458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526576218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1526576218
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4132422021
Short name T730
Test name
Test status
Simulation time 1359722573 ps
CPU time 7.53 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:47 PM PDT 24
Peak memory 208196 kb
Host smart-820e42f5-86d3-4069-bb85-e6c6cf4a3307
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132422021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4132422021
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.875928863
Short name T654
Test name
Test status
Simulation time 340425215 ps
CPU time 2.63 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:41 PM PDT 24
Peak memory 207400 kb
Host smart-ca310033-8437-4d1d-b369-61655f33859b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875928863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.875928863
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3440203541
Short name T889
Test name
Test status
Simulation time 455233507 ps
CPU time 3.72 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 208852 kb
Host smart-08280ff3-74ad-436e-9aee-f9a070b44a4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440203541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3440203541
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2190386343
Short name T545
Test name
Test status
Simulation time 2183936574 ps
CPU time 14.03 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 208640 kb
Host smart-419cf81e-5f57-4f49-bcdf-48e95e3688e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190386343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2190386343
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3282272200
Short name T460
Test name
Test status
Simulation time 181121162 ps
CPU time 2.63 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:40 PM PDT 24
Peak memory 206072 kb
Host smart-15671471-6c2c-4431-83ef-20a9e33e3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282272200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3282272200
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.212653746
Short name T81
Test name
Test status
Simulation time 963441749 ps
CPU time 15.11 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 220416 kb
Host smart-574faeff-e3d0-4eb2-96e5-d37ab7806608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212653746 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.212653746
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.103148998
Short name T581
Test name
Test status
Simulation time 121876120 ps
CPU time 5.47 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:47 PM PDT 24
Peak memory 214472 kb
Host smart-3ea14a49-288b-422c-b06d-7182ecbc8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103148998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.103148998
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3848010966
Short name T877
Test name
Test status
Simulation time 47419829 ps
CPU time 1.8 seconds
Started May 14 02:21:40 PM PDT 24
Finished May 14 02:21:43 PM PDT 24
Peak memory 209884 kb
Host smart-e4f7e4be-bf6d-4e1a-93de-0a25c1141ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848010966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3848010966
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3319557278
Short name T428
Test name
Test status
Simulation time 85320293 ps
CPU time 0.75 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 205944 kb
Host smart-c8a24ccb-1bce-4792-80f2-2db119c48220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319557278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3319557278
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1965468560
Short name T35
Test name
Test status
Simulation time 214694245 ps
CPU time 2.5 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:52 PM PDT 24
Peak memory 218308 kb
Host smart-396a3aed-e3cc-43d7-a6a1-96cd5aae41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965468560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1965468560
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1243017415
Short name T798
Test name
Test status
Simulation time 47807791 ps
CPU time 2.41 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:49 PM PDT 24
Peak memory 210404 kb
Host smart-6dd6e9ae-c4f9-49e0-aa70-baeb67b1c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243017415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1243017415
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.719293538
Short name T777
Test name
Test status
Simulation time 241996735 ps
CPU time 5.29 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:21:51 PM PDT 24
Peak memory 214308 kb
Host smart-b96d8e43-85dc-4ec1-b942-6b5e9ee438c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719293538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.719293538
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_random.2943289872
Short name T685
Test name
Test status
Simulation time 1050895960 ps
CPU time 3.84 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 214616 kb
Host smart-2f67cb38-ba8b-4669-ae9d-0e7d9fe6e925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943289872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2943289872
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1171553861
Short name T485
Test name
Test status
Simulation time 67764332 ps
CPU time 2.98 seconds
Started May 14 02:21:39 PM PDT 24
Finished May 14 02:21:44 PM PDT 24
Peak memory 208404 kb
Host smart-a6555560-b738-457f-8437-e68cd112d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171553861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1171553861
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4267148643
Short name T852
Test name
Test status
Simulation time 297503152 ps
CPU time 2.98 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:42 PM PDT 24
Peak memory 206904 kb
Host smart-55569898-9ecc-45e3-9ca9-690bca8cdddf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267148643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4267148643
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.98062083
Short name T187
Test name
Test status
Simulation time 180807700 ps
CPU time 5.59 seconds
Started May 14 02:21:38 PM PDT 24
Finished May 14 02:21:46 PM PDT 24
Peak memory 208948 kb
Host smart-4f330947-df21-4398-977b-0ffbc9c03810
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98062083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.98062083
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2605315247
Short name T390
Test name
Test status
Simulation time 940869176 ps
CPU time 4.56 seconds
Started May 14 02:21:37 PM PDT 24
Finished May 14 02:21:42 PM PDT 24
Peak memory 208160 kb
Host smart-b292b6de-3ef7-441b-9d45-400b32bdae60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605315247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2605315247
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1568589648
Short name T254
Test name
Test status
Simulation time 761506070 ps
CPU time 3.76 seconds
Started May 14 02:21:51 PM PDT 24
Finished May 14 02:21:56 PM PDT 24
Peak memory 209852 kb
Host smart-34837fa9-413d-4523-a4ba-10aa10949252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568589648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1568589648
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.161867240
Short name T174
Test name
Test status
Simulation time 200841713 ps
CPU time 4.52 seconds
Started May 14 02:21:36 PM PDT 24
Finished May 14 02:21:42 PM PDT 24
Peak memory 208144 kb
Host smart-7efb44fa-dede-43cc-ad13-d2958acefb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161867240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.161867240
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1971715770
Short name T60
Test name
Test status
Simulation time 700907386 ps
CPU time 5.79 seconds
Started May 14 02:21:51 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 220488 kb
Host smart-e4eb580d-1204-482b-a9c5-13fff229ac0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971715770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1971715770
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2339195587
Short name T181
Test name
Test status
Simulation time 124588596 ps
CPU time 4.28 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 209008 kb
Host smart-660be4ce-4510-4a8d-b2ca-000a2f0c6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339195587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2339195587
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3551323329
Short name T846
Test name
Test status
Simulation time 163668407 ps
CPU time 2.11 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 209940 kb
Host smart-8b028069-6188-47a8-9070-fb142396abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551323329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3551323329
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1225948572
Short name T629
Test name
Test status
Simulation time 25479606 ps
CPU time 0.76 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 205940 kb
Host smart-307050ad-8915-457d-a2fe-82308b4492ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225948572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1225948572
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.288062326
Short name T783
Test name
Test status
Simulation time 154808970 ps
CPU time 5.98 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:53 PM PDT 24
Peak memory 221920 kb
Host smart-fe58211f-ec56-4c5f-b1f7-b541bfb09952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288062326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.288062326
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3980106664
Short name T454
Test name
Test status
Simulation time 99473249 ps
CPU time 1.67 seconds
Started May 14 02:21:49 PM PDT 24
Finished May 14 02:21:53 PM PDT 24
Peak memory 208368 kb
Host smart-27e5a885-ad9e-4705-902b-fd8f1bed72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980106664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3980106664
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.587639785
Short name T222
Test name
Test status
Simulation time 215112327 ps
CPU time 3.36 seconds
Started May 14 02:21:50 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 214364 kb
Host smart-a9f84294-2852-4031-99dd-979bd974a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587639785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.587639785
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2997435603
Short name T42
Test name
Test status
Simulation time 634796179 ps
CPU time 3.35 seconds
Started May 14 02:21:52 PM PDT 24
Finished May 14 02:21:56 PM PDT 24
Peak memory 209856 kb
Host smart-43ed0401-0773-4346-bb04-69f9684d190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997435603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2997435603
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2407357204
Short name T512
Test name
Test status
Simulation time 88513422 ps
CPU time 3.6 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:51 PM PDT 24
Peak memory 208220 kb
Host smart-771a9330-ace6-4b2a-b4d2-906de76e5209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407357204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2407357204
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2977720859
Short name T857
Test name
Test status
Simulation time 70963108 ps
CPU time 3.18 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:52 PM PDT 24
Peak memory 208296 kb
Host smart-a14febb5-0664-4585-b811-d23f0a226bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977720859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2977720859
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3371351207
Short name T521
Test name
Test status
Simulation time 154921830 ps
CPU time 2.58 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:21:48 PM PDT 24
Peak memory 207100 kb
Host smart-bd732047-6498-4f81-bab2-1d4d94a3897f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371351207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3371351207
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2148020404
Short name T709
Test name
Test status
Simulation time 37996302 ps
CPU time 1.77 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 206888 kb
Host smart-31c0d181-2608-4b3e-9524-d60f99e6c3bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148020404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2148020404
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.576263720
Short name T835
Test name
Test status
Simulation time 94725224 ps
CPU time 2.64 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 207032 kb
Host smart-0e9e7828-d104-4dfd-ba4b-f4f845222bfa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576263720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.576263720
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1995782351
Short name T407
Test name
Test status
Simulation time 380976481 ps
CPU time 2.59 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:52 PM PDT 24
Peak memory 210264 kb
Host smart-c23b6853-889c-4e24-aa9d-20b1a2d3a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995782351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1995782351
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2985692163
Short name T458
Test name
Test status
Simulation time 55255580 ps
CPU time 2.45 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 207984 kb
Host smart-ca72cf37-4261-4805-bb04-c0f71cd2307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985692163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2985692163
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2311291627
Short name T256
Test name
Test status
Simulation time 9520421236 ps
CPU time 32.45 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:22:19 PM PDT 24
Peak memory 216364 kb
Host smart-2523a402-9375-4d97-bccb-1bccf1a533a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311291627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2311291627
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3067643581
Short name T762
Test name
Test status
Simulation time 1796912126 ps
CPU time 52.6 seconds
Started May 14 02:21:52 PM PDT 24
Finished May 14 02:22:46 PM PDT 24
Peak memory 218436 kb
Host smart-5c43651e-52e9-46e0-9e41-0aee12d11283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067643581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3067643581
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.739511562
Short name T711
Test name
Test status
Simulation time 59223147 ps
CPU time 2.26 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 210132 kb
Host smart-d51339de-2d88-4d96-bdcb-95841392bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739511562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.739511562
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1604985215
Short name T657
Test name
Test status
Simulation time 21208758 ps
CPU time 0.75 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 205864 kb
Host smart-11fa57ac-7889-4d80-a70b-7540d5fb51c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604985215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1604985215
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3930915197
Short name T413
Test name
Test status
Simulation time 1715368929 ps
CPU time 91.1 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:23:17 PM PDT 24
Peak memory 216748 kb
Host smart-82ad9449-2e00-4e22-ae07-e75bf240c0a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930915197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3930915197
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1388255588
Short name T201
Test name
Test status
Simulation time 566199442 ps
CPU time 4.59 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:01 PM PDT 24
Peak memory 208892 kb
Host smart-9cd2961a-df15-4d30-9d1f-28c3085496d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388255588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1388255588
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2448829192
Short name T840
Test name
Test status
Simulation time 148642905 ps
CPU time 1.83 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 208388 kb
Host smart-75f46a18-335a-4820-8d28-fd50265b4dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448829192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2448829192
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.755329717
Short name T21
Test name
Test status
Simulation time 1025950048 ps
CPU time 19.96 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:16 PM PDT 24
Peak memory 214284 kb
Host smart-2410832a-8363-4127-a8af-040661c72ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755329717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.755329717
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2756362678
Short name T666
Test name
Test status
Simulation time 106996473 ps
CPU time 2.31 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 214360 kb
Host smart-b9b1008c-218d-4dc0-a3ff-406f790d57c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756362678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2756362678
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1927825170
Short name T51
Test name
Test status
Simulation time 153845041 ps
CPU time 4.08 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:53 PM PDT 24
Peak memory 219972 kb
Host smart-ad7a44bf-f0bb-414b-b2d5-e44db7a8d6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927825170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1927825170
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2035256910
Short name T466
Test name
Test status
Simulation time 134475603 ps
CPU time 2.56 seconds
Started May 14 02:21:46 PM PDT 24
Finished May 14 02:21:50 PM PDT 24
Peak memory 207408 kb
Host smart-7798ea5a-1c61-4fff-ad69-a2955642ea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035256910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2035256910
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3364503521
Short name T476
Test name
Test status
Simulation time 1890596417 ps
CPU time 5.81 seconds
Started May 14 02:21:48 PM PDT 24
Finished May 14 02:21:55 PM PDT 24
Peak memory 207980 kb
Host smart-38b48502-f355-4f01-8aee-707a552edb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364503521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3364503521
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.714876478
Short name T617
Test name
Test status
Simulation time 351374113 ps
CPU time 5.63 seconds
Started May 14 02:21:51 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 208988 kb
Host smart-c49dae4d-ed9a-4fee-a39d-9ccd4b32c709
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714876478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.714876478
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.579680568
Short name T648
Test name
Test status
Simulation time 280202470 ps
CPU time 3.08 seconds
Started May 14 02:21:49 PM PDT 24
Finished May 14 02:21:54 PM PDT 24
Peak memory 207044 kb
Host smart-852d4ba4-46af-4892-b8d7-4d33ae0e3a2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579680568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.579680568
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.331698993
Short name T560
Test name
Test status
Simulation time 269852664 ps
CPU time 3.31 seconds
Started May 14 02:21:49 PM PDT 24
Finished May 14 02:21:54 PM PDT 24
Peak memory 208056 kb
Host smart-ad44d2ce-ee78-42e8-a675-df02414632f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331698993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.331698993
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1471997024
Short name T753
Test name
Test status
Simulation time 83011527 ps
CPU time 2.72 seconds
Started May 14 02:22:00 PM PDT 24
Finished May 14 02:22:03 PM PDT 24
Peak memory 209704 kb
Host smart-464b8c17-74d8-4e4f-a4cb-5c76bec3f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471997024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1471997024
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4157011304
Short name T429
Test name
Test status
Simulation time 63987036 ps
CPU time 2.75 seconds
Started May 14 02:21:47 PM PDT 24
Finished May 14 02:21:51 PM PDT 24
Peak memory 208256 kb
Host smart-725ceb75-eeb4-4c50-ac2c-2cb977c991c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157011304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4157011304
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4293296107
Short name T170
Test name
Test status
Simulation time 3656671898 ps
CPU time 33.03 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:30 PM PDT 24
Peak memory 221100 kb
Host smart-1b28a3c7-f9d6-4305-ad7a-86daed107687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293296107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4293296107
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1326523526
Short name T909
Test name
Test status
Simulation time 273261598 ps
CPU time 13.24 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:10 PM PDT 24
Peak memory 220364 kb
Host smart-f23eaf9b-07b1-4c2f-a037-a47e41d98096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326523526 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1326523526
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2321909389
Short name T394
Test name
Test status
Simulation time 1462439819 ps
CPU time 25.31 seconds
Started May 14 02:21:45 PM PDT 24
Finished May 14 02:22:12 PM PDT 24
Peak memory 208372 kb
Host smart-3c62e4dc-ee0e-4f30-9650-79bc7a72d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321909389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2321909389
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2827132506
Short name T882
Test name
Test status
Simulation time 20880169 ps
CPU time 0.99 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:21:59 PM PDT 24
Peak memory 206116 kb
Host smart-aa178c78-bea8-4919-b328-883fff2dc000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827132506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2827132506
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.831864122
Short name T16
Test name
Test status
Simulation time 74491467 ps
CPU time 1.13 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 222788 kb
Host smart-a6dec668-8beb-441e-b760-06a89cac27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831864122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.831864122
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1720409448
Short name T30
Test name
Test status
Simulation time 115447569 ps
CPU time 2.05 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:21:58 PM PDT 24
Peak memory 208108 kb
Host smart-b0d11e9e-7027-4e99-8b95-5d0b9ff26818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720409448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1720409448
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2517566070
Short name T362
Test name
Test status
Simulation time 1289846119 ps
CPU time 28.17 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:25 PM PDT 24
Peak memory 220276 kb
Host smart-9258692c-b557-425c-a76e-215c11333ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517566070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2517566070
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2238052733
Short name T271
Test name
Test status
Simulation time 113818343 ps
CPU time 5.55 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:03 PM PDT 24
Peak memory 222416 kb
Host smart-b4bafb21-658b-4f56-91af-ee87e0db879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238052733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2238052733
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4269856797
Short name T749
Test name
Test status
Simulation time 224515577 ps
CPU time 5.08 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:03 PM PDT 24
Peak memory 220348 kb
Host smart-56936473-74e6-438a-93ca-8256a1d68ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269856797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4269856797
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1503130245
Short name T164
Test name
Test status
Simulation time 75523363 ps
CPU time 3.82 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:01 PM PDT 24
Peak memory 214388 kb
Host smart-815810d9-af23-4b2b-98e7-853892b45432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503130245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1503130245
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1378828525
Short name T265
Test name
Test status
Simulation time 1140292196 ps
CPU time 25.5 seconds
Started May 14 02:21:53 PM PDT 24
Finished May 14 02:22:21 PM PDT 24
Peak memory 207972 kb
Host smart-f5bb5cda-692f-47f3-99ca-d18c4c491902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378828525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1378828525
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1883880241
Short name T481
Test name
Test status
Simulation time 7683986068 ps
CPU time 47.73 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:22:46 PM PDT 24
Peak memory 208568 kb
Host smart-d082613f-0127-461e-bd2d-188fa59ec325
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883880241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1883880241
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3226610771
Short name T299
Test name
Test status
Simulation time 93613678 ps
CPU time 3.44 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:00 PM PDT 24
Peak memory 208648 kb
Host smart-3807f445-a384-4841-a97b-c32ac72459ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226610771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3226610771
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2900728143
Short name T489
Test name
Test status
Simulation time 49629982 ps
CPU time 2.63 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:22:01 PM PDT 24
Peak memory 208676 kb
Host smart-ca534311-806d-46a4-865b-bedf37881002
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900728143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2900728143
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.667159066
Short name T551
Test name
Test status
Simulation time 89006344 ps
CPU time 1.92 seconds
Started May 14 02:21:53 PM PDT 24
Finished May 14 02:21:56 PM PDT 24
Peak memory 218384 kb
Host smart-3ec6b36b-baf5-47f8-9403-ebaa908607ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667159066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.667159066
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3964104877
Short name T700
Test name
Test status
Simulation time 649008561 ps
CPU time 4.08 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:22:01 PM PDT 24
Peak memory 206736 kb
Host smart-0102b89c-c875-414a-b6f6-91e4c3b37b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964104877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3964104877
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.946262242
Short name T304
Test name
Test status
Simulation time 20768456007 ps
CPU time 239.17 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:25:58 PM PDT 24
Peak memory 220632 kb
Host smart-1c5ddddf-6b93-465a-aa5c-114b23578d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946262242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.946262242
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.968908573
Short name T172
Test name
Test status
Simulation time 196083116 ps
CPU time 4.1 seconds
Started May 14 02:21:56 PM PDT 24
Finished May 14 02:22:03 PM PDT 24
Peak memory 209844 kb
Host smart-bcfccce4-93cf-4f3d-994c-90438b087681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968908573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.968908573
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4148454543
Short name T623
Test name
Test status
Simulation time 14188638 ps
CPU time 0.77 seconds
Started May 14 02:20:04 PM PDT 24
Finished May 14 02:20:06 PM PDT 24
Peak memory 205860 kb
Host smart-1002adbd-8773-416c-987e-04d68a3c5c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148454543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4148454543
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.17326909
Short name T571
Test name
Test status
Simulation time 484714616 ps
CPU time 2 seconds
Started May 14 02:19:54 PM PDT 24
Finished May 14 02:19:57 PM PDT 24
Peak memory 222792 kb
Host smart-b3aa8805-c8d6-4baa-b5ee-617f8aece3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17326909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.17326909
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.722568544
Short name T184
Test name
Test status
Simulation time 48221662 ps
CPU time 1.71 seconds
Started May 14 02:19:55 PM PDT 24
Finished May 14 02:19:57 PM PDT 24
Peak memory 209908 kb
Host smart-85fe4c62-3f2e-450c-93e2-98c76a0bd360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722568544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.722568544
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1369426114
Short name T193
Test name
Test status
Simulation time 109887588 ps
CPU time 2.76 seconds
Started May 14 02:19:55 PM PDT 24
Finished May 14 02:19:59 PM PDT 24
Peak memory 209848 kb
Host smart-c2f03d3f-1d79-4173-832c-67604f4cda1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369426114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1369426114
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3467350446
Short name T455
Test name
Test status
Simulation time 1258087853 ps
CPU time 8.79 seconds
Started May 14 02:19:53 PM PDT 24
Finished May 14 02:20:03 PM PDT 24
Peak memory 208900 kb
Host smart-5e98dfbd-34ed-485d-bf16-0b04d266a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467350446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3467350446
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2444778772
Short name T746
Test name
Test status
Simulation time 342603411 ps
CPU time 5.74 seconds
Started May 14 02:19:46 PM PDT 24
Finished May 14 02:19:52 PM PDT 24
Peak memory 208148 kb
Host smart-b709d060-e8f7-44df-8bf6-4d973e766eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444778772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2444778772
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2024893353
Short name T280
Test name
Test status
Simulation time 1660509292 ps
CPU time 7.55 seconds
Started May 14 02:19:46 PM PDT 24
Finished May 14 02:19:54 PM PDT 24
Peak memory 207016 kb
Host smart-3945cb55-b54d-48fa-9203-f59420861030
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024893353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2024893353
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2969029219
Short name T844
Test name
Test status
Simulation time 423724202 ps
CPU time 1.94 seconds
Started May 14 02:19:46 PM PDT 24
Finished May 14 02:19:48 PM PDT 24
Peak memory 206880 kb
Host smart-47821a06-b31e-48e5-8e1a-cc1dfbc2792a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969029219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2969029219
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2799663941
Short name T432
Test name
Test status
Simulation time 3392001390 ps
CPU time 22.55 seconds
Started May 14 02:19:52 PM PDT 24
Finished May 14 02:20:15 PM PDT 24
Peak memory 208904 kb
Host smart-f758686c-2da7-47b0-abe5-a68917f14a86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799663941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2799663941
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3107993068
Short name T461
Test name
Test status
Simulation time 27459605 ps
CPU time 2.23 seconds
Started May 14 02:19:54 PM PDT 24
Finished May 14 02:19:57 PM PDT 24
Peak memory 214444 kb
Host smart-bb76b2e2-ff7a-4e58-bdfc-a88945c7d34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107993068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3107993068
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.417828422
Short name T645
Test name
Test status
Simulation time 147188186 ps
CPU time 2.09 seconds
Started May 14 02:19:45 PM PDT 24
Finished May 14 02:19:48 PM PDT 24
Peak memory 206864 kb
Host smart-322c352a-64b9-4e53-996e-034bbc058b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417828422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.417828422
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.990328722
Short name T272
Test name
Test status
Simulation time 159397042 ps
CPU time 3.23 seconds
Started May 14 02:19:54 PM PDT 24
Finished May 14 02:19:59 PM PDT 24
Peak memory 214628 kb
Host smart-43db99b8-c001-481b-92eb-02ed2a0553bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990328722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.990328722
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1659901390
Short name T886
Test name
Test status
Simulation time 130662368 ps
CPU time 2.34 seconds
Started May 14 02:19:55 PM PDT 24
Finished May 14 02:19:58 PM PDT 24
Peak memory 209748 kb
Host smart-7486198c-c3b2-4a5f-8897-6000d5ac9c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659901390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1659901390
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3125474014
Short name T421
Test name
Test status
Simulation time 53105057 ps
CPU time 0.81 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:49 PM PDT 24
Peak memory 205924 kb
Host smart-f422b606-a433-47b4-8f11-47e78c55ffaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125474014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3125474014
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2648674752
Short name T262
Test name
Test status
Simulation time 667991292 ps
CPU time 11.58 seconds
Started May 14 02:22:03 PM PDT 24
Finished May 14 02:22:15 PM PDT 24
Peak memory 214692 kb
Host smart-bfcd5584-9a6f-4fbe-bf48-6d4b14308231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648674752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2648674752
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3614441873
Short name T894
Test name
Test status
Simulation time 77651118 ps
CPU time 2.69 seconds
Started May 14 02:22:05 PM PDT 24
Finished May 14 02:22:08 PM PDT 24
Peak memory 209776 kb
Host smart-d81351a4-f2e9-451c-81f9-2c0c9477c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614441873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3614441873
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.860049389
Short name T46
Test name
Test status
Simulation time 290569324 ps
CPU time 3.26 seconds
Started May 14 02:22:05 PM PDT 24
Finished May 14 02:22:09 PM PDT 24
Peak memory 215564 kb
Host smart-7d9ff7a0-e315-4d91-b14b-bfcadf354034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860049389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.860049389
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2025934965
Short name T302
Test name
Test status
Simulation time 96571868 ps
CPU time 4.58 seconds
Started May 14 02:22:04 PM PDT 24
Finished May 14 02:22:10 PM PDT 24
Peak memory 222360 kb
Host smart-3d503d25-7ad5-42ee-8e03-cdea0d8b1e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025934965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2025934965
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.606164161
Short name T613
Test name
Test status
Simulation time 362658120 ps
CPU time 3.33 seconds
Started May 14 02:22:04 PM PDT 24
Finished May 14 02:22:08 PM PDT 24
Peak memory 214280 kb
Host smart-62a2fccc-1045-4d9f-b1b7-51f559fdb064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606164161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.606164161
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2065966775
Short name T810
Test name
Test status
Simulation time 60542837 ps
CPU time 2.35 seconds
Started May 14 02:22:04 PM PDT 24
Finished May 14 02:22:07 PM PDT 24
Peak memory 214440 kb
Host smart-11d7ec3e-5d92-4b8a-82ce-9908aa4a3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065966775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2065966775
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1532637179
Short name T41
Test name
Test status
Simulation time 171242561 ps
CPU time 3.26 seconds
Started May 14 02:21:53 PM PDT 24
Finished May 14 02:21:57 PM PDT 24
Peak memory 206704 kb
Host smart-29a8aed4-818a-4f2a-96cc-081959335ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532637179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1532637179
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1375201217
Short name T577
Test name
Test status
Simulation time 135420998 ps
CPU time 2.5 seconds
Started May 14 02:21:54 PM PDT 24
Finished May 14 02:21:59 PM PDT 24
Peak memory 206984 kb
Host smart-77c2ba1e-e251-423e-990c-ca1e54fad8cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375201217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1375201217
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2851771257
Short name T673
Test name
Test status
Simulation time 8486939756 ps
CPU time 55.44 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:52 PM PDT 24
Peak memory 208544 kb
Host smart-7c58d2e0-d609-4f06-84e5-8b20292c8cce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851771257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2851771257
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3254749716
Short name T897
Test name
Test status
Simulation time 153148618 ps
CPU time 2.32 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:21:59 PM PDT 24
Peak memory 206812 kb
Host smart-339e858c-0a7a-482f-b030-6679a35e5e7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254749716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3254749716
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.613077172
Short name T759
Test name
Test status
Simulation time 148516786 ps
CPU time 3.52 seconds
Started May 14 02:22:02 PM PDT 24
Finished May 14 02:22:06 PM PDT 24
Peak memory 208452 kb
Host smart-8afe5b78-2903-4903-b8aa-c16d21f45923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613077172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.613077172
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1336058101
Short name T420
Test name
Test status
Simulation time 922484174 ps
CPU time 15.77 seconds
Started May 14 02:21:55 PM PDT 24
Finished May 14 02:22:13 PM PDT 24
Peak memory 208200 kb
Host smart-a9c1ff56-cc8e-42bd-a980-24e0310feba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336058101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1336058101
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3240190393
Short name T294
Test name
Test status
Simulation time 199210207 ps
CPU time 8.7 seconds
Started May 14 02:22:06 PM PDT 24
Finished May 14 02:22:15 PM PDT 24
Peak memory 208064 kb
Host smart-5c0b8107-4498-40bc-9b88-63c842496ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240190393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3240190393
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3390113450
Short name T114
Test name
Test status
Simulation time 309117840 ps
CPU time 10.92 seconds
Started May 14 02:22:02 PM PDT 24
Finished May 14 02:22:13 PM PDT 24
Peak memory 222644 kb
Host smart-389d6883-7bda-4d08-8b6b-ceab51bd2cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390113450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3390113450
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2607904281
Short name T214
Test name
Test status
Simulation time 5692660113 ps
CPU time 41.8 seconds
Started May 14 02:22:02 PM PDT 24
Finished May 14 02:22:45 PM PDT 24
Peak memory 208600 kb
Host smart-c1b3e5f2-f69e-42cb-bddb-c6a7f6eed427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607904281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2607904281
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3261668916
Short name T562
Test name
Test status
Simulation time 191930601 ps
CPU time 3.36 seconds
Started May 14 02:22:05 PM PDT 24
Finished May 14 02:22:09 PM PDT 24
Peak memory 210168 kb
Host smart-e456a7cd-fd40-494e-a622-cb61882165ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261668916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3261668916
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.789324823
Short name T692
Test name
Test status
Simulation time 15815171 ps
CPU time 0.71 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:49 PM PDT 24
Peak memory 205960 kb
Host smart-e3dc1725-328f-4524-9ba6-96d4fbcd787e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789324823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.789324823
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3308885453
Short name T397
Test name
Test status
Simulation time 1187024885 ps
CPU time 15.98 seconds
Started May 14 02:24:50 PM PDT 24
Finished May 14 02:25:07 PM PDT 24
Peak memory 215840 kb
Host smart-ae7d6668-a051-45ce-b18f-f295e8a14681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308885453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3308885453
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4183301044
Short name T50
Test name
Test status
Simulation time 18073890 ps
CPU time 1.3 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:51 PM PDT 24
Peak memory 209036 kb
Host smart-23564998-21ea-46f1-8f08-3a1ec76dc652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183301044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4183301044
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.423563452
Short name T219
Test name
Test status
Simulation time 1206970081 ps
CPU time 3.29 seconds
Started May 14 02:24:46 PM PDT 24
Finished May 14 02:24:50 PM PDT 24
Peak memory 214288 kb
Host smart-60c2f3a2-02d0-4b3b-b7c7-92a866e39e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423563452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.423563452
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.369965354
Short name T320
Test name
Test status
Simulation time 71353465 ps
CPU time 3.59 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:51 PM PDT 24
Peak memory 214276 kb
Host smart-4ef59ea3-5a65-4362-815c-96ad05fd09cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369965354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.369965354
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2860317712
Short name T195
Test name
Test status
Simulation time 598997988 ps
CPU time 4.07 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:52 PM PDT 24
Peak memory 214780 kb
Host smart-9ef11645-fb97-4562-b1ec-83573f4419a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860317712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2860317712
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2675376439
Short name T621
Test name
Test status
Simulation time 1116935252 ps
CPU time 30.59 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:25:19 PM PDT 24
Peak memory 208740 kb
Host smart-4b3d1035-e560-460b-a470-d1184ea00adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675376439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2675376439
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1607661657
Short name T839
Test name
Test status
Simulation time 46247039 ps
CPU time 2.54 seconds
Started May 14 02:24:50 PM PDT 24
Finished May 14 02:24:54 PM PDT 24
Peak memory 206784 kb
Host smart-88646846-4a08-4d07-8a31-4f35facd752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607661657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1607661657
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1497437101
Short name T578
Test name
Test status
Simulation time 2031914112 ps
CPU time 15.64 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:25:04 PM PDT 24
Peak memory 208768 kb
Host smart-8646b3a0-249a-4425-b607-f60b08a3f17b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497437101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1497437101
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2845825933
Short name T868
Test name
Test status
Simulation time 239687195 ps
CPU time 2.46 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:51 PM PDT 24
Peak memory 206852 kb
Host smart-84e1c747-d0f7-44cd-b20c-919124d0d503
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845825933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2845825933
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1269800493
Short name T426
Test name
Test status
Simulation time 20841967 ps
CPU time 1.87 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:52 PM PDT 24
Peak memory 207004 kb
Host smart-cd77230d-6f95-4025-8347-3c3c0a478b71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269800493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1269800493
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4151602148
Short name T665
Test name
Test status
Simulation time 379512701 ps
CPU time 3.94 seconds
Started May 14 02:24:46 PM PDT 24
Finished May 14 02:24:51 PM PDT 24
Peak memory 214276 kb
Host smart-8e6c6dce-ba06-436c-b029-eea75a696adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151602148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4151602148
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.359700640
Short name T622
Test name
Test status
Simulation time 43029993 ps
CPU time 2.37 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:50 PM PDT 24
Peak memory 206868 kb
Host smart-395b561a-2325-4abb-a0e6-2ddf6e58eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359700640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.359700640
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.895373369
Short name T177
Test name
Test status
Simulation time 383638959 ps
CPU time 5.11 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:53 PM PDT 24
Peak memory 209568 kb
Host smart-c0126de3-6029-4564-9025-efeb9c7f832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895373369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.895373369
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1761080840
Short name T368
Test name
Test status
Simulation time 902297543 ps
CPU time 13.62 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:25:02 PM PDT 24
Peak memory 211144 kb
Host smart-0364da2b-6dae-4144-9ac6-1a1724fd09c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761080840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1761080840
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2364555178
Short name T744
Test name
Test status
Simulation time 36471505 ps
CPU time 0.74 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:24:59 PM PDT 24
Peak memory 205992 kb
Host smart-f6bfba56-f394-4e00-9a7d-0f0727e3dd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364555178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2364555178
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1567442974
Short name T274
Test name
Test status
Simulation time 1584913083 ps
CPU time 5.98 seconds
Started May 14 02:24:50 PM PDT 24
Finished May 14 02:24:57 PM PDT 24
Peak memory 215200 kb
Host smart-faaa833d-a9c7-4e30-8033-0c1ac7c5a1e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567442974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1567442974
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3425011863
Short name T677
Test name
Test status
Simulation time 351814918 ps
CPU time 3.61 seconds
Started May 14 02:25:02 PM PDT 24
Finished May 14 02:25:07 PM PDT 24
Peak memory 219168 kb
Host smart-ede7b850-0b82-4ce9-a4be-a3f74ed330f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425011863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3425011863
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.4161639201
Short name T484
Test name
Test status
Simulation time 26771948 ps
CPU time 1.87 seconds
Started May 14 02:24:47 PM PDT 24
Finished May 14 02:24:50 PM PDT 24
Peak memory 209880 kb
Host smart-95f4b58e-62d1-4c06-84e9-285f02ab9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161639201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.4161639201
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1855847886
Short name T710
Test name
Test status
Simulation time 58538786 ps
CPU time 2.31 seconds
Started May 14 02:25:02 PM PDT 24
Finished May 14 02:25:06 PM PDT 24
Peak memory 214416 kb
Host smart-6aaf163f-7979-49b6-b16c-8efeeb06e73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855847886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1855847886
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1432699710
Short name T805
Test name
Test status
Simulation time 425210805 ps
CPU time 9.69 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:25:08 PM PDT 24
Peak memory 221676 kb
Host smart-d8e0f796-dcba-47ff-b89d-4ae158980764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432699710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1432699710
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1491714096
Short name T48
Test name
Test status
Simulation time 98459687 ps
CPU time 3.64 seconds
Started May 14 02:24:57 PM PDT 24
Finished May 14 02:25:03 PM PDT 24
Peak memory 206260 kb
Host smart-b5515f82-2508-43dc-87c2-aaacb109ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491714096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1491714096
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.94438352
Short name T568
Test name
Test status
Simulation time 2087340313 ps
CPU time 7.32 seconds
Started May 14 02:24:45 PM PDT 24
Finished May 14 02:24:53 PM PDT 24
Peak memory 209304 kb
Host smart-63e26271-02a2-4482-bc38-e2ecf66b6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94438352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.94438352
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2936940787
Short name T900
Test name
Test status
Simulation time 333960231 ps
CPU time 2.31 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:53 PM PDT 24
Peak memory 207048 kb
Host smart-9a06e31f-e52a-466a-82dd-a13561ff81b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936940787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2936940787
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2031031429
Short name T306
Test name
Test status
Simulation time 1021625692 ps
CPU time 24.64 seconds
Started May 14 02:24:46 PM PDT 24
Finished May 14 02:25:12 PM PDT 24
Peak memory 208868 kb
Host smart-3e8050c8-b6c4-4ce8-b782-91d76127b1dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031031429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2031031429
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1419616025
Short name T542
Test name
Test status
Simulation time 78490324 ps
CPU time 3.67 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:53 PM PDT 24
Peak memory 208320 kb
Host smart-77669fe4-7d58-49b7-8921-65040c7ca038
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419616025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1419616025
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1331270451
Short name T662
Test name
Test status
Simulation time 62414492 ps
CPU time 2.28 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:52 PM PDT 24
Peak memory 206868 kb
Host smart-1701c11f-515c-4045-b593-3be163139317
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331270451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1331270451
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1684597199
Short name T755
Test name
Test status
Simulation time 16952886 ps
CPU time 1.48 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:25:00 PM PDT 24
Peak memory 207640 kb
Host smart-85950d61-f37c-471e-a79e-13ccbba48109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684597199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1684597199
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1345838747
Short name T573
Test name
Test status
Simulation time 115951653 ps
CPU time 3.04 seconds
Started May 14 02:24:49 PM PDT 24
Finished May 14 02:24:53 PM PDT 24
Peak memory 208428 kb
Host smart-95727473-f014-4f29-89e5-1a2f5d0c3173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345838747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1345838747
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1091587118
Short name T816
Test name
Test status
Simulation time 309510232 ps
CPU time 17.6 seconds
Started May 14 02:24:57 PM PDT 24
Finished May 14 02:25:16 PM PDT 24
Peak memory 222488 kb
Host smart-f3980384-b307-4cb0-84fc-3efce851b7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091587118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1091587118
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1448369658
Short name T86
Test name
Test status
Simulation time 177781384 ps
CPU time 4.38 seconds
Started May 14 02:24:58 PM PDT 24
Finished May 14 02:25:04 PM PDT 24
Peak memory 208952 kb
Host smart-f588b83c-03a2-4a77-a6f6-c1179e4c94dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448369658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1448369658
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2858127524
Short name T118
Test name
Test status
Simulation time 136395639 ps
CPU time 2.24 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:25:00 PM PDT 24
Peak memory 210404 kb
Host smart-0c8aff93-3e04-4838-a114-37a5655f2931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858127524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2858127524
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3186836332
Short name T819
Test name
Test status
Simulation time 17508242 ps
CPU time 0.82 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 205984 kb
Host smart-d5be3fba-6032-4f0d-8509-36266dcf7c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186836332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3186836332
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3311763498
Short name T244
Test name
Test status
Simulation time 54681960 ps
CPU time 2.5 seconds
Started May 14 02:24:58 PM PDT 24
Finished May 14 02:25:02 PM PDT 24
Peak memory 218240 kb
Host smart-83443837-5851-4d0c-83f6-22cc64582484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311763498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3311763498
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3549405464
Short name T276
Test name
Test status
Simulation time 2573019125 ps
CPU time 42.97 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:50 PM PDT 24
Peak memory 214540 kb
Host smart-5d5213e6-19d7-43d9-962a-8a89d3dccfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549405464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3549405464
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1844277079
Short name T528
Test name
Test status
Simulation time 28480966 ps
CPU time 1.4 seconds
Started May 14 02:24:57 PM PDT 24
Finished May 14 02:25:01 PM PDT 24
Peak memory 206200 kb
Host smart-04ce8cdd-2b43-4eec-aaa8-2a8f318e61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844277079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1844277079
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.646111261
Short name T504
Test name
Test status
Simulation time 148326569 ps
CPU time 5.22 seconds
Started May 14 02:24:58 PM PDT 24
Finished May 14 02:25:05 PM PDT 24
Peak memory 209180 kb
Host smart-9f8ac0e6-0518-497c-a3dd-4a253a5cf958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646111261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.646111261
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3822215883
Short name T526
Test name
Test status
Simulation time 181754835 ps
CPU time 6.04 seconds
Started May 14 02:24:57 PM PDT 24
Finished May 14 02:25:05 PM PDT 24
Peak memory 207232 kb
Host smart-2c105eee-0399-4b1c-b72a-4f7a7ac0dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822215883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3822215883
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3804725056
Short name T713
Test name
Test status
Simulation time 87226938 ps
CPU time 1.88 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:25:00 PM PDT 24
Peak memory 207008 kb
Host smart-16b98206-2828-410c-b7de-880876d24802
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804725056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3804725056
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1928086713
Short name T289
Test name
Test status
Simulation time 72227589 ps
CPU time 3.06 seconds
Started May 14 02:24:57 PM PDT 24
Finished May 14 02:25:02 PM PDT 24
Peak memory 208684 kb
Host smart-7a166d46-a00c-4423-a0ab-2a8b0b8eb435
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928086713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1928086713
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1602220163
Short name T684
Test name
Test status
Simulation time 25058182 ps
CPU time 2.15 seconds
Started May 14 02:25:02 PM PDT 24
Finished May 14 02:25:05 PM PDT 24
Peak memory 208860 kb
Host smart-8112f6ad-800a-481d-98cb-2cae65a35ce3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602220163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1602220163
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.363037187
Short name T884
Test name
Test status
Simulation time 640035475 ps
CPU time 3.09 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 207704 kb
Host smart-2f009623-c355-44cc-86c5-43957c3f088c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363037187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.363037187
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2437240856
Short name T464
Test name
Test status
Simulation time 166433470 ps
CPU time 3.17 seconds
Started May 14 02:24:56 PM PDT 24
Finished May 14 02:25:01 PM PDT 24
Peak memory 208880 kb
Host smart-b765aef8-90ae-406e-a8c3-b3050df749de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437240856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2437240856
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1807829064
Short name T696
Test name
Test status
Simulation time 1402153309 ps
CPU time 41.6 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:51 PM PDT 24
Peak memory 216476 kb
Host smart-a70d4764-ddd7-45a0-b4ea-aafc4e6f97fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807829064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1807829064
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.219433419
Short name T73
Test name
Test status
Simulation time 284550620 ps
CPU time 18.23 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 222672 kb
Host smart-4c1444ee-b4fa-4e57-bcb6-75783762937a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219433419 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.219433419
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4108077685
Short name T691
Test name
Test status
Simulation time 853328404 ps
CPU time 11.11 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:18 PM PDT 24
Peak memory 214348 kb
Host smart-92669e12-d530-4253-9b4f-8a94276c7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108077685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4108077685
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4291072633
Short name T57
Test name
Test status
Simulation time 48971954 ps
CPU time 2.3 seconds
Started May 14 02:25:09 PM PDT 24
Finished May 14 02:25:13 PM PDT 24
Peak memory 210116 kb
Host smart-a4099d93-a367-4ec0-b6db-d46ab6468ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291072633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4291072633
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.58128445
Short name T423
Test name
Test status
Simulation time 13231365 ps
CPU time 0.87 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 205924 kb
Host smart-88d4f381-3922-4c69-9dc8-9746d2e67169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58128445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.58128445
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3384653117
Short name T558
Test name
Test status
Simulation time 1107325021 ps
CPU time 5.01 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:14 PM PDT 24
Peak memory 214764 kb
Host smart-e3372ef6-d675-4b21-86b0-6ff876f40e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384653117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3384653117
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2267918351
Short name T393
Test name
Test status
Simulation time 25661130 ps
CPU time 1.46 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:08 PM PDT 24
Peak memory 208036 kb
Host smart-77ef1414-2d5d-45ec-b626-d2c02ecf0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267918351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2267918351
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.496687347
Short name T801
Test name
Test status
Simulation time 1751497875 ps
CPU time 38.6 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 214328 kb
Host smart-5ff5b984-932d-4d9b-9f2a-6c0537c200a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496687347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.496687347
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_random.4294072330
Short name T649
Test name
Test status
Simulation time 798228692 ps
CPU time 15.13 seconds
Started May 14 02:25:09 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 209240 kb
Host smart-b4fc916d-d119-4d49-92d6-fb1761e5a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294072330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4294072330
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.974420920
Short name T291
Test name
Test status
Simulation time 31884499 ps
CPU time 2.4 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:11 PM PDT 24
Peak memory 206632 kb
Host smart-dc7c90b5-8a87-4eb8-97e9-46727089edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974420920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.974420920
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3608591335
Short name T533
Test name
Test status
Simulation time 73454535 ps
CPU time 2.37 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 206908 kb
Host smart-bbf72998-ea66-43d4-9128-58ac67d20558
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608591335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3608591335
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1933622453
Short name T779
Test name
Test status
Simulation time 79679046 ps
CPU time 1.8 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:11 PM PDT 24
Peak memory 206924 kb
Host smart-16d744fb-0501-4cbb-bf4c-0e135d7f911d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933622453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1933622453
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2644636959
Short name T499
Test name
Test status
Simulation time 379824041 ps
CPU time 6.31 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:15 PM PDT 24
Peak memory 208032 kb
Host smart-2e077e41-8d67-465d-9c2d-6a890cfd37bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644636959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2644636959
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2071489021
Short name T189
Test name
Test status
Simulation time 127218490 ps
CPU time 2.02 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:10 PM PDT 24
Peak memory 209264 kb
Host smart-185f3f61-70a5-4bca-b6da-841383a7b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071489021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2071489021
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.265790078
Short name T487
Test name
Test status
Simulation time 135980664 ps
CPU time 2.36 seconds
Started May 14 02:25:06 PM PDT 24
Finished May 14 02:25:09 PM PDT 24
Peak memory 206684 kb
Host smart-5621a38f-26d3-4ed5-a0dc-3ef24cbb5220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265790078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.265790078
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3233066686
Short name T561
Test name
Test status
Simulation time 996102900 ps
CPU time 14.32 seconds
Started May 14 02:25:09 PM PDT 24
Finished May 14 02:25:25 PM PDT 24
Peak memory 222496 kb
Host smart-bb986896-95ce-4ee4-be70-d256a952e123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233066686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3233066686
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3836569549
Short name T116
Test name
Test status
Simulation time 223194034 ps
CPU time 7.99 seconds
Started May 14 02:25:08 PM PDT 24
Finished May 14 02:25:18 PM PDT 24
Peak memory 222600 kb
Host smart-ad98f8f5-0b32-4314-97f2-3cbb7a5a1ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836569549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3836569549
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1984432098
Short name T173
Test name
Test status
Simulation time 1146848014 ps
CPU time 11.21 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:19 PM PDT 24
Peak memory 209852 kb
Host smart-670ffd8d-3c80-48bc-9d65-a1fcc5f7cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984432098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1984432098
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3048123740
Short name T364
Test name
Test status
Simulation time 75370214 ps
CPU time 3.31 seconds
Started May 14 02:25:07 PM PDT 24
Finished May 14 02:25:12 PM PDT 24
Peak memory 210304 kb
Host smart-6dbceeb7-cbf7-447b-ad85-1cc9f863ea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048123740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3048123740
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1525034548
Short name T760
Test name
Test status
Simulation time 206275890 ps
CPU time 0.87 seconds
Started May 14 02:25:18 PM PDT 24
Finished May 14 02:25:20 PM PDT 24
Peak memory 205992 kb
Host smart-32187bd7-e617-41c1-a2f4-fe3d35e71854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525034548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1525034548
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1085320813
Short name T616
Test name
Test status
Simulation time 110803962 ps
CPU time 4.78 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 208748 kb
Host smart-4fa415e0-8ad3-4d9d-a82b-163ca0d370e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085320813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1085320813
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3336059932
Short name T771
Test name
Test status
Simulation time 136235296 ps
CPU time 2.36 seconds
Started May 14 02:25:21 PM PDT 24
Finished May 14 02:25:24 PM PDT 24
Peak memory 209380 kb
Host smart-b376b555-2584-46dc-bc76-76d831641be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336059932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3336059932
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2754385035
Short name T350
Test name
Test status
Simulation time 245769894 ps
CPU time 5.91 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:28 PM PDT 24
Peak memory 214380 kb
Host smart-b8624f96-557a-4764-bf9c-0dba11eaf0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754385035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2754385035
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2223347972
Short name T284
Test name
Test status
Simulation time 1304106418 ps
CPU time 4.82 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 214440 kb
Host smart-a4ee52e3-cb4d-4f4b-902e-690ccf22d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223347972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2223347972
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.724361598
Short name T743
Test name
Test status
Simulation time 228577343 ps
CPU time 6.64 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:28 PM PDT 24
Peak memory 209544 kb
Host smart-5e38fe08-578b-45d4-8a9b-8237d811c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724361598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.724361598
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2079659966
Short name T293
Test name
Test status
Simulation time 2452058829 ps
CPU time 7.91 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:29 PM PDT 24
Peak memory 208688 kb
Host smart-91651755-87e7-4ea3-a170-fa40975ce65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079659966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2079659966
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.670677605
Short name T525
Test name
Test status
Simulation time 435273136 ps
CPU time 3.21 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:24 PM PDT 24
Peak memory 206820 kb
Host smart-1cec49c4-1186-4fb2-ba2c-ca05324372c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670677605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.670677605
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1464317084
Short name T337
Test name
Test status
Simulation time 134656097 ps
CPU time 2.63 seconds
Started May 14 02:25:21 PM PDT 24
Finished May 14 02:25:25 PM PDT 24
Peak memory 208708 kb
Host smart-7aa277a9-836d-4d55-97f6-2dc9e670f627
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464317084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1464317084
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.689069300
Short name T611
Test name
Test status
Simulation time 766685948 ps
CPU time 4.62 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 207020 kb
Host smart-c4d3816b-07d4-490c-8cbc-365e4e8054fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689069300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.689069300
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2472060376
Short name T668
Test name
Test status
Simulation time 78385501 ps
CPU time 2.41 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:23 PM PDT 24
Peak memory 206972 kb
Host smart-c61daf6b-c725-476e-89fc-3c5b0c453afa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472060376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2472060376
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1000723895
Short name T754
Test name
Test status
Simulation time 2298418400 ps
CPU time 19.58 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:40 PM PDT 24
Peak memory 209500 kb
Host smart-36098974-66da-4680-b695-69d6ce4ce66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000723895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1000723895
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3200157227
Short name T687
Test name
Test status
Simulation time 349003285 ps
CPU time 4.88 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:26 PM PDT 24
Peak memory 207944 kb
Host smart-080634ef-6f45-443e-842f-eaacb4335e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200157227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3200157227
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1693068292
Short name T742
Test name
Test status
Simulation time 258976163 ps
CPU time 9.52 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:30 PM PDT 24
Peak memory 222600 kb
Host smart-a6e535b3-b43c-4b61-a55d-406309b4c6bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693068292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1693068292
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3066666304
Short name T826
Test name
Test status
Simulation time 344640178 ps
CPU time 7.14 seconds
Started May 14 02:25:21 PM PDT 24
Finished May 14 02:25:29 PM PDT 24
Peak memory 214388 kb
Host smart-349375d1-b03f-4e94-b1f3-74a0f493ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066666304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3066666304
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2539262000
Short name T566
Test name
Test status
Simulation time 96352884 ps
CPU time 2.31 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:23 PM PDT 24
Peak memory 210176 kb
Host smart-c3ffcb11-cef9-4885-bc30-48d6560cd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539262000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2539262000
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3422402462
Short name T607
Test name
Test status
Simulation time 182032244 ps
CPU time 0.74 seconds
Started May 14 02:25:33 PM PDT 24
Finished May 14 02:25:35 PM PDT 24
Peak memory 205940 kb
Host smart-7781a208-d177-4cd9-a0cf-ac5aadfe832f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422402462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3422402462
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4250671689
Short name T197
Test name
Test status
Simulation time 343006951 ps
CPU time 4.27 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:37 PM PDT 24
Peak memory 208604 kb
Host smart-8d3b3f27-0d9b-4c95-8b24-e37fff719683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250671689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4250671689
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2765631844
Short name T510
Test name
Test status
Simulation time 1719710729 ps
CPU time 11.08 seconds
Started May 14 02:25:34 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 208996 kb
Host smart-61e3e2bf-be1c-48d9-9301-415ef5c37761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765631844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2765631844
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.862167814
Short name T283
Test name
Test status
Simulation time 33307370 ps
CPU time 2.08 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:25:35 PM PDT 24
Peak memory 214284 kb
Host smart-a17b414f-f615-442e-9b13-bd97229ee676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862167814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.862167814
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.811512352
Short name T343
Test name
Test status
Simulation time 46362397 ps
CPU time 3.25 seconds
Started May 14 02:25:33 PM PDT 24
Finished May 14 02:25:38 PM PDT 24
Peak memory 222660 kb
Host smart-ece1cbd8-ceb6-497f-9738-191c2b28b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811512352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.811512352
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.538221595
Short name T592
Test name
Test status
Simulation time 1092970394 ps
CPU time 19.13 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:51 PM PDT 24
Peak memory 214424 kb
Host smart-4d5875bd-d518-4009-b4ee-1887fed54318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538221595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.538221595
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3013886507
Short name T282
Test name
Test status
Simulation time 1601056607 ps
CPU time 39.9 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:26:13 PM PDT 24
Peak memory 218164 kb
Host smart-a52b7d8d-0aac-4bd1-9dc0-ddc7a81b4c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013886507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3013886507
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1135186435
Short name T586
Test name
Test status
Simulation time 37894878 ps
CPU time 2.56 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:23 PM PDT 24
Peak memory 208740 kb
Host smart-af62d6f1-1357-4c1a-86b2-0776675b108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135186435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1135186435
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3145798612
Short name T13
Test name
Test status
Simulation time 373906486 ps
CPU time 4.81 seconds
Started May 14 02:25:19 PM PDT 24
Finished May 14 02:25:25 PM PDT 24
Peak memory 208664 kb
Host smart-391b7760-39f6-4841-af69-0a83b636067d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145798612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3145798612
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2052212008
Short name T425
Test name
Test status
Simulation time 69180578 ps
CPU time 1.87 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:23 PM PDT 24
Peak memory 206880 kb
Host smart-fe8e1529-f645-44d0-b619-a702016e96df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052212008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2052212008
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.664903048
Short name T318
Test name
Test status
Simulation time 54350357 ps
CPU time 2.52 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:35 PM PDT 24
Peak memory 206656 kb
Host smart-0075ce09-e0d0-4137-9987-f00dc804a91b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664903048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.664903048
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3394842161
Short name T841
Test name
Test status
Simulation time 79946412 ps
CPU time 3.29 seconds
Started May 14 02:25:34 PM PDT 24
Finished May 14 02:25:38 PM PDT 24
Peak memory 214584 kb
Host smart-363f9247-4e24-4443-b83e-834e55b11e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394842161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3394842161
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3920626757
Short name T414
Test name
Test status
Simulation time 50093659 ps
CPU time 2.37 seconds
Started May 14 02:25:20 PM PDT 24
Finished May 14 02:25:24 PM PDT 24
Peak memory 206924 kb
Host smart-f1dd1e29-335a-498d-ae82-8bb107ed940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920626757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3920626757
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.264694288
Short name T75
Test name
Test status
Simulation time 5745991963 ps
CPU time 62.86 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:26:35 PM PDT 24
Peak memory 222488 kb
Host smart-193706a1-f922-47e0-a103-93e0e8411670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264694288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.264694288
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1470061636
Short name T676
Test name
Test status
Simulation time 446101949 ps
CPU time 16.81 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 222728 kb
Host smart-ca442c2c-02c2-404a-a3e1-435a02ea01fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470061636 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1470061636
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3793549659
Short name T243
Test name
Test status
Simulation time 592768885 ps
CPU time 9.18 seconds
Started May 14 02:25:30 PM PDT 24
Finished May 14 02:25:39 PM PDT 24
Peak memory 222524 kb
Host smart-230c7000-e5c3-4550-a31d-704665e324d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793549659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3793549659
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2741015836
Short name T773
Test name
Test status
Simulation time 1267281250 ps
CPU time 3.31 seconds
Started May 14 02:25:33 PM PDT 24
Finished May 14 02:25:37 PM PDT 24
Peak memory 209876 kb
Host smart-1e326c50-3961-43c7-a3e8-3c1d343f4a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741015836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2741015836
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2031761113
Short name T679
Test name
Test status
Simulation time 18040486 ps
CPU time 0.82 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:45 PM PDT 24
Peak memory 205992 kb
Host smart-cac5b6d0-63db-415e-94c5-3d9895cd6efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031761113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2031761113
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2717294819
Short name T273
Test name
Test status
Simulation time 609480226 ps
CPU time 9.2 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:25:42 PM PDT 24
Peak memory 214364 kb
Host smart-3a51b8fc-fa5e-4225-b006-f3518cc13601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717294819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2717294819
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.36383014
Short name T532
Test name
Test status
Simulation time 31373090 ps
CPU time 1.7 seconds
Started May 14 02:25:30 PM PDT 24
Finished May 14 02:25:33 PM PDT 24
Peak memory 207996 kb
Host smart-c610dc40-d138-4e89-8107-85bef7189703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36383014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.36383014
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2999194590
Short name T247
Test name
Test status
Simulation time 178733266 ps
CPU time 5.49 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:50 PM PDT 24
Peak memory 222380 kb
Host smart-ebdb9309-2c22-4754-97f5-90e8fadfa103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999194590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2999194590
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.331530746
Short name T54
Test name
Test status
Simulation time 1448197383 ps
CPU time 4.87 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:36 PM PDT 24
Peak memory 209860 kb
Host smart-41a2bc44-b809-4be9-9c69-4eb643a43822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331530746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.331530746
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1620153120
Short name T498
Test name
Test status
Simulation time 289172162 ps
CPU time 3.67 seconds
Started May 14 02:25:35 PM PDT 24
Finished May 14 02:25:39 PM PDT 24
Peak memory 207556 kb
Host smart-057a2874-0e09-46f5-9459-4cf39faa92cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620153120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1620153120
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2350508669
Short name T229
Test name
Test status
Simulation time 2042643303 ps
CPU time 15.1 seconds
Started May 14 02:25:30 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 208448 kb
Host smart-ca282e08-58a5-4e77-a266-18bcd46e2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350508669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2350508669
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3880812276
Short name T495
Test name
Test status
Simulation time 240241328 ps
CPU time 3.05 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:25:36 PM PDT 24
Peak memory 206808 kb
Host smart-5fa89eb7-174a-4fd8-bc1c-26790533837f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880812276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3880812276
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2377732880
Short name T517
Test name
Test status
Simulation time 129890147 ps
CPU time 3.1 seconds
Started May 14 02:25:32 PM PDT 24
Finished May 14 02:25:36 PM PDT 24
Peak memory 208648 kb
Host smart-5d4800fe-20ff-4506-99ee-2c1790034ca7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377732880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2377732880
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3701312400
Short name T433
Test name
Test status
Simulation time 1952787677 ps
CPU time 20.45 seconds
Started May 14 02:25:31 PM PDT 24
Finished May 14 02:25:52 PM PDT 24
Peak memory 207952 kb
Host smart-0d5731c7-4dd6-4bd1-a7ed-b1403d708a47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701312400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3701312400
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3200902980
Short name T309
Test name
Test status
Simulation time 121865054 ps
CPU time 3.45 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:47 PM PDT 24
Peak memory 218276 kb
Host smart-b13a8099-9cd1-4f32-80c1-3c0b12570cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200902980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3200902980
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1184310924
Short name T576
Test name
Test status
Simulation time 151711394 ps
CPU time 4.26 seconds
Started May 14 02:25:29 PM PDT 24
Finished May 14 02:25:33 PM PDT 24
Peak memory 208512 kb
Host smart-d4729839-bd85-4ab4-8688-b5f132bc4f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184310924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1184310924
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2122760376
Short name T437
Test name
Test status
Simulation time 396318411 ps
CPU time 10.87 seconds
Started May 14 02:25:30 PM PDT 24
Finished May 14 02:25:41 PM PDT 24
Peak memory 218364 kb
Host smart-a9a6b89f-fb91-4222-bc23-6decbbbae314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122760376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2122760376
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1412517559
Short name T66
Test name
Test status
Simulation time 172832368 ps
CPU time 2.92 seconds
Started May 14 02:25:39 PM PDT 24
Finished May 14 02:25:43 PM PDT 24
Peak memory 210544 kb
Host smart-e5f9ceed-7d99-417c-a69c-2580bfebce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412517559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1412517559
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1929109640
Short name T444
Test name
Test status
Simulation time 32122636 ps
CPU time 0.76 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:43 PM PDT 24
Peak memory 206024 kb
Host smart-476b9dc1-c793-494b-aaee-c7cb4a85d930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929109640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1929109640
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.168478467
Short name T619
Test name
Test status
Simulation time 69493668 ps
CPU time 2.79 seconds
Started May 14 02:25:39 PM PDT 24
Finished May 14 02:25:43 PM PDT 24
Peak memory 221860 kb
Host smart-efe1faf0-5fe1-4442-9db1-9b0a50b722dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168478467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.168478467
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.151490612
Short name T830
Test name
Test status
Simulation time 116575495 ps
CPU time 2.25 seconds
Started May 14 02:25:41 PM PDT 24
Finished May 14 02:25:45 PM PDT 24
Peak memory 218464 kb
Host smart-69aaf777-80e3-4878-a1e9-757fddc884b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151490612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.151490612
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2625717436
Short name T210
Test name
Test status
Simulation time 1735727908 ps
CPU time 5.61 seconds
Started May 14 02:25:39 PM PDT 24
Finished May 14 02:25:47 PM PDT 24
Peak memory 214404 kb
Host smart-5f3281c0-17a9-4010-b63b-c7cee064cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625717436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2625717436
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3149793167
Short name T250
Test name
Test status
Simulation time 469123320 ps
CPU time 3.6 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:48 PM PDT 24
Peak memory 214256 kb
Host smart-07bdac59-ab86-48e9-a722-df67019dfd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149793167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3149793167
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1919655205
Short name T63
Test name
Test status
Simulation time 473478942 ps
CPU time 3.76 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 218644 kb
Host smart-0b178c69-7ac1-4eae-af53-e2754a0a28f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919655205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1919655205
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3846444987
Short name T790
Test name
Test status
Simulation time 133021800 ps
CPU time 4.63 seconds
Started May 14 02:25:38 PM PDT 24
Finished May 14 02:25:44 PM PDT 24
Peak memory 207556 kb
Host smart-ed7366a8-e100-4de9-b941-46f4ed4f262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846444987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3846444987
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2710017134
Short name T786
Test name
Test status
Simulation time 227965789 ps
CPU time 3.99 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 207000 kb
Host smart-2cda7353-d985-423e-8f3a-1564c1fae692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710017134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2710017134
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.916649331
Short name T475
Test name
Test status
Simulation time 228885289 ps
CPU time 3.23 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:45 PM PDT 24
Peak memory 206936 kb
Host smart-d4a87687-d38f-48c2-8137-825aaf73af63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916649331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.916649331
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2782027743
Short name T725
Test name
Test status
Simulation time 98650571 ps
CPU time 2.17 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:25:47 PM PDT 24
Peak memory 208684 kb
Host smart-6758ba0e-6247-416d-a897-5ebcc81b9605
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782027743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2782027743
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3031485730
Short name T231
Test name
Test status
Simulation time 128647862 ps
CPU time 4.07 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 208528 kb
Host smart-ac3d8024-5520-4aa9-bf6f-3f97c4302e4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031485730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3031485730
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.612273687
Short name T176
Test name
Test status
Simulation time 252737189 ps
CPU time 6.21 seconds
Started May 14 02:25:41 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 214280 kb
Host smart-2af05602-4bfd-4fc1-b6b4-01e80c5282a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612273687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.612273687
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2680348784
Short name T845
Test name
Test status
Simulation time 404424522 ps
CPU time 4.46 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 206832 kb
Host smart-65c7b38f-5336-4fd4-a946-f530ac2df2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680348784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2680348784
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.784676144
Short name T505
Test name
Test status
Simulation time 112898700 ps
CPU time 4.27 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 214296 kb
Host smart-18e45823-0bb1-481a-9a94-fd52c11959d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784676144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.784676144
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.663802283
Short name T552
Test name
Test status
Simulation time 93459562 ps
CPU time 1.47 seconds
Started May 14 02:25:41 PM PDT 24
Finished May 14 02:25:45 PM PDT 24
Peak memory 210792 kb
Host smart-11040e86-aa99-4e65-a559-4ee46216101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663802283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.663802283
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.945105916
Short name T469
Test name
Test status
Simulation time 14574182 ps
CPU time 0.89 seconds
Started May 14 02:25:52 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 206100 kb
Host smart-1f0a6462-2908-4fca-8c3c-ec928c3869a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945105916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.945105916
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3991795554
Short name T847
Test name
Test status
Simulation time 317018746 ps
CPU time 9.49 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:26:01 PM PDT 24
Peak memory 218308 kb
Host smart-f67eaa17-c0ae-489d-87cf-4d43089a36dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991795554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3991795554
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2296593804
Short name T64
Test name
Test status
Simulation time 79823308 ps
CPU time 3.61 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:48 PM PDT 24
Peak memory 210316 kb
Host smart-e6ca7fc2-b6ac-4438-8ebd-a54576697f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296593804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2296593804
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2328513395
Short name T825
Test name
Test status
Simulation time 330375892 ps
CPU time 3.82 seconds
Started May 14 02:25:49 PM PDT 24
Finished May 14 02:25:53 PM PDT 24
Peak memory 214256 kb
Host smart-814ed367-efec-4779-9c3d-91c5e8948a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328513395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2328513395
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.772561915
Short name T39
Test name
Test status
Simulation time 846456472 ps
CPU time 3.89 seconds
Started May 14 02:25:53 PM PDT 24
Finished May 14 02:25:58 PM PDT 24
Peak memory 219624 kb
Host smart-cdef88a4-447b-4fda-a858-cca2a87ab0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772561915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.772561915
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_random.2370697720
Short name T215
Test name
Test status
Simulation time 315435556 ps
CPU time 5.8 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:25:51 PM PDT 24
Peak memory 210240 kb
Host smart-3c4c488e-e329-4e0a-87b2-814d753cbd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370697720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2370697720
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1079630265
Short name T445
Test name
Test status
Simulation time 133830501 ps
CPU time 1.72 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:46 PM PDT 24
Peak memory 207116 kb
Host smart-cd1ab427-8cd8-4688-bd16-9656dc2ee717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079630265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1079630265
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.461767519
Short name T83
Test name
Test status
Simulation time 187396652 ps
CPU time 3.42 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:48 PM PDT 24
Peak memory 208648 kb
Host smart-731b8348-67e8-4e42-91e7-f0c92a9db519
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461767519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.461767519
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1911962913
Short name T308
Test name
Test status
Simulation time 686511855 ps
CPU time 4.89 seconds
Started May 14 02:25:42 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 208444 kb
Host smart-4b3d6575-d90b-4036-a0f8-7831c2a21f0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911962913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1911962913
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3453255571
Short name T260
Test name
Test status
Simulation time 65354114 ps
CPU time 2.9 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:25:45 PM PDT 24
Peak memory 207032 kb
Host smart-b5bd092e-64e6-45e0-bc3f-1998fb86c052
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453255571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3453255571
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3281018185
Short name T452
Test name
Test status
Simulation time 1759212427 ps
CPU time 22.67 seconds
Started May 14 02:25:53 PM PDT 24
Finished May 14 02:26:17 PM PDT 24
Peak memory 218276 kb
Host smart-8ead47f6-ffcc-4346-ae84-1c84b72b5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281018185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3281018185
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.546851770
Short name T463
Test name
Test status
Simulation time 218488832 ps
CPU time 2.95 seconds
Started May 14 02:25:43 PM PDT 24
Finished May 14 02:25:48 PM PDT 24
Peak memory 208552 kb
Host smart-5122939c-35e4-4b0f-8e83-dc9cd1d8b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546851770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.546851770
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3535307006
Short name T167
Test name
Test status
Simulation time 7716818895 ps
CPU time 52.28 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 216004 kb
Host smart-4a67f474-b51c-480d-b1a2-89ffff2596d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535307006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3535307006
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2032023887
Short name T738
Test name
Test status
Simulation time 109303020 ps
CPU time 6.29 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:26:00 PM PDT 24
Peak memory 219800 kb
Host smart-c0a32a87-47e4-417b-baed-303ba0370cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032023887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2032023887
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3166109313
Short name T440
Test name
Test status
Simulation time 892952173 ps
CPU time 22.91 seconds
Started May 14 02:25:40 PM PDT 24
Finished May 14 02:26:05 PM PDT 24
Peak memory 209896 kb
Host smart-bcca89af-8e89-4c5f-8184-f17c822695c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166109313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3166109313
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1396249280
Short name T155
Test name
Test status
Simulation time 354698139 ps
CPU time 1.69 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:54 PM PDT 24
Peak memory 209756 kb
Host smart-d46eabca-74a5-4d37-8bbe-d381c42b0e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396249280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1396249280
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.823821053
Short name T95
Test name
Test status
Simulation time 75609564 ps
CPU time 0.71 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:14 PM PDT 24
Peak memory 205944 kb
Host smart-64e1ca0c-2585-4439-9d6c-c099b829fd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823821053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.823821053
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2068841489
Short name T396
Test name
Test status
Simulation time 159229989 ps
CPU time 2.51 seconds
Started May 14 02:20:02 PM PDT 24
Finished May 14 02:20:05 PM PDT 24
Peak memory 214308 kb
Host smart-2e245cb5-3c95-465c-9fe4-b1ff9073a655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068841489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2068841489
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2693748899
Short name T747
Test name
Test status
Simulation time 140132494 ps
CPU time 4.93 seconds
Started May 14 02:20:16 PM PDT 24
Finished May 14 02:20:22 PM PDT 24
Peak memory 214588 kb
Host smart-2385e326-a1fb-491c-b8da-e7f7964029d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693748899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2693748899
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2309510841
Short name T596
Test name
Test status
Simulation time 128123578 ps
CPU time 1.7 seconds
Started May 14 02:20:02 PM PDT 24
Finished May 14 02:20:04 PM PDT 24
Peak memory 208212 kb
Host smart-17b20bc4-da5c-4414-832f-3c8dc5bc69c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309510841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2309510841
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2473805061
Short name T342
Test name
Test status
Simulation time 381191473 ps
CPU time 3.66 seconds
Started May 14 02:20:02 PM PDT 24
Finished May 14 02:20:07 PM PDT 24
Peak memory 214304 kb
Host smart-2075486f-48d7-4884-9cdb-6a3574367a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473805061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2473805061
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3181306613
Short name T804
Test name
Test status
Simulation time 90626733 ps
CPU time 3.21 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:16 PM PDT 24
Peak memory 217160 kb
Host smart-b8aaf8bb-9514-42bb-836a-fdcc9f7942b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181306613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3181306613
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1332471527
Short name T70
Test name
Test status
Simulation time 311519376 ps
CPU time 5.39 seconds
Started May 14 02:20:03 PM PDT 24
Finished May 14 02:20:09 PM PDT 24
Peak memory 220380 kb
Host smart-6ad5ec3f-f9c5-4d32-b33c-f50d2efd393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332471527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1332471527
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.345854847
Short name T450
Test name
Test status
Simulation time 206275547 ps
CPU time 7.5 seconds
Started May 14 02:20:04 PM PDT 24
Finished May 14 02:20:13 PM PDT 24
Peak memory 207732 kb
Host smart-a521b087-c33a-4077-b923-6a30933ed634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345854847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.345854847
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1233768619
Short name T567
Test name
Test status
Simulation time 213995040 ps
CPU time 2.99 seconds
Started May 14 02:20:03 PM PDT 24
Finished May 14 02:20:07 PM PDT 24
Peak memory 208608 kb
Host smart-462ea93e-d10c-4b3f-9df7-1cabeff57122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233768619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1233768619
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3319210328
Short name T723
Test name
Test status
Simulation time 139504101 ps
CPU time 4.44 seconds
Started May 14 02:20:05 PM PDT 24
Finished May 14 02:20:10 PM PDT 24
Peak memory 207008 kb
Host smart-3d1b1b86-b3ec-48f1-b583-a80b971e409b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319210328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3319210328
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.577008250
Short name T456
Test name
Test status
Simulation time 974312711 ps
CPU time 32.13 seconds
Started May 14 02:20:03 PM PDT 24
Finished May 14 02:20:36 PM PDT 24
Peak memory 207864 kb
Host smart-fa151084-9125-422a-9c10-7764a7780e59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577008250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.577008250
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1816245802
Short name T382
Test name
Test status
Simulation time 309968146 ps
CPU time 3.61 seconds
Started May 14 02:20:02 PM PDT 24
Finished May 14 02:20:07 PM PDT 24
Peak memory 208676 kb
Host smart-f071f226-042e-4cee-b6e3-844b5d8be9e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816245802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1816245802
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2005282800
Short name T238
Test name
Test status
Simulation time 100030919 ps
CPU time 1.39 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:15 PM PDT 24
Peak memory 208104 kb
Host smart-5c175fe9-0508-4771-ac85-73e1e278679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005282800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2005282800
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.938484278
Short name T893
Test name
Test status
Simulation time 511055383 ps
CPU time 3.2 seconds
Started May 14 02:20:04 PM PDT 24
Finished May 14 02:20:08 PM PDT 24
Peak memory 206704 kb
Host smart-68763a9c-4420-4c4f-9746-f518a2fbb0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938484278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.938484278
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4122214224
Short name T890
Test name
Test status
Simulation time 1630182057 ps
CPU time 31.72 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:44 PM PDT 24
Peak memory 215032 kb
Host smart-c1fa59d0-501b-46a4-a80a-0af32656dda7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122214224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4122214224
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4090223543
Short name T479
Test name
Test status
Simulation time 498137592 ps
CPU time 7.44 seconds
Started May 14 02:20:03 PM PDT 24
Finished May 14 02:20:11 PM PDT 24
Peak memory 208168 kb
Host smart-49e74036-5da7-4af2-a4ca-ace7cc1ea685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090223543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4090223543
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1814537614
Short name T703
Test name
Test status
Simulation time 83753113 ps
CPU time 2.12 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:14 PM PDT 24
Peak memory 210240 kb
Host smart-f987f36b-1d41-4fd6-88c3-80ce87e9f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814537614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1814537614
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2085076113
Short name T477
Test name
Test status
Simulation time 10125514 ps
CPU time 0.81 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:53 PM PDT 24
Peak memory 205988 kb
Host smart-b8ab09a1-e3a8-4af2-907d-e53632069800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085076113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2085076113
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2352292487
Short name T132
Test name
Test status
Simulation time 174608915 ps
CPU time 3.82 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 214360 kb
Host smart-0064e777-1da5-476f-b176-e2106fb7223e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352292487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2352292487
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3882486058
Short name T161
Test name
Test status
Simulation time 309155420 ps
CPU time 7.53 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:26:00 PM PDT 24
Peak memory 222828 kb
Host smart-319229b6-c965-4a2e-bad3-3ec0e4ceab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882486058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3882486058
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4249413565
Short name T875
Test name
Test status
Simulation time 127143220 ps
CPU time 2.51 seconds
Started May 14 02:25:52 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 206956 kb
Host smart-d4889d66-eedb-4f6b-8f88-e6578b8c0067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249413565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4249413565
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.903683716
Short name T758
Test name
Test status
Simulation time 217662756 ps
CPU time 4.05 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:56 PM PDT 24
Peak memory 210284 kb
Host smart-64f04e31-61eb-4933-8a65-f8d6ad249e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903683716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.903683716
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2820690509
Short name T717
Test name
Test status
Simulation time 1541925559 ps
CPU time 6.67 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:59 PM PDT 24
Peak memory 214360 kb
Host smart-97ce1404-71e1-4735-bf8c-44946acb54bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820690509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2820690509
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2245012268
Short name T345
Test name
Test status
Simulation time 84609230 ps
CPU time 2.48 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 208512 kb
Host smart-b6b7726d-74f5-47af-9bce-3507d785dbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245012268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2245012268
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1260154006
Short name T720
Test name
Test status
Simulation time 36221110 ps
CPU time 1.88 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 206868 kb
Host smart-7d252325-0eb2-4a5b-ac59-a94617822354
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260154006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1260154006
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.184729447
Short name T615
Test name
Test status
Simulation time 1184785717 ps
CPU time 22.02 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:26:15 PM PDT 24
Peak memory 209076 kb
Host smart-9695518c-e362-430f-8fe8-2c86af7f7d29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184729447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.184729447
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1143404899
Short name T435
Test name
Test status
Simulation time 2420266412 ps
CPU time 7.37 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:59 PM PDT 24
Peak memory 208000 kb
Host smart-b17ed1de-a4d5-42a6-8885-f28f61b9e79e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143404899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1143404899
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3381454987
Short name T402
Test name
Test status
Simulation time 38498048 ps
CPU time 2.72 seconds
Started May 14 02:25:53 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 209988 kb
Host smart-e223118d-cd10-4f8f-936c-4f1310a40b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381454987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3381454987
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3166311987
Short name T764
Test name
Test status
Simulation time 555957331 ps
CPU time 3.76 seconds
Started May 14 02:25:49 PM PDT 24
Finished May 14 02:25:54 PM PDT 24
Peak memory 206664 kb
Host smart-75ea5084-762a-417a-a396-f9fd468dd370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166311987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3166311987
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2360765567
Short name T712
Test name
Test status
Simulation time 310835414 ps
CPU time 11.3 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:26:05 PM PDT 24
Peak memory 209244 kb
Host smart-b38a4849-d486-4ea1-8a8b-70c61503395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360765567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2360765567
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.888815863
Short name T369
Test name
Test status
Simulation time 409700071 ps
CPU time 1.64 seconds
Started May 14 02:25:49 PM PDT 24
Finished May 14 02:25:52 PM PDT 24
Peak memory 209848 kb
Host smart-470272bc-bfc3-4eea-8068-36d023b970d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888815863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.888815863
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3311177156
Short name T472
Test name
Test status
Simulation time 16582063 ps
CPU time 0.76 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:06 PM PDT 24
Peak memory 205844 kb
Host smart-c5ef2052-3e36-4d57-b949-59a2319c3c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311177156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3311177156
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3326636303
Short name T833
Test name
Test status
Simulation time 66127774 ps
CPU time 1.6 seconds
Started May 14 02:25:52 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 208124 kb
Host smart-eb2a761b-53fa-487a-95f9-7fac0451e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326636303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3326636303
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4086105887
Short name T300
Test name
Test status
Simulation time 200935913 ps
CPU time 2.4 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:12 PM PDT 24
Peak memory 214356 kb
Host smart-82314b51-6bbe-4017-a792-c1a7dbca65b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086105887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4086105887
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3444776519
Short name T248
Test name
Test status
Simulation time 74536889 ps
CPU time 3.53 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:09 PM PDT 24
Peak memory 214212 kb
Host smart-ef9bb08b-b9a9-47e2-bdf5-c4dfe2706bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444776519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3444776519
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3085080043
Short name T554
Test name
Test status
Simulation time 246790462 ps
CPU time 2.09 seconds
Started May 14 02:25:47 PM PDT 24
Finished May 14 02:25:49 PM PDT 24
Peak memory 206628 kb
Host smart-c2bff271-5d6f-4c76-8465-e94b78b47547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085080043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3085080043
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3247739133
Short name T494
Test name
Test status
Simulation time 44589892 ps
CPU time 3.28 seconds
Started May 14 02:25:51 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 218472 kb
Host smart-bc7d7ba6-d31f-4122-8dd3-3d27975bf92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247739133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3247739133
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.579333463
Short name T175
Test name
Test status
Simulation time 41758533 ps
CPU time 2.42 seconds
Started May 14 02:25:53 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 206896 kb
Host smart-480ca9de-64f7-4fe4-a8ca-af482dca4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579333463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.579333463
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3340983045
Short name T655
Test name
Test status
Simulation time 62711547 ps
CPU time 3.13 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 208216 kb
Host smart-2547c4ee-34ef-4a6e-bd36-aba8ca6f348b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340983045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3340983045
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.466988387
Short name T811
Test name
Test status
Simulation time 307420962 ps
CPU time 3.28 seconds
Started May 14 02:25:52 PM PDT 24
Finished May 14 02:25:57 PM PDT 24
Peak memory 209216 kb
Host smart-6dd289d6-bf25-4714-a321-a715a2c38e69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466988387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.466988387
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3937152917
Short name T797
Test name
Test status
Simulation time 201395791 ps
CPU time 2.84 seconds
Started May 14 02:25:50 PM PDT 24
Finished May 14 02:25:55 PM PDT 24
Peak memory 206956 kb
Host smart-0ea8bd89-12bd-47bf-9bb0-b0e9e4a44e05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937152917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3937152917
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3986070493
Short name T564
Test name
Test status
Simulation time 108326426 ps
CPU time 2 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:07 PM PDT 24
Peak memory 208484 kb
Host smart-f9118570-34a2-4848-893e-75f1f63c1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986070493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3986070493
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3626116474
Short name T465
Test name
Test status
Simulation time 40278946 ps
CPU time 2.52 seconds
Started May 14 02:25:49 PM PDT 24
Finished May 14 02:25:54 PM PDT 24
Peak memory 208648 kb
Host smart-fbf3451e-ac38-4c96-9d11-81af737bcd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626116474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3626116474
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.591423655
Short name T202
Test name
Test status
Simulation time 2174431302 ps
CPU time 34.45 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:40 PM PDT 24
Peak memory 216676 kb
Host smart-a497e802-a9f3-4cae-ae26-82cb3cca8f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591423655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.591423655
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2445252011
Short name T58
Test name
Test status
Simulation time 839681210 ps
CPU time 10.63 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:17 PM PDT 24
Peak memory 222732 kb
Host smart-2651067e-b2aa-40ab-ada5-9486bc5482d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445252011 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2445252011
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1251657180
Short name T212
Test name
Test status
Simulation time 42698101 ps
CPU time 2.83 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:09 PM PDT 24
Peak memory 208292 kb
Host smart-133b25de-f936-4cd0-9594-404832bd2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251657180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1251657180
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2091174884
Short name T821
Test name
Test status
Simulation time 12660168 ps
CPU time 0.88 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:09 PM PDT 24
Peak memory 205972 kb
Host smart-ea26a5d1-23ce-4167-a2ca-c1fb5b8e11b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091174884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2091174884
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3729625276
Short name T263
Test name
Test status
Simulation time 101259349 ps
CPU time 3.98 seconds
Started May 14 02:26:03 PM PDT 24
Finished May 14 02:26:08 PM PDT 24
Peak memory 214364 kb
Host smart-87291436-4ef7-49c5-b754-26e4cd340620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729625276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3729625276
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.861441097
Short name T36
Test name
Test status
Simulation time 137417090 ps
CPU time 2.07 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 218144 kb
Host smart-62a163ac-4265-446e-9fbd-1fbf35b3b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861441097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.861441097
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3633468933
Short name T718
Test name
Test status
Simulation time 306452854 ps
CPU time 3.67 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 207864 kb
Host smart-30d89e59-ca65-4541-b69d-c5079f5ecdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633468933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3633468933
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2373041033
Short name T659
Test name
Test status
Simulation time 52893997 ps
CPU time 1.83 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:10 PM PDT 24
Peak memory 215268 kb
Host smart-67eeb5a7-dfc8-4df2-8fc2-7c1971e8f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373041033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2373041033
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1825938534
Short name T326
Test name
Test status
Simulation time 95629212 ps
CPU time 4.18 seconds
Started May 14 02:26:12 PM PDT 24
Finished May 14 02:26:17 PM PDT 24
Peak memory 214216 kb
Host smart-07208d05-3ee4-49e0-9dce-b8a150ef7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825938534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1825938534
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2035253719
Short name T838
Test name
Test status
Simulation time 2872052805 ps
CPU time 15.44 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:25 PM PDT 24
Peak memory 208972 kb
Host smart-553e0f72-737f-4532-b084-b130437ad0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035253719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2035253719
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1750047729
Short name T862
Test name
Test status
Simulation time 238325230 ps
CPU time 6.4 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:12 PM PDT 24
Peak memory 209084 kb
Host smart-4fd61132-b428-45da-8e11-9ef28e724ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750047729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1750047729
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1121314630
Short name T486
Test name
Test status
Simulation time 223583425 ps
CPU time 3.29 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:09 PM PDT 24
Peak memory 208304 kb
Host smart-6cab4924-6931-4fc1-a028-fd6ce0b9e015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121314630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1121314630
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.785148851
Short name T597
Test name
Test status
Simulation time 21335211 ps
CPU time 1.98 seconds
Started May 14 02:26:03 PM PDT 24
Finished May 14 02:26:05 PM PDT 24
Peak memory 207012 kb
Host smart-4eea32e9-3917-42c7-b158-c513ca9794dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785148851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.785148851
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2704095935
Short name T639
Test name
Test status
Simulation time 245220897 ps
CPU time 3.07 seconds
Started May 14 02:26:04 PM PDT 24
Finished May 14 02:26:09 PM PDT 24
Peak memory 208716 kb
Host smart-13491be4-3de1-4804-a547-e67a64728b1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704095935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2704095935
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1902491801
Short name T614
Test name
Test status
Simulation time 124344435 ps
CPU time 1.59 seconds
Started May 14 02:26:06 PM PDT 24
Finished May 14 02:26:08 PM PDT 24
Peak memory 207008 kb
Host smart-33f4f4ce-7074-4ced-837e-b71d0a2ab2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902491801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1902491801
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3845036165
Short name T695
Test name
Test status
Simulation time 68640026 ps
CPU time 3.32 seconds
Started May 14 02:26:03 PM PDT 24
Finished May 14 02:26:06 PM PDT 24
Peak memory 208748 kb
Host smart-36d28d8f-f194-45d5-a1ee-a38ea984d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845036165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3845036165
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2097912497
Short name T314
Test name
Test status
Simulation time 932114330 ps
CPU time 21.57 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:31 PM PDT 24
Peak memory 208156 kb
Host smart-e666d34f-b5f4-4c88-ac9b-a91f8f5e4146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097912497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2097912497
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3795429908
Short name T367
Test name
Test status
Simulation time 285303375 ps
CPU time 5.14 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:15 PM PDT 24
Peak memory 210504 kb
Host smart-5259cc92-9fe3-427a-a5aa-6a2263232d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795429908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3795429908
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3523850048
Short name T516
Test name
Test status
Simulation time 19539262 ps
CPU time 1.06 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 206140 kb
Host smart-8dc65e61-83a6-45fe-85ba-b2e67caf73c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523850048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3523850048
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2474840953
Short name T854
Test name
Test status
Simulation time 643571962 ps
CPU time 3.21 seconds
Started May 14 02:26:12 PM PDT 24
Finished May 14 02:26:16 PM PDT 24
Peak memory 221884 kb
Host smart-d2f94368-e542-41e4-a042-84778388dc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474840953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2474840953
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4118083899
Short name T697
Test name
Test status
Simulation time 20999066 ps
CPU time 1.79 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 206936 kb
Host smart-1feb4d41-e99d-4e59-95ca-159531a130b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118083899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4118083899
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3538387325
Short name T91
Test name
Test status
Simulation time 112927637 ps
CPU time 5.52 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:14 PM PDT 24
Peak memory 221244 kb
Host smart-1c9e8275-45d2-4a71-8c5a-0376b029ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538387325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3538387325
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3235694296
Short name T905
Test name
Test status
Simulation time 64793220 ps
CPU time 1.55 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 214252 kb
Host smart-89ede12c-1718-4aaa-bc57-71157ed6f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235694296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3235694296
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2952759473
Short name T870
Test name
Test status
Simulation time 136168455 ps
CPU time 3.46 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:13 PM PDT 24
Peak memory 215588 kb
Host smart-e84c52bf-9620-43f6-8539-1b34f0384289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952759473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2952759473
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.256760072
Short name T785
Test name
Test status
Simulation time 334100259 ps
CPU time 7.73 seconds
Started May 14 02:26:06 PM PDT 24
Finished May 14 02:26:15 PM PDT 24
Peak memory 214360 kb
Host smart-1fa2db78-bfc6-4d87-bc5d-de4702d97aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256760072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.256760072
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.358509472
Short name T714
Test name
Test status
Simulation time 255334095 ps
CPU time 3.38 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:14 PM PDT 24
Peak memory 206916 kb
Host smart-bd450d86-1fa6-40b2-93f1-9612d3749892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358509472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.358509472
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1713973601
Short name T859
Test name
Test status
Simulation time 275163354 ps
CPU time 3.47 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:13 PM PDT 24
Peak memory 208960 kb
Host smart-585eac96-bc82-481a-8f97-e403d7150edb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713973601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1713973601
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3230708505
Short name T741
Test name
Test status
Simulation time 46070465 ps
CPU time 2.36 seconds
Started May 14 02:26:08 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 207052 kb
Host smart-0eeb5341-625c-470b-b2ee-ecbad726a1bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230708505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3230708505
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3867529272
Short name T650
Test name
Test status
Simulation time 519945837 ps
CPU time 4.03 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 208560 kb
Host smart-5694efb6-d7ad-474d-9453-0930ad594f93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867529272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3867529272
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3802852288
Short name T664
Test name
Test status
Simulation time 86170956 ps
CPU time 2.44 seconds
Started May 14 02:26:07 PM PDT 24
Finished May 14 02:26:11 PM PDT 24
Peak memory 208060 kb
Host smart-10273ac1-d326-412b-9ffe-e7b38033411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802852288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3802852288
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1640402921
Short name T766
Test name
Test status
Simulation time 100582858 ps
CPU time 2.72 seconds
Started May 14 02:26:06 PM PDT 24
Finished May 14 02:26:10 PM PDT 24
Peak memory 206864 kb
Host smart-1ead8135-0d3a-4347-9e8f-665b9dae22ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640402921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1640402921
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2401320321
Short name T305
Test name
Test status
Simulation time 1398034124 ps
CPU time 9.46 seconds
Started May 14 02:26:12 PM PDT 24
Finished May 14 02:26:22 PM PDT 24
Peak memory 214368 kb
Host smart-684bfd30-c78c-4e20-be9a-9bd26edaeda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401320321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2401320321
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.53276256
Short name T647
Test name
Test status
Simulation time 407094739 ps
CPU time 4.05 seconds
Started May 14 02:26:09 PM PDT 24
Finished May 14 02:26:14 PM PDT 24
Peak memory 214244 kb
Host smart-bb9b2907-afa4-4df3-9cf9-e970c8d472c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53276256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.53276256
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3444701465
Short name T682
Test name
Test status
Simulation time 121703173 ps
CPU time 0.77 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:18 PM PDT 24
Peak memory 205984 kb
Host smart-ac11c23b-fd0f-4517-8a37-38b577fe58cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444701465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3444701465
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.792214710
Short name T239
Test name
Test status
Simulation time 997224607 ps
CPU time 14.01 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 215712 kb
Host smart-dd15bf93-f23d-4063-95da-cace6db464b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792214710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.792214710
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3186801373
Short name T27
Test name
Test status
Simulation time 1134704166 ps
CPU time 2.92 seconds
Started May 14 02:26:18 PM PDT 24
Finished May 14 02:26:23 PM PDT 24
Peak memory 208884 kb
Host smart-9f8cc151-d85e-41de-bdca-74c950785a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186801373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3186801373
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.787142269
Short name T772
Test name
Test status
Simulation time 228933819 ps
CPU time 6.1 seconds
Started May 14 02:26:20 PM PDT 24
Finished May 14 02:26:27 PM PDT 24
Peak memory 214448 kb
Host smart-107f77f6-0b96-4054-b46a-aea62c5b124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787142269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.787142269
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3877129978
Short name T535
Test name
Test status
Simulation time 227313701 ps
CPU time 2.8 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:21 PM PDT 24
Peak memory 214388 kb
Host smart-7422024c-bc0d-476a-9dac-76b574428415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877129978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3877129978
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3056252926
Short name T876
Test name
Test status
Simulation time 73879969 ps
CPU time 3.15 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:22 PM PDT 24
Peak memory 207140 kb
Host smart-9f46b370-4075-4fd1-9a25-a30ce96e259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056252926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3056252926
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2585360391
Short name T550
Test name
Test status
Simulation time 58034664 ps
CPU time 2.32 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 207612 kb
Host smart-31475ad5-2f3c-4bad-b75f-1474190e1be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585360391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2585360391
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3992962754
Short name T442
Test name
Test status
Simulation time 803593646 ps
CPU time 5.89 seconds
Started May 14 02:26:18 PM PDT 24
Finished May 14 02:26:25 PM PDT 24
Peak memory 206880 kb
Host smart-4743c6cb-9629-4356-96b1-76c5518983fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992962754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3992962754
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.167259191
Short name T681
Test name
Test status
Simulation time 24481044 ps
CPU time 2.03 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:18 PM PDT 24
Peak memory 208596 kb
Host smart-3563baf3-1244-4984-ae55-ef9185886ad4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167259191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.167259191
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3751146538
Short name T501
Test name
Test status
Simulation time 141154702 ps
CPU time 3.94 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:22 PM PDT 24
Peak memory 208632 kb
Host smart-e3fb8f0b-0aec-4da2-8e35-0f5b31ffc689
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751146538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3751146538
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2603019958
Short name T872
Test name
Test status
Simulation time 42232491 ps
CPU time 1.83 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:19 PM PDT 24
Peak memory 206756 kb
Host smart-fa43ad38-b774-4be0-84a7-1c87c949a95e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603019958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2603019958
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3754515413
Short name T874
Test name
Test status
Simulation time 62127504 ps
CPU time 2.44 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 207784 kb
Host smart-7947a772-1b73-47c5-aa80-4c932564e589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754515413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3754515413
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.733842983
Short name T776
Test name
Test status
Simulation time 2111333673 ps
CPU time 20.02 seconds
Started May 14 02:26:19 PM PDT 24
Finished May 14 02:26:40 PM PDT 24
Peak memory 208724 kb
Host smart-c2a29ee3-de9d-47dd-896f-3fdf97101c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733842983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.733842983
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3695653332
Short name T600
Test name
Test status
Simulation time 173494876 ps
CPU time 3.03 seconds
Started May 14 02:26:23 PM PDT 24
Finished May 14 02:26:26 PM PDT 24
Peak memory 216128 kb
Host smart-5e4dbc9d-336d-4da0-af01-8a7c76026aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695653332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3695653332
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2825526446
Short name T806
Test name
Test status
Simulation time 206420257 ps
CPU time 4.91 seconds
Started May 14 02:26:19 PM PDT 24
Finished May 14 02:26:25 PM PDT 24
Peak memory 210336 kb
Host smart-81a503ad-6e22-43d7-b09c-815bf1b53fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825526446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2825526446
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4066687266
Short name T506
Test name
Test status
Simulation time 11139900 ps
CPU time 0.86 seconds
Started May 14 02:26:26 PM PDT 24
Finished May 14 02:26:28 PM PDT 24
Peak memory 206028 kb
Host smart-97223fc9-aa22-42c4-b32a-0f8aa8b1a7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066687266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4066687266
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.853560979
Short name T317
Test name
Test status
Simulation time 2498492554 ps
CPU time 33.96 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:51 PM PDT 24
Peak memory 214368 kb
Host smart-a651c3c3-165f-4a32-a53b-65908a886979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853560979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.853560979
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.418511404
Short name T72
Test name
Test status
Simulation time 352837754 ps
CPU time 4.64 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:21 PM PDT 24
Peak memory 209224 kb
Host smart-db6556d5-f9ea-4b4a-8893-4d6f22209fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418511404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.418511404
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1055329486
Short name T522
Test name
Test status
Simulation time 180098871 ps
CPU time 4.59 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:22 PM PDT 24
Peak memory 209336 kb
Host smart-5721aa60-29ca-45c9-b4d8-0b90f7f94e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055329486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1055329486
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3670783690
Short name T90
Test name
Test status
Simulation time 123384096 ps
CPU time 4.16 seconds
Started May 14 02:26:18 PM PDT 24
Finished May 14 02:26:24 PM PDT 24
Peak memory 214328 kb
Host smart-040f0f81-cedb-4fed-8d7e-39368629005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670783690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3670783690
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2847916130
Short name T321
Test name
Test status
Simulation time 2458015817 ps
CPU time 17.11 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:36 PM PDT 24
Peak memory 214220 kb
Host smart-e7f2a7db-7e42-4c87-9abd-682b1539c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847916130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2847916130
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3464406806
Short name T206
Test name
Test status
Simulation time 58427705 ps
CPU time 2.99 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:21 PM PDT 24
Peak memory 214404 kb
Host smart-b305dbc9-1cd1-4c4a-9e84-5749a10f5614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464406806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3464406806
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.663581521
Short name T594
Test name
Test status
Simulation time 109013499 ps
CPU time 4.58 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:21 PM PDT 24
Peak memory 207320 kb
Host smart-c0a004f9-855a-4bf2-8b10-c03c1d1ed980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663581521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.663581521
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2126272063
Short name T298
Test name
Test status
Simulation time 133431021 ps
CPU time 2.49 seconds
Started May 14 02:26:20 PM PDT 24
Finished May 14 02:26:23 PM PDT 24
Peak memory 206860 kb
Host smart-c6b449ea-77f4-4de7-9eec-a78a7daa7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126272063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2126272063
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.524950580
Short name T803
Test name
Test status
Simulation time 92620451 ps
CPU time 2 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 207792 kb
Host smart-b2887a02-1756-4109-a370-47574c08f92f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524950580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.524950580
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1152391123
Short name T601
Test name
Test status
Simulation time 126516453 ps
CPU time 2.92 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 208648 kb
Host smart-eb2430aa-098b-49d0-a2bd-00681f6f24f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152391123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1152391123
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1245617933
Short name T651
Test name
Test status
Simulation time 154260877 ps
CPU time 2.97 seconds
Started May 14 02:26:15 PM PDT 24
Finished May 14 02:26:19 PM PDT 24
Peak memory 206932 kb
Host smart-54ce2f80-4d22-4134-a7d2-863d50dad47b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245617933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1245617933
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3956185164
Short name T331
Test name
Test status
Simulation time 458761822 ps
CPU time 4.88 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:26:36 PM PDT 24
Peak memory 220456 kb
Host smart-5f071b15-307f-46e7-95b0-03503c3343af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956185164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3956185164
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4243113412
Short name T557
Test name
Test status
Simulation time 2951273894 ps
CPU time 32.99 seconds
Started May 14 02:26:16 PM PDT 24
Finished May 14 02:26:51 PM PDT 24
Peak memory 208548 kb
Host smart-5754f191-0f98-49ec-b0b3-884a3fd95c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243113412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4243113412
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1320396657
Short name T908
Test name
Test status
Simulation time 613888854 ps
CPU time 17.84 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:46 PM PDT 24
Peak memory 222376 kb
Host smart-13741af4-1ff4-4e2b-9f86-2f8ef851cef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320396657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1320396657
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3645778461
Short name T610
Test name
Test status
Simulation time 389170980 ps
CPU time 9.35 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:39 PM PDT 24
Peak memory 220044 kb
Host smart-97a001d6-fb7d-407a-84b9-b419522fae0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645778461 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3645778461
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1037705714
Short name T606
Test name
Test status
Simulation time 26696505 ps
CPU time 2.21 seconds
Started May 14 02:26:17 PM PDT 24
Finished May 14 02:26:20 PM PDT 24
Peak memory 207044 kb
Host smart-7f7648e3-186e-49db-aa32-09e391a329c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037705714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1037705714
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3659341579
Short name T365
Test name
Test status
Simulation time 48595657 ps
CPU time 2.32 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 209928 kb
Host smart-12edc890-db63-483b-8a69-6e97ad25e866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659341579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3659341579
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2829314678
Short name T443
Test name
Test status
Simulation time 50808414 ps
CPU time 0.77 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:29 PM PDT 24
Peak memory 205944 kb
Host smart-d4457d17-c964-48c2-8dbe-910d03e97764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829314678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2829314678
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1223477037
Short name T412
Test name
Test status
Simulation time 59427851 ps
CPU time 4.2 seconds
Started May 14 02:26:25 PM PDT 24
Finished May 14 02:26:30 PM PDT 24
Peak memory 215476 kb
Host smart-1eec98f0-1ebe-4784-94f7-56239d5e694e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223477037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1223477037
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1392169118
Short name T408
Test name
Test status
Simulation time 374231388 ps
CPU time 5.17 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:35 PM PDT 24
Peak memory 208384 kb
Host smart-67623ee4-1f09-4a0a-b737-bb676f78117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392169118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1392169118
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1666624173
Short name T89
Test name
Test status
Simulation time 228729584 ps
CPU time 3.72 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:34 PM PDT 24
Peak memory 209528 kb
Host smart-ab03e95b-33d1-4f70-8c1c-4304da9400e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666624173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1666624173
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1701310881
Short name T269
Test name
Test status
Simulation time 54998753 ps
CPU time 1.69 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:31 PM PDT 24
Peak memory 214268 kb
Host smart-e1570fa1-8dd2-48aa-9817-6c68607753f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701310881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1701310881
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1260959980
Short name T204
Test name
Test status
Simulation time 941706494 ps
CPU time 13.03 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:43 PM PDT 24
Peak memory 222540 kb
Host smart-7054aecd-69bc-48f7-ab30-22e97a4ab09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260959980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1260959980
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3962208770
Short name T281
Test name
Test status
Simulation time 593610766 ps
CPU time 4.07 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:35 PM PDT 24
Peak memory 209252 kb
Host smart-e1fccd0c-ad27-4c3e-afe0-b16104a6feea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962208770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3962208770
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1371573283
Short name T251
Test name
Test status
Simulation time 116723898 ps
CPU time 2.87 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 208292 kb
Host smart-7c84c61f-37ef-422f-b886-627fe38a9ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371573283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1371573283
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2532554760
Short name T351
Test name
Test status
Simulation time 341000660 ps
CPU time 3.86 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 208880 kb
Host smart-55ac3da1-abbe-4eba-9c59-49b0e8d3418d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532554760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2532554760
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2383480853
Short name T672
Test name
Test status
Simulation time 128261982 ps
CPU time 2.4 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 206912 kb
Host smart-d446123d-9dc9-4c91-bdf8-94bec0847bf1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383480853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2383480853
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.306573302
Short name T459
Test name
Test status
Simulation time 137282725 ps
CPU time 3.41 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:26:34 PM PDT 24
Peak memory 208124 kb
Host smart-4a09a2df-901a-4d90-9439-5e77ac267302
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306573302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.306573302
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2193848493
Short name T434
Test name
Test status
Simulation time 108265007 ps
CPU time 3.75 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 208728 kb
Host smart-558aaecc-f434-4a7e-a064-19f35b97fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193848493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2193848493
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1303493883
Short name T536
Test name
Test status
Simulation time 46232148 ps
CPU time 2.33 seconds
Started May 14 02:26:26 PM PDT 24
Finished May 14 02:26:29 PM PDT 24
Peak memory 206788 kb
Host smart-6063d26d-3d3d-4fb4-8866-f2564da341ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303493883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1303493883
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4266281733
Short name T751
Test name
Test status
Simulation time 11699785282 ps
CPU time 49.89 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:27:21 PM PDT 24
Peak memory 216752 kb
Host smart-20652fc4-94cf-4539-a39a-e4282eb5b10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266281733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4266281733
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2247001128
Short name T162
Test name
Test status
Simulation time 1728728767 ps
CPU time 17.82 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:48 PM PDT 24
Peak memory 222656 kb
Host smart-82563f90-b85a-41de-8f4e-c08c1ee30b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247001128 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2247001128
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.781702266
Short name T182
Test name
Test status
Simulation time 683567792 ps
CPU time 10.17 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:40 PM PDT 24
Peak memory 208708 kb
Host smart-01120eac-bc66-4cef-8f68-2a4ca85cafdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781702266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.781702266
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.465003569
Short name T903
Test name
Test status
Simulation time 406727618 ps
CPU time 4.24 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:34 PM PDT 24
Peak memory 210448 kb
Host smart-99a47b83-7ba5-4796-9e17-e1572af8f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465003569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.465003569
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2558619798
Short name T575
Test name
Test status
Simulation time 53262577 ps
CPU time 0.78 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:42 PM PDT 24
Peak memory 205948 kb
Host smart-c2639397-57dd-4bb5-9f4f-92a8d3f1ca1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558619798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2558619798
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2573399885
Short name T883
Test name
Test status
Simulation time 139440359 ps
CPU time 2.59 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 222384 kb
Host smart-434f5297-3bf9-41f7-afe1-7f6462ce77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573399885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2573399885
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2172061660
Short name T235
Test name
Test status
Simulation time 30037086 ps
CPU time 1.47 seconds
Started May 14 02:26:26 PM PDT 24
Finished May 14 02:26:29 PM PDT 24
Peak memory 206880 kb
Host smart-6ed74748-ada2-44c7-adad-6e6f1244f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172061660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2172061660
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1408002961
Short name T855
Test name
Test status
Simulation time 144828388 ps
CPU time 2.75 seconds
Started May 14 02:26:29 PM PDT 24
Finished May 14 02:26:34 PM PDT 24
Peak memory 214304 kb
Host smart-b8ddd5e5-e60c-414b-867c-57413848dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408002961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1408002961
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.60652667
Short name T403
Test name
Test status
Simulation time 89995091 ps
CPU time 4.55 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:34 PM PDT 24
Peak memory 220560 kb
Host smart-1854e23b-b923-4e4a-8ba0-a39dd2bcb680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60652667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.60652667
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.303655951
Short name T891
Test name
Test status
Simulation time 199943044 ps
CPU time 3.56 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 207576 kb
Host smart-2bc09030-827d-4277-a62c-5766b13bef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303655951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.303655951
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2716213406
Short name T789
Test name
Test status
Simulation time 941648154 ps
CPU time 7.14 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:38 PM PDT 24
Peak memory 208608 kb
Host smart-4f741788-8176-414d-a926-e089b8bd878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716213406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2716213406
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.576857243
Short name T509
Test name
Test status
Simulation time 74681135 ps
CPU time 3.58 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 208492 kb
Host smart-a9447e0a-8011-4e20-8b4f-fdc267adfcd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576857243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.576857243
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2236900983
Short name T745
Test name
Test status
Simulation time 1202370155 ps
CPU time 12.17 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:42 PM PDT 24
Peak memory 208572 kb
Host smart-3615b1ef-573d-4b35-a4ca-ca5011996a3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236900983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2236900983
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1678220565
Short name T888
Test name
Test status
Simulation time 21079589 ps
CPU time 2.02 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 206804 kb
Host smart-e7d3f588-339b-48f0-acbc-207899ec5b55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678220565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1678220565
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2660444630
Short name T880
Test name
Test status
Simulation time 633487391 ps
CPU time 15.09 seconds
Started May 14 02:26:27 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 209216 kb
Host smart-902c03e7-4740-4dea-a8c2-f48900c63e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660444630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2660444630
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2860983710
Short name T447
Test name
Test status
Simulation time 70710263 ps
CPU time 2.46 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:33 PM PDT 24
Peak memory 207400 kb
Host smart-22f02e57-a532-4717-89ea-bef64a9e8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860983710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2860983710
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1933585134
Short name T496
Test name
Test status
Simulation time 257704583 ps
CPU time 3.75 seconds
Started May 14 02:26:30 PM PDT 24
Finished May 14 02:26:35 PM PDT 24
Peak memory 207324 kb
Host smart-9517b95a-ac0a-4884-a3a2-139d47492c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933585134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1933585134
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1948984622
Short name T38
Test name
Test status
Simulation time 136364682 ps
CPU time 2.03 seconds
Started May 14 02:26:28 PM PDT 24
Finished May 14 02:26:32 PM PDT 24
Peak memory 214396 kb
Host smart-9d6338e6-b107-44e1-8344-1d53931d8fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948984622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1948984622
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2741085468
Short name T636
Test name
Test status
Simulation time 60872912 ps
CPU time 0.75 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:39 PM PDT 24
Peak memory 205896 kb
Host smart-42e8c3ba-441f-4bda-8d49-be011912319d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741085468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2741085468
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3456200743
Short name T234
Test name
Test status
Simulation time 922753396 ps
CPU time 5.16 seconds
Started May 14 02:26:37 PM PDT 24
Finished May 14 02:26:43 PM PDT 24
Peak memory 207392 kb
Host smart-616bba19-9bc1-4c52-b7c3-f469e08402b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456200743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3456200743
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2403907854
Short name T515
Test name
Test status
Simulation time 157596187 ps
CPU time 5.62 seconds
Started May 14 02:26:35 PM PDT 24
Finished May 14 02:26:42 PM PDT 24
Peak memory 221092 kb
Host smart-ecbb7aaf-5c2d-45cd-be0e-534c4a552fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403907854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2403907854
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3462372472
Short name T354
Test name
Test status
Simulation time 620052822 ps
CPU time 3.99 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:45 PM PDT 24
Peak memory 215616 kb
Host smart-26ca661c-6b41-4343-9b02-a207c61e7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462372472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3462372472
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3258492031
Short name T570
Test name
Test status
Simulation time 111639201 ps
CPU time 4.59 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 218012 kb
Host smart-c9017218-9130-4e79-9bdc-63c4e536a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258492031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3258492031
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3191070947
Short name T451
Test name
Test status
Simulation time 128712307 ps
CPU time 4.89 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:46 PM PDT 24
Peak memory 209568 kb
Host smart-2b7d1e57-7f69-4189-9b42-a1d429727d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191070947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3191070947
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.721354314
Short name T186
Test name
Test status
Simulation time 181039568 ps
CPU time 2.44 seconds
Started May 14 02:26:40 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 206872 kb
Host smart-ef83217b-4fe0-4ef8-9190-e11c692723f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721354314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.721354314
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.273509503
Short name T820
Test name
Test status
Simulation time 162221116 ps
CPU time 3.67 seconds
Started May 14 02:26:44 PM PDT 24
Finished May 14 02:26:49 PM PDT 24
Peak memory 207000 kb
Host smart-8a2c0c98-32dc-4b53-87b1-dd25b8f87bb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273509503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.273509503
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2928734909
Short name T635
Test name
Test status
Simulation time 2848808326 ps
CPU time 12.1 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:54 PM PDT 24
Peak memory 208748 kb
Host smart-60960963-aa01-4efd-b5d6-e89a4a414df1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928734909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2928734909
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3439753192
Short name T769
Test name
Test status
Simulation time 259743484 ps
CPU time 2.89 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:46 PM PDT 24
Peak memory 206928 kb
Host smart-75e5e769-0ec3-4173-96b1-c1e91016ca3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439753192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3439753192
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2312900810
Short name T226
Test name
Test status
Simulation time 48432590 ps
CPU time 2.97 seconds
Started May 14 02:26:44 PM PDT 24
Finished May 14 02:26:48 PM PDT 24
Peak memory 218528 kb
Host smart-5aea3555-cfab-488c-b411-c67798b12d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312900810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2312900810
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1715692897
Short name T705
Test name
Test status
Simulation time 258739758 ps
CPU time 3.39 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 207092 kb
Host smart-cf39e579-d7eb-4e4f-9d20-0cf87c7ab182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715692897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1715692897
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1183062618
Short name T80
Test name
Test status
Simulation time 3987871578 ps
CPU time 40.79 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:27:20 PM PDT 24
Peak memory 222552 kb
Host smart-64402a7d-8eb9-4f8b-baf9-f80e84725cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183062618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1183062618
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3884903982
Short name T15
Test name
Test status
Simulation time 128342843 ps
CPU time 4.71 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:47 PM PDT 24
Peak memory 207464 kb
Host smart-8761312b-071e-4658-ae82-ab941e78a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884903982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3884903982
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3462338853
Short name T370
Test name
Test status
Simulation time 482294918 ps
CPU time 3.03 seconds
Started May 14 02:26:40 PM PDT 24
Finished May 14 02:26:45 PM PDT 24
Peak memory 210308 kb
Host smart-7a85e5b8-d725-4582-b3ba-29cc2f82991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462338853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3462338853
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4002872338
Short name T778
Test name
Test status
Simulation time 10811469 ps
CPU time 0.76 seconds
Started May 14 02:26:40 PM PDT 24
Finished May 14 02:26:43 PM PDT 24
Peak memory 205956 kb
Host smart-fd950748-9225-46da-8a4c-4e935b7fbe0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002872338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4002872338
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1807250474
Short name T377
Test name
Test status
Simulation time 158004313 ps
CPU time 4.19 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:45 PM PDT 24
Peak memory 222412 kb
Host smart-e99729c4-133e-4813-8379-7bcea57d349b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807250474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1807250474
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1145219530
Short name T25
Test name
Test status
Simulation time 125659408 ps
CPU time 2.04 seconds
Started May 14 02:26:37 PM PDT 24
Finished May 14 02:26:40 PM PDT 24
Peak memory 214632 kb
Host smart-c25b60c4-71fe-447f-ae28-44c933eb4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145219530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1145219530
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3774359235
Short name T667
Test name
Test status
Simulation time 402359156 ps
CPU time 2.64 seconds
Started May 14 02:26:42 PM PDT 24
Finished May 14 02:26:46 PM PDT 24
Peak memory 209064 kb
Host smart-5655ae80-31c7-4fc1-9384-d109114715bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774359235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3774359235
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1743393694
Short name T98
Test name
Test status
Simulation time 217328546 ps
CPU time 5.77 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:49 PM PDT 24
Peak memory 222464 kb
Host smart-715a5b49-753c-4069-9b6d-6876edb82ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743393694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1743393694
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2854248680
Short name T731
Test name
Test status
Simulation time 923297464 ps
CPU time 13.74 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:55 PM PDT 24
Peak memory 222536 kb
Host smart-c7104f37-5fad-4d46-b7e5-e1de97163a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854248680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2854248680
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.615036231
Short name T360
Test name
Test status
Simulation time 234709485 ps
CPU time 3.65 seconds
Started May 14 02:26:42 PM PDT 24
Finished May 14 02:26:47 PM PDT 24
Peak memory 207304 kb
Host smart-83bb0d6c-60f8-4ec7-8a67-f05bb11ae073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615036231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.615036231
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3828436048
Short name T101
Test name
Test status
Simulation time 35901134 ps
CPU time 2.44 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:42 PM PDT 24
Peak memory 207628 kb
Host smart-3dc87abc-6201-4d7b-bdc4-6af8e66245f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828436048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3828436048
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2568285983
Short name T640
Test name
Test status
Simulation time 36147642 ps
CPU time 2.74 seconds
Started May 14 02:26:37 PM PDT 24
Finished May 14 02:26:41 PM PDT 24
Peak memory 208500 kb
Host smart-2689a310-3761-4c2b-b6f1-3816c834ab2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568285983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2568285983
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.342088102
Short name T637
Test name
Test status
Simulation time 107295757 ps
CPU time 4.47 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:47 PM PDT 24
Peak memory 208720 kb
Host smart-e97d6365-0634-4df2-8de9-885ea80d2685
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342088102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.342088102
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3852993821
Short name T380
Test name
Test status
Simulation time 1069292569 ps
CPU time 9.51 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:52 PM PDT 24
Peak memory 208692 kb
Host smart-34fe2ac0-c4bb-4005-90be-f434f80acb97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852993821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3852993821
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1846362555
Short name T794
Test name
Test status
Simulation time 83369548 ps
CPU time 3.5 seconds
Started May 14 02:26:46 PM PDT 24
Finished May 14 02:26:50 PM PDT 24
Peak memory 207388 kb
Host smart-82ec8252-0fa5-4974-bc75-b04be7d88494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846362555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1846362555
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1335464217
Short name T784
Test name
Test status
Simulation time 257922539 ps
CPU time 3.38 seconds
Started May 14 02:26:39 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 208716 kb
Host smart-70365b61-602f-4242-b33c-a5f90dfa6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335464217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1335464217
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.332876464
Short name T907
Test name
Test status
Simulation time 1411723846 ps
CPU time 5.05 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:44 PM PDT 24
Peak memory 215800 kb
Host smart-c2c9665f-1b44-4ed4-be78-c38b17b97d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332876464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.332876464
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.980166397
Short name T787
Test name
Test status
Simulation time 227586531 ps
CPU time 8.51 seconds
Started May 14 02:26:41 PM PDT 24
Finished May 14 02:26:51 PM PDT 24
Peak memory 209892 kb
Host smart-60861423-346b-4f14-8ddc-0e5e5455e8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980166397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.980166397
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2719922424
Short name T171
Test name
Test status
Simulation time 89431661 ps
CPU time 2.34 seconds
Started May 14 02:26:42 PM PDT 24
Finished May 14 02:26:45 PM PDT 24
Peak memory 210164 kb
Host smart-1c573fa3-7ec8-4aba-a732-e1a0e2753a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719922424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2719922424
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.117910669
Short name T430
Test name
Test status
Simulation time 41784297 ps
CPU time 0.86 seconds
Started May 14 02:20:20 PM PDT 24
Finished May 14 02:20:22 PM PDT 24
Peak memory 205948 kb
Host smart-ccd7ad37-6f1b-47ae-a7ed-1b5ec7bcde84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117910669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.117910669
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3535559070
Short name T313
Test name
Test status
Simulation time 290342348 ps
CPU time 8.8 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:21 PM PDT 24
Peak memory 215176 kb
Host smart-65f3cf77-d800-4a6f-82ea-beb460a92414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535559070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3535559070
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2286629123
Short name T29
Test name
Test status
Simulation time 77884765 ps
CPU time 2.78 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:16 PM PDT 24
Peak memory 221748 kb
Host smart-4f0328ce-ea7f-41c2-be75-b148cec30380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286629123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2286629123
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3561330542
Short name T590
Test name
Test status
Simulation time 1399253240 ps
CPU time 9.61 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:22 PM PDT 24
Peak memory 214424 kb
Host smart-462ecdab-916f-417f-95d5-cd093f307f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561330542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3561330542
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4161923485
Short name T334
Test name
Test status
Simulation time 127345159 ps
CPU time 5.72 seconds
Started May 14 02:20:10 PM PDT 24
Finished May 14 02:20:17 PM PDT 24
Peak memory 211368 kb
Host smart-4d013f93-2e00-49c1-bbbf-21d2efc1a374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161923485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4161923485
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3668593841
Short name T327
Test name
Test status
Simulation time 580270156 ps
CPU time 5.09 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:17 PM PDT 24
Peak memory 222404 kb
Host smart-7f958926-4cf5-4c4b-8821-5c84fac43f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668593841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3668593841
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1867023432
Short name T47
Test name
Test status
Simulation time 409276044 ps
CPU time 1.95 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:14 PM PDT 24
Peak memory 214504 kb
Host smart-985505f5-110d-43c6-b58e-1262c02c90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867023432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1867023432
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.414968282
Short name T385
Test name
Test status
Simulation time 130111816 ps
CPU time 5.25 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:18 PM PDT 24
Peak memory 218472 kb
Host smart-290dedb6-52a6-49b4-916e-05f834098648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414968282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.414968282
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.88673306
Short name T99
Test name
Test status
Simulation time 611449287 ps
CPU time 6.64 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:25 PM PDT 24
Peak memory 233420 kb
Host smart-e9516b25-90ee-456b-8b6a-f1b4953b7704
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88673306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.88673306
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3468792194
Short name T544
Test name
Test status
Simulation time 971845073 ps
CPU time 24.4 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:36 PM PDT 24
Peak memory 208360 kb
Host smart-422e20da-0be3-4c8d-8b83-20a046448f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468792194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3468792194
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1444011640
Short name T699
Test name
Test status
Simulation time 21541784 ps
CPU time 1.89 seconds
Started May 14 02:20:10 PM PDT 24
Finished May 14 02:20:13 PM PDT 24
Peak memory 206956 kb
Host smart-4b2ba20e-bb60-4e3d-aab1-85c9cd8e6159
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444011640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1444011640
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.116834656
Short name T333
Test name
Test status
Simulation time 296546662 ps
CPU time 3.4 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:16 PM PDT 24
Peak memory 208764 kb
Host smart-63f6fd9d-794d-4814-8927-2bce87c2ea65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116834656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.116834656
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.466392030
Short name T823
Test name
Test status
Simulation time 808074390 ps
CPU time 2.93 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:15 PM PDT 24
Peak memory 207020 kb
Host smart-25aba3b9-8dba-4c4e-99bc-9ff1a0a43c97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466392030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.466392030
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1197545996
Short name T449
Test name
Test status
Simulation time 80141108 ps
CPU time 1.81 seconds
Started May 14 02:20:11 PM PDT 24
Finished May 14 02:20:14 PM PDT 24
Peak memory 207044 kb
Host smart-e4057b84-f6c2-4f51-bb6a-1dd43acfa7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197545996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1197545996
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1158716908
Short name T378
Test name
Test status
Simulation time 490185047 ps
CPU time 6.07 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:19 PM PDT 24
Peak memory 208532 kb
Host smart-766c4f99-dc3c-48f4-b86c-4eb0b102bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158716908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1158716908
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3725509591
Short name T767
Test name
Test status
Simulation time 536214152 ps
CPU time 12.34 seconds
Started May 14 02:20:21 PM PDT 24
Finished May 14 02:20:34 PM PDT 24
Peak memory 222620 kb
Host smart-7dc6f14a-3de9-48ca-a0a7-195bb7debdb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725509591 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3725509591
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3416773443
Short name T387
Test name
Test status
Simulation time 59132389 ps
CPU time 2.81 seconds
Started May 14 02:20:16 PM PDT 24
Finished May 14 02:20:19 PM PDT 24
Peak memory 207512 kb
Host smart-d365cf72-51c0-4d2c-ab13-e33c1666c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416773443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3416773443
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.319068169
Short name T547
Test name
Test status
Simulation time 730583572 ps
CPU time 18.92 seconds
Started May 14 02:20:12 PM PDT 24
Finished May 14 02:20:32 PM PDT 24
Peak memory 210988 kb
Host smart-9614b61d-3dde-48aa-8131-e64cdef11d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319068169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.319068169
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1461084626
Short name T602
Test name
Test status
Simulation time 23185047 ps
CPU time 0.92 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:26:54 PM PDT 24
Peak memory 205876 kb
Host smart-4c5e4c65-9da8-4d96-a1ed-f80a2407ce2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461084626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1461084626
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4288045632
Short name T316
Test name
Test status
Simulation time 67223369 ps
CPU time 2.87 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:26:56 PM PDT 24
Peak memory 214472 kb
Host smart-94647692-cd5b-4da5-afa3-3f22d9f506be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288045632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4288045632
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4269133772
Short name T757
Test name
Test status
Simulation time 81451958 ps
CPU time 2.77 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 221280 kb
Host smart-5683e42a-0492-4fa5-a396-f837eea1d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269133772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4269133772
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.581608136
Short name T727
Test name
Test status
Simulation time 482026526 ps
CPU time 2.28 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:55 PM PDT 24
Peak memory 208332 kb
Host smart-b34964c9-c52f-4dc2-a3df-8b3899464822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581608136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.581608136
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3643919877
Short name T94
Test name
Test status
Simulation time 70970567 ps
CPU time 2.79 seconds
Started May 14 02:26:50 PM PDT 24
Finished May 14 02:26:54 PM PDT 24
Peak memory 209308 kb
Host smart-2563f849-a49c-4e14-ae47-b818acad096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643919877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3643919877
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1735238450
Short name T683
Test name
Test status
Simulation time 256479152 ps
CPU time 6.73 seconds
Started May 14 02:26:54 PM PDT 24
Finished May 14 02:27:02 PM PDT 24
Peak memory 214372 kb
Host smart-4e540789-01e6-4e7e-a30c-ad8226dcf1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735238450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1735238450
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1342935038
Short name T467
Test name
Test status
Simulation time 268803837 ps
CPU time 3.1 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 209396 kb
Host smart-3c336aed-3ed5-4187-b537-934ee61ac840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342935038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1342935038
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1116551223
Short name T591
Test name
Test status
Simulation time 80636498 ps
CPU time 3.88 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 209164 kb
Host smart-b40f8e1a-d4fc-4563-9b1f-82fe67756a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116551223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1116551223
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1799271821
Short name T881
Test name
Test status
Simulation time 80777985 ps
CPU time 2.9 seconds
Started May 14 02:26:43 PM PDT 24
Finished May 14 02:26:47 PM PDT 24
Peak memory 209040 kb
Host smart-ecf69745-9846-4cde-bf66-e2c6030bd143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799271821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1799271821
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4274711422
Short name T768
Test name
Test status
Simulation time 114877238 ps
CPU time 4.72 seconds
Started May 14 02:26:40 PM PDT 24
Finished May 14 02:26:47 PM PDT 24
Peak memory 206984 kb
Host smart-47bb077d-c29b-42c1-bb55-416ace54cb1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274711422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4274711422
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2306778307
Short name T899
Test name
Test status
Simulation time 48507986 ps
CPU time 2.89 seconds
Started May 14 02:26:44 PM PDT 24
Finished May 14 02:26:48 PM PDT 24
Peak memory 208672 kb
Host smart-e8bc5682-4d4e-43cc-af89-493554dfb4fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306778307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2306778307
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1675032139
Short name T774
Test name
Test status
Simulation time 37975742 ps
CPU time 2.4 seconds
Started May 14 02:26:38 PM PDT 24
Finished May 14 02:26:42 PM PDT 24
Peak memory 208156 kb
Host smart-fd42312a-c174-4ce2-ae6f-fbed122de16a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675032139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1675032139
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2043219571
Short name T471
Test name
Test status
Simulation time 83905093 ps
CPU time 1.99 seconds
Started May 14 02:26:54 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 207444 kb
Host smart-f615a78a-8e81-4601-b76a-248f870523aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043219571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2043219571
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1160429846
Short name T438
Test name
Test status
Simulation time 2802799555 ps
CPU time 41.59 seconds
Started May 14 02:26:42 PM PDT 24
Finished May 14 02:27:25 PM PDT 24
Peak memory 208712 kb
Host smart-dc74190c-0122-4171-a33b-835b5eac0ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160429846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1160429846
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1860376373
Short name T813
Test name
Test status
Simulation time 167386984 ps
CPU time 4.78 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:27:00 PM PDT 24
Peak memory 209888 kb
Host smart-583eab3a-ef8f-4380-a3cb-2ce21f444dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860376373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1860376373
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1902411453
Short name T724
Test name
Test status
Simulation time 473842798 ps
CPU time 1.93 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 210208 kb
Host smart-930262c6-8394-40d0-9dff-07821b862374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902411453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1902411453
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.774949463
Short name T579
Test name
Test status
Simulation time 10377661 ps
CPU time 0.9 seconds
Started May 14 02:26:54 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 205988 kb
Host smart-5a7818d2-1404-45ad-97b4-f833a60b8977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774949463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.774949463
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1535745218
Short name T353
Test name
Test status
Simulation time 237889440 ps
CPU time 4.82 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 214396 kb
Host smart-b7d4a65f-f2f6-47f9-b5e1-03d26f1c346b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535745218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1535745218
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.120290024
Short name T71
Test name
Test status
Simulation time 33046156 ps
CPU time 1.99 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:54 PM PDT 24
Peak memory 216796 kb
Host smart-fcf402bf-35cb-48e4-aab2-0799ecd3b698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120290024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.120290024
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.982490966
Short name T734
Test name
Test status
Simulation time 703316830 ps
CPU time 3.41 seconds
Started May 14 02:26:55 PM PDT 24
Finished May 14 02:27:00 PM PDT 24
Peak memory 214320 kb
Host smart-ba9576df-2ddc-43a7-ac0b-4b2f2eef3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982490966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.982490966
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.155736568
Short name T24
Test name
Test status
Simulation time 73048967 ps
CPU time 4.76 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 220700 kb
Host smart-e26c8cc2-b694-46ac-85ae-f68d3a5d80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155736568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.155736568
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1129195070
Short name T270
Test name
Test status
Simulation time 572160344 ps
CPU time 4.23 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 222492 kb
Host smart-0d6747ba-4992-4c13-aecd-f22a8925abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129195070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1129195070
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3961705091
Short name T43
Test name
Test status
Simulation time 619664478 ps
CPU time 5.9 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:27:00 PM PDT 24
Peak memory 214316 kb
Host smart-fc3cc2fe-51ae-4859-aa36-acb4934ed8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961705091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3961705091
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1377248651
Short name T493
Test name
Test status
Simulation time 1799083348 ps
CPU time 16.74 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 209556 kb
Host smart-b2e7c14b-dd17-4b6a-bed5-a0de6b2bf584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377248651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1377248651
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1398131110
Short name T462
Test name
Test status
Simulation time 493739738 ps
CPU time 2.52 seconds
Started May 14 02:26:54 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 206668 kb
Host smart-ca4690c3-eec6-4f35-87ab-0dc7f80fcc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398131110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1398131110
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1774197335
Short name T680
Test name
Test status
Simulation time 488262065 ps
CPU time 7.27 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:27:01 PM PDT 24
Peak memory 208036 kb
Host smart-e3a00ae1-f057-4886-b53c-ba580341e34c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774197335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1774197335
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3783018714
Short name T307
Test name
Test status
Simulation time 49157620 ps
CPU time 2.88 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 208804 kb
Host smart-7ef20d32-e656-4103-88f8-57e409103494
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783018714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3783018714
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3587088430
Short name T793
Test name
Test status
Simulation time 418416463 ps
CPU time 2.48 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 206932 kb
Host smart-445b571a-c849-4a06-ae47-925ffab2dae1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587088430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3587088430
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.458935587
Short name T559
Test name
Test status
Simulation time 98898451 ps
CPU time 2.5 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 209452 kb
Host smart-c8aa413c-d1bb-4eb6-8052-93a4cd062ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458935587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.458935587
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2319207804
Short name T381
Test name
Test status
Simulation time 286967009 ps
CPU time 3.21 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 208628 kb
Host smart-bce00687-7136-433a-a29b-ec1028e3cbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319207804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2319207804
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3137520978
Short name T242
Test name
Test status
Simulation time 2257871076 ps
CPU time 49.77 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:27:45 PM PDT 24
Peak memory 218800 kb
Host smart-c663d29d-846e-4618-bf65-a3ac43fb4dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137520978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3137520978
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3705598688
Short name T115
Test name
Test status
Simulation time 987732423 ps
CPU time 12.64 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:27:05 PM PDT 24
Peak memory 220268 kb
Host smart-2d4b3088-4ed0-4aa9-9485-4ca6e5ef92da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705598688 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3705598688
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3228999457
Short name T815
Test name
Test status
Simulation time 411196351 ps
CPU time 5.14 seconds
Started May 14 02:26:51 PM PDT 24
Finished May 14 02:26:58 PM PDT 24
Peak memory 207780 kb
Host smart-47053664-82a3-4861-b8e9-bea33520f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228999457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3228999457
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4146833620
Short name T149
Test name
Test status
Simulation time 1983584978 ps
CPU time 17.93 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:27:13 PM PDT 24
Peak memory 211176 kb
Host smart-e7dc7f26-47f4-4c2d-be48-bf89dad204e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146833620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4146833620
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2111166216
Short name T583
Test name
Test status
Simulation time 54395836 ps
CPU time 0.79 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:05 PM PDT 24
Peak memory 206032 kb
Host smart-18f9e765-3eaf-40b4-950d-fb817eb26b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111166216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2111166216
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3966162461
Short name T232
Test name
Test status
Simulation time 294711790 ps
CPU time 14.51 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:19 PM PDT 24
Peak memory 214796 kb
Host smart-d1a245a5-d251-43e0-869d-4636a75b21e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966162461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3966162461
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1014975504
Short name T18
Test name
Test status
Simulation time 79052648 ps
CPU time 3.42 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:06 PM PDT 24
Peak memory 221640 kb
Host smart-824f7588-40f2-4972-bf19-4d64b1a221a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014975504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1014975504
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4266354753
Short name T669
Test name
Test status
Simulation time 62770980 ps
CPU time 2.8 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:06 PM PDT 24
Peak memory 209828 kb
Host smart-ed1aca38-52af-4f60-b009-0ce0a8fc6b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266354753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4266354753
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2857433157
Short name T514
Test name
Test status
Simulation time 358233650 ps
CPU time 5.26 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 209284 kb
Host smart-56b679a4-6f9d-42be-b8b0-43ce738d42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857433157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2857433157
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1698947493
Short name T323
Test name
Test status
Simulation time 244008886 ps
CPU time 3.48 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:10 PM PDT 24
Peak memory 221412 kb
Host smart-06c126e7-fe48-4dcd-ae3d-3a24ef2b1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698947493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1698947493
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.598849052
Short name T409
Test name
Test status
Simulation time 34182259 ps
CPU time 2.48 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:05 PM PDT 24
Peak memory 207932 kb
Host smart-61455ac7-99d7-4389-8235-69407814dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598849052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.598849052
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2897919646
Short name T241
Test name
Test status
Simulation time 482610166 ps
CPU time 11.93 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 208640 kb
Host smart-92f74ecc-9564-462d-9ba2-a2a8a4145abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897919646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2897919646
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.79109724
Short name T252
Test name
Test status
Simulation time 89271427 ps
CPU time 2.03 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 208820 kb
Host smart-2256ba6a-373e-4dd0-89dd-c1b33537ee32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79109724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.79109724
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2684991510
Short name T627
Test name
Test status
Simulation time 310300879 ps
CPU time 6.11 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 207996 kb
Host smart-ee514012-2f07-422e-b419-e1008923fda0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684991510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2684991510
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3919980799
Short name T518
Test name
Test status
Simulation time 538651526 ps
CPU time 6.68 seconds
Started May 14 02:26:52 PM PDT 24
Finished May 14 02:27:00 PM PDT 24
Peak memory 209040 kb
Host smart-0d15da5a-607c-42b4-8ced-9a79e03fdc26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919980799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3919980799
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3973362210
Short name T87
Test name
Test status
Simulation time 49430706 ps
CPU time 2.74 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:06 PM PDT 24
Peak memory 208080 kb
Host smart-fa327084-9a30-40d4-947e-268055902325
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973362210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3973362210
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1619699777
Short name T867
Test name
Test status
Simulation time 876710291 ps
CPU time 3.3 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 214328 kb
Host smart-e09548cd-ec4f-4fe7-8aff-9dc4ebaf133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619699777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1619699777
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2623603675
Short name T511
Test name
Test status
Simulation time 197015708 ps
CPU time 2.48 seconds
Started May 14 02:26:53 PM PDT 24
Finished May 14 02:26:57 PM PDT 24
Peak memory 206792 kb
Host smart-6041c29e-93c6-43d0-8b85-37396a220e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623603675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2623603675
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3616246086
Short name T896
Test name
Test status
Simulation time 71832005 ps
CPU time 0.76 seconds
Started May 14 02:26:59 PM PDT 24
Finished May 14 02:27:01 PM PDT 24
Peak memory 205920 kb
Host smart-3a445c62-c58a-463c-8228-447b8f0303c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616246086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3616246086
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2120111737
Short name T716
Test name
Test status
Simulation time 810584960 ps
CPU time 12.39 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:20 PM PDT 24
Peak memory 222540 kb
Host smart-39e9792b-4499-4446-a3bf-b55b72d2e7bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120111737 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2120111737
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.4149757844
Short name T726
Test name
Test status
Simulation time 1274667453 ps
CPU time 33.92 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:36 PM PDT 24
Peak memory 209104 kb
Host smart-07bbe5f7-3f8a-439f-a648-8409fea01e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149757844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.4149757844
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.743845983
Short name T371
Test name
Test status
Simulation time 60557738 ps
CPU time 2.12 seconds
Started May 14 02:26:59 PM PDT 24
Finished May 14 02:27:02 PM PDT 24
Peak memory 209780 kb
Host smart-592e996e-c45c-49ed-85f8-825d52dd13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743845983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.743845983
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3036439334
Short name T470
Test name
Test status
Simulation time 111662970 ps
CPU time 0.79 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:07 PM PDT 24
Peak memory 205968 kb
Host smart-490811f6-c784-4f59-a4c7-af9132a789de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036439334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3036439334
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2533742286
Short name T853
Test name
Test status
Simulation time 449770737 ps
CPU time 12.72 seconds
Started May 14 02:26:57 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 214280 kb
Host smart-3b4fa963-eee3-4da3-a265-199c1a88c3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533742286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2533742286
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4032324746
Short name T448
Test name
Test status
Simulation time 49802967 ps
CPU time 2.13 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 208736 kb
Host smart-ab271aef-9ba7-47c2-8559-6ea41d2d8614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032324746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4032324746
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3960749001
Short name T799
Test name
Test status
Simulation time 770078401 ps
CPU time 8.05 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 209340 kb
Host smart-ca2d5e86-a41f-4b0a-8089-ca2c9b3a1fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960749001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3960749001
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.494076018
Short name T661
Test name
Test status
Simulation time 209059997 ps
CPU time 5.13 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 222452 kb
Host smart-2e886650-0d38-4044-b3ab-a3d368e38b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494076018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.494076018
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3184959353
Short name T67
Test name
Test status
Simulation time 88407274 ps
CPU time 4.36 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:15 PM PDT 24
Peak memory 209724 kb
Host smart-f35b6103-88d3-4b0d-aa0b-8e2d80350b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184959353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3184959353
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1207531919
Short name T642
Test name
Test status
Simulation time 126865152 ps
CPU time 2.71 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:07 PM PDT 24
Peak memory 209804 kb
Host smart-c10d3f8e-1207-438b-902d-707953179e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207531919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1207531919
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3140144764
Short name T638
Test name
Test status
Simulation time 239962419 ps
CPU time 5.94 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:10 PM PDT 24
Peak memory 208660 kb
Host smart-f43061c1-5c0c-442f-81e8-1a2b1c47bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140144764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3140144764
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.642771438
Short name T807
Test name
Test status
Simulation time 566614246 ps
CPU time 7.47 seconds
Started May 14 02:27:04 PM PDT 24
Finished May 14 02:27:15 PM PDT 24
Peak memory 208540 kb
Host smart-01007df6-bf35-43c8-8d26-39408878e5b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642771438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.642771438
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3171038626
Short name T237
Test name
Test status
Simulation time 197487932 ps
CPU time 2.83 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 208956 kb
Host smart-03ea2bd0-584e-4f32-95e1-4f05c0dcd28e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171038626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3171038626
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.207577385
Short name T534
Test name
Test status
Simulation time 285574990 ps
CPU time 11.09 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 208168 kb
Host smart-5a851ef0-2c73-40c4-b62e-92176cb4e257
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207577385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.207577385
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.437963663
Short name T277
Test name
Test status
Simulation time 701990672 ps
CPU time 10.69 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:17 PM PDT 24
Peak memory 214320 kb
Host smart-318f944a-eff7-4e66-bd1d-ccbdbd6d69a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437963663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.437963663
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1427045335
Short name T416
Test name
Test status
Simulation time 470350440 ps
CPU time 4.87 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 208248 kb
Host smart-f76f8a04-dc86-435a-8878-5b4640fb6e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427045335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1427045335
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.589262668
Short name T216
Test name
Test status
Simulation time 461032088 ps
CPU time 5.41 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:13 PM PDT 24
Peak memory 207524 kb
Host smart-e013adf6-9f30-4a33-915a-d1b697600fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589262668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.589262668
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2608379416
Short name T119
Test name
Test status
Simulation time 346540136 ps
CPU time 3.14 seconds
Started May 14 02:27:01 PM PDT 24
Finished May 14 02:27:07 PM PDT 24
Peak memory 210520 kb
Host smart-8316535b-c3a3-4a0b-bfda-e8479086cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608379416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2608379416
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3131478555
Short name T736
Test name
Test status
Simulation time 15209291 ps
CPU time 0.98 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 206120 kb
Host smart-15786198-0c1b-4494-967b-12f38944fc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131478555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3131478555
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2771589767
Short name T236
Test name
Test status
Simulation time 397304066 ps
CPU time 4.7 seconds
Started May 14 02:27:00 PM PDT 24
Finished May 14 02:27:07 PM PDT 24
Peak memory 214912 kb
Host smart-8ab84493-a1fc-449c-af2d-2c7eeb21050d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771589767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2771589767
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1334886196
Short name T856
Test name
Test status
Simulation time 556262360 ps
CPU time 4.98 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:16 PM PDT 24
Peak memory 214248 kb
Host smart-32579c3b-d65f-4244-8a6f-f87a26ebe4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334886196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1334886196
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1368201414
Short name T347
Test name
Test status
Simulation time 86912688 ps
CPU time 3.14 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 214420 kb
Host smart-d7d249a5-b0f3-4ce8-86ad-19b6f2d39fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368201414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1368201414
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3187250783
Short name T587
Test name
Test status
Simulation time 277632172 ps
CPU time 3.9 seconds
Started May 14 02:27:04 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 209352 kb
Host smart-2f35b096-5a0b-42d7-8ee3-45d0badb233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187250783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3187250783
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.193754331
Short name T675
Test name
Test status
Simulation time 224988739 ps
CPU time 2.95 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 206916 kb
Host smart-bfb18711-85ab-43d9-95d9-3543ddf99f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193754331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.193754331
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3505857723
Short name T480
Test name
Test status
Simulation time 222362262 ps
CPU time 2.86 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 206964 kb
Host smart-33275892-bb3c-4144-aa36-cdf0185e0e70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505857723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3505857723
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3087848607
Short name T556
Test name
Test status
Simulation time 126682712 ps
CPU time 2.56 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:08 PM PDT 24
Peak memory 206940 kb
Host smart-4b605bc7-df68-4688-9577-32cf79b04ff2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087848607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3087848607
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2896325330
Short name T887
Test name
Test status
Simulation time 246729275 ps
CPU time 3.29 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 206972 kb
Host smart-7073710b-be51-420f-b59f-af058cd24a15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896325330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2896325330
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1450719795
Short name T240
Test name
Test status
Simulation time 171897967 ps
CPU time 6.23 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:17 PM PDT 24
Peak memory 214412 kb
Host smart-96b09a41-720b-46e3-9d7f-16f4aa3c0901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450719795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1450719795
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3654584278
Short name T584
Test name
Test status
Simulation time 249047840 ps
CPU time 3.08 seconds
Started May 14 02:27:06 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 208632 kb
Host smart-8cf1f958-5267-4d70-9dc2-8138e7a86dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654584278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3654584278
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1774994008
Short name T836
Test name
Test status
Simulation time 11943141148 ps
CPU time 67.14 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:28:13 PM PDT 24
Peak memory 219180 kb
Host smart-56ebbdea-a9d3-45dd-b587-3181b945fbbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774994008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1774994008
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1950684345
Short name T503
Test name
Test status
Simulation time 1091624684 ps
CPU time 6.8 seconds
Started May 14 02:27:10 PM PDT 24
Finished May 14 02:27:18 PM PDT 24
Peak memory 209248 kb
Host smart-fa6f137d-600f-4611-b190-de962e277771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950684345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1950684345
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2310352136
Short name T850
Test name
Test status
Simulation time 54325369 ps
CPU time 1.75 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 209812 kb
Host smart-2c2111c1-7e08-4a36-9836-d8c9a7c2db8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310352136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2310352136
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.56440026
Short name T608
Test name
Test status
Simulation time 13507770 ps
CPU time 0.78 seconds
Started May 14 02:28:03 PM PDT 24
Finished May 14 02:28:06 PM PDT 24
Peak memory 205940 kb
Host smart-810c1653-43ad-4aa9-b6de-00e11f7edf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56440026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.56440026
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3587284967
Short name T827
Test name
Test status
Simulation time 106127066 ps
CPU time 3.01 seconds
Started May 14 02:27:11 PM PDT 24
Finished May 14 02:27:16 PM PDT 24
Peak memory 214392 kb
Host smart-d74c561e-d25a-4ffd-9564-f3b0948de5cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587284967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3587284967
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.85663405
Short name T834
Test name
Test status
Simulation time 63586448 ps
CPU time 2.81 seconds
Started May 14 02:27:11 PM PDT 24
Finished May 14 02:27:16 PM PDT 24
Peak memory 209920 kb
Host smart-68785adf-31db-410c-96df-1f73a2f6d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85663405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.85663405
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2704336267
Short name T217
Test name
Test status
Simulation time 42665441 ps
CPU time 2.8 seconds
Started May 14 02:27:10 PM PDT 24
Finished May 14 02:27:16 PM PDT 24
Peak memory 218272 kb
Host smart-96c75997-d439-4525-aa83-8494c8cbdf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704336267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2704336267
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.123017490
Short name T363
Test name
Test status
Simulation time 76224193 ps
CPU time 2.76 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:14 PM PDT 24
Peak memory 209656 kb
Host smart-414c7629-1ffd-4cf3-af24-d4b83b34fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123017490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.123017490
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3355222941
Short name T221
Test name
Test status
Simulation time 80452207 ps
CPU time 2.79 seconds
Started May 14 02:27:10 PM PDT 24
Finished May 14 02:27:15 PM PDT 24
Peak memory 214304 kb
Host smart-46a05c47-3215-4f90-af0e-0b290b22e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355222941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3355222941
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4213208530
Short name T203
Test name
Test status
Simulation time 1039501516 ps
CPU time 3.84 seconds
Started May 14 02:27:10 PM PDT 24
Finished May 14 02:27:17 PM PDT 24
Peak memory 214308 kb
Host smart-1cfb725a-49ae-44c3-9444-3ae59e2d2534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213208530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4213208530
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.97268182
Short name T817
Test name
Test status
Simulation time 11598200873 ps
CPU time 23.55 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:35 PM PDT 24
Peak memory 209508 kb
Host smart-113ade4c-c1ba-41b5-8338-90bf96ed3471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97268182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.97268182
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.768897360
Short name T906
Test name
Test status
Simulation time 74272852 ps
CPU time 2.87 seconds
Started May 14 02:27:05 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 208768 kb
Host smart-ce65341b-adad-4b2e-9cda-55e802b910c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768897360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.768897360
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3873027118
Short name T628
Test name
Test status
Simulation time 150934570 ps
CPU time 2.36 seconds
Started May 14 02:27:10 PM PDT 24
Finished May 14 02:27:15 PM PDT 24
Peak memory 207472 kb
Host smart-0b73831e-75f9-4dd4-9b95-11a48585c023
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873027118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3873027118
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.243200440
Short name T427
Test name
Test status
Simulation time 51259004 ps
CPU time 2.64 seconds
Started May 14 02:27:03 PM PDT 24
Finished May 14 02:27:09 PM PDT 24
Peak memory 208416 kb
Host smart-e87d81d8-bd63-4460-bd0c-5a11232d7803
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243200440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.243200440
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3525334943
Short name T690
Test name
Test status
Simulation time 28301064 ps
CPU time 2.22 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:13 PM PDT 24
Peak memory 208848 kb
Host smart-ccc68e12-2c28-4dd4-9f20-a233c6a7ed6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525334943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3525334943
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3214745338
Short name T488
Test name
Test status
Simulation time 38067755 ps
CPU time 1.8 seconds
Started May 14 02:27:11 PM PDT 24
Finished May 14 02:27:15 PM PDT 24
Peak memory 214472 kb
Host smart-77f0af5b-3f66-458c-b89f-4a3b2bb4c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214745338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3214745338
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4068005985
Short name T418
Test name
Test status
Simulation time 175714501 ps
CPU time 5.39 seconds
Started May 14 02:27:02 PM PDT 24
Finished May 14 02:27:11 PM PDT 24
Peak memory 207700 kb
Host smart-3a351794-051a-4dce-b896-24f3a804302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068005985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4068005985
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.786527580
Short name T529
Test name
Test status
Simulation time 391137835 ps
CPU time 4.2 seconds
Started May 14 02:27:11 PM PDT 24
Finished May 14 02:27:17 PM PDT 24
Peak memory 207788 kb
Host smart-bc4bd2b9-2335-4c85-8a6c-407cb9c7c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786527580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.786527580
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1259308995
Short name T56
Test name
Test status
Simulation time 174049996 ps
CPU time 1.65 seconds
Started May 14 02:27:09 PM PDT 24
Finished May 14 02:27:12 PM PDT 24
Peak memory 210068 kb
Host smart-6c82c8ba-c579-4b25-90ad-f8085620c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259308995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1259308995
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1685902173
Short name T824
Test name
Test status
Simulation time 91379348 ps
CPU time 0.94 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:37 PM PDT 24
Peak memory 206028 kb
Host smart-64329bf2-6d2e-4c57-a8ed-19154da361d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685902173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1685902173
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2010147706
Short name T228
Test name
Test status
Simulation time 1288059864 ps
CPU time 17.82 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:54 PM PDT 24
Peak memory 214336 kb
Host smart-74dedd4d-ee22-4239-93ca-2cc7652d3446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010147706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2010147706
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3791000282
Short name T524
Test name
Test status
Simulation time 45983741 ps
CPU time 1.71 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:38 PM PDT 24
Peak memory 214344 kb
Host smart-8ad302b6-c521-4ad6-ad7c-9acf0f4de360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791000282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3791000282
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1378356818
Short name T595
Test name
Test status
Simulation time 504363264 ps
CPU time 7.01 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:43 PM PDT 24
Peak memory 209224 kb
Host smart-ec63a2c5-bc5e-456a-b77a-a30ac76c29b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378356818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1378356818
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2677768816
Short name T357
Test name
Test status
Simulation time 69184144 ps
CPU time 4.08 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:39 PM PDT 24
Peak memory 220716 kb
Host smart-19be2deb-6839-4e7a-a5a9-8502aed97253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677768816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2677768816
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3152732774
Short name T693
Test name
Test status
Simulation time 147549276 ps
CPU time 3.21 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:27:41 PM PDT 24
Peak memory 209476 kb
Host smart-ee64fbd3-54b4-4f45-a9e0-096e34357a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152732774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3152732774
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2716531214
Short name T632
Test name
Test status
Simulation time 239488772 ps
CPU time 8.27 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:44 PM PDT 24
Peak memory 209380 kb
Host smart-37f09759-8b6a-4e77-b0de-1a1b66985847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716531214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2716531214
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4067745162
Short name T253
Test name
Test status
Simulation time 138326115 ps
CPU time 3.01 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:38 PM PDT 24
Peak memory 208348 kb
Host smart-d289a108-903d-41f0-8143-b42409327c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067745162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4067745162
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1771177758
Short name T828
Test name
Test status
Simulation time 7010989494 ps
CPU time 63.88 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:28:40 PM PDT 24
Peak memory 209312 kb
Host smart-1c727bf0-6e9f-419c-8e45-c260006da1c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771177758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1771177758
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1297534817
Short name T775
Test name
Test status
Simulation time 468048830 ps
CPU time 2.27 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:27:39 PM PDT 24
Peak memory 206944 kb
Host smart-5d09eee4-81bf-4e68-9396-f83371a26922
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297534817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1297534817
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1848934392
Short name T866
Test name
Test status
Simulation time 4774465141 ps
CPU time 14.47 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:27:53 PM PDT 24
Peak memory 208324 kb
Host smart-4a1593e3-f49a-4141-9fbd-cadbacc2ddac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848934392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1848934392
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.419962285
Short name T612
Test name
Test status
Simulation time 24649011 ps
CPU time 2.02 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:39 PM PDT 24
Peak memory 214340 kb
Host smart-1a8ed902-6630-42e6-b9f3-4d70076cb6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419962285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.419962285
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1827844149
Short name T869
Test name
Test status
Simulation time 458527678 ps
CPU time 4.66 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:40 PM PDT 24
Peak memory 208620 kb
Host smart-3e8cc77a-a6c1-4988-81c9-79f1b22aa894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827844149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1827844149
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2605359840
Short name T800
Test name
Test status
Simulation time 4766891749 ps
CPU time 80.52 seconds
Started May 14 02:27:34 PM PDT 24
Finished May 14 02:28:57 PM PDT 24
Peak memory 219984 kb
Host smart-a4613617-869d-4224-987e-ac52e27c0b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605359840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2605359840
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3289657444
Short name T198
Test name
Test status
Simulation time 2102547393 ps
CPU time 22.03 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:57 PM PDT 24
Peak memory 220888 kb
Host smart-70e4e989-5c37-4423-ba6f-5c76acf98871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289657444 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3289657444
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3092802093
Short name T255
Test name
Test status
Simulation time 107068656 ps
CPU time 4.87 seconds
Started May 14 02:27:33 PM PDT 24
Finished May 14 02:27:39 PM PDT 24
Peak memory 208348 kb
Host smart-9c77f149-ab7d-4d34-ab29-6f1fc4a06b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092802093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3092802093
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3566487160
Short name T863
Test name
Test status
Simulation time 234442169 ps
CPU time 2.51 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:40 PM PDT 24
Peak memory 210264 kb
Host smart-5c110dc6-96df-4f98-9c0b-cfa9ef16f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566487160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3566487160
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1869466123
Short name T860
Test name
Test status
Simulation time 26001956 ps
CPU time 1.12 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:45 PM PDT 24
Peak memory 206180 kb
Host smart-4dd54491-3070-44ac-a5bb-44c40bea7234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869466123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1869466123
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1813075967
Short name T411
Test name
Test status
Simulation time 41531589660 ps
CPU time 123.61 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:29:41 PM PDT 24
Peak memory 216792 kb
Host smart-6890ee45-18f9-4e4c-bc97-b8c97499d70b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813075967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1813075967
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.182981
Short name T290
Test name
Test status
Simulation time 219312939 ps
CPU time 2.67 seconds
Started May 14 02:27:41 PM PDT 24
Finished May 14 02:27:45 PM PDT 24
Peak memory 208544 kb
Host smart-cf304b28-925a-4084-8e8a-b1ce6661af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.182981
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2288867537
Short name T341
Test name
Test status
Simulation time 59095118 ps
CPU time 2.19 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:27:40 PM PDT 24
Peak memory 214352 kb
Host smart-ed897652-9ceb-41c4-8b5e-3ce858558b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288867537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2288867537
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1273344193
Short name T223
Test name
Test status
Simulation time 92448963 ps
CPU time 2.82 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 214300 kb
Host smart-29495290-5864-4150-a6a3-4a3b9a091617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273344193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1273344193
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.903385848
Short name T328
Test name
Test status
Simulation time 49850294 ps
CPU time 2.93 seconds
Started May 14 02:27:44 PM PDT 24
Finished May 14 02:27:48 PM PDT 24
Peak memory 214348 kb
Host smart-591fefd9-dec4-4a84-af06-25ecaa8e115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903385848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.903385848
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1944787235
Short name T8
Test name
Test status
Simulation time 221872425 ps
CPU time 5.62 seconds
Started May 14 02:27:37 PM PDT 24
Finished May 14 02:27:44 PM PDT 24
Peak memory 222436 kb
Host smart-6218cdd7-01e2-46a3-822d-9653284c14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944787235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1944787235
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4124968115
Short name T722
Test name
Test status
Simulation time 153269387 ps
CPU time 4.6 seconds
Started May 14 02:27:36 PM PDT 24
Finished May 14 02:27:43 PM PDT 24
Peak memory 207324 kb
Host smart-ec5a3153-e26b-439d-9d20-9a91a33d33d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124968115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4124968115
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.92012204
Short name T84
Test name
Test status
Simulation time 134835045 ps
CPU time 4.16 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:42 PM PDT 24
Peak memory 206788 kb
Host smart-7ca762a2-6771-4509-b258-8adcd1919125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92012204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.92012204
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3812840887
Short name T453
Test name
Test status
Simulation time 231974670 ps
CPU time 3.35 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:41 PM PDT 24
Peak memory 206940 kb
Host smart-aeda0f2f-ed55-4708-84cf-9d65d7ad2a63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812840887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3812840887
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.348685859
Short name T763
Test name
Test status
Simulation time 255196980 ps
CPU time 3.4 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:40 PM PDT 24
Peak memory 207048 kb
Host smart-635db1b7-653f-4381-8fb5-8a038bfb649c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348685859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.348685859
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1914529485
Short name T729
Test name
Test status
Simulation time 262751558 ps
CPU time 4.13 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:27:42 PM PDT 24
Peak memory 208784 kb
Host smart-c70f8980-00de-4a5b-9ffa-916934f385b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914529485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1914529485
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2667085037
Short name T392
Test name
Test status
Simulation time 134094791 ps
CPU time 2.32 seconds
Started May 14 02:27:50 PM PDT 24
Finished May 14 02:27:55 PM PDT 24
Peak memory 219892 kb
Host smart-b88fdd67-0951-44fb-917f-9ae27f0566d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667085037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2667085037
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4178960414
Short name T735
Test name
Test status
Simulation time 1121906106 ps
CPU time 24.29 seconds
Started May 14 02:27:35 PM PDT 24
Finished May 14 02:28:02 PM PDT 24
Peak memory 208424 kb
Host smart-a17de423-4917-4843-bce7-ac9104c9e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178960414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4178960414
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.136949097
Short name T165
Test name
Test status
Simulation time 263463847 ps
CPU time 11.15 seconds
Started May 14 02:27:50 PM PDT 24
Finished May 14 02:28:04 PM PDT 24
Peak memory 222496 kb
Host smart-501ae1ce-41ab-45ec-986b-acc7a5ce7923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136949097 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.136949097
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.346500517
Short name T483
Test name
Test status
Simulation time 5300474903 ps
CPU time 55.81 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:28:42 PM PDT 24
Peak memory 220200 kb
Host smart-fa6bde5f-7ce7-40b6-a7d8-09ed843111f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346500517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.346500517
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2651972573
Short name T770
Test name
Test status
Simulation time 86967299 ps
CPU time 2.79 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:50 PM PDT 24
Peak memory 210020 kb
Host smart-f7d53432-8182-46c2-bbd0-df1c74428207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651972573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2651972573
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1675283535
Short name T765
Test name
Test status
Simulation time 12615653 ps
CPU time 0.9 seconds
Started May 14 02:27:42 PM PDT 24
Finished May 14 02:27:44 PM PDT 24
Peak memory 206024 kb
Host smart-9007f24c-e58b-4588-a305-1c6ecd24de37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675283535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1675283535
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.580226030
Short name T376
Test name
Test status
Simulation time 299740275 ps
CPU time 4.38 seconds
Started May 14 02:27:42 PM PDT 24
Finished May 14 02:27:47 PM PDT 24
Peak memory 214376 kb
Host smart-90471047-3d9e-4ccf-af35-cd29304b03a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580226030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.580226030
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3000572415
Short name T898
Test name
Test status
Simulation time 120198351 ps
CPU time 1.95 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 209544 kb
Host smart-f40519af-9b35-48bb-9c0f-f61a6c928162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000572415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3000572415
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2101175124
Short name T589
Test name
Test status
Simulation time 165127723 ps
CPU time 4.07 seconds
Started May 14 02:27:50 PM PDT 24
Finished May 14 02:27:56 PM PDT 24
Peak memory 209228 kb
Host smart-e4bddabd-1685-4319-8b77-74efa2b21c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101175124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2101175124
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3165657363
Short name T358
Test name
Test status
Simulation time 28372350 ps
CPU time 2.44 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:47 PM PDT 24
Peak memory 214304 kb
Host smart-106189e4-281c-4d14-b944-0e26b9cbc106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165657363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3165657363
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1167417399
Short name T286
Test name
Test status
Simulation time 119202765 ps
CPU time 4.4 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 220352 kb
Host smart-16a8fbf9-a89a-4437-9474-31c93bcacbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167417399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1167417399
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1215286332
Short name T653
Test name
Test status
Simulation time 169276017 ps
CPU time 2.73 seconds
Started May 14 02:27:40 PM PDT 24
Finished May 14 02:27:44 PM PDT 24
Peak memory 206108 kb
Host smart-406c6f00-8995-4993-8f9f-23fea61e63c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215286332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1215286332
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2897295586
Short name T802
Test name
Test status
Simulation time 1383785472 ps
CPU time 19.22 seconds
Started May 14 02:27:44 PM PDT 24
Finished May 14 02:28:04 PM PDT 24
Peak memory 218360 kb
Host smart-616dcd95-12ae-47f9-9bf2-4ee06c94561a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897295586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2897295586
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3861355790
Short name T698
Test name
Test status
Simulation time 1805937003 ps
CPU time 8.09 seconds
Started May 14 02:27:50 PM PDT 24
Finished May 14 02:28:00 PM PDT 24
Peak memory 206488 kb
Host smart-f90248e3-6506-429f-a5c9-6f6cd88424e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861355790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3861355790
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.717922662
Short name T100
Test name
Test status
Simulation time 36397184 ps
CPU time 2.56 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:49 PM PDT 24
Peak memory 209092 kb
Host smart-6c796ad0-dcee-4ea1-a246-c15a3b6de248
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717922662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.717922662
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1055529258
Short name T732
Test name
Test status
Simulation time 80451599 ps
CPU time 3.05 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:48 PM PDT 24
Peak memory 208728 kb
Host smart-cec64365-e546-4d22-9437-dc06c3538b38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055529258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1055529258
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.31075309
Short name T508
Test name
Test status
Simulation time 102098594 ps
CPU time 3.03 seconds
Started May 14 02:27:44 PM PDT 24
Finished May 14 02:27:49 PM PDT 24
Peak memory 209004 kb
Host smart-e659ba29-ea83-464e-bb91-909c1dd64f09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.31075309
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2264009735
Short name T620
Test name
Test status
Simulation time 49081432 ps
CPU time 2.07 seconds
Started May 14 02:27:41 PM PDT 24
Finished May 14 02:27:44 PM PDT 24
Peak memory 210124 kb
Host smart-ba0cb2d7-1a16-4420-8bf4-5cf49b691875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264009735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2264009735
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3629421385
Short name T424
Test name
Test status
Simulation time 49943509 ps
CPU time 2.79 seconds
Started May 14 02:27:44 PM PDT 24
Finished May 14 02:27:48 PM PDT 24
Peak memory 206792 kb
Host smart-f6976866-198b-4ae5-9e97-02e31742ef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629421385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3629421385
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2050030087
Short name T267
Test name
Test status
Simulation time 1121744926 ps
CPU time 15.9 seconds
Started May 14 02:27:40 PM PDT 24
Finished May 14 02:27:57 PM PDT 24
Peak memory 222492 kb
Host smart-c2f36483-3b7c-4ce4-aec5-707ec7998729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050030087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2050030087
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1769293331
Short name T117
Test name
Test status
Simulation time 449568222 ps
CPU time 10.01 seconds
Started May 14 02:27:42 PM PDT 24
Finished May 14 02:27:53 PM PDT 24
Peak memory 222668 kb
Host smart-926374cf-67e5-4f96-9db9-7d329f66402f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769293331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1769293331
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2367466230
Short name T656
Test name
Test status
Simulation time 829549350 ps
CPU time 6.81 seconds
Started May 14 02:27:42 PM PDT 24
Finished May 14 02:27:50 PM PDT 24
Peak memory 214340 kb
Host smart-8443b8a7-110d-4e87-be62-f673af38142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367466230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2367466230
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2317472229
Short name T546
Test name
Test status
Simulation time 1425770288 ps
CPU time 11.29 seconds
Started May 14 02:27:41 PM PDT 24
Finished May 14 02:27:53 PM PDT 24
Peak memory 210572 kb
Host smart-1932cca7-9f16-403c-b570-22be2680b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317472229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2317472229
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1499626891
Short name T892
Test name
Test status
Simulation time 27046851 ps
CPU time 0.77 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:27:49 PM PDT 24
Peak memory 205932 kb
Host smart-9e6998a9-5169-459b-8d25-e0f96cd72502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499626891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1499626891
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3955503342
Short name T379
Test name
Test status
Simulation time 1906926275 ps
CPU time 9.13 seconds
Started May 14 02:27:46 PM PDT 24
Finished May 14 02:27:56 PM PDT 24
Peak memory 222440 kb
Host smart-b62cbaea-92bc-45c5-9f1f-7ebd8ffd83e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955503342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3955503342
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3478510665
Short name T644
Test name
Test status
Simulation time 977116562 ps
CPU time 10.99 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:58 PM PDT 24
Peak memory 209944 kb
Host smart-04344e07-d49c-4477-ab6a-22a4778d03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478510665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3478510665
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2637373245
Short name T52
Test name
Test status
Simulation time 662986387 ps
CPU time 2.56 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:47 PM PDT 24
Peak memory 209088 kb
Host smart-370df987-a206-46f2-9118-be980f9343a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637373245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2637373245
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4293320305
Short name T756
Test name
Test status
Simulation time 212517109 ps
CPU time 3.51 seconds
Started May 14 02:27:40 PM PDT 24
Finished May 14 02:27:45 PM PDT 24
Peak memory 209476 kb
Host smart-c338c33f-8c98-4569-99a9-eedee82a62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293320305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4293320305
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2634628190
Short name T674
Test name
Test status
Simulation time 807621947 ps
CPU time 5.62 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:52 PM PDT 24
Peak memory 214300 kb
Host smart-14b59769-e3b6-4be6-b81f-6e605eeef4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634628190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2634628190
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.1863010229
Short name T468
Test name
Test status
Simulation time 693494980 ps
CPU time 4.63 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 209864 kb
Host smart-556cd6bd-96d6-4d69-ae22-3a02c145ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863010229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1863010229
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.68715893
Short name T500
Test name
Test status
Simulation time 97813906 ps
CPU time 3.92 seconds
Started May 14 02:27:46 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 208596 kb
Host smart-18165cb3-b0b3-47a5-9af4-50e94183776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68715893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.68715893
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4123545127
Short name T482
Test name
Test status
Simulation time 86907230 ps
CPU time 3.78 seconds
Started May 14 02:27:50 PM PDT 24
Finished May 14 02:27:56 PM PDT 24
Peak memory 208032 kb
Host smart-58ea0365-29c2-4916-b331-bc79f61462ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123545127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4123545127
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2962974408
Short name T502
Test name
Test status
Simulation time 3273954999 ps
CPU time 33.8 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:28:18 PM PDT 24
Peak memory 208644 kb
Host smart-404ac3b4-72d5-4297-b5dc-ac86e2c89af6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962974408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2962974408
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2270361459
Short name T569
Test name
Test status
Simulation time 166509744 ps
CPU time 5.09 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:49 PM PDT 24
Peak memory 208148 kb
Host smart-da3a5f89-5141-4cb6-ab80-50fcded06efb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270361459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2270361459
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2646396692
Short name T185
Test name
Test status
Simulation time 142132166 ps
CPU time 3.46 seconds
Started May 14 02:27:43 PM PDT 24
Finished May 14 02:27:48 PM PDT 24
Peak memory 214312 kb
Host smart-00b85fd5-56fd-45a0-9739-252d49fd77e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646396692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2646396692
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3307509833
Short name T415
Test name
Test status
Simulation time 118316864 ps
CPU time 1.66 seconds
Started May 14 02:27:45 PM PDT 24
Finished May 14 02:27:49 PM PDT 24
Peak memory 206720 kb
Host smart-0d42ca06-0dce-439c-882a-1cd104d2c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307509833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3307509833
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2131736971
Short name T633
Test name
Test status
Simulation time 4470918712 ps
CPU time 23.56 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:28:12 PM PDT 24
Peak memory 220988 kb
Host smart-edf3d0e0-7a42-4b59-9202-d9d02d1f9bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131736971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2131736971
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3802533729
Short name T553
Test name
Test status
Simulation time 76166647 ps
CPU time 2.65 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:27:51 PM PDT 24
Peak memory 208148 kb
Host smart-47687bcc-2762-43e6-b678-5f0c69fa431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802533729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3802533729
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1548337042
Short name T34
Test name
Test status
Simulation time 32973621 ps
CPU time 1.85 seconds
Started May 14 02:27:47 PM PDT 24
Finished May 14 02:27:50 PM PDT 24
Peak memory 208532 kb
Host smart-927164c0-b79f-494d-b52d-257bf054f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548337042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1548337042
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2306154292
Short name T538
Test name
Test status
Simulation time 18204962 ps
CPU time 0.78 seconds
Started May 14 02:20:27 PM PDT 24
Finished May 14 02:20:29 PM PDT 24
Peak memory 205972 kb
Host smart-958e3c2a-cf0e-464f-885c-61ca34576f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306154292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2306154292
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1955914004
Short name T375
Test name
Test status
Simulation time 148531401 ps
CPU time 2.88 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:22 PM PDT 24
Peak memory 215284 kb
Host smart-8868b242-d67b-4e07-a023-ad061f170924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955914004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1955914004
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4043771000
Short name T878
Test name
Test status
Simulation time 560583799 ps
CPU time 7.11 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:26 PM PDT 24
Peak memory 214472 kb
Host smart-db83cca7-17e8-4106-9884-626bf09cea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043771000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4043771000
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1851845066
Short name T814
Test name
Test status
Simulation time 357652727 ps
CPU time 3.76 seconds
Started May 14 02:20:20 PM PDT 24
Finished May 14 02:20:24 PM PDT 24
Peak memory 218424 kb
Host smart-d39e8f9f-2a9d-429a-b30e-57bc31db8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851845066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1851845066
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.457532340
Short name T301
Test name
Test status
Simulation time 86930104 ps
CPU time 1.91 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:21 PM PDT 24
Peak memory 214396 kb
Host smart-6ab10c30-0a9b-49c9-b107-72ee58b5d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457532340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.457532340
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1158121109
Short name T192
Test name
Test status
Simulation time 169433863 ps
CPU time 2.48 seconds
Started May 14 02:20:17 PM PDT 24
Finished May 14 02:20:21 PM PDT 24
Peak memory 214316 kb
Host smart-5e9b7e5f-6f15-4e11-80bd-766db419f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158121109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1158121109
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2604748632
Short name T391
Test name
Test status
Simulation time 273815961 ps
CPU time 2.39 seconds
Started May 14 02:20:19 PM PDT 24
Finished May 14 02:20:22 PM PDT 24
Peak memory 206088 kb
Host smart-9f550c84-4086-4b35-b139-df23672c17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604748632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2604748632
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1126259308
Short name T338
Test name
Test status
Simulation time 126991505 ps
CPU time 5.63 seconds
Started May 14 02:20:17 PM PDT 24
Finished May 14 02:20:23 PM PDT 24
Peak memory 218436 kb
Host smart-1cb53a45-4c11-4429-98c8-906159b775c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126259308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1126259308
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1662228215
Short name T519
Test name
Test status
Simulation time 1728341392 ps
CPU time 7.7 seconds
Started May 14 02:20:20 PM PDT 24
Finished May 14 02:20:28 PM PDT 24
Peak memory 208784 kb
Host smart-937131ab-b2f7-4377-92b3-6ae52f693176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662228215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1662228215
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1745142071
Short name T704
Test name
Test status
Simulation time 891589239 ps
CPU time 9.91 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:29 PM PDT 24
Peak memory 208908 kb
Host smart-66178a7b-65c1-4f42-9515-4e415e6f886f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745142071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1745142071
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.433964580
Short name T808
Test name
Test status
Simulation time 253030989 ps
CPU time 3.16 seconds
Started May 14 02:20:20 PM PDT 24
Finished May 14 02:20:24 PM PDT 24
Peak memory 206988 kb
Host smart-f40f7af8-5561-4d9d-99ed-a491a893c132
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433964580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.433964580
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2208374936
Short name T721
Test name
Test status
Simulation time 4377025193 ps
CPU time 60.98 seconds
Started May 14 02:20:20 PM PDT 24
Finished May 14 02:21:21 PM PDT 24
Peak memory 207068 kb
Host smart-7e863ea2-ebab-4a53-898d-ca8a340dad43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208374936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2208374936
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1822173579
Short name T473
Test name
Test status
Simulation time 85107436 ps
CPU time 2.14 seconds
Started May 14 02:20:25 PM PDT 24
Finished May 14 02:20:28 PM PDT 24
Peak memory 208248 kb
Host smart-460b48e8-9336-483f-9b04-0e74c243fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822173579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1822173579
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3610206333
Short name T543
Test name
Test status
Simulation time 758514456 ps
CPU time 3.61 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:23 PM PDT 24
Peak memory 208704 kb
Host smart-1d99333a-c1bb-4de1-a032-ad26f0d6d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610206333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3610206333
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1800302641
Short name T303
Test name
Test status
Simulation time 803169767 ps
CPU time 6.95 seconds
Started May 14 02:20:18 PM PDT 24
Finished May 14 02:20:26 PM PDT 24
Peak memory 209832 kb
Host smart-0e0eeb51-ecad-4f10-b4d7-a2b25551a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800302641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1800302641
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3987519912
Short name T531
Test name
Test status
Simulation time 5070682632 ps
CPU time 25.97 seconds
Started May 14 02:20:26 PM PDT 24
Finished May 14 02:20:53 PM PDT 24
Peak memory 211608 kb
Host smart-c85f4470-184f-45c3-8847-e0ccbbaa5ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987519912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3987519912
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.803878716
Short name T417
Test name
Test status
Simulation time 9146238 ps
CPU time 0.72 seconds
Started May 14 02:20:40 PM PDT 24
Finished May 14 02:20:42 PM PDT 24
Peak memory 205968 kb
Host smart-e092a1a4-9402-454e-884d-df5ff5d034d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803878716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.803878716
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2376084251
Short name T401
Test name
Test status
Simulation time 3717225292 ps
CPU time 53.59 seconds
Started May 14 02:20:29 PM PDT 24
Finished May 14 02:21:24 PM PDT 24
Peak memory 216936 kb
Host smart-fe5a6948-d3ee-48a7-b253-e4333cee6b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376084251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2376084251
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3575534539
Short name T781
Test name
Test status
Simulation time 51661778 ps
CPU time 1.31 seconds
Started May 14 02:20:27 PM PDT 24
Finished May 14 02:20:28 PM PDT 24
Peak memory 206860 kb
Host smart-92e322db-21fd-4408-ac9e-a5c70861025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575534539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3575534539
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2551620708
Short name T658
Test name
Test status
Simulation time 260842413 ps
CPU time 6.04 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:41 PM PDT 24
Peak memory 209208 kb
Host smart-d55484d4-5c55-4906-b777-9469abce836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551620708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2551620708
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.339784317
Short name T322
Test name
Test status
Simulation time 371252478 ps
CPU time 3.13 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:39 PM PDT 24
Peak memory 214256 kb
Host smart-8f0659f7-8767-493c-a900-1cc7a308259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339784317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.339784317
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3745865144
Short name T5
Test name
Test status
Simulation time 307515404 ps
CPU time 7.41 seconds
Started May 14 02:20:27 PM PDT 24
Finished May 14 02:20:35 PM PDT 24
Peak memory 209680 kb
Host smart-f5787ea8-f69e-4bdc-9d86-6bab39eaf590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745865144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3745865144
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3927992691
Short name T339
Test name
Test status
Simulation time 208231713 ps
CPU time 5.4 seconds
Started May 14 02:20:26 PM PDT 24
Finished May 14 02:20:32 PM PDT 24
Peak memory 208896 kb
Host smart-e026f167-7000-4cd6-ba9f-2e547b29aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927992691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3927992691
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3200504312
Short name T702
Test name
Test status
Simulation time 87408249 ps
CPU time 1.81 seconds
Started May 14 02:20:26 PM PDT 24
Finished May 14 02:20:28 PM PDT 24
Peak memory 206940 kb
Host smart-866d5d97-1287-4da0-a80e-2a9fdba29a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200504312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3200504312
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2323847829
Short name T646
Test name
Test status
Simulation time 703389380 ps
CPU time 5.42 seconds
Started May 14 02:20:27 PM PDT 24
Finished May 14 02:20:33 PM PDT 24
Peak memory 207104 kb
Host smart-c271e33c-70b3-4080-8950-d4f99f44d8c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323847829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2323847829
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3615126249
Short name T441
Test name
Test status
Simulation time 89024602 ps
CPU time 2.76 seconds
Started May 14 02:20:30 PM PDT 24
Finished May 14 02:20:33 PM PDT 24
Peak memory 206892 kb
Host smart-f163d087-30c2-4665-8983-41fc846e71fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615126249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3615126249
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1035678034
Short name T213
Test name
Test status
Simulation time 160289723 ps
CPU time 2.87 seconds
Started May 14 02:20:27 PM PDT 24
Finished May 14 02:20:30 PM PDT 24
Peak memory 206932 kb
Host smart-35754847-bf21-4762-87be-f55af9c59719
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035678034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1035678034
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3678834913
Short name T780
Test name
Test status
Simulation time 247393073 ps
CPU time 3.26 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:39 PM PDT 24
Peak memory 215940 kb
Host smart-833cc027-32b3-4de5-9413-613159299b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678834913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3678834913
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.135147481
Short name T389
Test name
Test status
Simulation time 110024367 ps
CPU time 2.87 seconds
Started May 14 02:20:24 PM PDT 24
Finished May 14 02:20:28 PM PDT 24
Peak memory 206812 kb
Host smart-5da12af6-3700-4c8b-ae00-11455feecd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135147481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.135147481
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1072062388
Short name T31
Test name
Test status
Simulation time 722426006 ps
CPU time 5.67 seconds
Started May 14 02:20:40 PM PDT 24
Finished May 14 02:20:47 PM PDT 24
Peak memory 214344 kb
Host smart-d8030a17-8083-4171-940f-1a327b7c9eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072062388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1072062388
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1166978185
Short name T663
Test name
Test status
Simulation time 109105782 ps
CPU time 4.63 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:41 PM PDT 24
Peak memory 207964 kb
Host smart-ee1c622b-aa86-4dc2-a567-031c34662d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166978185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1166978185
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3161657571
Short name T792
Test name
Test status
Simulation time 199256594 ps
CPU time 5.62 seconds
Started May 14 02:20:40 PM PDT 24
Finished May 14 02:20:46 PM PDT 24
Peak memory 210020 kb
Host smart-e1a080cd-51dc-44f9-89f2-3f4b14208eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161657571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3161657571
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.383176199
Short name T748
Test name
Test status
Simulation time 12305509 ps
CPU time 0.87 seconds
Started May 14 02:20:43 PM PDT 24
Finished May 14 02:20:45 PM PDT 24
Peak memory 206196 kb
Host smart-23d2550d-f248-43be-835a-bf052fcf21ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383176199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.383176199
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1250000574
Short name T585
Test name
Test status
Simulation time 370278283 ps
CPU time 4.1 seconds
Started May 14 02:20:39 PM PDT 24
Finished May 14 02:20:44 PM PDT 24
Peak memory 214344 kb
Host smart-025f9492-3abf-4f7a-ad44-321ccf1f506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250000574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1250000574
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1195713219
Short name T88
Test name
Test status
Simulation time 83005154 ps
CPU time 4.06 seconds
Started May 14 02:20:39 PM PDT 24
Finished May 14 02:20:44 PM PDT 24
Peak memory 209512 kb
Host smart-0bd2dea0-9bed-48f3-9b35-654f49c9ffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195713219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1195713219
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2405015873
Short name T344
Test name
Test status
Simulation time 104653997 ps
CPU time 2.33 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:20:45 PM PDT 24
Peak memory 214236 kb
Host smart-68c0a0f9-fdcb-4ac6-9c75-702b9c21de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405015873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2405015873
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1112518294
Short name T474
Test name
Test status
Simulation time 100897121 ps
CPU time 4.35 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:41 PM PDT 24
Peak memory 222408 kb
Host smart-9b92b1d5-00f2-4f79-804d-95580a58a369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112518294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1112518294
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3755625320
Short name T513
Test name
Test status
Simulation time 2880455359 ps
CPU time 66.57 seconds
Started May 14 02:20:34 PM PDT 24
Finished May 14 02:21:41 PM PDT 24
Peak memory 214380 kb
Host smart-8db6e8be-cb3a-4593-9cd9-a2dce03a1943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755625320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3755625320
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2025095982
Short name T719
Test name
Test status
Simulation time 109561310 ps
CPU time 4.03 seconds
Started May 14 02:20:35 PM PDT 24
Finished May 14 02:20:39 PM PDT 24
Peak memory 206864 kb
Host smart-042c11b1-df2b-4a7f-ac46-148cf261a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025095982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2025095982
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3568700385
Short name T689
Test name
Test status
Simulation time 31723210 ps
CPU time 2.33 seconds
Started May 14 02:20:36 PM PDT 24
Finished May 14 02:20:39 PM PDT 24
Peak memory 206960 kb
Host smart-c056abad-b466-4bef-b9d9-1e4230f4874b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568700385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3568700385
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4166030072
Short name T312
Test name
Test status
Simulation time 717502685 ps
CPU time 5.82 seconds
Started May 14 02:20:36 PM PDT 24
Finished May 14 02:20:43 PM PDT 24
Peak memory 208156 kb
Host smart-41aa67bf-8a35-4932-bfbd-72b6e1deb4f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166030072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4166030072
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1720123478
Short name T641
Test name
Test status
Simulation time 94392163 ps
CPU time 2.62 seconds
Started May 14 02:20:38 PM PDT 24
Finished May 14 02:20:42 PM PDT 24
Peak memory 208808 kb
Host smart-4da6894b-b4fd-4952-94bd-3572e15e2a77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720123478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1720123478
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2847557236
Short name T809
Test name
Test status
Simulation time 50878616 ps
CPU time 2.01 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:20:46 PM PDT 24
Peak memory 209272 kb
Host smart-b83c1c54-8cc5-4401-ab80-2d7b79f8a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847557236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2847557236
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.178935352
Short name T733
Test name
Test status
Simulation time 1471497892 ps
CPU time 5.83 seconds
Started May 14 02:20:34 PM PDT 24
Finished May 14 02:20:41 PM PDT 24
Peak memory 208668 kb
Host smart-a3b4367b-bc90-468d-9afe-65959c8ae890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178935352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.178935352
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1797113604
Short name T818
Test name
Test status
Simulation time 3179048059 ps
CPU time 33.7 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:21:17 PM PDT 24
Peak memory 221032 kb
Host smart-13b39a88-122c-409c-9346-55a5923182ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797113604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1797113604
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1977845861
Short name T822
Test name
Test status
Simulation time 1104298825 ps
CPU time 18.62 seconds
Started May 14 02:20:44 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 222576 kb
Host smart-cc7e8b0c-71e5-4d91-a8f9-6dd46e54145f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977845861 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1977845861
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2548962653
Short name T901
Test name
Test status
Simulation time 594364880 ps
CPU time 5.35 seconds
Started May 14 02:20:40 PM PDT 24
Finished May 14 02:20:46 PM PDT 24
Peak memory 208136 kb
Host smart-a6be8c37-7cb2-4f58-9b8f-1b24c36c5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548962653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2548962653
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.334448609
Short name T32
Test name
Test status
Simulation time 113494666 ps
CPU time 3.8 seconds
Started May 14 02:20:43 PM PDT 24
Finished May 14 02:20:48 PM PDT 24
Peak memory 210416 kb
Host smart-a22b72ad-f36b-43c7-b5dc-b5ef3b1afb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334448609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.334448609
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4229463263
Short name T618
Test name
Test status
Simulation time 17031798 ps
CPU time 0.81 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:53 PM PDT 24
Peak memory 205960 kb
Host smart-8a1f0232-16f6-4146-ada8-063a722db191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229463263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4229463263
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1065973388
Short name T405
Test name
Test status
Simulation time 93462421 ps
CPU time 3.39 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 214320 kb
Host smart-8a54334e-c7a3-48e4-ae14-39914ed6e608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065973388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1065973388
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1352711266
Short name T28
Test name
Test status
Simulation time 1190980897 ps
CPU time 7.76 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:21:00 PM PDT 24
Peak memory 221784 kb
Host smart-739fe327-d7d3-41c8-9cf7-674ac51bfad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352711266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1352711266
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2768344193
Short name T179
Test name
Test status
Simulation time 4748489097 ps
CPU time 47.53 seconds
Started May 14 02:20:57 PM PDT 24
Finished May 14 02:21:45 PM PDT 24
Peak memory 214416 kb
Host smart-9d746979-f2e9-4bdf-9706-cec6b8c2fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768344193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2768344193
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2804412997
Short name T246
Test name
Test status
Simulation time 115764397 ps
CPU time 2.12 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 214464 kb
Host smart-a76c743e-1d6f-40ad-8a98-de19433c0774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804412997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2804412997
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3125783190
Short name T325
Test name
Test status
Simulation time 384246680 ps
CPU time 2.86 seconds
Started May 14 02:20:56 PM PDT 24
Finished May 14 02:21:00 PM PDT 24
Peak memory 214156 kb
Host smart-aa93a49a-325a-4825-b3ee-ba3bc10ee107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125783190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3125783190
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1316575708
Short name T196
Test name
Test status
Simulation time 610170562 ps
CPU time 3.4 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:56 PM PDT 24
Peak memory 222380 kb
Host smart-10a919ab-cca2-441f-a80c-a39d8630fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316575708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1316575708
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3049872421
Short name T739
Test name
Test status
Simulation time 5551495354 ps
CPU time 38.05 seconds
Started May 14 02:20:41 PM PDT 24
Finished May 14 02:21:20 PM PDT 24
Peak memory 217360 kb
Host smart-bbd1147e-b465-4a70-8141-4f34d606a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049872421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3049872421
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2355195261
Short name T549
Test name
Test status
Simulation time 900366773 ps
CPU time 7.65 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:20:51 PM PDT 24
Peak memory 208712 kb
Host smart-4462f93e-4d04-4437-89a4-916a739951c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355195261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2355195261
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1835033886
Short name T288
Test name
Test status
Simulation time 113856069 ps
CPU time 3.42 seconds
Started May 14 02:20:41 PM PDT 24
Finished May 14 02:20:45 PM PDT 24
Peak memory 208548 kb
Host smart-998faec5-b889-47d2-873a-e7d85ff817eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835033886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1835033886
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1914137521
Short name T605
Test name
Test status
Simulation time 472065161 ps
CPU time 5.06 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:20:48 PM PDT 24
Peak memory 208092 kb
Host smart-ed7fd1cd-7820-4c61-9510-3edb63f8e486
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914137521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1914137521
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.856106535
Short name T895
Test name
Test status
Simulation time 256858052 ps
CPU time 4.17 seconds
Started May 14 02:20:44 PM PDT 24
Finished May 14 02:20:49 PM PDT 24
Peak memory 208768 kb
Host smart-815c6507-949d-4081-93d3-0ce608c8bd21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856106535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.856106535
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4007415353
Short name T761
Test name
Test status
Simulation time 79341121 ps
CPU time 3.42 seconds
Started May 14 02:20:50 PM PDT 24
Finished May 14 02:20:54 PM PDT 24
Peak memory 209364 kb
Host smart-2256658a-fc85-42d4-9de2-8bed94a5f994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007415353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4007415353
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2045260304
Short name T609
Test name
Test status
Simulation time 4757999507 ps
CPU time 23.75 seconds
Started May 14 02:20:42 PM PDT 24
Finished May 14 02:21:07 PM PDT 24
Peak memory 208504 kb
Host smart-1895305a-02df-4de2-ba86-299d5b06bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045260304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2045260304
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4255827511
Short name T352
Test name
Test status
Simulation time 275469601 ps
CPU time 3.69 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 208156 kb
Host smart-dc9ac23c-5ef7-4fbb-b4f8-b1559bf19caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255827511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4255827511
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1465373386
Short name T55
Test name
Test status
Simulation time 179759121 ps
CPU time 2.87 seconds
Started May 14 02:20:52 PM PDT 24
Finished May 14 02:20:56 PM PDT 24
Peak memory 210048 kb
Host smart-707e3c3a-50d2-4084-a89c-4c2f3b8e3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465373386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1465373386
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.494128436
Short name T523
Test name
Test status
Simulation time 10285042 ps
CPU time 0.74 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 205928 kb
Host smart-11b14b2e-1e3a-4fb8-ab61-5c3aa10b95a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494128436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.494128436
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1889111079
Short name T17
Test name
Test status
Simulation time 73159874 ps
CPU time 4.07 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:57 PM PDT 24
Peak memory 210092 kb
Host smart-64ed22c9-7810-4d7a-b8a0-b15eac0399ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889111079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1889111079
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3933238272
Short name T266
Test name
Test status
Simulation time 1551067233 ps
CPU time 27.1 seconds
Started May 14 02:20:52 PM PDT 24
Finished May 14 02:21:20 PM PDT 24
Peak memory 209016 kb
Host smart-088618e6-3a9c-4edf-a75b-2640ac6c49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933238272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3933238272
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.459842130
Short name T45
Test name
Test status
Simulation time 30465469 ps
CPU time 1.87 seconds
Started May 14 02:20:52 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 214412 kb
Host smart-36b78d14-eda6-439d-9351-286e7c301ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459842130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.459842130
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1301645711
Short name T873
Test name
Test status
Simulation time 42369273 ps
CPU time 2.44 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:54 PM PDT 24
Peak memory 218464 kb
Host smart-e518ddde-0312-46f7-a931-40b8e0e936df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301645711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1301645711
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1383918845
Short name T190
Test name
Test status
Simulation time 165456625 ps
CPU time 3.7 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:56 PM PDT 24
Peak memory 214244 kb
Host smart-398b88b1-6bbb-4578-aa82-31f4a2f32ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383918845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1383918845
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3496001207
Short name T457
Test name
Test status
Simulation time 269245807 ps
CPU time 5.99 seconds
Started May 14 02:20:52 PM PDT 24
Finished May 14 02:20:59 PM PDT 24
Peak memory 209268 kb
Host smart-90fc3d9a-cd9a-4d67-a5b6-321446fc76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496001207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3496001207
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.710328734
Short name T497
Test name
Test status
Simulation time 837210241 ps
CPU time 8.14 seconds
Started May 14 02:20:52 PM PDT 24
Finished May 14 02:21:01 PM PDT 24
Peak memory 208052 kb
Host smart-721f3737-b861-4ecc-8def-d8b9226245f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710328734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.710328734
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2824050812
Short name T310
Test name
Test status
Simulation time 139755797 ps
CPU time 1.99 seconds
Started May 14 02:20:50 PM PDT 24
Finished May 14 02:20:53 PM PDT 24
Peak memory 208880 kb
Host smart-e77d6c24-8ab0-4637-b9c7-115a243fc242
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824050812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2824050812
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3114617169
Short name T643
Test name
Test status
Simulation time 39871692 ps
CPU time 1.77 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:53 PM PDT 24
Peak memory 206968 kb
Host smart-1701f9d7-a44f-4899-99b9-31fd1f484ad6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114617169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3114617169
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3195559052
Short name T843
Test name
Test status
Simulation time 148515222 ps
CPU time 2.68 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:55 PM PDT 24
Peak memory 208872 kb
Host smart-c7c770be-ea3b-49a9-aaef-a342228b1cbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195559052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3195559052
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2535656969
Short name T788
Test name
Test status
Simulation time 231024647 ps
CPU time 2.45 seconds
Started May 14 02:21:01 PM PDT 24
Finished May 14 02:21:05 PM PDT 24
Peak memory 209196 kb
Host smart-d341a45b-7b3c-4a0b-8d63-d7cebf7e7081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535656969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2535656969
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.4001350646
Short name T678
Test name
Test status
Simulation time 92098936 ps
CPU time 3.3 seconds
Started May 14 02:20:56 PM PDT 24
Finished May 14 02:21:00 PM PDT 24
Peak memory 208420 kb
Host smart-142c41eb-5d82-45e6-bad2-69cb81a03e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001350646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.4001350646
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2197687280
Short name T209
Test name
Test status
Simulation time 2839707244 ps
CPU time 76.7 seconds
Started May 14 02:20:59 PM PDT 24
Finished May 14 02:22:16 PM PDT 24
Peak memory 216880 kb
Host smart-16a3c8d7-502f-4735-ab66-f8a65a0388bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197687280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2197687280
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1956617851
Short name T861
Test name
Test status
Simulation time 467313111 ps
CPU time 6.04 seconds
Started May 14 02:20:51 PM PDT 24
Finished May 14 02:20:58 PM PDT 24
Peak memory 218344 kb
Host smart-88b06f7b-2d21-4f28-8361-d0643963cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956617851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1956617851
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1180345137
Short name T120
Test name
Test status
Simulation time 83337778 ps
CPU time 2.47 seconds
Started May 14 02:21:00 PM PDT 24
Finished May 14 02:21:03 PM PDT 24
Peak memory 210212 kb
Host smart-a645eb27-9819-4fe0-98e4-ecb6819bf614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180345137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1180345137
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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