Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
50 |
1 |
|
|
T16 |
1 |
|
T44 |
1 |
|
T26 |
1 |
auto[OpGenId] |
16 |
1 |
|
|
T25 |
1 |
|
T64 |
1 |
|
T62 |
1 |
auto[OpGenSwOut] |
17 |
1 |
|
|
T64 |
1 |
|
T132 |
1 |
|
T240 |
1 |
auto[OpGenHwOut] |
16 |
1 |
|
|
T5 |
1 |
|
T20 |
1 |
|
T6 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1569 |
1 |
|
|
T3 |
1 |
|
T15 |
1 |
|
T18 |
1 |
auto[StInit] |
94 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T16 |
1 |
auto[StCreatorRootKey] |
61 |
1 |
|
|
T13 |
1 |
|
T44 |
1 |
|
T19 |
1 |
auto[StOwnerIntKey] |
46 |
1 |
|
|
T36 |
1 |
|
T5 |
1 |
|
T45 |
1 |
auto[StOwnerKey] |
43 |
1 |
|
|
T15 |
1 |
|
T37 |
1 |
|
T42 |
1 |
auto[StDisabled] |
479 |
1 |
|
|
T3 |
3 |
|
T15 |
2 |
|
T18 |
7 |
auto[StInvalid] |
50 |
1 |
|
|
T49 |
1 |
|
T50 |
1 |
|
T51 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3331 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
5 |
auto[1] |
99 |
1 |
|
|
T16 |
1 |
|
T44 |
1 |
|
T25 |
1 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1568 |
1 |
|
|
T3 |
1 |
|
T15 |
1 |
|
T18 |
1 |
auto[StReset] |
auto[1] |
1 |
1 |
|
|
T52 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[0] |
49 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T54 |
1 |
auto[StInit] |
auto[1] |
45 |
1 |
|
|
T16 |
1 |
|
T44 |
1 |
|
T25 |
1 |
auto[StCreatorRootKey] |
auto[0] |
43 |
1 |
|
|
T13 |
1 |
|
T44 |
1 |
|
T19 |
1 |
auto[StCreatorRootKey] |
auto[1] |
18 |
1 |
|
|
T46 |
1 |
|
T63 |
1 |
|
T241 |
1 |
auto[StOwnerIntKey] |
auto[0] |
34 |
1 |
|
|
T36 |
1 |
|
T45 |
1 |
|
T59 |
1 |
auto[StOwnerIntKey] |
auto[1] |
12 |
1 |
|
|
T5 |
1 |
|
T132 |
1 |
|
T7 |
1 |
auto[StOwnerKey] |
auto[0] |
31 |
1 |
|
|
T15 |
1 |
|
T37 |
1 |
|
T42 |
1 |
auto[StOwnerKey] |
auto[1] |
12 |
1 |
|
|
T45 |
1 |
|
T62 |
1 |
|
T240 |
1 |
auto[StDisabled] |
auto[0] |
468 |
1 |
|
|
T3 |
3 |
|
T15 |
2 |
|
T18 |
7 |
auto[StDisabled] |
auto[1] |
11 |
1 |
|
|
T64 |
2 |
|
T65 |
1 |
|
T116 |
1 |
auto[StInvalid] |
auto[0] |
50 |
1 |
|
|
T49 |
1 |
|
T50 |
1 |
|
T51 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
16 |
19 |
54.29 |
16 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset]] |
[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
4 |
|
[auto[StInit] , auto[StCreatorRootKey]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StOwnerIntKey]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StOwnerIntKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StDisabled]] |
[auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
2 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
1 |
1 |
|
|
T52 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[OpAdvance] |
22 |
1 |
|
|
T16 |
1 |
|
T44 |
1 |
|
T26 |
1 |
auto[StInit] |
auto[OpGenId] |
7 |
1 |
|
|
T25 |
1 |
|
T124 |
1 |
|
T66 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
7 |
1 |
|
|
T213 |
1 |
|
T52 |
1 |
|
T242 |
1 |
auto[StInit] |
auto[OpGenHwOut] |
9 |
1 |
|
|
T20 |
1 |
|
T6 |
1 |
|
T243 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
11 |
1 |
|
|
T46 |
1 |
|
T63 |
1 |
|
T241 |
1 |
auto[StCreatorRootKey] |
auto[OpGenId] |
2 |
1 |
|
|
T216 |
1 |
|
T143 |
1 |
|
- |
- |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
4 |
1 |
|
|
T27 |
1 |
|
T244 |
1 |
|
T245 |
1 |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T215 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpAdvance] |
5 |
1 |
|
|
T215 |
1 |
|
T216 |
1 |
|
T162 |
1 |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T132 |
1 |
|
T246 |
1 |
|
T247 |
1 |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
4 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T248 |
1 |
auto[StOwnerKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T45 |
1 |
|
T204 |
1 |
|
T206 |
1 |
auto[StOwnerKey] |
auto[OpGenId] |
2 |
1 |
|
|
T62 |
1 |
|
T249 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T240 |
1 |
|
T144 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T250 |
1 |
|
T251 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpAdvance] |
5 |
1 |
|
|
T126 |
1 |
|
T252 |
1 |
|
T253 |
1 |
auto[StDisabled] |
auto[OpGenId] |
5 |
1 |
|
|
T64 |
1 |
|
T65 |
1 |
|
T116 |
1 |
auto[StDisabled] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T64 |
1 |
|
- |
- |
|
- |
- |