Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11218

1

T1

1

T2

5

T3

37

auto[Attestation]

8112

1

T1

1

T2

3

T3

30

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2820	1			T3	12		T4	2		T14	3
auto[Aes]	3501	1			T1	1		T3	7		T4	3
auto[Kmac]	3414	1			T3	10		T4	2		T14	5
auto[Otbn]	3474	1			T2	8		T3	6		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7965	1			T1	1		T2	8		T3	32
auto[OpGenId]	6121	1			T1	1		T3	32		T4	5
auto[OpGenSwOut]	6115	1			T1	1		T3	18		T4	4
auto[OpGenHwOut]	7094	1			T2	8		T3	17		T4	5
auto[OpDisable]	127	1			T18	2		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10962

1

T1

1

T2

8

T3

43

auto[OpDoneFail]

16460

1

T1

2

T2

8

T3

56

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6665	1			T1	1		T2	1		T3	7
auto[StInit]	3782	1			T1	2		T2	2		T3	12
auto[StCreatorRootKey]	3257	1			T2	2		T3	11		T4	2
auto[StOwnerIntKey]	2948	1			T2	2		T3	10		T4	3
auto[StOwnerKey]	2494	1			T2	2		T3	14		T4	4
auto[StDisabled]	8276	1			T2	7		T3	45		T4	11

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	337	1			T15	1		T18	4		T129	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T3	1		T18	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T3	1		T18	2		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T15	1		T18	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	71	1			T18	2		T38	1		T233	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	218	1			T3	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	349	1			T15	1		T18	4		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T3	1		T16	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	90	1			T47	2		T44	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	80	1			T4	1		T18	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T18	1		T38	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	218	1			T3	2		T15	1		T18	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	326	1			T15	2		T18	3		T128	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	89	1			T16	1		T18	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	60	1			T24	1		T141	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T18	1		T83	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T18	3		T44	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	228	1			T3	1		T15	2		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T15	1		T18	4		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	92	1			T14	1		T38	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T18	2		T83	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T18	1		T44	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T14	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	211	1			T3	2		T14	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	87	1			T44	1		T64	1		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T3	1		T15	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	90	1			T3	1		T18	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	81	1			T128	1		T48	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T24	1		T44	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	220	1			T3	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	102	1			T44	6		T5	2		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T1	1		T233	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T83	1		T59	3		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	62	1			T128	1		T130	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T18	1		T129	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	236	1			T4	1		T18	2		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T15	1		T44	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T16	1		T36	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T15	1		T18	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T130	1		T5	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T3	1		T18	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	248	1			T3	3		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T15	1		T44	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T18	1		T129	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T13	1		T18	2		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T15	1		T79	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	74	1			T3	1		T18	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	248	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	284	1			T15	1		T18	5		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	101	1			T3	1		T18	2		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	68	1			T18	1		T37	1		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T3	2		T235	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	53	1			T15	1		T128	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	199	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	440	1			T18	2		T82	12		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T13	1		T129	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T3	1		T82	1		T236	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	114	1			T15	1		T82	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T18	3		T82	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	287	1			T3	1		T14	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	477	1			T3	1		T14	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T15	1		T33	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T33	1		T237	1		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T4	1		T237	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	79	1			T18	1		T83	1		T233	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	295	1			T3	2		T14	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	488	1			T18	1		T128	2		T129	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T2	1		T18	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	122	1			T2	1		T33	1		T128	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	114	1			T18	2		T130	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	72	1			T2	1		T33	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	267	1			T2	2		T3	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T44	2		T5	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T33	1		T130	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	93	1			T3	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T18	1		T83	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T3	1		T18	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	167	1			T4	1		T18	2		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	69	1			T44	1		T64	1		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T18	4		T82	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T234	3		T142	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	105	1			T18	3		T128	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T233	1		T141	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	303	1			T3	2		T4	1		T18	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T45	1		T59	3		T68	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T16	1		T38	1		T237	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T3	1		T14	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T33	1		T24	1		T238	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	105	1			T3	1		T14	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T15	1		T18	2		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T5	1		T45	2		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T24	1		T37	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T18	1		T33	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T2	1		T18	2		T239	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T38	1		T128	1		T233	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	287	1			T2	2		T3	1		T4	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	201	1			T3	1		T15	1		T18	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	678	1			T3	2		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	221	1			T4	1		T18	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	699	1			T3	3		T15	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	178	1			T18	4		T24	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	655	1			T3	1		T15	4		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T14	1		T15	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	649	1			T3	2		T14	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	205	1			T3	1		T18	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	422	1			T3	2		T14	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	182	1			T83	1		T128	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	477	1			T1	1		T4	1		T18	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	221	1			T3	1		T15	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	446	1			T3	3		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	246	1			T3	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	446	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T3	2		T18	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	601	1			T3	2		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	287	1			T3	1		T15	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	853	1			T3	1		T13	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T4	1		T18	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	900	1			T3	3		T14	2		T15	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T2	2		T18	2		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	899	1			T2	3		T3	1		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T3	2		T18	2		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	350	1			T4	1		T18	3		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	261	1			T18	2		T128	1		T233	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	521	1			T3	2		T4	1		T18	9
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T3	2		T14	2		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	469	1			T15	1		T16	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T2	1		T18	3		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	483	1			T2	2		T3	1		T4	1