Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33700

1

T1

3

T2

19

T3

110

auto[1]

295

1

T33

6

T83

4

T130

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33708	1			T1	3		T2	19		T3	110
auto[134217728:268435455]	10	1			T33	1		T108	1		T320	1
auto[268435456:402653183]	11	1			T131	1		T345	1		T283	1
auto[402653184:536870911]	8	1			T314	1		T429	1		T313	1
auto[536870912:671088639]	12	1			T272	2		T418	1		T382	1
auto[671088640:805306367]	9	1			T130	1		T263	1		T416	1
auto[805306368:939524095]	8	1			T263	1		T320	1		T389	1
auto[939524096:1073741823]	5	1			T320	1		T418	1		T283	1
auto[1073741824:1207959551]	7	1			T83	1		T283	2		T196	1
auto[1207959552:1342177279]	6	1			T320	1		T272	1		T227	1
auto[1342177280:1476395007]	13	1			T33	1		T130	1		T131	1
auto[1476395008:1610612735]	5	1			T430	1		T316	1		T431	1
auto[1610612736:1744830463]	14	1			T33	1		T83	1		T272	1
auto[1744830464:1879048191]	11	1			T33	1		T345	1		T263	1
auto[1879048192:2013265919]	12	1			T130	1		T141	1		T108	1
auto[2013265920:2147483647]	10	1			T345	1		T389	1		T385	1
auto[2147483648:2281701375]	6	1			T263	1		T320	1		T429	1
auto[2281701376:2415919103]	12	1			T142	1		T345	2		T389	1
auto[2415919104:2550136831]	10	1			T320	1		T409	1		T389	1
auto[2550136832:2684354559]	9	1			T83	1		T130	1		T409	1
auto[2684354560:2818572287]	10	1			T131	1		T345	1		T409	1
auto[2818572288:2952790015]	10	1			T130	1		T141	1		T320	1
auto[2952790016:3087007743]	14	1			T131	1		T345	2		T272	2
auto[3087007744:3221225471]	7	1			T83	1		T263	1		T389	1
auto[3221225472:3355443199]	12	1			T141	1		T345	1		T263	1
auto[3355443200:3489660927]	6	1			T131	1		T416	1		T389	1
auto[3489660928:3623878655]	11	1			T33	1		T108	1		T345	1
auto[3623878656:3758096383]	4	1			T283	1		T316	1		T432	1
auto[3758096384:3892314111]	10	1			T141	1		T389	1		T376	2
auto[3892314112:4026531839]	7	1			T263	1		T409	1		T403	1
auto[4026531840:4160749567]	7	1			T33	1		T142	1		T345	1
auto[4160749568:4294967295]	11	1			T130	1		T409	1		T305	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33700	1			T1	3		T2	19		T3	110
auto[0:134217727]	auto[1]	8	1			T320	1		T409	2		T376	1
auto[134217728:268435455]	auto[1]	10	1			T33	1		T108	1		T320	1
auto[268435456:402653183]	auto[1]	11	1			T131	1		T345	1		T283	1
auto[402653184:536870911]	auto[1]	8	1			T314	1		T429	1		T313	1
auto[536870912:671088639]	auto[1]	12	1			T272	2		T418	1		T382	1
auto[671088640:805306367]	auto[1]	9	1			T130	1		T263	1		T416	1
auto[805306368:939524095]	auto[1]	8	1			T263	1		T320	1		T389	1
auto[939524096:1073741823]	auto[1]	5	1			T320	1		T418	1		T283	1
auto[1073741824:1207959551]	auto[1]	7	1			T83	1		T283	2		T196	1
auto[1207959552:1342177279]	auto[1]	6	1			T320	1		T272	1		T227	1
auto[1342177280:1476395007]	auto[1]	13	1			T33	1		T130	1		T131	1
auto[1476395008:1610612735]	auto[1]	5	1			T430	1		T316	1		T431	1
auto[1610612736:1744830463]	auto[1]	14	1			T33	1		T83	1		T272	1
auto[1744830464:1879048191]	auto[1]	11	1			T33	1		T345	1		T263	1
auto[1879048192:2013265919]	auto[1]	12	1			T130	1		T141	1		T108	1
auto[2013265920:2147483647]	auto[1]	10	1			T345	1		T389	1		T385	1
auto[2147483648:2281701375]	auto[1]	6	1			T263	1		T320	1		T429	1
auto[2281701376:2415919103]	auto[1]	12	1			T142	1		T345	2		T389	1
auto[2415919104:2550136831]	auto[1]	10	1			T320	1		T409	1		T389	1
auto[2550136832:2684354559]	auto[1]	9	1			T83	1		T130	1		T409	1
auto[2684354560:2818572287]	auto[1]	10	1			T131	1		T345	1		T409	1
auto[2818572288:2952790015]	auto[1]	10	1			T130	1		T141	1		T320	1
auto[2952790016:3087007743]	auto[1]	14	1			T131	1		T345	2		T272	2
auto[3087007744:3221225471]	auto[1]	7	1			T83	1		T263	1		T389	1
auto[3221225472:3355443199]	auto[1]	12	1			T141	1		T345	1		T263	1
auto[3355443200:3489660927]	auto[1]	6	1			T131	1		T416	1		T389	1
auto[3489660928:3623878655]	auto[1]	11	1			T33	1		T108	1		T345	1
auto[3623878656:3758096383]	auto[1]	4	1			T283	1		T316	1		T432	1
auto[3758096384:3892314111]	auto[1]	10	1			T141	1		T389	1		T376	2
auto[3892314112:4026531839]	auto[1]	7	1			T263	1		T409	1		T403	1
auto[4026531840:4160749567]	auto[1]	7	1			T33	1		T142	1		T345	1
auto[4160749568:4294967295]	auto[1]	11	1			T130	1		T409	1		T305	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1644

1

T3

4

T14

3

T15

1

auto[1]

1800

1

T3

5

T4

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T18	1		T83	1		T128	1
auto[134217728:268435455]	84	1			T3	1		T15	1		T38	1
auto[268435456:402653183]	103	1			T18	1		T33	1		T47	1
auto[402653184:536870911]	97	1			T18	1		T83	1		T128	1
auto[536870912:671088639]	106	1			T3	1		T5	1		T26	1
auto[671088640:805306367]	103	1			T14	1		T44	1		T141	1
auto[805306368:939524095]	98	1			T44	1		T5	1		T64	1
auto[939524096:1073741823]	93	1			T15	1		T18	1		T38	1
auto[1073741824:1207959551]	101	1			T3	1		T18	2		T33	1
auto[1207959552:1342177279]	114	1			T4	1		T14	1		T18	1
auto[1342177280:1476395007]	109	1			T3	1		T18	1		T38	1
auto[1476395008:1610612735]	126	1			T33	1		T130	1		T49	1
auto[1610612736:1744830463]	111	1			T49	1		T50	1		T236	2
auto[1744830464:1879048191]	118	1			T33	1		T83	1		T128	1
auto[1879048192:2013265919]	123	1			T15	2		T25	1		T142	1
auto[2013265920:2147483647]	99	1			T14	1		T50	1		T142	1
auto[2147483648:2281701375]	106	1			T44	1		T25	1		T142	1
auto[2281701376:2415919103]	126	1			T15	1		T16	1		T5	2
auto[2415919104:2550136831]	98	1			T18	2		T129	1		T44	1
auto[2550136832:2684354559]	118	1			T47	1		T5	1		T64	1
auto[2684354560:2818572287]	109	1			T14	1		T18	1		T44	1
auto[2818572288:2952790015]	106	1			T18	3		T53	1		T59	3
auto[2952790016:3087007743]	95	1			T18	2		T44	1		T5	2
auto[3087007744:3221225471]	123	1			T14	1		T15	1		T18	1
auto[3221225472:3355443199]	122	1			T3	2		T18	1		T33	1
auto[3355443200:3489660927]	115	1			T3	1		T18	1		T47	1
auto[3489660928:3623878655]	111	1			T3	1		T18	1		T24	1
auto[3623878656:3758096383]	105	1			T18	3		T5	2		T45	2
auto[3758096384:3892314111]	113	1			T18	1		T50	1		T48	1
auto[3892314112:4026531839]	105	1			T3	1		T15	2		T18	1
auto[4026531840:4160749567]	104	1			T38	1		T128	1		T47	1
auto[4160749568:4294967295]	103	1			T24	1		T83	1		T130	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T18	1		T128	1		T45	1
auto[0:134217727]	auto[1]	56	1			T83	1		T142	1		T59	2
auto[134217728:268435455]	auto[0]	46	1			T59	2		T87	1		T310	2
auto[134217728:268435455]	auto[1]	38	1			T3	1		T15	1		T38	1
auto[268435456:402653183]	auto[0]	50	1			T18	1		T47	1		T50	1
auto[268435456:402653183]	auto[1]	53	1			T33	1		T48	1		T5	1
auto[402653184:536870911]	auto[0]	46	1			T128	1		T5	1		T26	1
auto[402653184:536870911]	auto[1]	51	1			T18	1		T83	1		T5	1
auto[536870912:671088639]	auto[0]	55	1			T3	1		T5	1		T60	1
auto[536870912:671088639]	auto[1]	51	1			T26	1		T45	1		T59	1
auto[671088640:805306367]	auto[0]	60	1			T14	1		T44	1		T141	1
auto[671088640:805306367]	auto[1]	43	1			T5	2		T67	1		T106	1
auto[805306368:939524095]	auto[0]	46	1			T265	1		T131	1		T90	1
auto[805306368:939524095]	auto[1]	52	1			T44	1		T5	1		T64	1
auto[939524096:1073741823]	auto[0]	32	1			T44	1		T45	1		T59	1
auto[939524096:1073741823]	auto[1]	61	1			T15	1		T18	1		T38	1
auto[1073741824:1207959551]	auto[0]	48	1			T3	1		T18	2		T50	1
auto[1073741824:1207959551]	auto[1]	53	1			T33	1		T44	1		T64	1
auto[1207959552:1342177279]	auto[0]	59	1			T14	1		T18	1		T128	1
auto[1207959552:1342177279]	auto[1]	55	1			T4	1		T24	1		T130	1
auto[1342177280:1476395007]	auto[0]	52	1			T3	1		T129	1		T44	1
auto[1342177280:1476395007]	auto[1]	57	1			T18	1		T38	1		T142	1
auto[1476395008:1610612735]	auto[0]	57	1			T44	2		T141	1		T142	1
auto[1476395008:1610612735]	auto[1]	69	1			T33	1		T130	1		T49	1
auto[1610612736:1744830463]	auto[0]	56	1			T50	1		T236	2		T48	1
auto[1610612736:1744830463]	auto[1]	55	1			T49	1		T59	1		T88	1
auto[1744830464:1879048191]	auto[0]	54	1			T33	1		T128	1		T45	1
auto[1744830464:1879048191]	auto[1]	64	1			T83	1		T130	1		T44	1
auto[1879048192:2013265919]	auto[0]	56	1			T15	1		T5	1		T45	1
auto[1879048192:2013265919]	auto[1]	67	1			T15	1		T25	1		T142	1
auto[2013265920:2147483647]	auto[0]	46	1			T50	1		T142	1		T45	1
auto[2013265920:2147483647]	auto[1]	53	1			T14	1		T5	2		T59	1
auto[2147483648:2281701375]	auto[0]	51	1			T44	1		T5	1		T59	2
auto[2147483648:2281701375]	auto[1]	55	1			T25	1		T142	1		T5	1
auto[2281701376:2415919103]	auto[0]	66	1			T5	1		T60	1		T64	1
auto[2281701376:2415919103]	auto[1]	60	1			T15	1		T16	1		T5	1
auto[2415919104:2550136831]	auto[0]	43	1			T44	1		T141	1		T5	1
auto[2415919104:2550136831]	auto[1]	55	1			T18	2		T129	1		T19	1
auto[2550136832:2684354559]	auto[0]	58	1			T47	1		T67	1		T28	1
auto[2550136832:2684354559]	auto[1]	60	1			T5	1		T64	1		T45	1
auto[2684354560:2818572287]	auto[0]	45	1			T14	1		T44	1		T5	2
auto[2684354560:2818572287]	auto[1]	64	1			T18	1		T25	1		T5	1
auto[2818572288:2952790015]	auto[0]	50	1			T18	1		T53	1		T111	1
auto[2818572288:2952790015]	auto[1]	56	1			T18	2		T59	3		T111	2
auto[2952790016:3087007743]	auto[0]	48	1			T18	1		T5	1		T26	1
auto[2952790016:3087007743]	auto[1]	47	1			T18	1		T44	1		T5	1
auto[3087007744:3221225471]	auto[0]	73	1			T5	1		T51	1		T60	2
auto[3087007744:3221225471]	auto[1]	50	1			T14	1		T15	1		T18	1
auto[3221225472:3355443199]	auto[0]	59	1			T49	1		T5	2		T45	1
auto[3221225472:3355443199]	auto[1]	63	1			T3	2		T18	1		T33	1
auto[3355443200:3489660927]	auto[0]	52	1			T5	1		T45	2		T68	1
auto[3355443200:3489660927]	auto[1]	63	1			T3	1		T18	1		T47	1
auto[3489660928:3623878655]	auto[0]	60	1			T3	1		T18	1		T83	1
auto[3489660928:3623878655]	auto[1]	51	1			T24	1		T60	1		T64	1
auto[3623878656:3758096383]	auto[0]	51	1			T18	1		T5	2		T45	2
auto[3623878656:3758096383]	auto[1]	54	1			T18	2		T94	1		T269	1
auto[3758096384:3892314111]	auto[0]	45	1			T50	1		T45	1		T59	1
auto[3758096384:3892314111]	auto[1]	68	1			T18	1		T48	1		T5	1
auto[3892314112:4026531839]	auto[0]	46	1			T18	1		T33	1		T47	1
auto[3892314112:4026531839]	auto[1]	59	1			T3	1		T15	2		T45	1
auto[4026531840:4160749567]	auto[0]	48	1			T128	1		T44	1		T60	1
auto[4026531840:4160749567]	auto[1]	56	1			T38	1		T47	1		T141	1
auto[4160749568:4294967295]	auto[0]	42	1			T130	1		T45	1		T222	1
auto[4160749568:4294967295]	auto[1]	61	1			T24	1		T83	1		T44	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1634

1

T3

3

T14

3

T15

1

auto[1]

1810

1

T3

6

T4

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T18	1		T33	1		T128	1
auto[134217728:268435455]	100	1			T18	1		T33	2		T48	1
auto[268435456:402653183]	89	1			T15	1		T18	1		T33	1
auto[402653184:536870911]	110	1			T3	1		T44	2		T48	1
auto[536870912:671088639]	113	1			T18	1		T129	1		T130	1
auto[671088640:805306367]	105	1			T3	1		T18	1		T129	1
auto[805306368:939524095]	101	1			T24	1		T83	1		T129	1
auto[939524096:1073741823]	120	1			T4	1		T15	1		T18	1
auto[1073741824:1207959551]	117	1			T38	1		T50	1		T142	1
auto[1207959552:1342177279]	113	1			T15	1		T18	1		T130	1
auto[1342177280:1476395007]	99	1			T18	1		T128	1		T5	2
auto[1476395008:1610612735]	103	1			T33	1		T47	1		T50	1
auto[1610612736:1744830463]	100	1			T14	1		T130	2		T44	1
auto[1744830464:1879048191]	101	1			T18	2		T130	1		T5	1
auto[1879048192:2013265919]	118	1			T15	1		T16	1		T83	1
auto[2013265920:2147483647]	107	1			T3	1		T18	1		T83	1
auto[2147483648:2281701375]	115	1			T3	1		T14	1		T18	1
auto[2281701376:2415919103]	102	1			T15	1		T83	1		T44	1
auto[2415919104:2550136831]	92	1			T18	1		T5	1		T64	2
auto[2550136832:2684354559]	118	1			T24	1		T128	1		T50	2
auto[2684354560:2818572287]	127	1			T3	1		T18	1		T44	1
auto[2818572288:2952790015]	105	1			T3	1		T14	1		T18	1
auto[2952790016:3087007743]	110	1			T3	1		T18	1		T38	1
auto[3087007744:3221225471]	111	1			T3	1		T49	1		T44	1
auto[3221225472:3355443199]	117	1			T14	1		T18	2		T49	2
auto[3355443200:3489660927]	100	1			T14	1		T18	1		T44	1
auto[3489660928:3623878655]	108	1			T15	1		T18	1		T38	1
auto[3623878656:3758096383]	109	1			T3	1		T15	1		T18	1
auto[3758096384:3892314111]	96	1			T18	3		T130	1		T44	1
auto[3892314112:4026531839]	108	1			T15	1		T18	1		T83	1
auto[4026531840:4160749567]	106	1			T5	1		T64	1		T45	1
auto[4160749568:4294967295]	122	1			T128	1		T44	2		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T18	1		T142	1		T26	1
auto[0:134217727]	auto[1]	46	1			T33	1		T128	1		T47	1
auto[134217728:268435455]	auto[0]	46	1			T33	2		T45	2		T87	1
auto[134217728:268435455]	auto[1]	54	1			T18	1		T48	1		T5	1
auto[268435456:402653183]	auto[0]	35	1			T51	1		T64	1		T45	1
auto[268435456:402653183]	auto[1]	54	1			T15	1		T18	1		T33	1
auto[402653184:536870911]	auto[0]	58	1			T142	1		T60	1		T45	2
auto[402653184:536870911]	auto[1]	52	1			T3	1		T44	2		T48	1
auto[536870912:671088639]	auto[0]	46	1			T18	1		T68	2		T28	1
auto[536870912:671088639]	auto[1]	67	1			T129	1		T130	1		T25	1
auto[671088640:805306367]	auto[0]	49	1			T3	1		T51	1		T60	1
auto[671088640:805306367]	auto[1]	56	1			T18	1		T129	1		T235	1
auto[805306368:939524095]	auto[0]	59	1			T129	1		T5	1		T45	1
auto[805306368:939524095]	auto[1]	42	1			T24	1		T83	1		T45	1
auto[939524096:1073741823]	auto[0]	44	1			T45	1		T59	1		T350	1
auto[939524096:1073741823]	auto[1]	76	1			T4	1		T15	1		T18	1
auto[1073741824:1207959551]	auto[0]	50	1			T50	1		T142	1		T5	1
auto[1073741824:1207959551]	auto[1]	67	1			T38	1		T5	3		T112	1
auto[1207959552:1342177279]	auto[0]	60	1			T130	1		T44	1		T212	2
auto[1207959552:1342177279]	auto[1]	53	1			T15	1		T18	1		T5	1
auto[1342177280:1476395007]	auto[0]	43	1			T5	1		T111	1		T21	1
auto[1342177280:1476395007]	auto[1]	56	1			T18	1		T128	1		T5	1
auto[1476395008:1610612735]	auto[0]	45	1			T47	1		T50	1		T45	1
auto[1476395008:1610612735]	auto[1]	58	1			T33	1		T64	1		T59	2
auto[1610612736:1744830463]	auto[0]	53	1			T44	1		T53	1		T59	1
auto[1610612736:1744830463]	auto[1]	47	1			T14	1		T130	2		T48	1
auto[1744830464:1879048191]	auto[0]	41	1			T20	1		T350	1		T212	1
auto[1744830464:1879048191]	auto[1]	60	1			T18	2		T130	1		T5	1
auto[1879048192:2013265919]	auto[0]	53	1			T83	1		T26	1		T87	1
auto[1879048192:2013265919]	auto[1]	65	1			T15	1		T16	1		T142	1
auto[2013265920:2147483647]	auto[0]	50	1			T236	1		T5	1		T60	1
auto[2013265920:2147483647]	auto[1]	57	1			T3	1		T18	1		T83	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T14	1		T47	1
auto[2147483648:2281701375]	auto[1]	62	1			T18	1		T24	1		T236	1
auto[2281701376:2415919103]	auto[0]	54	1			T15	1		T83	1		T60	1
auto[2281701376:2415919103]	auto[1]	48	1			T44	1		T59	1		T112	1
auto[2415919104:2550136831]	auto[0]	46	1			T18	1		T5	1		T64	1
auto[2415919104:2550136831]	auto[1]	46	1			T64	1		T111	1		T112	1
auto[2550136832:2684354559]	auto[0]	58	1			T128	1		T50	1		T5	1
auto[2550136832:2684354559]	auto[1]	60	1			T24	1		T50	1		T5	2
auto[2684354560:2818572287]	auto[0]	60	1			T18	1		T44	1		T5	2
auto[2684354560:2818572287]	auto[1]	67	1			T3	1		T60	1		T59	2
auto[2818572288:2952790015]	auto[0]	51	1			T3	1		T14	1		T128	1
auto[2818572288:2952790015]	auto[1]	54	1			T18	1		T47	1		T49	1
auto[2952790016:3087007743]	auto[0]	56	1			T128	1		T50	1		T5	3
auto[2952790016:3087007743]	auto[1]	54	1			T3	1		T18	1		T38	1
auto[3087007744:3221225471]	auto[0]	55	1			T49	1		T44	1		T45	3
auto[3087007744:3221225471]	auto[1]	56	1			T3	1		T19	1		T45	1
auto[3221225472:3355443199]	auto[0]	50	1			T14	1		T18	1		T44	1
auto[3221225472:3355443199]	auto[1]	67	1			T18	1		T49	2		T44	1
auto[3355443200:3489660927]	auto[0]	53	1			T60	1		T45	1		T59	1
auto[3355443200:3489660927]	auto[1]	47	1			T14	1		T18	1		T44	1
auto[3489660928:3623878655]	auto[0]	45	1			T222	1		T21	1		T94	1
auto[3489660928:3623878655]	auto[1]	63	1			T15	1		T18	1		T38	1
auto[3623878656:3758096383]	auto[0]	48	1			T47	1		T141	2		T265	1
auto[3623878656:3758096383]	auto[1]	61	1			T3	1		T15	1		T18	1
auto[3758096384:3892314111]	auto[0]	43	1			T18	2		T5	2		T51	1
auto[3758096384:3892314111]	auto[1]	53	1			T18	1		T130	1		T44	1
auto[3892314112:4026531839]	auto[0]	58	1			T18	1		T141	1		T5	1
auto[3892314112:4026531839]	auto[1]	50	1			T15	1		T83	1		T38	1
auto[4026531840:4160749567]	auto[0]	53	1			T5	1		T45	1		T111	1
auto[4026531840:4160749567]	auto[1]	53	1			T64	1		T59	2		T28	1
auto[4160749568:4294967295]	auto[0]	63	1			T128	1		T59	1		T6	1
auto[4160749568:4294967295]	auto[1]	59	1			T44	2		T5	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1632

1

T3

4

T14

2

T15

2

auto[1]

1812

1

T3

5

T4

1

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T3	1		T47	1		T5	3
auto[134217728:268435455]	94	1			T18	1		T47	2		T50	1
auto[268435456:402653183]	136	1			T3	1		T15	1		T47	1
auto[402653184:536870911]	116	1			T14	2		T18	1		T83	2
auto[536870912:671088639]	136	1			T18	1		T33	1		T128	1
auto[671088640:805306367]	101	1			T18	1		T128	1		T25	2
auto[805306368:939524095]	105	1			T33	2		T130	2		T44	1
auto[939524096:1073741823]	93	1			T18	2		T24	1		T129	1
auto[1073741824:1207959551]	111	1			T3	1		T15	1		T18	1
auto[1207959552:1342177279]	95	1			T130	1		T59	1		T112	1
auto[1342177280:1476395007]	109	1			T15	1		T25	1		T5	1
auto[1476395008:1610612735]	93	1			T3	1		T25	1		T5	4
auto[1610612736:1744830463]	102	1			T18	2		T44	1		T50	1
auto[1744830464:1879048191]	120	1			T15	1		T18	1		T49	1
auto[1879048192:2013265919]	112	1			T14	1		T15	1		T142	2
auto[2013265920:2147483647]	109	1			T3	1		T18	1		T130	1
auto[2147483648:2281701375]	98	1			T15	1		T18	1		T33	1
auto[2281701376:2415919103]	116	1			T16	1		T18	1		T44	2
auto[2415919104:2550136831]	115	1			T24	1		T128	2		T5	1
auto[2550136832:2684354559]	99	1			T15	1		T18	1		T44	1
auto[2684354560:2818572287]	108	1			T18	1		T83	1		T38	1
auto[2818572288:2952790015]	113	1			T18	1		T50	2		T141	3
auto[2952790016:3087007743]	105	1			T4	1		T14	1		T18	1
auto[3087007744:3221225471]	97	1			T18	1		T44	1		T45	2
auto[3221225472:3355443199]	102	1			T3	1		T18	2		T38	1
auto[3355443200:3489660927]	117	1			T49	1		T53	1		T60	1
auto[3489660928:3623878655]	94	1			T38	1		T5	1		T45	1
auto[3623878656:3758096383]	99	1			T3	1		T18	2		T24	1
auto[3758096384:3892314111]	95	1			T3	2		T14	1		T18	1
auto[3892314112:4026531839]	104	1			T18	1		T33	1		T44	1
auto[4026531840:4160749567]	107	1			T18	1		T130	1		T48	1
auto[4160749568:4294967295]	132	1			T15	1		T33	1		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T3	1		T5	1		T60	1
auto[0:134217727]	auto[1]	58	1			T47	1		T5	2		T64	1
auto[134217728:268435455]	auto[0]	48	1			T50	1		T5	2		T26	1
auto[134217728:268435455]	auto[1]	46	1			T18	1		T47	2		T45	3
auto[268435456:402653183]	auto[0]	75	1			T3	1		T47	1		T44	1
auto[268435456:402653183]	auto[1]	61	1			T15	1		T44	1		T142	1
auto[402653184:536870911]	auto[0]	54	1			T14	1		T128	1		T5	1
auto[402653184:536870911]	auto[1]	62	1			T14	1		T18	1		T83	2
auto[536870912:671088639]	auto[0]	63	1			T128	1		T47	1		T141	1
auto[536870912:671088639]	auto[1]	73	1			T18	1		T33	1		T5	1
auto[671088640:805306367]	auto[0]	48	1			T128	1		T142	1		T5	2
auto[671088640:805306367]	auto[1]	53	1			T18	1		T25	2		T64	1
auto[805306368:939524095]	auto[0]	54	1			T33	1		T130	2		T44	1
auto[805306368:939524095]	auto[1]	51	1			T33	1		T142	1		T5	2
auto[939524096:1073741823]	auto[0]	46	1			T18	1		T45	1		T59	1
auto[939524096:1073741823]	auto[1]	47	1			T18	1		T24	1		T129	1
auto[1073741824:1207959551]	auto[0]	57	1			T3	1		T5	1		T59	2
auto[1073741824:1207959551]	auto[1]	54	1			T15	1		T18	1		T83	1
auto[1207959552:1342177279]	auto[0]	38	1			T59	1		T65	1		T433	1
auto[1207959552:1342177279]	auto[1]	57	1			T130	1		T112	1		T212	1
auto[1342177280:1476395007]	auto[0]	58	1			T15	1		T51	1		T60	1
auto[1342177280:1476395007]	auto[1]	51	1			T25	1		T5	1		T111	1
auto[1476395008:1610612735]	auto[0]	49	1			T5	2		T87	1		T89	1
auto[1476395008:1610612735]	auto[1]	44	1			T3	1		T25	1		T5	2
auto[1610612736:1744830463]	auto[0]	39	1			T18	1		T44	1		T50	1
auto[1610612736:1744830463]	auto[1]	63	1			T18	1		T48	1		T19	1
auto[1744830464:1879048191]	auto[0]	56	1			T15	1		T236	1		T45	2
auto[1744830464:1879048191]	auto[1]	64	1			T18	1		T49	1		T5	2
auto[1879048192:2013265919]	auto[0]	49	1			T142	1		T45	1		T59	1
auto[1879048192:2013265919]	auto[1]	63	1			T14	1		T15	1		T142	1
auto[2013265920:2147483647]	auto[0]	50	1			T3	1		T5	1		T59	1
auto[2013265920:2147483647]	auto[1]	59	1			T18	1		T130	1		T5	1
auto[2147483648:2281701375]	auto[0]	51	1			T49	1		T59	1		T212	1
auto[2147483648:2281701375]	auto[1]	47	1			T15	1		T18	1		T33	1
auto[2281701376:2415919103]	auto[0]	65	1			T18	1		T44	1		T26	1
auto[2281701376:2415919103]	auto[1]	51	1			T16	1		T44	1		T5	1
auto[2415919104:2550136831]	auto[0]	54	1			T128	1		T5	1		T59	1
auto[2415919104:2550136831]	auto[1]	61	1			T24	1		T128	1		T59	2
auto[2550136832:2684354559]	auto[0]	50	1			T18	1		T51	1		T64	1
auto[2550136832:2684354559]	auto[1]	49	1			T15	1		T44	1		T111	1
auto[2684354560:2818572287]	auto[0]	50	1			T83	1		T26	1		T59	1
auto[2684354560:2818572287]	auto[1]	58	1			T18	1		T38	1		T129	1
auto[2818572288:2952790015]	auto[0]	54	1			T50	1		T141	2		T5	1
auto[2818572288:2952790015]	auto[1]	59	1			T18	1		T50	1		T141	1
auto[2952790016:3087007743]	auto[0]	45	1			T14	1		T18	1		T142	1
auto[2952790016:3087007743]	auto[1]	60	1			T4	1		T83	1		T130	1
auto[3087007744:3221225471]	auto[0]	48	1			T59	1		T88	1		T213	1
auto[3087007744:3221225471]	auto[1]	49	1			T18	1		T44	1		T45	2
auto[3221225472:3355443199]	auto[0]	45	1			T18	1		T38	1		T44	1
auto[3221225472:3355443199]	auto[1]	57	1			T3	1		T18	1		T130	1
auto[3355443200:3489660927]	auto[0]	55	1			T53	1		T60	1		T45	2
auto[3355443200:3489660927]	auto[1]	62	1			T49	1		T45	1		T222	1
auto[3489660928:3623878655]	auto[0]	38	1			T5	1		T45	1		T65	1
auto[3489660928:3623878655]	auto[1]	56	1			T38	1		T59	1		T112	1
auto[3623878656:3758096383]	auto[0]	53	1			T5	1		T88	1		T434	1
auto[3623878656:3758096383]	auto[1]	46	1			T3	1		T18	2		T24	1
auto[3758096384:3892314111]	auto[0]	39	1			T18	1		T44	1		T60	1
auto[3758096384:3892314111]	auto[1]	56	1			T3	2		T14	1		T142	1
auto[3892314112:4026531839]	auto[0]	43	1			T18	1		T33	1		T60	1
auto[3892314112:4026531839]	auto[1]	61	1			T44	1		T25	1		T48	1
auto[4026531840:4160749567]	auto[0]	47	1			T5	1		T59	2		T68	1
auto[4026531840:4160749567]	auto[1]	60	1			T18	1		T130	1		T48	1
auto[4160749568:4294967295]	auto[0]	58	1			T33	1		T128	1		T129	1
auto[4160749568:4294967295]	auto[1]	74	1			T15	1		T38	1		T49	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1620

1

T3

2

T14

3

T15

1

auto[1]

1822

1

T3

7

T4

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T18	1		T44	1		T5	3
auto[134217728:268435455]	108	1			T38	1		T128	1		T47	1
auto[268435456:402653183]	109	1			T18	1		T33	1		T83	1
auto[402653184:536870911]	89	1			T3	1		T18	2		T49	1
auto[536870912:671088639]	91	1			T59	2		T350	1		T28	1
auto[671088640:805306367]	106	1			T3	1		T18	1		T47	1
auto[805306368:939524095]	117	1			T18	3		T130	3		T44	1
auto[939524096:1073741823]	103	1			T15	1		T33	1		T24	1
auto[1073741824:1207959551]	96	1			T3	1		T15	1		T83	1
auto[1207959552:1342177279]	108	1			T18	1		T141	1		T5	2
auto[1342177280:1476395007]	98	1			T16	1		T128	1		T129	1
auto[1476395008:1610612735]	103	1			T3	1		T15	2		T24	1
auto[1610612736:1744830463]	103	1			T14	1		T128	1		T130	1
auto[1744830464:1879048191]	113	1			T3	1		T18	2		T47	1
auto[1879048192:2013265919]	116	1			T18	4		T83	1		T129	1
auto[2013265920:2147483647]	113	1			T38	1		T130	1		T44	1
auto[2147483648:2281701375]	103	1			T18	1		T33	1		T48	1
auto[2281701376:2415919103]	131	1			T47	1		T142	1		T5	1
auto[2415919104:2550136831]	106	1			T14	2		T83	1		T47	1
auto[2550136832:2684354559]	110	1			T38	1		T44	2		T25	1
auto[2684354560:2818572287]	120	1			T15	1		T33	1		T50	1
auto[2818572288:2952790015]	118	1			T3	1		T15	1		T49	1
auto[2952790016:3087007743]	99	1			T18	1		T33	1		T128	1
auto[3087007744:3221225471]	111	1			T3	1		T14	2		T18	2
auto[3221225472:3355443199]	103	1			T15	1		T18	1		T38	1
auto[3355443200:3489660927]	117	1			T18	2		T44	1		T141	1
auto[3489660928:3623878655]	110	1			T128	1		T5	4		T45	2
auto[3623878656:3758096383]	112	1			T18	1		T130	1		T25	1
auto[3758096384:3892314111]	100	1			T3	1		T128	1		T129	1
auto[3892314112:4026531839]	111	1			T18	1		T128	1		T44	3
auto[4026531840:4160749567]	115	1			T3	1		T4	1		T33	1
auto[4160749568:4294967295]	101	1			T15	1		T18	1		T50	1