Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3067

1

T3

9

T4

1

T14

5

auto[1]

325

1

T33

5

T83

5

T130

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T18	1		T130	1		T47	2
auto[134217728:268435455]	110	1			T3	1		T18	2		T5	3
auto[268435456:402653183]	109	1			T3	2		T83	1		T44	1
auto[402653184:536870911]	124	1			T3	1		T18	2		T33	1
auto[536870912:671088639]	109	1			T15	1		T141	1		T51	1
auto[671088640:805306367]	105	1			T14	1		T18	1		T83	1
auto[805306368:939524095]	105	1			T14	1		T83	1		T130	1
auto[939524096:1073741823]	117	1			T15	1		T18	1		T83	1
auto[1073741824:1207959551]	101	1			T33	1		T24	1		T83	1
auto[1207959552:1342177279]	114	1			T18	1		T44	1		T141	1
auto[1342177280:1476395007]	106	1			T3	1		T15	1		T18	1
auto[1476395008:1610612735]	106	1			T15	1		T33	1		T83	1
auto[1610612736:1744830463]	111	1			T3	1		T18	1		T128	2
auto[1744830464:1879048191]	104	1			T15	1		T18	1		T33	1
auto[1879048192:2013265919]	98	1			T3	1		T129	1		T130	1
auto[2013265920:2147483647]	111	1			T14	1		T128	1		T5	3
auto[2147483648:2281701375]	120	1			T18	1		T83	1		T130	1
auto[2281701376:2415919103]	115	1			T18	1		T33	3		T24	1
auto[2415919104:2550136831]	108	1			T18	1		T83	1		T38	1
auto[2550136832:2684354559]	110	1			T18	1		T24	1		T50	1
auto[2684354560:2818572287]	100	1			T47	1		T141	1		T5	1
auto[2818572288:2952790015]	111	1			T33	1		T128	1		T236	1
auto[2952790016:3087007743]	96	1			T33	1		T44	1		T50	1
auto[3087007744:3221225471]	98	1			T18	1		T33	1		T38	1
auto[3221225472:3355443199]	114	1			T3	1		T4	1		T15	1
auto[3355443200:3489660927]	100	1			T3	1		T14	1		T18	2
auto[3489660928:3623878655]	98	1			T129	1		T130	1		T48	1
auto[3623878656:3758096383]	86	1			T18	1		T83	1		T5	2
auto[3758096384:3892314111]	109	1			T14	1		T16	1		T18	1
auto[3892314112:4026531839]	98	1			T18	3		T38	1		T5	2
auto[4026531840:4160749567]	114	1			T18	1		T128	1		T129	1
auto[4160749568:4294967295]	99	1			T15	2		T18	1		T33	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	81	1			T18	1		T130	1		T47	2
auto[0:134217727]	auto[1]	5	1			T141	1		T320	1		T376	1
auto[134217728:268435455]	auto[0]	98	1			T3	1		T18	2		T5	3
auto[134217728:268435455]	auto[1]	12	1			T108	1		T320	2		T389	1
auto[268435456:402653183]	auto[0]	103	1			T3	2		T83	1		T44	1
auto[268435456:402653183]	auto[1]	6	1			T131	1		T305	1		T403	1
auto[402653184:536870911]	auto[0]	108	1			T3	1		T18	2		T49	2
auto[402653184:536870911]	auto[1]	16	1			T33	1		T130	1		T416	1
auto[536870912:671088639]	auto[0]	98	1			T15	1		T141	1		T51	1
auto[536870912:671088639]	auto[1]	11	1			T263	1		T320	1		T402	1
auto[671088640:805306367]	auto[0]	96	1			T14	1		T18	1		T50	1
auto[671088640:805306367]	auto[1]	9	1			T83	1		T142	1		T345	1
auto[805306368:939524095]	auto[0]	95	1			T14	1		T25	1		T5	1
auto[805306368:939524095]	auto[1]	10	1			T83	1		T130	1		T131	1
auto[939524096:1073741823]	auto[0]	101	1			T15	1		T18	1		T128	1
auto[939524096:1073741823]	auto[1]	16	1			T83	1		T345	1		T263	1
auto[1073741824:1207959551]	auto[0]	92	1			T33	1		T24	1		T83	1
auto[1073741824:1207959551]	auto[1]	9	1			T131	1		T272	1		T418	1
auto[1207959552:1342177279]	auto[0]	107	1			T18	1		T44	1		T141	1
auto[1207959552:1342177279]	auto[1]	7	1			T263	1		T409	1		T385	1
auto[1342177280:1476395007]	auto[0]	95	1			T3	1		T15	1		T18	1
auto[1342177280:1476395007]	auto[1]	11	1			T108	1		T409	2		T389	1
auto[1476395008:1610612735]	auto[0]	96	1			T15	1		T33	1		T83	1
auto[1476395008:1610612735]	auto[1]	10	1			T141	1		T345	1		T305	1
auto[1610612736:1744830463]	auto[0]	99	1			T3	1		T18	1		T128	2
auto[1610612736:1744830463]	auto[1]	12	1			T320	1		T305	2		T403	1
auto[1744830464:1879048191]	auto[0]	89	1			T15	1		T18	1		T130	1
auto[1744830464:1879048191]	auto[1]	15	1			T33	1		T131	1		T320	1
auto[1879048192:2013265919]	auto[0]	92	1			T3	1		T129	1		T130	1
auto[1879048192:2013265919]	auto[1]	6	1			T345	1		T305	1		T376	1
auto[2013265920:2147483647]	auto[0]	97	1			T14	1		T128	1		T5	3
auto[2013265920:2147483647]	auto[1]	14	1			T108	1		T345	1		T272	1
auto[2147483648:2281701375]	auto[0]	108	1			T18	1		T47	1		T49	1
auto[2147483648:2281701375]	auto[1]	12	1			T83	1		T130	1		T142	1
auto[2281701376:2415919103]	auto[0]	104	1			T18	1		T33	1		T24	1
auto[2281701376:2415919103]	auto[1]	11	1			T33	2		T130	3		T409	1
auto[2415919104:2550136831]	auto[0]	98	1			T18	1		T83	1		T38	1
auto[2415919104:2550136831]	auto[1]	10	1			T130	1		T131	1		T345	1
auto[2550136832:2684354559]	auto[0]	103	1			T18	1		T24	1		T50	1
auto[2550136832:2684354559]	auto[1]	7	1			T389	1		T382	1		T305	1
auto[2684354560:2818572287]	auto[0]	93	1			T47	1		T141	1		T5	1
auto[2684354560:2818572287]	auto[1]	7	1			T131	1		T272	1		T305	1
auto[2818572288:2952790015]	auto[0]	102	1			T33	1		T128	1		T236	1
auto[2818572288:2952790015]	auto[1]	9	1			T263	2		T272	2		T389	1
auto[2952790016:3087007743]	auto[0]	89	1			T33	1		T44	1		T50	1
auto[2952790016:3087007743]	auto[1]	7	1			T263	1		T389	1		T314	1
auto[3087007744:3221225471]	auto[0]	86	1			T18	1		T38	1		T111	1
auto[3087007744:3221225471]	auto[1]	12	1			T33	1		T141	1		T409	1
auto[3221225472:3355443199]	auto[0]	96	1			T3	1		T4	1		T15	1
auto[3221225472:3355443199]	auto[1]	18	1			T141	1		T345	1		T320	1
auto[3355443200:3489660927]	auto[0]	96	1			T3	1		T14	1		T18	2
auto[3355443200:3489660927]	auto[1]	4	1			T409	1		T389	1		T313	1
auto[3489660928:3623878655]	auto[0]	88	1			T129	1		T48	1		T142	1
auto[3489660928:3623878655]	auto[1]	10	1			T130	1		T416	1		T417	1
auto[3623878656:3758096383]	auto[0]	74	1			T18	1		T83	1		T5	2
auto[3623878656:3758096383]	auto[1]	12	1			T131	1		T320	2		T389	2
auto[3758096384:3892314111]	auto[0]	97	1			T14	1		T16	1		T18	1
auto[3758096384:3892314111]	auto[1]	12	1			T272	1		T283	1		T382	1
auto[3892314112:4026531839]	auto[0]	91	1			T18	3		T38	1		T5	2
auto[3892314112:4026531839]	auto[1]	7	1			T416	1		T283	1		T257	1
auto[4026531840:4160749567]	auto[0]	104	1			T18	1		T128	1		T129	1
auto[4026531840:4160749567]	auto[1]	10	1			T345	1		T263	1		T409	1
auto[4160749568:4294967295]	auto[0]	91	1			T15	2		T18	1		T33	1
auto[4160749568:4294967295]	auto[1]	8	1			T83	1		T416	1		T314	1