Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.04 97.68 98.65 100.00 99.02 98.41 91.14


Total test records in report: 1088
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T1011 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2729713827 May 16 02:41:04 PM PDT 24 May 16 02:41:07 PM PDT 24 15233870 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3137506907 May 16 02:41:03 PM PDT 24 May 16 02:41:10 PM PDT 24 121619317 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1871859413 May 16 02:40:42 PM PDT 24 May 16 02:40:47 PM PDT 24 683986895 ps
T1014 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3190727085 May 16 02:41:24 PM PDT 24 May 16 02:41:32 PM PDT 24 423061350 ps
T1015 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1531843866 May 16 02:41:09 PM PDT 24 May 16 02:41:12 PM PDT 24 21971491 ps
T166 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1380585429 May 16 02:41:22 PM PDT 24 May 16 02:41:30 PM PDT 24 290064365 ps
T1016 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2347312782 May 16 02:41:30 PM PDT 24 May 16 02:41:34 PM PDT 24 33358355 ps
T1017 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1707851908 May 16 02:41:29 PM PDT 24 May 16 02:41:33 PM PDT 24 57682647 ps
T1018 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.115406624 May 16 02:40:42 PM PDT 24 May 16 02:40:47 PM PDT 24 226641231 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3632999356 May 16 02:41:19 PM PDT 24 May 16 02:41:25 PM PDT 24 394329631 ps
T1020 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3927302465 May 16 02:41:21 PM PDT 24 May 16 02:41:26 PM PDT 24 44348278 ps
T1021 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.578197576 May 16 02:41:30 PM PDT 24 May 16 02:41:36 PM PDT 24 14782121 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3404264602 May 16 02:40:53 PM PDT 24 May 16 02:40:58 PM PDT 24 160445140 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2688202603 May 16 02:40:53 PM PDT 24 May 16 02:40:57 PM PDT 24 106270356 ps
T1024 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2195588084 May 16 02:41:20 PM PDT 24 May 16 02:41:28 PM PDT 24 338930677 ps
T177 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1995540239 May 16 02:41:03 PM PDT 24 May 16 02:41:10 PM PDT 24 95756491 ps
T1025 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3728908519 May 16 02:41:22 PM PDT 24 May 16 02:41:28 PM PDT 24 330366884 ps
T1026 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4227936824 May 16 02:41:19 PM PDT 24 May 16 02:41:24 PM PDT 24 574567969 ps
T1027 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3501110377 May 16 02:41:22 PM PDT 24 May 16 02:41:36 PM PDT 24 1372115280 ps
T1028 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2319892771 May 16 02:41:20 PM PDT 24 May 16 02:41:24 PM PDT 24 43288662 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1437307801 May 16 02:40:54 PM PDT 24 May 16 02:41:06 PM PDT 24 401030622 ps
T1030 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.85885490 May 16 02:41:21 PM PDT 24 May 16 02:41:27 PM PDT 24 78321821 ps
T158 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2042257264 May 16 02:41:18 PM PDT 24 May 16 02:41:25 PM PDT 24 680503281 ps
T1031 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2479574716 May 16 02:41:02 PM PDT 24 May 16 02:41:07 PM PDT 24 96267363 ps
T1032 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2344979436 May 16 02:41:22 PM PDT 24 May 16 02:41:27 PM PDT 24 121561959 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3256787875 May 16 02:41:21 PM PDT 24 May 16 02:41:29 PM PDT 24 88848385 ps
T1034 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.656760560 May 16 02:41:29 PM PDT 24 May 16 02:41:33 PM PDT 24 11483153 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1094363663 May 16 02:41:11 PM PDT 24 May 16 02:41:21 PM PDT 24 142599819 ps
T1036 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3170561197 May 16 02:41:32 PM PDT 24 May 16 02:41:38 PM PDT 24 29389519 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.313668111 May 16 02:41:20 PM PDT 24 May 16 02:41:25 PM PDT 24 136413477 ps
T1038 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1461311167 May 16 02:41:28 PM PDT 24 May 16 02:41:32 PM PDT 24 36835922 ps
T1039 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.360702942 May 16 02:41:21 PM PDT 24 May 16 02:41:26 PM PDT 24 86005854 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2572845345 May 16 02:40:43 PM PDT 24 May 16 02:40:49 PM PDT 24 49310277 ps
T176 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2591990786 May 16 02:41:28 PM PDT 24 May 16 02:41:33 PM PDT 24 105455904 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4007600234 May 16 02:41:10 PM PDT 24 May 16 02:41:21 PM PDT 24 1442636485 ps
T167 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2755899843 May 16 02:40:44 PM PDT 24 May 16 02:40:52 PM PDT 24 100340172 ps
T1042 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3821579495 May 16 02:41:09 PM PDT 24 May 16 02:41:13 PM PDT 24 69152305 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1483768246 May 16 02:41:03 PM PDT 24 May 16 02:41:09 PM PDT 24 116097049 ps
T1044 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4134360869 May 16 02:41:30 PM PDT 24 May 16 02:41:35 PM PDT 24 54869736 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3592608176 May 16 02:41:11 PM PDT 24 May 16 02:41:19 PM PDT 24 1400375721 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1694312150 May 16 02:40:53 PM PDT 24 May 16 02:41:10 PM PDT 24 1728099166 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2929722538 May 16 02:41:13 PM PDT 24 May 16 02:41:20 PM PDT 24 235520290 ps
T1048 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4046427932 May 16 02:41:01 PM PDT 24 May 16 02:41:05 PM PDT 24 119625819 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1590242590 May 16 02:40:42 PM PDT 24 May 16 02:40:47 PM PDT 24 94432967 ps
T1050 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1939628630 May 16 02:41:10 PM PDT 24 May 16 02:41:13 PM PDT 24 93419017 ps
T1051 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.397814225 May 16 02:40:55 PM PDT 24 May 16 02:40:58 PM PDT 24 409300121 ps
T1052 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2275628492 May 16 02:41:19 PM PDT 24 May 16 02:41:22 PM PDT 24 52531716 ps
T161 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4148334785 May 16 02:40:40 PM PDT 24 May 16 02:40:49 PM PDT 24 729803131 ps
T1053 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2075050361 May 16 02:40:55 PM PDT 24 May 16 02:40:59 PM PDT 24 18899529 ps
T1054 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2150200565 May 16 02:41:21 PM PDT 24 May 16 02:41:26 PM PDT 24 11921126 ps
T155 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.954680605 May 16 02:40:59 PM PDT 24 May 16 02:41:05 PM PDT 24 447798641 ps
T1055 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.691727213 May 16 02:41:31 PM PDT 24 May 16 02:41:36 PM PDT 24 25235509 ps
T1056 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2444167475 May 16 02:41:20 PM PDT 24 May 16 02:41:24 PM PDT 24 118241397 ps
T1057 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.74595578 May 16 02:41:10 PM PDT 24 May 16 02:41:15 PM PDT 24 85379067 ps
T1058 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2596158347 May 16 02:41:02 PM PDT 24 May 16 02:41:06 PM PDT 24 193792925 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3506372780 May 16 02:40:45 PM PDT 24 May 16 02:40:57 PM PDT 24 469880528 ps
T1060 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.519755070 May 16 02:41:32 PM PDT 24 May 16 02:41:37 PM PDT 24 9626422 ps
T1061 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2160641341 May 16 02:41:32 PM PDT 24 May 16 02:41:37 PM PDT 24 132875608 ps
T1062 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1322501732 May 16 02:41:32 PM PDT 24 May 16 02:41:37 PM PDT 24 18984817 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3242791246 May 16 02:41:00 PM PDT 24 May 16 02:41:03 PM PDT 24 85517121 ps
T1064 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3348475850 May 16 02:41:19 PM PDT 24 May 16 02:41:25 PM PDT 24 119807670 ps
T1065 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1336515553 May 16 02:41:03 PM PDT 24 May 16 02:41:07 PM PDT 24 165174897 ps
T1066 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3372610538 May 16 02:40:54 PM PDT 24 May 16 02:41:00 PM PDT 24 825213615 ps
T1067 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.714350196 May 16 02:41:02 PM PDT 24 May 16 02:41:06 PM PDT 24 49671988 ps
T1068 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3033609360 May 16 02:41:31 PM PDT 24 May 16 02:41:36 PM PDT 24 12558071 ps
T156 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1418786652 May 16 02:40:53 PM PDT 24 May 16 02:41:02 PM PDT 24 2921710616 ps
T1069 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2905760611 May 16 02:41:04 PM PDT 24 May 16 02:41:08 PM PDT 24 46040290 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2871675867 May 16 02:41:12 PM PDT 24 May 16 02:41:17 PM PDT 24 13723371 ps
T168 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1938526997 May 16 02:41:13 PM PDT 24 May 16 02:41:25 PM PDT 24 632325553 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.926214546 May 16 02:41:22 PM PDT 24 May 16 02:41:27 PM PDT 24 38629423 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3587120146 May 16 02:41:00 PM PDT 24 May 16 02:41:04 PM PDT 24 345919160 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2385682976 May 16 02:40:52 PM PDT 24 May 16 02:41:25 PM PDT 24 5110810822 ps
T1074 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4058407414 May 16 02:40:43 PM PDT 24 May 16 02:40:49 PM PDT 24 156956445 ps
T1075 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1815338111 May 16 02:41:30 PM PDT 24 May 16 02:41:34 PM PDT 24 29280759 ps
T1076 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1583794210 May 16 02:41:19 PM PDT 24 May 16 02:41:23 PM PDT 24 72542010 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3010099978 May 16 02:40:55 PM PDT 24 May 16 02:41:06 PM PDT 24 538124887 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1107207577 May 16 02:41:02 PM PDT 24 May 16 02:41:05 PM PDT 24 146211477 ps
T1079 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1675671195 May 16 02:41:31 PM PDT 24 May 16 02:41:36 PM PDT 24 12558936 ps
T174 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3990854457 May 16 02:41:22 PM PDT 24 May 16 02:41:28 PM PDT 24 256146721 ps
T1080 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.30723401 May 16 02:41:01 PM PDT 24 May 16 02:41:07 PM PDT 24 161777722 ps
T1081 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.813845004 May 16 02:41:28 PM PDT 24 May 16 02:41:33 PM PDT 24 49817116 ps
T1082 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.656076920 May 16 02:40:43 PM PDT 24 May 16 02:40:49 PM PDT 24 79719444 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3677780721 May 16 02:40:53 PM PDT 24 May 16 02:40:56 PM PDT 24 22531626 ps
T1084 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.436617442 May 16 02:41:31 PM PDT 24 May 16 02:41:36 PM PDT 24 20401854 ps
T1085 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2985727737 May 16 02:41:22 PM PDT 24 May 16 02:41:27 PM PDT 24 68565221 ps
T1086 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1702051114 May 16 02:40:54 PM PDT 24 May 16 02:41:02 PM PDT 24 345062782 ps
T1087 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4136629006 May 16 02:41:02 PM PDT 24 May 16 02:41:08 PM PDT 24 50322774 ps
T1088 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.413176314 May 16 02:41:11 PM PDT 24 May 16 02:41:18 PM PDT 24 93417384 ps

Test location /workspace/coverage/default/3.keymgr_stress_all.3060715187
Short name T18
Test name
Test status
Simulation time 761693581 ps
CPU time 27.88 seconds
Started May 16 03:13:38 PM PDT 24
Finished May 16 03:14:10 PM PDT 24
Peak memory 222620 kb
Host smart-1fb8d6fd-5ef7-40b6-a9dd-65afe9e293f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060715187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3060715187
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.343325623
Short name T5
Test name
Test status
Simulation time 7417374856 ps
CPU time 60.2 seconds
Started May 16 03:14:55 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 222608 kb
Host smart-b67c0fbe-39df-4712-984c-b0fbc118e3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343325623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.343325623
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1485904404
Short name T44
Test name
Test status
Simulation time 4851464102 ps
CPU time 29.98 seconds
Started May 16 03:16:48 PM PDT 24
Finished May 16 03:17:22 PM PDT 24
Peak memory 214628 kb
Host smart-2acc7b41-a29a-4fc1-86fc-6927689a7e7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485904404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1485904404
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2872798962
Short name T10
Test name
Test status
Simulation time 674836095 ps
CPU time 16.89 seconds
Started May 16 03:13:11 PM PDT 24
Finished May 16 03:13:31 PM PDT 24
Peak memory 237168 kb
Host smart-b4b67654-1ed9-4aa6-b65a-8b3e6b06538d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872798962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2872798962
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.462482184
Short name T15
Test name
Test status
Simulation time 217103575 ps
CPU time 8.23 seconds
Started May 16 03:14:23 PM PDT 24
Finished May 16 03:14:34 PM PDT 24
Peak memory 222052 kb
Host smart-3e98bfab-b962-4c7c-834c-c433043865b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462482184 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.462482184
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2594868464
Short name T152
Test name
Test status
Simulation time 316206208 ps
CPU time 6.61 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 213976 kb
Host smart-e29a718c-2459-456b-a4ba-f87bbc8e3ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594868464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2594868464
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3037903949
Short name T59
Test name
Test status
Simulation time 1974477309 ps
CPU time 25.78 seconds
Started May 16 03:17:57 PM PDT 24
Finished May 16 03:18:28 PM PDT 24
Peak memory 216092 kb
Host smart-40623272-7dae-4d70-969f-57c7e17ab8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037903949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3037903949
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.857476230
Short name T45
Test name
Test status
Simulation time 3332787155 ps
CPU time 31.12 seconds
Started May 16 03:13:20 PM PDT 24
Finished May 16 03:13:56 PM PDT 24
Peak memory 222608 kb
Host smart-f0e20738-30a1-49fa-ac2f-3c876e377c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857476230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.857476230
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1373274405
Short name T130
Test name
Test status
Simulation time 884560121 ps
CPU time 11.09 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:18:07 PM PDT 24
Peak memory 214980 kb
Host smart-9d62d7b3-7e40-4521-86b4-38454c93ba69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373274405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1373274405
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4048621605
Short name T8
Test name
Test status
Simulation time 152750765 ps
CPU time 4.97 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:35 PM PDT 24
Peak memory 222720 kb
Host smart-897bb0b2-fe24-4137-84ce-571f353da2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048621605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4048621605
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2254525143
Short name T310
Test name
Test status
Simulation time 515475794 ps
CPU time 5.76 seconds
Started May 16 03:14:19 PM PDT 24
Finished May 16 03:14:27 PM PDT 24
Peak memory 214280 kb
Host smart-42c07dda-e12b-4908-8351-7bc56ce5b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254525143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2254525143
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.12605399
Short name T283
Test name
Test status
Simulation time 2213509720 ps
CPU time 122.97 seconds
Started May 16 03:16:12 PM PDT 24
Finished May 16 03:18:21 PM PDT 24
Peak memory 218580 kb
Host smart-9e5e1265-c5d1-4c4d-9414-df6c124be6d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12605399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.12605399
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2836300882
Short name T1
Test name
Test status
Simulation time 49545310 ps
CPU time 2.11 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 210072 kb
Host smart-0bdfb3e6-c578-4437-a0c4-14a8d211157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836300882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2836300882
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3015975460
Short name T116
Test name
Test status
Simulation time 2912842359 ps
CPU time 35.63 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:17:09 PM PDT 24
Peak memory 222696 kb
Host smart-90ec06dd-d163-44bd-9029-9f2a7f7c4d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015975460 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3015975460
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1049101418
Short name T114
Test name
Test status
Simulation time 699229955 ps
CPU time 13.39 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:20 PM PDT 24
Peak memory 214204 kb
Host smart-d36245c9-c1d8-4761-b90f-67aa4c7c431b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049101418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1049101418
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.532056058
Short name T314
Test name
Test status
Simulation time 2848925379 ps
CPU time 42.25 seconds
Started May 16 03:14:46 PM PDT 24
Finished May 16 03:15:30 PM PDT 24
Peak memory 215784 kb
Host smart-2a3687e2-3dd3-4137-8a0a-17b67151dab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532056058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.532056058
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3763103682
Short name T97
Test name
Test status
Simulation time 135321458 ps
CPU time 5.4 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:12 PM PDT 24
Peak memory 214464 kb
Host smart-ecd2a67a-e71c-494d-be1c-1da3026ffab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763103682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3763103682
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3052524493
Short name T83
Test name
Test status
Simulation time 60242047 ps
CPU time 4.05 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:02 PM PDT 24
Peak memory 215508 kb
Host smart-70348ed1-099d-4f76-b237-7a94a5f23bab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052524493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3052524493
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4006278324
Short name T213
Test name
Test status
Simulation time 7449816050 ps
CPU time 165.91 seconds
Started May 16 03:18:46 PM PDT 24
Finished May 16 03:21:37 PM PDT 24
Peak memory 222584 kb
Host smart-a1a9a3d0-72fa-479a-9242-a08a62bf1f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006278324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4006278324
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1528741520
Short name T320
Test name
Test status
Simulation time 219652954 ps
CPU time 9.79 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:58 PM PDT 24
Peak memory 214856 kb
Host smart-0f23f68d-a842-4b8b-8f4c-b230e6c05a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528741520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1528741520
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3737227198
Short name T313
Test name
Test status
Simulation time 2515411013 ps
CPU time 42.39 seconds
Started May 16 03:16:50 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 216196 kb
Host smart-2fa96077-b23c-4fe6-b8af-f2a56a05703d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737227198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3737227198
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1291563117
Short name T117
Test name
Test status
Simulation time 402382883 ps
CPU time 1.91 seconds
Started May 16 02:40:44 PM PDT 24
Finished May 16 02:40:48 PM PDT 24
Peak memory 214356 kb
Host smart-00a92e3c-ff07-4f16-b0f2-76f9ab364943
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291563117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1291563117
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.981965204
Short name T52
Test name
Test status
Simulation time 56647824337 ps
CPU time 568.44 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 222576 kb
Host smart-ec446df9-a56c-4a56-a8bf-36c8054b43bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981965204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.981965204
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4030606046
Short name T305
Test name
Test status
Simulation time 625696527 ps
CPU time 32.17 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:18:19 PM PDT 24
Peak memory 215824 kb
Host smart-4fd6aefd-c7f1-478a-8dc1-2d920e82c574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030606046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4030606046
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1516428655
Short name T41
Test name
Test status
Simulation time 1229874604 ps
CPU time 6.9 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 214324 kb
Host smart-d4a19055-ab8e-4c43-87ac-8edd31aa9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516428655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1516428655
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3296996691
Short name T144
Test name
Test status
Simulation time 87180774 ps
CPU time 5.27 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:43 PM PDT 24
Peak memory 222828 kb
Host smart-65980aeb-0506-46b9-be6b-f7240d05cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296996691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3296996691
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2049561947
Short name T20
Test name
Test status
Simulation time 175247200 ps
CPU time 4.25 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:00 PM PDT 24
Peak memory 222652 kb
Host smart-2f4d798d-3e0e-48a0-8b9f-da9408ea6218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049561947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2049561947
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2088041078
Short name T16
Test name
Test status
Simulation time 61162051 ps
CPU time 2.52 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:14:49 PM PDT 24
Peak memory 208440 kb
Host smart-108abaa8-6c1d-42cd-9c11-3740eab8dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088041078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2088041078
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2886504142
Short name T438
Test name
Test status
Simulation time 51516490 ps
CPU time 0.74 seconds
Started May 16 03:15:49 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 205888 kb
Host smart-ca06d61f-8c4a-4b13-aede-e145d4b28a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886504142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2886504142
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1230721805
Short name T257
Test name
Test status
Simulation time 2119852419 ps
CPU time 105.44 seconds
Started May 16 03:16:29 PM PDT 24
Finished May 16 03:18:20 PM PDT 24
Peak memory 214392 kb
Host smart-38cd4eb4-86fa-472a-abb3-f6724cf7f27e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230721805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1230721805
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1522768992
Short name T23
Test name
Test status
Simulation time 54355828 ps
CPU time 2.07 seconds
Started May 16 03:18:40 PM PDT 24
Finished May 16 03:18:46 PM PDT 24
Peak memory 208896 kb
Host smart-135db668-def0-48a7-a40c-9fa420730c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522768992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1522768992
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1520710463
Short name T95
Test name
Test status
Simulation time 409470667 ps
CPU time 7.68 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:13:31 PM PDT 24
Peak memory 209940 kb
Host smart-1571ad8f-73cd-414c-94dd-1112df362e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520710463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1520710463
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2972787243
Short name T246
Test name
Test status
Simulation time 1205369330 ps
CPU time 12.6 seconds
Started May 16 03:13:18 PM PDT 24
Finished May 16 03:13:35 PM PDT 24
Peak memory 222588 kb
Host smart-987b7e95-9027-42ad-8040-939cc44d36f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972787243 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2972787243
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3046860225
Short name T272
Test name
Test status
Simulation time 55887514 ps
CPU time 4.08 seconds
Started May 16 03:13:26 PM PDT 24
Finished May 16 03:13:36 PM PDT 24
Peak memory 214328 kb
Host smart-3b01ab48-2d3a-4994-80f8-1cb21fa55704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046860225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3046860225
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.331240285
Short name T212
Test name
Test status
Simulation time 10592570787 ps
CPU time 219.65 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 222564 kb
Host smart-189f802c-3427-4366-b8b0-189305a0dd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331240285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.331240285
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3025438989
Short name T215
Test name
Test status
Simulation time 3956057699 ps
CPU time 40.36 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 222480 kb
Host smart-101eb6c1-10bc-461d-b215-1cf088d6eb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025438989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3025438989
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3736758655
Short name T217
Test name
Test status
Simulation time 2386814314 ps
CPU time 54.21 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:19:02 PM PDT 24
Peak memory 221548 kb
Host smart-78be40b0-f4d0-4078-b195-b5344e76f543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736758655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3736758655
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1418786652
Short name T156
Test name
Test status
Simulation time 2921710616 ps
CPU time 7.19 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:41:02 PM PDT 24
Peak memory 215568 kb
Host smart-9f8a19fe-bcad-41b5-bb83-9d63f7d782ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418786652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1418786652
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3979836862
Short name T13
Test name
Test status
Simulation time 122480424 ps
CPU time 2.02 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:13:25 PM PDT 24
Peak memory 209888 kb
Host smart-5c95bb90-374a-4695-9126-46622927b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979836862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3979836862
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2595137028
Short name T33
Test name
Test status
Simulation time 174729207 ps
CPU time 8.21 seconds
Started May 16 03:13:21 PM PDT 24
Finished May 16 03:13:34 PM PDT 24
Peak memory 214732 kb
Host smart-e3b210f0-eeb8-42a9-ab32-47110f08bf5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595137028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2595137028
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.143221037
Short name T145
Test name
Test status
Simulation time 83074265 ps
CPU time 3.81 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:51 PM PDT 24
Peak memory 217820 kb
Host smart-260546e8-1152-44ac-a7bb-54148c8f58eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143221037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.143221037
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.121601986
Short name T214
Test name
Test status
Simulation time 1195411199 ps
CPU time 41.86 seconds
Started May 16 03:16:46 PM PDT 24
Finished May 16 03:17:30 PM PDT 24
Peak memory 220796 kb
Host smart-ff7d3c71-9ef7-4092-9f28-f3823d89840c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121601986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.121601986
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.860575678
Short name T50
Test name
Test status
Simulation time 136642505 ps
CPU time 6.19 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:18 PM PDT 24
Peak memory 214328 kb
Host smart-544b2f2c-b9f4-4fdf-b303-51fe1305d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860575678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.860575678
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3527824012
Short name T258
Test name
Test status
Simulation time 878289972 ps
CPU time 11.63 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:18:06 PM PDT 24
Peak memory 214616 kb
Host smart-672a3879-3387-4b8c-8b1e-f5d312e91fe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527824012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3527824012
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4256476984
Short name T293
Test name
Test status
Simulation time 135061952 ps
CPU time 4.45 seconds
Started May 16 03:14:31 PM PDT 24
Finished May 16 03:14:38 PM PDT 24
Peak memory 222528 kb
Host smart-f9123506-147a-4c1a-9ce3-4ed07d2b17e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256476984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4256476984
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4148334785
Short name T161
Test name
Test status
Simulation time 729803131 ps
CPU time 5.34 seconds
Started May 16 02:40:40 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 213960 kb
Host smart-9e811d53-650f-43bc-9942-693794f7766e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148334785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4148334785
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4005404466
Short name T146
Test name
Test status
Simulation time 167676122 ps
CPU time 4.27 seconds
Started May 16 03:16:12 PM PDT 24
Finished May 16 03:16:23 PM PDT 24
Peak memory 218284 kb
Host smart-715b41b0-49e2-473e-a9e9-e9eaed96696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005404466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4005404466
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2818463341
Short name T54
Test name
Test status
Simulation time 35679133 ps
CPU time 1.88 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:48 PM PDT 24
Peak memory 215328 kb
Host smart-43aad363-c0a5-4d2b-b39d-302d8a87ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818463341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2818463341
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3903405349
Short name T148
Test name
Test status
Simulation time 512424661 ps
CPU time 4.36 seconds
Started May 16 03:15:42 PM PDT 24
Finished May 16 03:15:52 PM PDT 24
Peak memory 218636 kb
Host smart-aa97d0fd-90b5-4a9a-9351-c4c01ffd4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903405349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3903405349
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1657514318
Short name T367
Test name
Test status
Simulation time 344892236 ps
CPU time 3.09 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 214292 kb
Host smart-f3da8908-8196-4357-aa8b-f68e38be1396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657514318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1657514318
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.362215161
Short name T238
Test name
Test status
Simulation time 38559409 ps
CPU time 2.68 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:42 PM PDT 24
Peak memory 209024 kb
Host smart-33b5845b-dfbd-47e5-b12b-e19f9a7e23d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362215161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.362215161
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.138036175
Short name T21
Test name
Test status
Simulation time 292796776 ps
CPU time 7.3 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:19 PM PDT 24
Peak memory 214372 kb
Host smart-ac5d8dd5-2a98-4c18-91dc-5855bb54b453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138036175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.138036175
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.530970267
Short name T392
Test name
Test status
Simulation time 409547611 ps
CPU time 3.46 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 222472 kb
Host smart-7ce800a8-1c95-4742-8a4e-4f9c61f1f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530970267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.530970267
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4202107087
Short name T34
Test name
Test status
Simulation time 2165489992 ps
CPU time 17.04 seconds
Started May 16 03:13:22 PM PDT 24
Finished May 16 03:13:44 PM PDT 24
Peak memory 231220 kb
Host smart-cc912a31-6145-4d02-960e-eeafc3fc8e47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202107087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4202107087
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2042257264
Short name T158
Test name
Test status
Simulation time 680503281 ps
CPU time 4.2 seconds
Started May 16 02:41:18 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 213968 kb
Host smart-e06e5f44-a2e4-4e5d-a8d2-8122446b4183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042257264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2042257264
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.232701429
Short name T395
Test name
Test status
Simulation time 287688541 ps
CPU time 15.66 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 215676 kb
Host smart-3bcc23a8-afd5-4aa0-918f-8649b8a3b3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232701429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.232701429
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3694987635
Short name T389
Test name
Test status
Simulation time 291534009 ps
CPU time 8.2 seconds
Started May 16 03:15:13 PM PDT 24
Finished May 16 03:15:25 PM PDT 24
Peak memory 214384 kb
Host smart-fdb1d514-52dc-4636-a9bf-328d1d764e19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694987635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3694987635
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.144392626
Short name T846
Test name
Test status
Simulation time 315639804 ps
CPU time 5.61 seconds
Started May 16 03:15:26 PM PDT 24
Finished May 16 03:15:38 PM PDT 24
Peak memory 214296 kb
Host smart-38053097-d7e4-4828-9fb9-092063f358de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144392626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.144392626
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3627050272
Short name T90
Test name
Test status
Simulation time 338662329 ps
CPU time 3.8 seconds
Started May 16 03:15:40 PM PDT 24
Finished May 16 03:15:50 PM PDT 24
Peak memory 221404 kb
Host smart-0adfc20c-3bfd-4e9d-86c1-d86d1654cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627050272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3627050272
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.277255076
Short name T276
Test name
Test status
Simulation time 1152220387 ps
CPU time 30.64 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:38 PM PDT 24
Peak memory 222616 kb
Host smart-872c9e2b-4388-4b7c-9a98-fd0fc727c1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277255076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.277255076
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1850735437
Short name T175
Test name
Test status
Simulation time 1167170590 ps
CPU time 8.94 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:14 PM PDT 24
Peak memory 213968 kb
Host smart-19387d14-0f3b-46c8-81e5-6f0affa060b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850735437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1850735437
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4250184364
Short name T93
Test name
Test status
Simulation time 192995226 ps
CPU time 5 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:51 PM PDT 24
Peak memory 219168 kb
Host smart-0725a612-045e-47c7-b972-55834d031365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250184364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4250184364
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1248312688
Short name T170
Test name
Test status
Simulation time 92739674 ps
CPU time 2.35 seconds
Started May 16 03:17:34 PM PDT 24
Finished May 16 03:17:48 PM PDT 24
Peak memory 210456 kb
Host smart-2876545f-985c-469e-9ab3-58f093da48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248312688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1248312688
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.836441935
Short name T69
Test name
Test status
Simulation time 51858222 ps
CPU time 2.74 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:04 PM PDT 24
Peak memory 222640 kb
Host smart-6d506718-3f7c-4bed-a09a-106712448502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836441935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.836441935
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3044653295
Short name T143
Test name
Test status
Simulation time 422917199 ps
CPU time 4.04 seconds
Started May 16 03:14:36 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 218184 kb
Host smart-73b4066e-26ff-4590-8a8d-226f0635e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044653295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3044653295
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1114039146
Short name T147
Test name
Test status
Simulation time 133170063 ps
CPU time 3.13 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 218372 kb
Host smart-d0e90eed-2161-44a0-98e6-16c46b0a6b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114039146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1114039146
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4174441001
Short name T88
Test name
Test status
Simulation time 99938464 ps
CPU time 3.37 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:01 PM PDT 24
Peak memory 221384 kb
Host smart-e0ce8842-dff1-44c4-a8a5-1da29f4b0a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174441001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4174441001
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.953816047
Short name T253
Test name
Test status
Simulation time 203808059 ps
CPU time 6.77 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:42 PM PDT 24
Peak memory 208920 kb
Host smart-6173eddd-7689-4205-93e6-be945a354486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953816047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.953816047
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1633422953
Short name T574
Test name
Test status
Simulation time 849179870 ps
CPU time 9.41 seconds
Started May 16 03:15:42 PM PDT 24
Finished May 16 03:15:57 PM PDT 24
Peak memory 208304 kb
Host smart-06a3487f-9e27-45c0-a145-60e4e45afe9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633422953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1633422953
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1728636913
Short name T249
Test name
Test status
Simulation time 57941089698 ps
CPU time 374.73 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:22:41 PM PDT 24
Peak memory 222548 kb
Host smart-ec7694aa-f8df-4259-bf3e-5fdca107ce3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728636913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1728636913
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.303520383
Short name T85
Test name
Test status
Simulation time 1247856817 ps
CPU time 5.32 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:44 PM PDT 24
Peak memory 215108 kb
Host smart-d023effb-6ed1-49d0-8ddb-f7db59e8fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303520383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.303520383
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3913640574
Short name T533
Test name
Test status
Simulation time 117035309 ps
CPU time 3.23 seconds
Started May 16 03:16:42 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 206832 kb
Host smart-0f724424-5624-4bb8-801e-b17009e45d0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913640574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3913640574
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1860798611
Short name T373
Test name
Test status
Simulation time 53392601 ps
CPU time 3.36 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 215544 kb
Host smart-dfbc3ae9-a3b5-4a42-b188-da04916f2199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860798611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1860798611
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3145592201
Short name T404
Test name
Test status
Simulation time 904771809 ps
CPU time 25.97 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 215036 kb
Host smart-e402bc29-1383-4275-8618-eecd720ad913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145592201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3145592201
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1120890661
Short name T244
Test name
Test status
Simulation time 323484081 ps
CPU time 21.25 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:56 PM PDT 24
Peak memory 222756 kb
Host smart-a3f216d5-4ca3-4935-ad1a-35bda82c358f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120890661 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1120890661
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2797103728
Short name T111
Test name
Test status
Simulation time 318224254 ps
CPU time 12.31 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:18:08 PM PDT 24
Peak memory 222560 kb
Host smart-8c3baddf-bb85-4d86-8b2d-fe3abc9dc47d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797103728 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2797103728
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.903641977
Short name T364
Test name
Test status
Simulation time 350003770 ps
CPU time 4.44 seconds
Started May 16 03:18:31 PM PDT 24
Finished May 16 03:18:40 PM PDT 24
Peak memory 222452 kb
Host smart-201a22c5-e18b-40c5-8fdb-f505fb5ecf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903641977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.903641977
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1938526997
Short name T168
Test name
Test status
Simulation time 632325553 ps
CPU time 7.48 seconds
Started May 16 02:41:13 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 213936 kb
Host smart-b0cad0aa-c84d-4fcd-9474-b9e66a6f80d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938526997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1938526997
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1050886817
Short name T178
Test name
Test status
Simulation time 632900238 ps
CPU time 3.87 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:19 PM PDT 24
Peak memory 214020 kb
Host smart-1df5fec8-b49f-43ce-9e3a-4d437c77b3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050886817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1050886817
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3990854457
Short name T174
Test name
Test status
Simulation time 256146721 ps
CPU time 2.65 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 213936 kb
Host smart-1f02de0f-2fd8-4ca5-af14-9479f21363ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990854457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3990854457
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1380585429
Short name T166
Test name
Test status
Simulation time 290064365 ps
CPU time 3.62 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:30 PM PDT 24
Peak memory 213896 kb
Host smart-bc9f1cac-6d45-4b4d-895c-b96589f3165f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380585429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1380585429
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2755899843
Short name T167
Test name
Test status
Simulation time 100340172 ps
CPU time 4.86 seconds
Started May 16 02:40:44 PM PDT 24
Finished May 16 02:40:52 PM PDT 24
Peak memory 213944 kb
Host smart-574aa5be-08ec-439b-861e-d3c815903b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755899843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2755899843
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1304335111
Short name T30
Test name
Test status
Simulation time 365347422 ps
CPU time 4.24 seconds
Started May 16 03:12:46 PM PDT 24
Finished May 16 03:12:52 PM PDT 24
Peak memory 222928 kb
Host smart-396a9289-a163-4066-90a1-2c1feb072112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304335111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1304335111
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3061680486
Short name T150
Test name
Test status
Simulation time 123968807 ps
CPU time 2.42 seconds
Started May 16 03:18:40 PM PDT 24
Finished May 16 03:18:47 PM PDT 24
Peak memory 218028 kb
Host smart-c8c9ad3f-014f-496a-8faf-82a9ade76749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061680486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3061680486
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3169294730
Short name T149
Test name
Test status
Simulation time 262526487 ps
CPU time 3.55 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:40 PM PDT 24
Peak memory 218508 kb
Host smart-8fb07687-301c-4c17-ba8e-e3372506cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169294730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3169294730
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2636581550
Short name T339
Test name
Test status
Simulation time 110553701 ps
CPU time 2.74 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:00 PM PDT 24
Peak memory 208892 kb
Host smart-fc33fdb5-c0eb-4208-b68a-f99ee32d18fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636581550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2636581550
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.4160348620
Short name T318
Test name
Test status
Simulation time 882188980 ps
CPU time 15.24 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:56 PM PDT 24
Peak memory 220976 kb
Host smart-9042c543-d266-4e4e-83f7-9dffa0a87bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160348620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4160348620
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1984915392
Short name T123
Test name
Test status
Simulation time 183284114 ps
CPU time 6.45 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:47 PM PDT 24
Peak memory 222684 kb
Host smart-34e1af11-818f-42de-814c-56f483eb10ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984915392 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1984915392
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3725903331
Short name T380
Test name
Test status
Simulation time 65352516 ps
CPU time 2.72 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:20 PM PDT 24
Peak memory 214400 kb
Host smart-13015768-207d-4aef-9098-5034e0e8d1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725903331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3725903331
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1724400323
Short name T634
Test name
Test status
Simulation time 48705909 ps
CPU time 2.4 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 209616 kb
Host smart-1599c063-6c44-40fe-9360-d4f281d60b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724400323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1724400323
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2615377738
Short name T250
Test name
Test status
Simulation time 661761802 ps
CPU time 3.98 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:15:49 PM PDT 24
Peak memory 210460 kb
Host smart-c40c404a-dadf-43f3-ba63-952308c5845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615377738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2615377738
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.420288825
Short name T345
Test name
Test status
Simulation time 324524360 ps
CPU time 9.66 seconds
Started May 16 03:15:51 PM PDT 24
Finished May 16 03:16:06 PM PDT 24
Peak memory 215484 kb
Host smart-53123037-20a4-4aaa-be66-fd126f9a206a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420288825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.420288825
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1459065337
Short name T398
Test name
Test status
Simulation time 167858346 ps
CPU time 2.87 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:22 PM PDT 24
Peak memory 215808 kb
Host smart-be32a7dc-1ec6-4955-8d95-8f4417114597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459065337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1459065337
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2984942053
Short name T544
Test name
Test status
Simulation time 485623557 ps
CPU time 3.93 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:16:58 PM PDT 24
Peak memory 207096 kb
Host smart-2338fc2e-93ea-480a-a5aa-1780adf22cf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984942053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2984942053
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4128481055
Short name T324
Test name
Test status
Simulation time 481881404 ps
CPU time 7.61 seconds
Started May 16 03:17:17 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 222356 kb
Host smart-d53153bf-bb20-446c-b8f8-632f9f58b6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128481055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4128481055
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3078514637
Short name T205
Test name
Test status
Simulation time 317169085 ps
CPU time 3.53 seconds
Started May 16 03:18:10 PM PDT 24
Finished May 16 03:18:16 PM PDT 24
Peak memory 208668 kb
Host smart-8250cc9b-1534-4342-bd63-6da7eb695cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078514637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3078514637
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3472925595
Short name T356
Test name
Test status
Simulation time 246216250 ps
CPU time 4.71 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 214696 kb
Host smart-ab508476-f114-4516-a038-f28226b238e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472925595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3472925595
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4135437394
Short name T64
Test name
Test status
Simulation time 889840820 ps
CPU time 11.56 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:38 PM PDT 24
Peak memory 215948 kb
Host smart-c7b84013-502d-4d09-8746-de5314c7f87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135437394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4135437394
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1622389651
Short name T151
Test name
Test status
Simulation time 222461599 ps
CPU time 4.98 seconds
Started May 16 03:16:24 PM PDT 24
Finished May 16 03:16:33 PM PDT 24
Peak memory 222624 kb
Host smart-ebd0132e-6f78-4ea7-b703-aab1f5b4cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622389651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1622389651
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3506372780
Short name T1059
Test name
Test status
Simulation time 469880528 ps
CPU time 9.98 seconds
Started May 16 02:40:45 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205732 kb
Host smart-0a921501-10cf-46f5-a12f-37389bc1ac32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506372780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
506372780
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1020707867
Short name T193
Test name
Test status
Simulation time 1842241757 ps
CPU time 16.78 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:41:03 PM PDT 24
Peak memory 205712 kb
Host smart-16449253-301e-47f7-a787-1396604541d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020707867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
020707867
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1073089801
Short name T926
Test name
Test status
Simulation time 178165926 ps
CPU time 1.11 seconds
Started May 16 02:40:44 PM PDT 24
Finished May 16 02:40:48 PM PDT 24
Peak memory 205652 kb
Host smart-543edba6-64c4-4e91-84df-97c207205a49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073089801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
073089801
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2068790568
Short name T182
Test name
Test status
Simulation time 51089086 ps
CPU time 1.64 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 213948 kb
Host smart-79b5092f-2366-47e2-a314-1f6b9f577314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068790568 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2068790568
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.905534226
Short name T944
Test name
Test status
Simulation time 33164292 ps
CPU time 0.96 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 205660 kb
Host smart-a6f78909-c62e-42fe-a890-f8e07e383ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905534226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.905534226
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.67381329
Short name T961
Test name
Test status
Simulation time 18102532 ps
CPU time 0.81 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 205528 kb
Host smart-deb39ed1-1ce9-4ba8-bb1f-3bd952726c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67381329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.67381329
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4143666652
Short name T940
Test name
Test status
Simulation time 21153913 ps
CPU time 1.38 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:48 PM PDT 24
Peak memory 205752 kb
Host smart-f5e5ee83-8203-464b-a21d-051618fb3943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143666652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4143666652
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3711596879
Short name T983
Test name
Test status
Simulation time 449663552 ps
CPU time 10.56 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 214392 kb
Host smart-bd7a7e39-e0c1-4c91-b543-09cc6bcc6783
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711596879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3711596879
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1590242590
Short name T1049
Test name
Test status
Simulation time 94432967 ps
CPU time 1.69 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 215948 kb
Host smart-0c73bebb-0fc6-4a4a-a5e6-a6f527d05da7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590242590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1590242590
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.369612948
Short name T1005
Test name
Test status
Simulation time 241954122 ps
CPU time 4.99 seconds
Started May 16 02:40:45 PM PDT 24
Finished May 16 02:40:52 PM PDT 24
Peak memory 205652 kb
Host smart-c329f1f6-a212-44af-a68c-50e3f45819a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369612948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.369612948
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2665120539
Short name T943
Test name
Test status
Simulation time 1783942033 ps
CPU time 15.64 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:41:01 PM PDT 24
Peak memory 205844 kb
Host smart-191c6aa4-83f0-4175-a691-3f51564aa82f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665120539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
665120539
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1730514084
Short name T1009
Test name
Test status
Simulation time 93888862 ps
CPU time 0.93 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:46 PM PDT 24
Peak memory 205576 kb
Host smart-b3300b00-21e5-4af2-bbb2-2ac49db9e82d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730514084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
730514084
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2572845345
Short name T1040
Test name
Test status
Simulation time 49310277 ps
CPU time 2.33 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 218040 kb
Host smart-de452268-9e67-48ab-91b2-dab627a8ad05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572845345 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2572845345
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.853017541
Short name T138
Test name
Test status
Simulation time 27197240 ps
CPU time 1.24 seconds
Started May 16 02:40:41 PM PDT 24
Finished May 16 02:40:46 PM PDT 24
Peak memory 205768 kb
Host smart-45ea7945-9327-467c-ac4a-eae001031964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853017541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.853017541
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1532435276
Short name T973
Test name
Test status
Simulation time 38166519 ps
CPU time 0.7 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:46 PM PDT 24
Peak memory 205520 kb
Host smart-220d5474-5119-46bf-93df-4366e72db215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532435276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1532435276
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1822601192
Short name T1004
Test name
Test status
Simulation time 182204838 ps
CPU time 2.56 seconds
Started May 16 02:40:45 PM PDT 24
Finished May 16 02:40:50 PM PDT 24
Peak memory 205668 kb
Host smart-da2ac450-9050-4d3f-90f0-dc6d9b0ef2f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822601192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1822601192
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.115406624
Short name T1018
Test name
Test status
Simulation time 226641231 ps
CPU time 2.37 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 214416 kb
Host smart-ed98325b-7fdb-4039-a637-52949cbe2cea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115406624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.115406624
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4252214512
Short name T988
Test name
Test status
Simulation time 288693005 ps
CPU time 3.78 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:50 PM PDT 24
Peak memory 214428 kb
Host smart-a5680ad0-df94-4017-b406-a4c34a018c8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252214512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4252214512
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4058407414
Short name T1074
Test name
Test status
Simulation time 156956445 ps
CPU time 3.29 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 214072 kb
Host smart-a8b826c7-69d1-4689-9cf4-813429162e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058407414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4058407414
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.621066568
Short name T172
Test name
Test status
Simulation time 199518381 ps
CPU time 3.56 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 213976 kb
Host smart-be8a7277-4178-40b0-bbe7-c21e5e36e6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621066568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
621066568
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1706031456
Short name T946
Test name
Test status
Simulation time 69209973 ps
CPU time 2.15 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:16 PM PDT 24
Peak memory 214036 kb
Host smart-e2a8b423-afbb-47dc-b594-5be1f371ac5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706031456 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1706031456
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.547487443
Short name T136
Test name
Test status
Simulation time 155397158 ps
CPU time 0.87 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:16 PM PDT 24
Peak memory 205596 kb
Host smart-f764be09-4576-4754-b004-53db4a716621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547487443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.547487443
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2871675867
Short name T1070
Test name
Test status
Simulation time 13723371 ps
CPU time 0.75 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:17 PM PDT 24
Peak memory 205536 kb
Host smart-d8aac473-f34f-4cdc-8558-eaeb84577b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871675867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2871675867
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3294765616
Short name T135
Test name
Test status
Simulation time 185648471 ps
CPU time 2.37 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:19 PM PDT 24
Peak memory 205800 kb
Host smart-665fc6fb-d303-41ce-86b8-c00daba7e0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294765616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3294765616
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.664447184
Short name T980
Test name
Test status
Simulation time 256219612 ps
CPU time 2.82 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:15 PM PDT 24
Peak memory 214388 kb
Host smart-f3d0fdec-44ec-4683-8418-be441e92c99c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664447184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.664447184
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.4007600234
Short name T1041
Test name
Test status
Simulation time 1442636485 ps
CPU time 8.85 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:21 PM PDT 24
Peak memory 221072 kb
Host smart-185a6f0f-e2d3-4735-9da8-40321f3c0d61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007600234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.4007600234
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3821579495
Short name T1042
Test name
Test status
Simulation time 69152305 ps
CPU time 2 seconds
Started May 16 02:41:09 PM PDT 24
Finished May 16 02:41:13 PM PDT 24
Peak memory 214012 kb
Host smart-b0908160-6e15-4661-b31d-497207fb6553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821579495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3821579495
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2929722538
Short name T1047
Test name
Test status
Simulation time 235520290 ps
CPU time 3.25 seconds
Started May 16 02:41:13 PM PDT 24
Finished May 16 02:41:20 PM PDT 24
Peak memory 213980 kb
Host smart-1e7ddea4-923c-40b9-ab26-dd218c274435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929722538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2929722538
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2233913562
Short name T153
Test name
Test status
Simulation time 90347664 ps
CPU time 1.1 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:17 PM PDT 24
Peak memory 205652 kb
Host smart-26cc15b8-9b2f-40f8-aed7-f4ae8da8146c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233913562 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2233913562
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2834877034
Short name T1010
Test name
Test status
Simulation time 47418745 ps
CPU time 0.94 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:16 PM PDT 24
Peak memory 205676 kb
Host smart-c50ae392-2553-46cc-bae7-d4e36689bdcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834877034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2834877034
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3289392750
Short name T972
Test name
Test status
Simulation time 43196247 ps
CPU time 0.78 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:16 PM PDT 24
Peak memory 205464 kb
Host smart-be508b9f-c421-4fe0-8770-f0ccdec95568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289392750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3289392750
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.74595578
Short name T1057
Test name
Test status
Simulation time 85379067 ps
CPU time 3.15 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:15 PM PDT 24
Peak memory 205776 kb
Host smart-22b79fae-db7e-441d-95bb-1bec2f77158a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74595578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sam
e_csr_outstanding.74595578
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.796361823
Short name T118
Test name
Test status
Simulation time 69535999 ps
CPU time 2.48 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:15 PM PDT 24
Peak memory 214340 kb
Host smart-18bef6bb-2956-4681-8512-6c384ef551b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796361823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.796361823
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1094363663
Short name T1035
Test name
Test status
Simulation time 142599819 ps
CPU time 6.08 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:21 PM PDT 24
Peak memory 220236 kb
Host smart-aac07648-713e-4764-979c-ee8f1fda0a78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094363663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1094363663
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1613991480
Short name T1003
Test name
Test status
Simulation time 371694121 ps
CPU time 4.15 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:20 PM PDT 24
Peak memory 216068 kb
Host smart-d12a6113-eeb3-4b9a-864e-a4f54ba0935d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613991480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1613991480
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1583794210
Short name T1076
Test name
Test status
Simulation time 72542010 ps
CPU time 1.46 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:23 PM PDT 24
Peak memory 214056 kb
Host smart-9ff046d7-708b-42ae-8473-078b654fd892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583794210 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1583794210
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.286128735
Short name T981
Test name
Test status
Simulation time 21958719 ps
CPU time 1.07 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:17 PM PDT 24
Peak memory 205760 kb
Host smart-807f7797-d379-4419-a300-ce8b9b649c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286128735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.286128735
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1531843866
Short name T1015
Test name
Test status
Simulation time 21971491 ps
CPU time 0.73 seconds
Started May 16 02:41:09 PM PDT 24
Finished May 16 02:41:12 PM PDT 24
Peak memory 205380 kb
Host smart-b6a5efee-c50a-457b-81f8-71c8018a8bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531843866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1531843866
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3190727085
Short name T1014
Test name
Test status
Simulation time 423061350 ps
CPU time 3.8 seconds
Started May 16 02:41:24 PM PDT 24
Finished May 16 02:41:32 PM PDT 24
Peak memory 205780 kb
Host smart-0d285669-5161-49b6-ae02-022e0a75f052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190727085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3190727085
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2290699438
Short name T975
Test name
Test status
Simulation time 126470385 ps
CPU time 2.18 seconds
Started May 16 02:41:13 PM PDT 24
Finished May 16 02:41:19 PM PDT 24
Peak memory 214224 kb
Host smart-14e8dee6-4ff8-40a2-8a20-e0c4e8b198e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290699438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2290699438
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1722378268
Short name T122
Test name
Test status
Simulation time 256482384 ps
CPU time 9.04 seconds
Started May 16 02:41:12 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 214256 kb
Host smart-854ad217-27f2-4300-b1b2-2d56214adbb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722378268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1722378268
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.413176314
Short name T1088
Test name
Test status
Simulation time 93417384 ps
CPU time 3.24 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:18 PM PDT 24
Peak memory 214040 kb
Host smart-42f4c17f-d1ce-4dc6-a55d-312bc2212a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413176314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.413176314
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1726549991
Short name T183
Test name
Test status
Simulation time 78256825 ps
CPU time 1.37 seconds
Started May 16 02:41:23 PM PDT 24
Finished May 16 02:41:29 PM PDT 24
Peak memory 214000 kb
Host smart-607665a1-7ac5-4ed1-80d5-593e17276389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726549991 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1726549991
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2150200565
Short name T1054
Test name
Test status
Simulation time 11921126 ps
CPU time 1.07 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:26 PM PDT 24
Peak memory 205636 kb
Host smart-1cbe7a0e-82b9-4b27-b969-451fa7f71032
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150200565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2150200565
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2319892771
Short name T1028
Test name
Test status
Simulation time 43288662 ps
CPU time 0.84 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:24 PM PDT 24
Peak memory 205504 kb
Host smart-1fcf70d7-cf04-43a7-9e2f-7eb442b255d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319892771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2319892771
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2483873411
Short name T999
Test name
Test status
Simulation time 65610986 ps
CPU time 1.77 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 205796 kb
Host smart-5cdaf320-dfb6-401c-8cc1-f305ccd5413d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483873411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2483873411
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3632999356
Short name T1019
Test name
Test status
Simulation time 394329631 ps
CPU time 3.16 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 214276 kb
Host smart-d0b5acbc-c15f-4417-a725-c4d95cc6af35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632999356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3632999356
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3501110377
Short name T1027
Test name
Test status
Simulation time 1372115280 ps
CPU time 9.23 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 214380 kb
Host smart-d1d92328-151f-436f-9137-0630fee6ee13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501110377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3501110377
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3256787875
Short name T1033
Test name
Test status
Simulation time 88848385 ps
CPU time 3.44 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:29 PM PDT 24
Peak memory 213996 kb
Host smart-b985db02-c720-47ce-a1a1-c6da02f0b74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256787875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3256787875
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1865798409
Short name T159
Test name
Test status
Simulation time 35696915 ps
CPU time 1.26 seconds
Started May 16 02:41:23 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 214044 kb
Host smart-2a020670-5751-42d3-81f8-de1147a20a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865798409 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1865798409
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.926214546
Short name T1071
Test name
Test status
Simulation time 38629423 ps
CPU time 0.9 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 205560 kb
Host smart-9329cb6e-c9db-4931-849e-8b48ae06703d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926214546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.926214546
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2950108855
Short name T930
Test name
Test status
Simulation time 13826855 ps
CPU time 0.77 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 205516 kb
Host smart-946d559c-2bff-4e96-92b5-cf6b98162102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950108855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2950108855
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.889349170
Short name T978
Test name
Test status
Simulation time 23957933 ps
CPU time 1.67 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 205788 kb
Host smart-cfa8810b-245b-4e8b-b58c-5f269741d7c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889349170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.889349170
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3532047934
Short name T991
Test name
Test status
Simulation time 79538434 ps
CPU time 1.65 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 214252 kb
Host smart-4b4dc72d-8d8e-4ea7-90d7-4144f78bd776
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532047934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3532047934
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3220349678
Short name T113
Test name
Test status
Simulation time 388363161 ps
CPU time 4.48 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:31 PM PDT 24
Peak memory 214332 kb
Host smart-9690ad97-b6a6-48e8-8675-8e1677002b66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220349678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3220349678
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3072964920
Short name T955
Test name
Test status
Simulation time 313379117 ps
CPU time 3.01 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:29 PM PDT 24
Peak memory 213984 kb
Host smart-06b43050-8a66-4684-aac8-c5814b037129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072964920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3072964920
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2591990786
Short name T176
Test name
Test status
Simulation time 105455904 ps
CPU time 2.6 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 214024 kb
Host smart-26c32384-b34e-4265-b894-edbabe92dcc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591990786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2591990786
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.513829535
Short name T996
Test name
Test status
Simulation time 63011215 ps
CPU time 1.43 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 217188 kb
Host smart-9c71ccc0-6729-472e-a76a-6cf03a3ba808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513829535 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.513829535
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.713010795
Short name T977
Test name
Test status
Simulation time 23472310 ps
CPU time 1.12 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 205764 kb
Host smart-f90cdf2d-e561-407f-b50a-6b8692358342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713010795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.713010795
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1324581286
Short name T971
Test name
Test status
Simulation time 66002153 ps
CPU time 0.73 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 205532 kb
Host smart-bbb7c430-34c4-48c0-9541-b82c817a39fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324581286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1324581286
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2444167475
Short name T1056
Test name
Test status
Simulation time 118241397 ps
CPU time 2.06 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:24 PM PDT 24
Peak memory 205748 kb
Host smart-8cd86bfe-fbe9-453c-ae10-0375a651347e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444167475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2444167475
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3728908519
Short name T1025
Test name
Test status
Simulation time 330366884 ps
CPU time 1.93 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 214428 kb
Host smart-ce4b1003-943f-4029-9642-fca3e576c94b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728908519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3728908519
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1210140877
Short name T942
Test name
Test status
Simulation time 303107233 ps
CPU time 3.87 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:31 PM PDT 24
Peak memory 219752 kb
Host smart-526af40c-ee43-41b6-b871-44a3eb5cd01b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210140877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1210140877
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.313668111
Short name T1037
Test name
Test status
Simulation time 136413477 ps
CPU time 2.27 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 217244 kb
Host smart-726b7ae8-4fd4-485c-9008-169b9ca8d25d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313668111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.313668111
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2248545519
Short name T932
Test name
Test status
Simulation time 87843720 ps
CPU time 1.23 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:24 PM PDT 24
Peak memory 205616 kb
Host smart-421ec2b8-58cb-46f0-abf6-9801a10684b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248545519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2248545519
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2985727737
Short name T1085
Test name
Test status
Simulation time 68565221 ps
CPU time 1.06 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 205628 kb
Host smart-698c19a3-5308-41dd-a514-c719e36c5207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985727737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2985727737
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3927302465
Short name T1020
Test name
Test status
Simulation time 44348278 ps
CPU time 0.75 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:26 PM PDT 24
Peak memory 205492 kb
Host smart-7f97611d-ef04-4171-a252-10f7028d1f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927302465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3927302465
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2344979436
Short name T1032
Test name
Test status
Simulation time 121561959 ps
CPU time 1.88 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 205872 kb
Host smart-ffae61c2-fb34-4a69-a551-4fdf0222eb90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344979436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2344979436
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.94781453
Short name T121
Test name
Test status
Simulation time 43289292 ps
CPU time 1.38 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 214356 kb
Host smart-b9afd6b7-cbad-4857-b56a-73313b192ffd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94781453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow
_reg_errors.94781453
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1074732562
Short name T970
Test name
Test status
Simulation time 695360954 ps
CPU time 6.11 seconds
Started May 16 02:41:23 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 219908 kb
Host smart-7c489f66-ea6b-49e0-ab69-1e50253480ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074732562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1074732562
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3193716322
Short name T958
Test name
Test status
Simulation time 187404960 ps
CPU time 3.73 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:30 PM PDT 24
Peak memory 213980 kb
Host smart-abae8ceb-42cf-4fad-b3b1-205bf5335609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193716322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3193716322
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.813845004
Short name T1081
Test name
Test status
Simulation time 49817116 ps
CPU time 1.88 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 213904 kb
Host smart-8f73a996-2b1f-4601-8983-1acbc7d8f4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813845004 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.813845004
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2275628492
Short name T1052
Test name
Test status
Simulation time 52531716 ps
CPU time 1.08 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:22 PM PDT 24
Peak memory 205780 kb
Host smart-60d152dd-720c-4e44-9d34-29b95ce89cd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275628492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2275628492
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1707851908
Short name T1017
Test name
Test status
Simulation time 57682647 ps
CPU time 0.83 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 205508 kb
Host smart-c755138f-5f98-4baf-beb2-e5cf3048ca20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707851908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1707851908
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3061728597
Short name T974
Test name
Test status
Simulation time 32596461 ps
CPU time 2.09 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 205788 kb
Host smart-ae7c3f93-6794-4b85-84a3-7bb4b067685d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061728597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3061728597
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4227936824
Short name T1026
Test name
Test status
Simulation time 574567969 ps
CPU time 3.5 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:24 PM PDT 24
Peak memory 214308 kb
Host smart-f87c30e6-bd03-4102-b010-32c9c4194387
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227936824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4227936824
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2195588084
Short name T1024
Test name
Test status
Simulation time 338930677 ps
CPU time 4.52 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 214404 kb
Host smart-c56a0f9c-121c-4730-87ec-9fd731e4c6ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195588084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2195588084
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3048354379
Short name T986
Test name
Test status
Simulation time 326450466 ps
CPU time 2.32 seconds
Started May 16 02:41:20 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 217056 kb
Host smart-a1833167-e9ab-4295-9ac7-ff232682692a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048354379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3048354379
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2458985682
Short name T154
Test name
Test status
Simulation time 221633630 ps
CPU time 5.87 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:31 PM PDT 24
Peak memory 213948 kb
Host smart-632d4f91-c2b0-46b1-911f-0704cd176595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458985682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2458985682
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.292439193
Short name T160
Test name
Test status
Simulation time 173349299 ps
CPU time 1.43 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:23 PM PDT 24
Peak memory 214004 kb
Host smart-5cdbcca0-b23c-44b7-a48d-196fa05e8e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292439193 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.292439193
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.96755800
Short name T137
Test name
Test status
Simulation time 29183214 ps
CPU time 1.57 seconds
Started May 16 02:41:23 PM PDT 24
Finished May 16 02:41:29 PM PDT 24
Peak memory 205704 kb
Host smart-eac8278d-9e69-499c-8b99-7b1d00c8b130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96755800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.96755800
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.158620192
Short name T939
Test name
Test status
Simulation time 48437763 ps
CPU time 0.84 seconds
Started May 16 02:41:27 PM PDT 24
Finished May 16 02:41:31 PM PDT 24
Peak memory 205512 kb
Host smart-0c22f37e-8ccd-4379-a272-5db5335321a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158620192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.158620192
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2681833648
Short name T139
Test name
Test status
Simulation time 72199289 ps
CPU time 2.36 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:28 PM PDT 24
Peak memory 205736 kb
Host smart-ac01cf78-6c68-4de1-827d-7c4ce14698a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681833648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2681833648
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3348475850
Short name T1064
Test name
Test status
Simulation time 119807670 ps
CPU time 3.77 seconds
Started May 16 02:41:19 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 214284 kb
Host smart-49618621-1a31-4b19-87ce-e798543fa796
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348475850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3348475850
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.345848939
Short name T950
Test name
Test status
Simulation time 1269649820 ps
CPU time 8.86 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 214372 kb
Host smart-9faa3969-192d-4811-b214-b7e068a79939
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345848939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.345848939
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3212435541
Short name T963
Test name
Test status
Simulation time 59077386 ps
CPU time 1.67 seconds
Started May 16 02:41:22 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 213988 kb
Host smart-b6897070-34c2-4be3-a245-8307dddaef80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212435541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3212435541
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2874937546
Short name T935
Test name
Test status
Simulation time 83298210 ps
CPU time 1.45 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:32 PM PDT 24
Peak memory 214056 kb
Host smart-5b011f02-0b0d-401a-b709-26d9684361f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874937546 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2874937546
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1675671195
Short name T1079
Test name
Test status
Simulation time 12558936 ps
CPU time 1.06 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205672 kb
Host smart-47ab1352-f43d-4c42-9998-bab6945bc265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675671195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1675671195
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3882673189
Short name T994
Test name
Test status
Simulation time 52633247 ps
CPU time 0.92 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:26 PM PDT 24
Peak memory 205488 kb
Host smart-dcbbdad3-05a3-44f3-8d09-f044dc291e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882673189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3882673189
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4088600749
Short name T966
Test name
Test status
Simulation time 45307755 ps
CPU time 1.86 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205692 kb
Host smart-9080dc35-eb24-4e68-97e5-ea296341daee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088600749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4088600749
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.360702942
Short name T1039
Test name
Test status
Simulation time 86005854 ps
CPU time 1.87 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:26 PM PDT 24
Peak memory 214356 kb
Host smart-5ee50eb8-cbbb-4863-8eda-36a238ba1de2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360702942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.360702942
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2072173836
Short name T960
Test name
Test status
Simulation time 260353084 ps
CPU time 4.98 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:30 PM PDT 24
Peak memory 214296 kb
Host smart-722851e7-b9fd-4d2d-b0a1-6d403602ab79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072173836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2072173836
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1957369782
Short name T992
Test name
Test status
Simulation time 154183634 ps
CPU time 2.48 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 213940 kb
Host smart-91a148c3-b8b1-41b9-a190-a1b53360f0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957369782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1957369782
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.85885490
Short name T1030
Test name
Test status
Simulation time 78321821 ps
CPU time 2.68 seconds
Started May 16 02:41:21 PM PDT 24
Finished May 16 02:41:27 PM PDT 24
Peak memory 205856 kb
Host smart-e65270fa-9af9-4729-9fc3-ce5847220b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85885490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.85885490
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3345353867
Short name T947
Test name
Test status
Simulation time 373444594 ps
CPU time 7.1 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:41:01 PM PDT 24
Peak memory 205788 kb
Host smart-7215c93e-610a-498f-b9c2-0d11c20cb4ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345353867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
345353867
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.25668987
Short name T968
Test name
Test status
Simulation time 256287815 ps
CPU time 8.33 seconds
Started May 16 02:40:56 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 205828 kb
Host smart-ab4c96b1-1f7e-4033-89b6-e991dbd71201
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.25668987
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2675035357
Short name T982
Test name
Test status
Simulation time 27866760 ps
CPU time 1.12 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 205772 kb
Host smart-b19721df-fb97-4917-b480-d3de31b8e065
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675035357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
675035357
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2596173440
Short name T933
Test name
Test status
Simulation time 156917898 ps
CPU time 1.53 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:56 PM PDT 24
Peak memory 214104 kb
Host smart-bfbc0988-fcf7-4c6e-8cb9-145cf046fdb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596173440 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2596173440
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2297478651
Short name T987
Test name
Test status
Simulation time 33663493 ps
CPU time 1.16 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205684 kb
Host smart-0ac5508e-a6ab-4b34-99c8-7916a69d80d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297478651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2297478651
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.566732101
Short name T964
Test name
Test status
Simulation time 13755796 ps
CPU time 0.75 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205444 kb
Host smart-1fe3658f-3f2f-4edc-ba16-4ff445697610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566732101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.566732101
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1483768246
Short name T1043
Test name
Test status
Simulation time 116097049 ps
CPU time 2.91 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:09 PM PDT 24
Peak memory 205696 kb
Host smart-4c066d93-d132-41ec-be2f-166bcb4abab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483768246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1483768246
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1871859413
Short name T1013
Test name
Test status
Simulation time 683986895 ps
CPU time 2.19 seconds
Started May 16 02:40:42 PM PDT 24
Finished May 16 02:40:47 PM PDT 24
Peak memory 218908 kb
Host smart-86210943-167d-4e49-adc4-64fcd0e28ad7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871859413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1871859413
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4222136180
Short name T948
Test name
Test status
Simulation time 182285134 ps
CPU time 6.91 seconds
Started May 16 02:40:44 PM PDT 24
Finished May 16 02:40:53 PM PDT 24
Peak memory 214276 kb
Host smart-121e1815-d097-4ec2-a9f2-6669aba639c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222136180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4222136180
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.656076920
Short name T1082
Test name
Test status
Simulation time 79719444 ps
CPU time 2.99 seconds
Started May 16 02:40:43 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 213936 kb
Host smart-af696dc2-19e0-4fc5-8c4b-12a89331259b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656076920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.656076920
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2749327228
Short name T993
Test name
Test status
Simulation time 37998176 ps
CPU time 0.82 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:38 PM PDT 24
Peak memory 205452 kb
Host smart-1562ac0c-b118-4ec2-9ce0-0c1e53085b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749327228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2749327228
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2022160712
Short name T937
Test name
Test status
Simulation time 23355239 ps
CPU time 0.79 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205536 kb
Host smart-9638a1c0-ea49-420e-8dc3-b073240d5ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022160712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2022160712
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4134360869
Short name T1044
Test name
Test status
Simulation time 54869736 ps
CPU time 0.9 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:35 PM PDT 24
Peak memory 205524 kb
Host smart-b343db94-b9c5-4f8b-8003-b6a3c727bfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134360869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4134360869
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.436617442
Short name T1084
Test name
Test status
Simulation time 20401854 ps
CPU time 0.75 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205472 kb
Host smart-1d810389-5b09-42ad-9436-b15f74e5bc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436617442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.436617442
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.578197576
Short name T1021
Test name
Test status
Simulation time 14782121 ps
CPU time 0.9 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205672 kb
Host smart-7d48cdc4-5180-46eb-aa0d-81c8bfe9f605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578197576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.578197576
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3086652029
Short name T998
Test name
Test status
Simulation time 27818647 ps
CPU time 0.69 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:35 PM PDT 24
Peak memory 205588 kb
Host smart-ebfaa3da-0816-4b93-a52b-0801dce28fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086652029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3086652029
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2347312782
Short name T1016
Test name
Test status
Simulation time 33358355 ps
CPU time 0.74 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205524 kb
Host smart-59bd7f57-3d15-478a-87b5-6e8458bc245c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347312782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2347312782
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3170561197
Short name T1036
Test name
Test status
Simulation time 29389519 ps
CPU time 0.71 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:38 PM PDT 24
Peak memory 205508 kb
Host smart-ddd737a4-0b39-4dcd-acb9-522d486a672a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170561197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3170561197
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2268018546
Short name T962
Test name
Test status
Simulation time 78173229 ps
CPU time 0.76 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205332 kb
Host smart-57a2d27c-3e83-47a4-a218-62b1534ead74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268018546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2268018546
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2160641341
Short name T1061
Test name
Test status
Simulation time 132875608 ps
CPU time 0.7 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:37 PM PDT 24
Peak memory 205460 kb
Host smart-d08f50d0-9b53-4536-8224-c328f79a252e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160641341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2160641341
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3408477795
Short name T956
Test name
Test status
Simulation time 493019372 ps
CPU time 10.51 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:41:05 PM PDT 24
Peak memory 205828 kb
Host smart-19719988-ee2e-444a-a6a0-08e819dcf9e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408477795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
408477795
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2385682976
Short name T1073
Test name
Test status
Simulation time 5110810822 ps
CPU time 32.66 seconds
Started May 16 02:40:52 PM PDT 24
Finished May 16 02:41:25 PM PDT 24
Peak memory 205852 kb
Host smart-140dee79-adc5-4f99-a7f5-5f66e7c88281
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385682976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
385682976
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.899975577
Short name T995
Test name
Test status
Simulation time 133016199 ps
CPU time 1.16 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205784 kb
Host smart-184fcea5-61e5-41a4-be9a-4373a8cae03c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899975577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.899975577
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2771556120
Short name T951
Test name
Test status
Simulation time 78516878 ps
CPU time 1.75 seconds
Started May 16 02:41:00 PM PDT 24
Finished May 16 02:41:04 PM PDT 24
Peak memory 214024 kb
Host smart-a14189a0-04d8-4f7a-8207-4269ea6918dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771556120 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2771556120
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1460085615
Short name T1007
Test name
Test status
Simulation time 28172514 ps
CPU time 1.57 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:55 PM PDT 24
Peak memory 205764 kb
Host smart-65bdd08f-76a0-4a34-8f02-00c780da4664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460085615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1460085615
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2482633051
Short name T989
Test name
Test status
Simulation time 11172386 ps
CPU time 0.77 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:56 PM PDT 24
Peak memory 205540 kb
Host smart-d06d351f-e6bc-4705-9aac-a9fe779fae0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482633051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2482633051
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3677780721
Short name T1083
Test name
Test status
Simulation time 22531626 ps
CPU time 1.45 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:56 PM PDT 24
Peak memory 205624 kb
Host smart-7d438d3c-0386-4a7f-8926-9159cae70095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677780721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3677780721
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.397814225
Short name T1051
Test name
Test status
Simulation time 409300121 ps
CPU time 1.48 seconds
Started May 16 02:40:55 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 214276 kb
Host smart-bbea73f1-a6ad-41dd-b79d-2e2b9bc4e78f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397814225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.397814225
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1437307801
Short name T1029
Test name
Test status
Simulation time 401030622 ps
CPU time 8.95 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 214276 kb
Host smart-7e22352d-3300-4b3a-9b2c-aeaee21cc34e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437307801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1437307801
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1702051114
Short name T1086
Test name
Test status
Simulation time 345062782 ps
CPU time 5.91 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:41:02 PM PDT 24
Peak memory 216460 kb
Host smart-fdf2604d-0d06-4259-b224-ac873bb50132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702051114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1702051114
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.519755070
Short name T1060
Test name
Test status
Simulation time 9626422 ps
CPU time 0.71 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:37 PM PDT 24
Peak memory 205540 kb
Host smart-009b86a1-80d9-4cca-be1b-93dc048193d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519755070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.519755070
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3392780737
Short name T925
Test name
Test status
Simulation time 44798323 ps
CPU time 0.82 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205492 kb
Host smart-3f5c6cde-deb1-44c8-b509-0078300e859c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392780737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3392780737
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1567410272
Short name T985
Test name
Test status
Simulation time 20703409 ps
CPU time 0.85 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 205516 kb
Host smart-4838c0cc-f5f2-4288-a18e-69250c65623a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567410272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1567410272
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3657470669
Short name T952
Test name
Test status
Simulation time 13277445 ps
CPU time 0.76 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205472 kb
Host smart-939a8636-c2d0-46ed-998b-fcc89cff5e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657470669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3657470669
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1313730747
Short name T945
Test name
Test status
Simulation time 10648501 ps
CPU time 0.72 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205528 kb
Host smart-d162add1-25c2-4b3b-bea5-5b1cc74555bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313730747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1313730747
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4006724190
Short name T927
Test name
Test status
Simulation time 20264896 ps
CPU time 0.87 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:38 PM PDT 24
Peak memory 205532 kb
Host smart-c30b6b88-a854-421a-b3a9-fd94b46873b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006724190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4006724190
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1322501732
Short name T1062
Test name
Test status
Simulation time 18984817 ps
CPU time 0.72 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:37 PM PDT 24
Peak memory 205292 kb
Host smart-4f6d757b-8364-459f-814c-dde0e06188a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322501732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1322501732
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.536579518
Short name T934
Test name
Test status
Simulation time 26557281 ps
CPU time 0.71 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:32 PM PDT 24
Peak memory 205508 kb
Host smart-80968da6-7aaf-4a1e-bcda-b52269f5d20e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536579518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.536579518
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3033609360
Short name T1068
Test name
Test status
Simulation time 12558071 ps
CPU time 0.76 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205532 kb
Host smart-dfc71213-f32b-4442-9c50-a9f4041caca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033609360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3033609360
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1461311167
Short name T1038
Test name
Test status
Simulation time 36835922 ps
CPU time 0.76 seconds
Started May 16 02:41:28 PM PDT 24
Finished May 16 02:41:32 PM PDT 24
Peak memory 205536 kb
Host smart-7ed74fe0-625d-40b5-a359-bb1bd8fabf3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461311167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1461311167
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3372610538
Short name T1066
Test name
Test status
Simulation time 825213615 ps
CPU time 4.06 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:41:00 PM PDT 24
Peak memory 205832 kb
Host smart-53eb350f-8242-4d3c-a37e-1549dc9fc756
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372610538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
372610538
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3010099978
Short name T1077
Test name
Test status
Simulation time 538124887 ps
CPU time 8.27 seconds
Started May 16 02:40:55 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 205688 kb
Host smart-f40e4412-10ae-4ac2-95eb-4f73be5c316d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010099978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
010099978
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2688202603
Short name T1023
Test name
Test status
Simulation time 106270356 ps
CPU time 1.42 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205864 kb
Host smart-d859f13a-1ba4-48ee-a1e5-4cca629c440e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688202603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
688202603
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2075050361
Short name T1053
Test name
Test status
Simulation time 18899529 ps
CPU time 1.12 seconds
Started May 16 02:40:55 PM PDT 24
Finished May 16 02:40:59 PM PDT 24
Peak memory 205788 kb
Host smart-63b44536-cef1-4ab6-a9c1-0c1d5cf4de45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075050361 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2075050361
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.208716855
Short name T1001
Test name
Test status
Simulation time 77128479 ps
CPU time 1.61 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 205780 kb
Host smart-8dd1aed2-deed-4d65-8a9d-6edc27340d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208716855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.208716855
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3592528137
Short name T979
Test name
Test status
Simulation time 120731418 ps
CPU time 0.83 seconds
Started May 16 02:40:49 PM PDT 24
Finished May 16 02:40:51 PM PDT 24
Peak memory 205452 kb
Host smart-cd1f9d69-aa68-42be-b1b0-b120861ebc95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592528137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3592528137
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.286787139
Short name T134
Test name
Test status
Simulation time 813582265 ps
CPU time 2.8 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:59 PM PDT 24
Peak memory 205764 kb
Host smart-5bce2413-27ba-49cb-bb87-591f549698c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286787139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.286787139
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3404264602
Short name T1022
Test name
Test status
Simulation time 160445140 ps
CPU time 3.43 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:40:58 PM PDT 24
Peak memory 214332 kb
Host smart-11914aa2-06e6-4723-a9e3-c9df2eac86f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404264602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3404264602
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2708811941
Short name T928
Test name
Test status
Simulation time 142540783 ps
CPU time 3.01 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 214880 kb
Host smart-62852dd1-de38-4dc7-bbed-dd025407ceb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708811941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2708811941
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1132992043
Short name T157
Test name
Test status
Simulation time 131050117 ps
CPU time 5.18 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:41:01 PM PDT 24
Peak memory 213908 kb
Host smart-3f7a0d98-0a66-443a-977d-56ed2cf0cbc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132992043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1132992043
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3693874355
Short name T957
Test name
Test status
Simulation time 11115989 ps
CPU time 0.76 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:37 PM PDT 24
Peak memory 205548 kb
Host smart-4b0047eb-c017-441f-b79b-72fb575a87de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693874355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3693874355
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2228345336
Short name T931
Test name
Test status
Simulation time 12093519 ps
CPU time 0.91 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205536 kb
Host smart-91360217-0348-44ed-80bf-6f96c55d99f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228345336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2228345336
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2175721806
Short name T1000
Test name
Test status
Simulation time 20633537 ps
CPU time 1.02 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205644 kb
Host smart-23ff0d62-bb5a-4b5b-a9c6-859802015f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175721806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2175721806
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.566914860
Short name T949
Test name
Test status
Simulation time 31216788 ps
CPU time 0.72 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205412 kb
Host smart-cea63d07-eefe-4758-9de1-26003b90380c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566914860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.566914860
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1815338111
Short name T1075
Test name
Test status
Simulation time 29280759 ps
CPU time 0.8 seconds
Started May 16 02:41:30 PM PDT 24
Finished May 16 02:41:34 PM PDT 24
Peak memory 205436 kb
Host smart-2fcd25f6-ff3b-4a8f-a738-fd7ca1a09024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815338111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1815338111
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.999051259
Short name T990
Test name
Test status
Simulation time 40470734 ps
CPU time 0.86 seconds
Started May 16 02:41:33 PM PDT 24
Finished May 16 02:41:38 PM PDT 24
Peak memory 205496 kb
Host smart-cb26e812-a743-4f5f-b61b-164b0f3b1393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999051259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.999051259
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.656760560
Short name T1034
Test name
Test status
Simulation time 11483153 ps
CPU time 0.88 seconds
Started May 16 02:41:29 PM PDT 24
Finished May 16 02:41:33 PM PDT 24
Peak memory 205544 kb
Host smart-3bc20c94-c7fa-42a7-b84d-081aa10499ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656760560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.656760560
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2520411176
Short name T1002
Test name
Test status
Simulation time 40752011 ps
CPU time 0.83 seconds
Started May 16 02:41:32 PM PDT 24
Finished May 16 02:41:38 PM PDT 24
Peak memory 205416 kb
Host smart-92481412-636a-4a97-9834-4d7e9f7c7a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520411176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2520411176
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.691727213
Short name T1055
Test name
Test status
Simulation time 25235509 ps
CPU time 0.74 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205540 kb
Host smart-9fb9a12f-1a9c-4f1e-b632-9d68a7e8c5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691727213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.691727213
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4222228941
Short name T976
Test name
Test status
Simulation time 62891034 ps
CPU time 0.71 seconds
Started May 16 02:41:31 PM PDT 24
Finished May 16 02:41:36 PM PDT 24
Peak memory 205508 kb
Host smart-38235f8d-0fc7-47a7-83d5-9db1800dd663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222228941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4222228941
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.714350196
Short name T1067
Test name
Test status
Simulation time 49671988 ps
CPU time 2.18 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 214040 kb
Host smart-db52e740-9949-4c03-b121-4d547b19ee4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714350196 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.714350196
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2673234001
Short name T954
Test name
Test status
Simulation time 9620961 ps
CPU time 1.08 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 205700 kb
Host smart-6019d5fe-72b5-46f8-9284-2cac7b6d2b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673234001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2673234001
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2381494203
Short name T959
Test name
Test status
Simulation time 12354674 ps
CPU time 0.72 seconds
Started May 16 02:41:04 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 205484 kb
Host smart-d4249580-7b5d-44d6-ac05-b7afde265613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381494203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2381494203
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4046427932
Short name T1048
Test name
Test status
Simulation time 119625819 ps
CPU time 1.68 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:05 PM PDT 24
Peak memory 205876 kb
Host smart-af5c9828-6221-4146-87a9-4428bbf8a01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046427932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4046427932
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1252401027
Short name T119
Test name
Test status
Simulation time 287815333 ps
CPU time 3.03 seconds
Started May 16 02:40:54 PM PDT 24
Finished May 16 02:40:59 PM PDT 24
Peak memory 214312 kb
Host smart-83a16aae-4dd7-4e99-a6f4-78a7c6237e81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252401027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1252401027
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1694312150
Short name T1046
Test name
Test status
Simulation time 1728099166 ps
CPU time 15.37 seconds
Started May 16 02:40:53 PM PDT 24
Finished May 16 02:41:10 PM PDT 24
Peak memory 214324 kb
Host smart-d7bf3adf-00f8-4311-a2e9-6e623fc0f0e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694312150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1694312150
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1218766457
Short name T929
Test name
Test status
Simulation time 95981921 ps
CPU time 2.06 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 213996 kb
Host smart-a36a1a69-1e49-45d5-93e0-cddddd1bc4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218766457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1218766457
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2479574716
Short name T1031
Test name
Test status
Simulation time 96267363 ps
CPU time 2.08 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 214040 kb
Host smart-19351879-82ab-4661-b719-22107f8cd5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479574716 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2479574716
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1107207577
Short name T1078
Test name
Test status
Simulation time 146211477 ps
CPU time 1.15 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:05 PM PDT 24
Peak memory 205696 kb
Host smart-56cb0c05-cd79-4196-8a79-667f7d59134c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107207577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1107207577
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2729713827
Short name T1011
Test name
Test status
Simulation time 15233870 ps
CPU time 0.9 seconds
Started May 16 02:41:04 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 205524 kb
Host smart-59f53871-c8f5-4111-aaee-c52069e22595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729713827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2729713827
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2938630348
Short name T140
Test name
Test status
Simulation time 33028888 ps
CPU time 2.12 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 205808 kb
Host smart-ec670b32-e0c1-4690-8193-b8f55753011b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938630348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2938630348
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2889132832
Short name T1008
Test name
Test status
Simulation time 100604625 ps
CPU time 2.86 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:09 PM PDT 24
Peak memory 214280 kb
Host smart-bc45d190-a901-4257-8e7b-29e34cf8690d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889132832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2889132832
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.81295474
Short name T938
Test name
Test status
Simulation time 846000221 ps
CPU time 6.33 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:12 PM PDT 24
Peak memory 214384 kb
Host smart-36998967-e472-4405-848a-ddd593c14a8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81295474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_shadow_reg_errors_with_csr_rw.81295474
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2590433738
Short name T984
Test name
Test status
Simulation time 296978220 ps
CPU time 3.69 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:09 PM PDT 24
Peak memory 213980 kb
Host smart-2584f0b2-5f7b-40ec-9260-5171288d8f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590433738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2590433738
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3153877455
Short name T173
Test name
Test status
Simulation time 53345220 ps
CPU time 2.91 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 206036 kb
Host smart-1e7e8770-6cd6-4050-b3c3-476046dba008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153877455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3153877455
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3242791246
Short name T1063
Test name
Test status
Simulation time 85517121 ps
CPU time 1.52 seconds
Started May 16 02:41:00 PM PDT 24
Finished May 16 02:41:03 PM PDT 24
Peak memory 213944 kb
Host smart-dd091749-6f0b-4a57-9daa-779a98c841e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242791246 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3242791246
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2456374457
Short name T941
Test name
Test status
Simulation time 44539621 ps
CPU time 1.48 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:04 PM PDT 24
Peak memory 205772 kb
Host smart-cbc9a7bb-f1a3-4c85-a264-66cf3086abbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456374457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2456374457
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2596158347
Short name T1058
Test name
Test status
Simulation time 193792925 ps
CPU time 0.87 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:06 PM PDT 24
Peak memory 205492 kb
Host smart-0544f7b9-5f48-4b44-a986-4b44245b4be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596158347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2596158347
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3137506907
Short name T1012
Test name
Test status
Simulation time 121619317 ps
CPU time 4.56 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:10 PM PDT 24
Peak memory 205700 kb
Host smart-6b2857be-3bf4-4420-b561-fa00ae44fb5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137506907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3137506907
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2156844749
Short name T969
Test name
Test status
Simulation time 573384061 ps
CPU time 6.87 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:09 PM PDT 24
Peak memory 218780 kb
Host smart-867c4067-90f6-48ce-96c9-c1d32e068778
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156844749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2156844749
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3305152131
Short name T120
Test name
Test status
Simulation time 405512976 ps
CPU time 7.51 seconds
Started May 16 02:41:05 PM PDT 24
Finished May 16 02:41:15 PM PDT 24
Peak memory 214320 kb
Host smart-ba40a498-82c5-4c76-8268-10f689d5026d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305152131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3305152131
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3376776680
Short name T1006
Test name
Test status
Simulation time 52261018 ps
CPU time 3.81 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 214036 kb
Host smart-bfa66765-c65b-4684-a522-831a87b2bc55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376776680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3376776680
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1995540239
Short name T177
Test name
Test status
Simulation time 95756491 ps
CPU time 4.33 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:10 PM PDT 24
Peak memory 213900 kb
Host smart-c439fc5b-4c80-4faf-8407-d66d46576462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995540239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1995540239
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2905760611
Short name T1069
Test name
Test status
Simulation time 46040290 ps
CPU time 1.64 seconds
Started May 16 02:41:04 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 214068 kb
Host smart-d4106722-c33f-49b7-9f77-ba234562d0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905760611 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2905760611
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.627444910
Short name T936
Test name
Test status
Simulation time 10746443 ps
CPU time 1.03 seconds
Started May 16 02:41:05 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 205628 kb
Host smart-ad80a799-1dbf-4a9e-b891-200b2e51586a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627444910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.627444910
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1658322417
Short name T965
Test name
Test status
Simulation time 9773419 ps
CPU time 0.74 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:03 PM PDT 24
Peak memory 205396 kb
Host smart-0dc823e7-2bc0-4a62-aeac-22d265671e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658322417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1658322417
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3587120146
Short name T1072
Test name
Test status
Simulation time 345919160 ps
CPU time 2.46 seconds
Started May 16 02:41:00 PM PDT 24
Finished May 16 02:41:04 PM PDT 24
Peak memory 205796 kb
Host smart-0ea0212e-e357-4970-b73e-7c9cec29ed2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587120146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3587120146
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.502532174
Short name T115
Test name
Test status
Simulation time 164753326 ps
CPU time 1.91 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 214280 kb
Host smart-d2cbd82a-9c4b-4eda-b494-157b920bb03a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502532174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.502532174
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.30723401
Short name T1080
Test name
Test status
Simulation time 161777722 ps
CPU time 4.44 seconds
Started May 16 02:41:01 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 214336 kb
Host smart-8262a240-ca23-4bc8-8439-c970316fc5b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.30723401
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4136629006
Short name T1087
Test name
Test status
Simulation time 50322774 ps
CPU time 3.7 seconds
Started May 16 02:41:02 PM PDT 24
Finished May 16 02:41:08 PM PDT 24
Peak memory 213968 kb
Host smart-0a403a65-0da0-4420-bf55-0f941aadcf3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136629006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4136629006
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.954680605
Short name T155
Test name
Test status
Simulation time 447798641 ps
CPU time 5.4 seconds
Started May 16 02:40:59 PM PDT 24
Finished May 16 02:41:05 PM PDT 24
Peak memory 213928 kb
Host smart-4384537e-e47e-405f-a3f5-ab2c6ac05952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954680605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
954680605
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1939628630
Short name T1050
Test name
Test status
Simulation time 93419017 ps
CPU time 1.61 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:13 PM PDT 24
Peak memory 213972 kb
Host smart-efdbd4eb-154c-4495-8c3f-446489a95a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939628630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1939628630
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3205328106
Short name T953
Test name
Test status
Simulation time 15432101 ps
CPU time 1.09 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:15 PM PDT 24
Peak memory 205788 kb
Host smart-5582d3e8-a88c-41f2-a10f-49de1f91cd01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205328106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3205328106
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2919107355
Short name T997
Test name
Test status
Simulation time 34636326 ps
CPU time 0.79 seconds
Started May 16 02:41:10 PM PDT 24
Finished May 16 02:41:13 PM PDT 24
Peak memory 205524 kb
Host smart-a9f0b7ca-76e5-442a-8304-6e41ab02b928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919107355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2919107355
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3755698279
Short name T133
Test name
Test status
Simulation time 21524073 ps
CPU time 1.62 seconds
Started May 16 02:41:09 PM PDT 24
Finished May 16 02:41:13 PM PDT 24
Peak memory 205704 kb
Host smart-ef8292f3-305e-4358-8f3c-5bd7f502babe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755698279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3755698279
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1336515553
Short name T1065
Test name
Test status
Simulation time 165174897 ps
CPU time 1.69 seconds
Started May 16 02:41:03 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 214268 kb
Host smart-5eef8942-dd3c-4607-8980-316777077a36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336515553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1336515553
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1518158112
Short name T967
Test name
Test status
Simulation time 240933143 ps
CPU time 5.52 seconds
Started May 16 02:41:09 PM PDT 24
Finished May 16 02:41:17 PM PDT 24
Peak memory 214332 kb
Host smart-0c1e6bf3-53ae-4ab5-ae7a-893b132558b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518158112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1518158112
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2354455170
Short name T181
Test name
Test status
Simulation time 158489409 ps
CPU time 5.47 seconds
Started May 16 02:41:13 PM PDT 24
Finished May 16 02:41:22 PM PDT 24
Peak memory 213912 kb
Host smart-cd173830-1e63-4b4f-be7a-7d87571d5e29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354455170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2354455170
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3592608176
Short name T1045
Test name
Test status
Simulation time 1400375721 ps
CPU time 4.06 seconds
Started May 16 02:41:11 PM PDT 24
Finished May 16 02:41:19 PM PDT 24
Peak memory 213988 kb
Host smart-f8b2f649-cbfd-4aba-871b-d287e5eb9c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592608176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3592608176
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1482331006
Short name T77
Test name
Test status
Simulation time 14278310 ps
CPU time 0.79 seconds
Started May 16 03:12:46 PM PDT 24
Finished May 16 03:12:49 PM PDT 24
Peak memory 206012 kb
Host smart-e287c12e-cd1f-4c3a-922c-9f153e03a60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482331006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1482331006
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1787680567
Short name T436
Test name
Test status
Simulation time 60036721 ps
CPU time 3.98 seconds
Started May 16 03:12:36 PM PDT 24
Finished May 16 03:12:41 PM PDT 24
Peak memory 215440 kb
Host smart-544b3062-567a-4e69-bbc2-5638a99b67e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787680567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1787680567
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1331079777
Short name T631
Test name
Test status
Simulation time 62066937 ps
CPU time 2.28 seconds
Started May 16 03:12:46 PM PDT 24
Finished May 16 03:12:49 PM PDT 24
Peak memory 207756 kb
Host smart-ad011319-6b4e-4667-b0ab-6d1da8477a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331079777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1331079777
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2869743742
Short name T838
Test name
Test status
Simulation time 72333239 ps
CPU time 2.56 seconds
Started May 16 03:12:48 PM PDT 24
Finished May 16 03:12:52 PM PDT 24
Peak memory 214608 kb
Host smart-b7534990-0e10-4994-868f-505ceeb52ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869743742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2869743742
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3471651741
Short name T760
Test name
Test status
Simulation time 58527144 ps
CPU time 3.22 seconds
Started May 16 03:12:48 PM PDT 24
Finished May 16 03:12:53 PM PDT 24
Peak memory 215600 kb
Host smart-41ed810e-8667-4972-803a-d9de63b0b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471651741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3471651741
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1585148947
Short name T575
Test name
Test status
Simulation time 53347320 ps
CPU time 3.82 seconds
Started May 16 03:12:46 PM PDT 24
Finished May 16 03:12:51 PM PDT 24
Peak memory 214544 kb
Host smart-65048253-a811-4119-a8a0-963a085db14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585148947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1585148947
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1640744327
Short name T548
Test name
Test status
Simulation time 326510756 ps
CPU time 3.98 seconds
Started May 16 03:12:36 PM PDT 24
Finished May 16 03:12:41 PM PDT 24
Peak memory 219212 kb
Host smart-1092e8a3-c9a5-4f2f-96e6-7d7e6797a619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640744327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1640744327
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1820527377
Short name T11
Test name
Test status
Simulation time 437498211 ps
CPU time 14.09 seconds
Started May 16 03:12:47 PM PDT 24
Finished May 16 03:13:02 PM PDT 24
Peak memory 238328 kb
Host smart-762b2d86-b267-44bf-9362-dd9765a0bebe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820527377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1820527377
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3431720388
Short name T775
Test name
Test status
Simulation time 69341650 ps
CPU time 2.53 seconds
Started May 16 03:12:37 PM PDT 24
Finished May 16 03:12:42 PM PDT 24
Peak memory 208524 kb
Host smart-b33d48ee-5e74-4aa3-9206-faa622c6412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431720388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3431720388
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1410311416
Short name T229
Test name
Test status
Simulation time 187427205 ps
CPU time 2.9 seconds
Started May 16 03:12:36 PM PDT 24
Finished May 16 03:12:41 PM PDT 24
Peak memory 207004 kb
Host smart-829976dd-f627-442c-ab33-1a64d3f5e13d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410311416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1410311416
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1886095637
Short name T699
Test name
Test status
Simulation time 284354323 ps
CPU time 3.74 seconds
Started May 16 03:12:38 PM PDT 24
Finished May 16 03:12:44 PM PDT 24
Peak memory 208672 kb
Host smart-ba283552-82f0-445b-b283-ddfbc5aacd5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886095637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1886095637
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4265512137
Short name T523
Test name
Test status
Simulation time 853218904 ps
CPU time 9.77 seconds
Started May 16 03:12:37 PM PDT 24
Finished May 16 03:12:48 PM PDT 24
Peak memory 207112 kb
Host smart-8a11f91f-7841-4819-92bd-179c49df391b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265512137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4265512137
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3650151488
Short name T222
Test name
Test status
Simulation time 1082241024 ps
CPU time 40.35 seconds
Started May 16 03:12:45 PM PDT 24
Finished May 16 03:13:27 PM PDT 24
Peak memory 218624 kb
Host smart-c1c1a89e-e88c-47f6-be04-dc20151d6e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650151488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3650151488
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3497885138
Short name T572
Test name
Test status
Simulation time 164905172 ps
CPU time 3.93 seconds
Started May 16 03:12:37 PM PDT 24
Finished May 16 03:12:43 PM PDT 24
Peak memory 208456 kb
Host smart-6a94aba8-51c0-4715-b3b0-35659e7c3dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497885138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3497885138
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.103774224
Short name T336
Test name
Test status
Simulation time 388925361 ps
CPU time 13.99 seconds
Started May 16 03:12:48 PM PDT 24
Finished May 16 03:13:03 PM PDT 24
Peak memory 219996 kb
Host smart-b033e6fe-08a6-4dc0-833c-0a6c2debe43f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103774224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.103774224
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2742272230
Short name T340
Test name
Test status
Simulation time 1483767913 ps
CPU time 11.52 seconds
Started May 16 03:12:47 PM PDT 24
Finished May 16 03:13:00 PM PDT 24
Peak memory 218348 kb
Host smart-38763841-3bdc-42ec-9df4-07b14ed13a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742272230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2742272230
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.994043705
Short name T37
Test name
Test status
Simulation time 45216736 ps
CPU time 2.42 seconds
Started May 16 03:12:45 PM PDT 24
Finished May 16 03:12:49 PM PDT 24
Peak memory 210152 kb
Host smart-afaf53e5-a0cd-4a86-b69e-cba034f74f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994043705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.994043705
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2302033608
Short name T853
Test name
Test status
Simulation time 10345205 ps
CPU time 0.78 seconds
Started May 16 03:13:12 PM PDT 24
Finished May 16 03:13:15 PM PDT 24
Peak memory 205968 kb
Host smart-677a288b-b3e4-4a4a-9197-30d4d4f47bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302033608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2302033608
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.403021617
Short name T864
Test name
Test status
Simulation time 304847362 ps
CPU time 3.21 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:02 PM PDT 24
Peak memory 218452 kb
Host smart-b803d901-1aea-4869-8237-7e51fa7dbccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403021617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.403021617
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1937628332
Short name T676
Test name
Test status
Simulation time 136488351 ps
CPU time 2.22 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:00 PM PDT 24
Peak memory 214448 kb
Host smart-b343318e-a9b5-4b17-bf9a-7e09abd3f8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937628332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1937628332
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3815141694
Short name T98
Test name
Test status
Simulation time 87200409 ps
CPU time 4.48 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:01 PM PDT 24
Peak memory 209252 kb
Host smart-e46d978e-d4f8-4a28-be6c-106d51401e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815141694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3815141694
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4023552341
Short name T248
Test name
Test status
Simulation time 131691265 ps
CPU time 7.14 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:06 PM PDT 24
Peak memory 210500 kb
Host smart-bdbec5c4-247f-4624-8f04-d1fd28302067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023552341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4023552341
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.436002942
Short name T434
Test name
Test status
Simulation time 678175627 ps
CPU time 10.71 seconds
Started May 16 03:12:57 PM PDT 24
Finished May 16 03:13:10 PM PDT 24
Peak memory 214444 kb
Host smart-bd1578f4-94a7-4303-8168-8e67c5b45a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436002942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.436002942
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3013752638
Short name T280
Test name
Test status
Simulation time 487423093 ps
CPU time 4.32 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:01 PM PDT 24
Peak memory 208580 kb
Host smart-b72af7d6-5ff9-448b-8580-7748d018d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013752638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3013752638
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.886565046
Short name T804
Test name
Test status
Simulation time 76200153 ps
CPU time 3.41 seconds
Started May 16 03:12:54 PM PDT 24
Finished May 16 03:12:59 PM PDT 24
Peak memory 209096 kb
Host smart-404eb702-20b5-4ad8-97cd-86f1b945531c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886565046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.886565046
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3392505072
Short name T396
Test name
Test status
Simulation time 1031918539 ps
CPU time 8.71 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:06 PM PDT 24
Peak memory 207992 kb
Host smart-a0243b8c-6f94-49bb-83e5-913dcad0ccec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392505072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3392505072
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2393314373
Short name T605
Test name
Test status
Simulation time 43965430 ps
CPU time 2.81 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:01 PM PDT 24
Peak memory 209208 kb
Host smart-0110ada7-df37-4140-8921-90a4f3275933
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393314373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2393314373
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3470966482
Short name T692
Test name
Test status
Simulation time 195508314 ps
CPU time 6 seconds
Started May 16 03:12:46 PM PDT 24
Finished May 16 03:12:54 PM PDT 24
Peak memory 208792 kb
Host smart-0651e052-3c1c-4094-b211-c3380ad5ea53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470966482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3470966482
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1720744553
Short name T675
Test name
Test status
Simulation time 9079139582 ps
CPU time 36.39 seconds
Started May 16 03:12:55 PM PDT 24
Finished May 16 03:13:34 PM PDT 24
Peak memory 222588 kb
Host smart-7eda1711-9f41-4bc6-8df0-d4c341773a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720744553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1720744553
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3249289609
Short name T125
Test name
Test status
Simulation time 180380868 ps
CPU time 10.87 seconds
Started May 16 03:13:11 PM PDT 24
Finished May 16 03:13:25 PM PDT 24
Peak memory 222508 kb
Host smart-4b2d69e6-9801-4506-b3bf-756b9ba916f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249289609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3249289609
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.413806400
Short name T798
Test name
Test status
Simulation time 1137450622 ps
CPU time 6.52 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:05 PM PDT 24
Peak memory 218372 kb
Host smart-5538065e-5baa-4212-a792-3839c17d403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413806400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.413806400
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4031917254
Short name T919
Test name
Test status
Simulation time 103430554 ps
CPU time 3.1 seconds
Started May 16 03:12:56 PM PDT 24
Finished May 16 03:13:02 PM PDT 24
Peak memory 210112 kb
Host smart-8ba0b11e-e668-424b-9c00-a30097a58225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031917254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4031917254
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1133785948
Short name T808
Test name
Test status
Simulation time 35779049 ps
CPU time 0.72 seconds
Started May 16 03:14:40 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 205988 kb
Host smart-26a6d9ad-9dc8-4eeb-8e57-17bae7d6033d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133785948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1133785948
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3040493801
Short name T316
Test name
Test status
Simulation time 1057295430 ps
CPU time 17.25 seconds
Started May 16 03:14:39 PM PDT 24
Finished May 16 03:15:00 PM PDT 24
Peak memory 214312 kb
Host smart-6fc2578c-e36d-4c51-a40d-421099e280cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040493801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3040493801
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3940364706
Short name T829
Test name
Test status
Simulation time 15767108 ps
CPU time 1.44 seconds
Started May 16 03:14:36 PM PDT 24
Finished May 16 03:14:41 PM PDT 24
Peak memory 207708 kb
Host smart-bc0e97e1-d53b-44e9-b4af-0ee7e6fc25cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940364706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3940364706
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3397058206
Short name T652
Test name
Test status
Simulation time 100723909 ps
CPU time 4.33 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:46 PM PDT 24
Peak memory 214280 kb
Host smart-dc9ddd80-f20a-4848-884d-15e5a80f9cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397058206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3397058206
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.548647391
Short name T179
Test name
Test status
Simulation time 37436380 ps
CPU time 2.71 seconds
Started May 16 03:14:39 PM PDT 24
Finished May 16 03:14:45 PM PDT 24
Peak memory 209840 kb
Host smart-ac7f681c-959e-453b-b740-e4178ad96edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548647391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.548647391
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.733318975
Short name T287
Test name
Test status
Simulation time 268914835 ps
CPU time 7.39 seconds
Started May 16 03:14:39 PM PDT 24
Finished May 16 03:14:50 PM PDT 24
Peak memory 219736 kb
Host smart-e330afeb-bf1c-4a69-8734-7cd45d4a2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733318975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.733318975
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.132996515
Short name T640
Test name
Test status
Simulation time 325171898 ps
CPU time 6.1 seconds
Started May 16 03:14:32 PM PDT 24
Finished May 16 03:14:41 PM PDT 24
Peak memory 208176 kb
Host smart-1af48b7b-d410-4bf7-81e3-15f25b487eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132996515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.132996515
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3137156979
Short name T794
Test name
Test status
Simulation time 61539037 ps
CPU time 2.46 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 206944 kb
Host smart-b5259339-4156-41e2-b364-7c8631a4885b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137156979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3137156979
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.379286669
Short name T722
Test name
Test status
Simulation time 112415011 ps
CPU time 3.09 seconds
Started May 16 03:14:36 PM PDT 24
Finished May 16 03:14:42 PM PDT 24
Peak memory 207008 kb
Host smart-496f32df-4cce-4c74-b2ce-5121d1ecee5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379286669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.379286669
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3745558117
Short name T917
Test name
Test status
Simulation time 836138358 ps
CPU time 6.34 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:48 PM PDT 24
Peak memory 208804 kb
Host smart-4ade47ed-d05f-48dc-b038-ee3608af7e98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745558117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3745558117
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.873827190
Short name T477
Test name
Test status
Simulation time 161898483 ps
CPU time 2.57 seconds
Started May 16 03:14:39 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 218488 kb
Host smart-45b7e242-9afb-4a33-bbf2-fab581f96dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873827190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.873827190
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.4200317645
Short name T822
Test name
Test status
Simulation time 64216971 ps
CPU time 2.87 seconds
Started May 16 03:14:31 PM PDT 24
Finished May 16 03:14:37 PM PDT 24
Peak memory 208732 kb
Host smart-11c1d426-505a-4049-b9bc-2ef892e6ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200317645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4200317645
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2063160059
Short name T401
Test name
Test status
Simulation time 323731892 ps
CPU time 8.95 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:49 PM PDT 24
Peak memory 208524 kb
Host smart-b4686991-8ab8-49bc-a396-e6beef784f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063160059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2063160059
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1411941639
Short name T226
Test name
Test status
Simulation time 478857578 ps
CPU time 2.33 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 210092 kb
Host smart-1000299b-8229-433d-9d17-cc6e0eb9b0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411941639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1411941639
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.960195423
Short name T510
Test name
Test status
Simulation time 54643435 ps
CPU time 0.9 seconds
Started May 16 03:14:45 PM PDT 24
Finished May 16 03:14:49 PM PDT 24
Peak memory 206132 kb
Host smart-93ee31aa-ab94-4e1f-bdc7-32096189e37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960195423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.960195423
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4292919344
Short name T108
Test name
Test status
Simulation time 599142362 ps
CPU time 3.97 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:45 PM PDT 24
Peak memory 214372 kb
Host smart-4425234e-182a-4cf3-843d-96f2e98a1578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292919344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4292919344
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3687164004
Short name T107
Test name
Test status
Simulation time 441876298 ps
CPU time 4.38 seconds
Started May 16 03:14:39 PM PDT 24
Finished May 16 03:14:46 PM PDT 24
Peak memory 208872 kb
Host smart-c9132576-24b9-4f9a-b4aa-a4a814a9611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687164004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3687164004
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3906193585
Short name T294
Test name
Test status
Simulation time 79360296 ps
CPU time 2.43 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:14:49 PM PDT 24
Peak memory 214444 kb
Host smart-352006d1-aad7-4ca9-9f1a-a6d610c85ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906193585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3906193585
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.550461922
Short name T228
Test name
Test status
Simulation time 242769849 ps
CPU time 3.89 seconds
Started May 16 03:14:47 PM PDT 24
Finished May 16 03:14:53 PM PDT 24
Peak memory 211648 kb
Host smart-8d52d93b-d91b-4002-8f2e-e51d0fa26485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550461922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.550461922
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.348622363
Short name T669
Test name
Test status
Simulation time 40979101 ps
CPU time 2.06 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:42 PM PDT 24
Peak memory 208244 kb
Host smart-08fa488f-f792-49fb-8f6f-a716638d2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348622363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.348622363
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.953529739
Short name T406
Test name
Test status
Simulation time 2685886819 ps
CPU time 23.13 seconds
Started May 16 03:14:40 PM PDT 24
Finished May 16 03:15:07 PM PDT 24
Peak memory 209140 kb
Host smart-c48df6be-6aa9-4deb-a497-c1c258bf19b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953529739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.953529739
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1468081115
Short name T637
Test name
Test status
Simulation time 67656221 ps
CPU time 3.46 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:45 PM PDT 24
Peak memory 208744 kb
Host smart-ae87bb9e-8069-43b7-ae2d-82626a8afe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468081115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1468081115
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1915746068
Short name T454
Test name
Test status
Simulation time 19781420 ps
CPU time 1.83 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 207012 kb
Host smart-4b1476ea-7c55-4d98-8744-dfacc2efa76b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915746068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1915746068
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3556522817
Short name T441
Test name
Test status
Simulation time 668103125 ps
CPU time 5.31 seconds
Started May 16 03:14:36 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 206948 kb
Host smart-9e695d55-cb7c-41bf-b421-8a79130e5612
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556522817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3556522817
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2074479321
Short name T532
Test name
Test status
Simulation time 258156961 ps
CPU time 4.55 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:46 PM PDT 24
Peak memory 208652 kb
Host smart-e9c82a11-0190-417b-9ca6-feb8a804fdde
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074479321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2074479321
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2167478708
Short name T236
Test name
Test status
Simulation time 150261427 ps
CPU time 2.86 seconds
Started May 16 03:14:48 PM PDT 24
Finished May 16 03:14:53 PM PDT 24
Peak memory 218408 kb
Host smart-a57053c1-49b2-497c-9c39-3eb63cc71f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167478708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2167478708
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4005079421
Short name T515
Test name
Test status
Simulation time 106948373 ps
CPU time 2.52 seconds
Started May 16 03:14:37 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 206996 kb
Host smart-35365e95-8faa-4499-aeb5-71bf0de6c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005079421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4005079421
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3780032292
Short name T247
Test name
Test status
Simulation time 1531717001 ps
CPU time 44.14 seconds
Started May 16 03:14:45 PM PDT 24
Finished May 16 03:15:31 PM PDT 24
Peak memory 220436 kb
Host smart-ea95a064-5435-4b7d-908f-a2564ea7f759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780032292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3780032292
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1107872788
Short name T884
Test name
Test status
Simulation time 454957732 ps
CPU time 9.99 seconds
Started May 16 03:14:45 PM PDT 24
Finished May 16 03:14:58 PM PDT 24
Peak memory 222824 kb
Host smart-3ae0a3a5-f312-4fe8-83cf-25dc9491e6dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107872788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1107872788
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.461543489
Short name T904
Test name
Test status
Simulation time 50452143 ps
CPU time 3.34 seconds
Started May 16 03:14:38 PM PDT 24
Finished May 16 03:14:45 PM PDT 24
Peak memory 207236 kb
Host smart-ce8d7f10-a600-4211-baeb-ea19b067c613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461543489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.461543489
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.541085368
Short name T414
Test name
Test status
Simulation time 43157201 ps
CPU time 2.19 seconds
Started May 16 03:14:47 PM PDT 24
Finished May 16 03:14:51 PM PDT 24
Peak memory 210016 kb
Host smart-f431c031-7e6b-4e56-8ddb-bf18fe153035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541085368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.541085368
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.433651763
Short name T483
Test name
Test status
Simulation time 105846847 ps
CPU time 0.94 seconds
Started May 16 03:14:57 PM PDT 24
Finished May 16 03:15:01 PM PDT 24
Peak memory 205992 kb
Host smart-f7db0cd9-8477-4b08-a2e7-c55343b9031c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433651763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.433651763
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2117861117
Short name T274
Test name
Test status
Simulation time 247194058 ps
CPU time 4.82 seconds
Started May 16 03:14:54 PM PDT 24
Finished May 16 03:15:02 PM PDT 24
Peak memory 214712 kb
Host smart-211a3435-39f4-4055-aebd-79b41dddc295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117861117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2117861117
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2730476634
Short name T681
Test name
Test status
Simulation time 127667399 ps
CPU time 3.14 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:14:50 PM PDT 24
Peak memory 218256 kb
Host smart-4ed55928-323f-4168-90cc-451290f38b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730476634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2730476634
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2947647213
Short name T87
Test name
Test status
Simulation time 99680476 ps
CPU time 2.12 seconds
Started May 16 03:14:53 PM PDT 24
Finished May 16 03:14:58 PM PDT 24
Peak memory 214388 kb
Host smart-c4ca791a-bcd5-4732-bfa2-3fe442afb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947647213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2947647213
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2882945353
Short name T807
Test name
Test status
Simulation time 59868171 ps
CPU time 3.2 seconds
Started May 16 03:14:53 PM PDT 24
Finished May 16 03:14:58 PM PDT 24
Peak memory 214320 kb
Host smart-ec3a0b21-cf87-4f18-b79a-fe4500878fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882945353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2882945353
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1867827462
Short name T579
Test name
Test status
Simulation time 51396177 ps
CPU time 2.44 seconds
Started May 16 03:14:53 PM PDT 24
Finished May 16 03:14:57 PM PDT 24
Peak memory 218796 kb
Host smart-28137a36-3907-4d01-b15b-9c3c63a56bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867827462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1867827462
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.227027420
Short name T503
Test name
Test status
Simulation time 592749607 ps
CPU time 5.4 seconds
Started May 16 03:14:48 PM PDT 24
Finished May 16 03:14:56 PM PDT 24
Peak memory 207188 kb
Host smart-ccf2818d-0c13-4504-8d85-2940c7a5843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227027420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.227027420
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.222297181
Short name T709
Test name
Test status
Simulation time 7343640548 ps
CPU time 71.83 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 208636 kb
Host smart-2b11cf61-999b-4b30-8b6b-01f1a1a19422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222297181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.222297181
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1774799462
Short name T208
Test name
Test status
Simulation time 283043206 ps
CPU time 3.6 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:14:51 PM PDT 24
Peak memory 208784 kb
Host smart-6bfcd944-e8e4-411d-af4b-71e7c2b1c7b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774799462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1774799462
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3183458442
Short name T875
Test name
Test status
Simulation time 164940576 ps
CPU time 2.92 seconds
Started May 16 03:14:44 PM PDT 24
Finished May 16 03:14:49 PM PDT 24
Peak memory 206912 kb
Host smart-e38cf29e-2c62-47e4-a121-48d11ba23d7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183458442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3183458442
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1257646351
Short name T397
Test name
Test status
Simulation time 146308445 ps
CPU time 2.65 seconds
Started May 16 03:14:47 PM PDT 24
Finished May 16 03:14:52 PM PDT 24
Peak memory 206928 kb
Host smart-ce5ea676-66b5-477c-814e-35c20a1726ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257646351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1257646351
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2571256658
Short name T832
Test name
Test status
Simulation time 2823016890 ps
CPU time 14.41 seconds
Started May 16 03:14:54 PM PDT 24
Finished May 16 03:15:11 PM PDT 24
Peak memory 209600 kb
Host smart-6a0be2f4-3ef6-4388-b960-1c4bf36a2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571256658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2571256658
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1581150640
Short name T630
Test name
Test status
Simulation time 36210632 ps
CPU time 2.34 seconds
Started May 16 03:14:46 PM PDT 24
Finished May 16 03:14:51 PM PDT 24
Peak memory 208912 kb
Host smart-2bc3bc99-4c28-4599-aead-c108981ac847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581150640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1581150640
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.842469148
Short name T162
Test name
Test status
Simulation time 1430919435 ps
CPU time 17.41 seconds
Started May 16 03:14:54 PM PDT 24
Finished May 16 03:15:14 PM PDT 24
Peak memory 220480 kb
Host smart-9169e8a5-9305-462f-8d13-cd363c4bff72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842469148 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.842469148
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3501986059
Short name T848
Test name
Test status
Simulation time 446346874 ps
CPU time 6.25 seconds
Started May 16 03:14:53 PM PDT 24
Finished May 16 03:15:01 PM PDT 24
Peak memory 210408 kb
Host smart-8af06df6-6534-49eb-8942-5ae67701cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501986059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3501986059
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1907697675
Short name T720
Test name
Test status
Simulation time 1467049502 ps
CPU time 18.65 seconds
Started May 16 03:14:54 PM PDT 24
Finished May 16 03:15:15 PM PDT 24
Peak memory 211252 kb
Host smart-857da59f-79be-4b88-b5a4-f56aec673704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907697675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1907697675
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2034830927
Short name T449
Test name
Test status
Simulation time 48536377 ps
CPU time 0.75 seconds
Started May 16 03:15:01 PM PDT 24
Finished May 16 03:15:05 PM PDT 24
Peak memory 205972 kb
Host smart-04a09076-9119-43ed-af47-ec372e0e255a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034830927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2034830927
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.806246764
Short name T376
Test name
Test status
Simulation time 110812437 ps
CPU time 6.27 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:12 PM PDT 24
Peak memory 215480 kb
Host smart-bdc2ed7b-5a21-49b7-8753-5913bf8773c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806246764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.806246764
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3093040356
Short name T29
Test name
Test status
Simulation time 56641917 ps
CPU time 2.3 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:08 PM PDT 24
Peak memory 208652 kb
Host smart-f88f73d6-7149-4552-9cac-281e0e950e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093040356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3093040356
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1614710121
Short name T735
Test name
Test status
Simulation time 146744437 ps
CPU time 3.2 seconds
Started May 16 03:15:01 PM PDT 24
Finished May 16 03:15:07 PM PDT 24
Peak memory 207224 kb
Host smart-81f17402-f63b-4dfc-9073-9fa89768b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614710121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1614710121
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3867799714
Short name T633
Test name
Test status
Simulation time 121232762 ps
CPU time 2.46 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:08 PM PDT 24
Peak memory 208712 kb
Host smart-a2c06486-3c9b-4bf9-8d24-6909fd9758d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867799714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3867799714
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.790723036
Short name T187
Test name
Test status
Simulation time 132078375 ps
CPU time 3.87 seconds
Started May 16 03:15:03 PM PDT 24
Finished May 16 03:15:10 PM PDT 24
Peak memory 214204 kb
Host smart-7f5d9cad-ab83-4d8c-88cb-d16e63f1a126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790723036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.790723036
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2615015259
Short name T534
Test name
Test status
Simulation time 283816521 ps
CPU time 3.36 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:09 PM PDT 24
Peak memory 207908 kb
Host smart-f4b772e1-ffce-4ff6-8cc5-b2e2ea802786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615015259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2615015259
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4041666543
Short name T734
Test name
Test status
Simulation time 852342056 ps
CPU time 30.71 seconds
Started May 16 03:15:01 PM PDT 24
Finished May 16 03:15:35 PM PDT 24
Peak memory 218232 kb
Host smart-128d4005-946b-4e2e-bdc6-1df1f82a5a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041666543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4041666543
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3182608093
Short name T674
Test name
Test status
Simulation time 29819582607 ps
CPU time 91.79 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:16:38 PM PDT 24
Peak memory 208572 kb
Host smart-ad9d2522-6919-45d4-a330-681df42a1dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182608093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3182608093
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1541185668
Short name T883
Test name
Test status
Simulation time 33698731 ps
CPU time 2.55 seconds
Started May 16 03:15:01 PM PDT 24
Finished May 16 03:15:07 PM PDT 24
Peak memory 206968 kb
Host smart-3b379766-8a65-4c26-bb2c-b4cfbeaeb1cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541185668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1541185668
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1049182977
Short name T297
Test name
Test status
Simulation time 347528818 ps
CPU time 6.13 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:12 PM PDT 24
Peak memory 208696 kb
Host smart-267bd9dc-e24e-4ac1-86d7-cf624fe58927
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049182977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1049182977
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1154834428
Short name T554
Test name
Test status
Simulation time 113601235 ps
CPU time 3.6 seconds
Started May 16 03:15:04 PM PDT 24
Finished May 16 03:15:12 PM PDT 24
Peak memory 207028 kb
Host smart-c038a543-f2a1-49cb-bfd0-5cad92279685
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154834428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1154834428
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3442918328
Short name T231
Test name
Test status
Simulation time 265257443 ps
CPU time 5 seconds
Started May 16 03:15:03 PM PDT 24
Finished May 16 03:15:12 PM PDT 24
Peak memory 218436 kb
Host smart-99684def-bf88-409e-93d9-a341ceb2bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442918328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3442918328
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.345434608
Short name T701
Test name
Test status
Simulation time 57460763 ps
CPU time 2.71 seconds
Started May 16 03:14:53 PM PDT 24
Finished May 16 03:14:57 PM PDT 24
Peak memory 208388 kb
Host smart-e8abcfaa-d682-486a-a169-85c18db2a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345434608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.345434608
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3002739578
Short name T197
Test name
Test status
Simulation time 230395810 ps
CPU time 3.97 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:10 PM PDT 24
Peak memory 209188 kb
Host smart-bcfba18b-ad14-4155-98d2-9be78d0a96ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002739578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3002739578
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1820598166
Short name T635
Test name
Test status
Simulation time 418099566 ps
CPU time 3.58 seconds
Started May 16 03:15:02 PM PDT 24
Finished May 16 03:15:10 PM PDT 24
Peak memory 211056 kb
Host smart-c404e53b-0ef6-4ae2-8418-26a563c07065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820598166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1820598166
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3875791725
Short name T461
Test name
Test status
Simulation time 64965998 ps
CPU time 0.74 seconds
Started May 16 03:15:16 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 206008 kb
Host smart-ebdc20be-25e4-4b38-b604-940af4fb7eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875791725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3875791725
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.685800308
Short name T403
Test name
Test status
Simulation time 2286504191 ps
CPU time 32.3 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:51 PM PDT 24
Peak memory 214496 kb
Host smart-8471023a-18bd-4187-b991-703442179c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685800308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.685800308
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2804674932
Short name T665
Test name
Test status
Simulation time 143177344 ps
CPU time 5.27 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:24 PM PDT 24
Peak memory 222760 kb
Host smart-ffdeb058-3229-4b39-ae93-b429deb65981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804674932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2804674932
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3675804175
Short name T892
Test name
Test status
Simulation time 28913003 ps
CPU time 1.65 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 209404 kb
Host smart-41a61dca-655f-4c8e-a846-8bbe53099e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675804175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3675804175
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2522162907
Short name T349
Test name
Test status
Simulation time 121579525 ps
CPU time 2.8 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 214464 kb
Host smart-f7b33157-a2ae-4d98-a8bd-1fbfa097cdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522162907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2522162907
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.833893529
Short name T311
Test name
Test status
Simulation time 43198366 ps
CPU time 3.06 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 214264 kb
Host smart-c9e2ef7e-1b06-4886-805c-630b381a41ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833893529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.833893529
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1549252566
Short name T612
Test name
Test status
Simulation time 1079026734 ps
CPU time 6.9 seconds
Started May 16 03:15:17 PM PDT 24
Finished May 16 03:15:29 PM PDT 24
Peak memory 219152 kb
Host smart-7de880ce-2e8b-42eb-a251-601951899ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549252566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1549252566
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4084164567
Short name T407
Test name
Test status
Simulation time 599524277 ps
CPU time 6.67 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:24 PM PDT 24
Peak memory 207620 kb
Host smart-28bfadae-5c9b-40fb-a7e0-ab69002f2234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084164567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4084164567
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2022446885
Short name T261
Test name
Test status
Simulation time 41202198 ps
CPU time 1.81 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 208544 kb
Host smart-822e7d66-61fb-4428-ba68-44d2a7d1c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022446885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2022446885
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1253042989
Short name T651
Test name
Test status
Simulation time 117430961 ps
CPU time 3.14 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 208852 kb
Host smart-8d50bb66-f557-4ebf-a67d-540cb7f1631a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253042989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1253042989
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3069632728
Short name T330
Test name
Test status
Simulation time 235675697 ps
CPU time 2.72 seconds
Started May 16 03:15:13 PM PDT 24
Finished May 16 03:15:18 PM PDT 24
Peak memory 208148 kb
Host smart-a9347692-2f20-43c5-aaed-ec00437b133e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069632728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3069632728
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4114735204
Short name T679
Test name
Test status
Simulation time 440651925 ps
CPU time 6.26 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:24 PM PDT 24
Peak memory 208620 kb
Host smart-cd4d6855-dd88-406a-8301-d9034b0a2619
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114735204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4114735204
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.349267133
Short name T901
Test name
Test status
Simulation time 668714720 ps
CPU time 15.98 seconds
Started May 16 03:15:13 PM PDT 24
Finished May 16 03:15:31 PM PDT 24
Peak memory 208964 kb
Host smart-d38bc2db-a2cc-4e44-8691-f3c3216731a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349267133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.349267133
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.426027646
Short name T837
Test name
Test status
Simulation time 33871128 ps
CPU time 2.21 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:20 PM PDT 24
Peak memory 206968 kb
Host smart-88e178fe-b3f4-403a-b3b0-9a4244796cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426027646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.426027646
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.278873746
Short name T55
Test name
Test status
Simulation time 4784312037 ps
CPU time 20.38 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:40 PM PDT 24
Peak memory 222632 kb
Host smart-ac7ed614-6bcc-49d0-a859-b936b58ad869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278873746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.278873746
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2046381345
Short name T42
Test name
Test status
Simulation time 57132359 ps
CPU time 2.92 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 210480 kb
Host smart-85c3e8ef-f26b-4640-8f50-b2bbec0f0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046381345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2046381345
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3430218958
Short name T869
Test name
Test status
Simulation time 50537481 ps
CPU time 0.83 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:35 PM PDT 24
Peak memory 205996 kb
Host smart-ec04fe82-6d28-4cf6-ad24-c3417814f79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430218958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3430218958
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3313164454
Short name T419
Test name
Test status
Simulation time 79921826 ps
CPU time 2.15 seconds
Started May 16 03:15:17 PM PDT 24
Finished May 16 03:15:24 PM PDT 24
Peak memory 214372 kb
Host smart-3026e48e-3c07-41dd-8bec-ce0b3dc48887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313164454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3313164454
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1878477200
Short name T99
Test name
Test status
Simulation time 101612276 ps
CPU time 4.7 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 214060 kb
Host smart-442545a3-2adf-4002-8529-3121459cfb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878477200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1878477200
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1372889849
Short name T260
Test name
Test status
Simulation time 160880031 ps
CPU time 4.55 seconds
Started May 16 03:15:26 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 221952 kb
Host smart-f173c9d0-b25f-4831-bd25-cd7471c25195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372889849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1372889849
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.333917203
Short name T744
Test name
Test status
Simulation time 316360726 ps
CPU time 4.68 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:24 PM PDT 24
Peak memory 219980 kb
Host smart-4ff1e16f-912e-4416-a834-a0536b9fb93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333917203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.333917203
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1170969056
Short name T220
Test name
Test status
Simulation time 107266090 ps
CPU time 3.88 seconds
Started May 16 03:15:17 PM PDT 24
Finished May 16 03:15:25 PM PDT 24
Peak memory 219732 kb
Host smart-2c226281-e9b9-4b67-ad47-66c40dcc91e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170969056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1170969056
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2139462428
Short name T354
Test name
Test status
Simulation time 132128944 ps
CPU time 2.71 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 208876 kb
Host smart-580eee16-53ac-4e35-ba1a-047378c56c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139462428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2139462428
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.534664634
Short name T195
Test name
Test status
Simulation time 182304088 ps
CPU time 6.68 seconds
Started May 16 03:15:17 PM PDT 24
Finished May 16 03:15:28 PM PDT 24
Peak memory 208240 kb
Host smart-ee88042a-80eb-4a1a-bbcc-87b9151a77a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534664634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.534664634
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3680656332
Short name T561
Test name
Test status
Simulation time 339589943 ps
CPU time 3.22 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 208876 kb
Host smart-3df7c557-3e65-4c38-96d2-125d6d1f3a8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680656332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3680656332
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1673633564
Short name T465
Test name
Test status
Simulation time 469076904 ps
CPU time 3.7 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 208808 kb
Host smart-f934d8e5-b72c-4484-a666-222907c21f28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673633564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1673633564
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1182797260
Short name T705
Test name
Test status
Simulation time 244853266 ps
CPU time 1.91 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:36 PM PDT 24
Peak memory 207884 kb
Host smart-0b1722f3-351a-4530-9d7e-127298eaa93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182797260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1182797260
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1418292848
Short name T874
Test name
Test status
Simulation time 177391590 ps
CPU time 2.32 seconds
Started May 16 03:15:15 PM PDT 24
Finished May 16 03:15:22 PM PDT 24
Peak memory 206976 kb
Host smart-0c41b5f5-8124-4212-a0ce-0ea301feb825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418292848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1418292848
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3565755588
Short name T894
Test name
Test status
Simulation time 1809941225 ps
CPU time 19.73 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:56 PM PDT 24
Peak memory 217004 kb
Host smart-d76b274b-f2fb-4d15-b636-4c7966d3ba7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565755588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3565755588
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3980324155
Short name T315
Test name
Test status
Simulation time 365939649 ps
CPU time 14.5 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:51 PM PDT 24
Peak memory 220340 kb
Host smart-71258034-1bb3-4cc9-8a8e-dc69f2aab37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980324155 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3980324155
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.675591147
Short name T587
Test name
Test status
Simulation time 62842034 ps
CPU time 2.59 seconds
Started May 16 03:15:14 PM PDT 24
Finished May 16 03:15:21 PM PDT 24
Peak memory 207244 kb
Host smart-74c1c5d0-65dc-4876-9462-93600f984a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675591147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.675591147
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1482176670
Short name T763
Test name
Test status
Simulation time 59141163 ps
CPU time 2.78 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 210360 kb
Host smart-71963899-8338-4c3a-a9a8-f78771d9928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482176670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1482176670
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2469071141
Short name T577
Test name
Test status
Simulation time 16108132 ps
CPU time 0.78 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 206004 kb
Host smart-50047d62-9599-40f9-ae48-de4a577b1fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469071141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2469071141
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4091832014
Short name T141
Test name
Test status
Simulation time 261734455 ps
CPU time 4.77 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:42 PM PDT 24
Peak memory 215524 kb
Host smart-e7cd2b9e-733e-459b-be26-8c6f6312c4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091832014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4091832014
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.44207828
Short name T859
Test name
Test status
Simulation time 89312296 ps
CPU time 3.7 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 218472 kb
Host smart-b9c381b9-f335-4003-a2ce-99c152f3baa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44207828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.44207828
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1960666690
Short name T911
Test name
Test status
Simulation time 595988421 ps
CPU time 5.18 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 222536 kb
Host smart-bc269344-c204-489e-bb7b-873968774ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960666690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1960666690
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.642973893
Short name T374
Test name
Test status
Simulation time 272562180 ps
CPU time 3.08 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 210292 kb
Host smart-000f4e8f-fb9b-4a0a-b6a9-1053cbc888b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642973893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.642973893
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.15501827
Short name T779
Test name
Test status
Simulation time 82394448 ps
CPU time 3.9 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:42 PM PDT 24
Peak memory 209304 kb
Host smart-437b9275-1ab8-4c77-9bff-b8926355be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15501827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.15501827
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3140744212
Short name T81
Test name
Test status
Simulation time 1417841843 ps
CPU time 4.16 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 206800 kb
Host smart-284a74de-de63-4fc6-9b16-f64b3bbc5131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140744212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3140744212
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3207432515
Short name T733
Test name
Test status
Simulation time 137256776 ps
CPU time 3.81 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:40 PM PDT 24
Peak memory 208832 kb
Host smart-500ad4a2-8fd1-4f37-93ba-2de56b29a20b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207432515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3207432515
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.718178630
Short name T782
Test name
Test status
Simulation time 930740261 ps
CPU time 11.08 seconds
Started May 16 03:15:26 PM PDT 24
Finished May 16 03:15:45 PM PDT 24
Peak memory 208528 kb
Host smart-232deb97-833a-472d-b755-1b3183054b31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718178630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.718178630
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4085053793
Short name T507
Test name
Test status
Simulation time 7371692471 ps
CPU time 30.04 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:16:08 PM PDT 24
Peak memory 208380 kb
Host smart-f4c4c489-ea24-404e-8ee5-57ac13b8e863
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085053793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4085053793
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1672463867
Short name T711
Test name
Test status
Simulation time 53044253 ps
CPU time 2.59 seconds
Started May 16 03:15:26 PM PDT 24
Finished May 16 03:15:36 PM PDT 24
Peak memory 206860 kb
Host smart-02e1a42b-e434-4616-a48c-3f46f261aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672463867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1672463867
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3407808908
Short name T826
Test name
Test status
Simulation time 627208435 ps
CPU time 13.47 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:47 PM PDT 24
Peak memory 214332 kb
Host smart-569d57d9-43a1-4567-8abf-b17894a10ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407808908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3407808908
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1004481085
Short name T718
Test name
Test status
Simulation time 45393905 ps
CPU time 3.13 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:32 PM PDT 24
Peak memory 207992 kb
Host smart-ceb5e0fc-98eb-458f-80b8-f8a962f055ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004481085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1004481085
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2536001007
Short name T43
Test name
Test status
Simulation time 43802058 ps
CPU time 2.1 seconds
Started May 16 03:15:30 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 209936 kb
Host smart-799f9778-24fa-4f2a-a601-b8dfcde32539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536001007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2536001007
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2146295688
Short name T447
Test name
Test status
Simulation time 41963190 ps
CPU time 0.72 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:36 PM PDT 24
Peak memory 205980 kb
Host smart-3fc64355-e76b-4b9e-a7e3-24d804edf600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146295688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2146295688
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.13593762
Short name T382
Test name
Test status
Simulation time 59586867 ps
CPU time 4.27 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:35 PM PDT 24
Peak memory 214356 kb
Host smart-50039a46-651b-48bf-8af5-aba882a0d80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13593762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.13593762
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2796786836
Short name T788
Test name
Test status
Simulation time 34328615 ps
CPU time 2.39 seconds
Started May 16 03:15:30 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 210260 kb
Host smart-ca1d50fd-70e5-49f7-95bc-655b1ad52018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796786836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2796786836
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2036234336
Short name T912
Test name
Test status
Simulation time 88406886 ps
CPU time 3.87 seconds
Started May 16 03:15:26 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 218532 kb
Host smart-0dea7bce-e3e8-41a4-8036-a589c0853735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036234336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2036234336
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4013361946
Short name T347
Test name
Test status
Simulation time 118789954 ps
CPU time 3.46 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 222284 kb
Host smart-ddad4967-36d0-4bce-842e-e5ea08ab90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013361946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4013361946
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3554422648
Short name T879
Test name
Test status
Simulation time 238737855 ps
CPU time 3.1 seconds
Started May 16 03:15:30 PM PDT 24
Finished May 16 03:15:42 PM PDT 24
Peak memory 208912 kb
Host smart-ecb694a1-41fe-4316-a20b-3446c46fb6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554422648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3554422648
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2469770649
Short name T645
Test name
Test status
Simulation time 113453360 ps
CPU time 4.91 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:40 PM PDT 24
Peak memory 209064 kb
Host smart-cbfc1640-3dda-4a56-b39b-353a80518c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469770649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2469770649
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.820785493
Short name T273
Test name
Test status
Simulation time 37905185 ps
CPU time 2.48 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 208520 kb
Host smart-192b2b3f-b62f-4d79-96f1-3786e699bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820785493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.820785493
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2298350142
Short name T610
Test name
Test status
Simulation time 2836970801 ps
CPU time 19.04 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 208248 kb
Host smart-1c86cf7f-4111-4c8c-86eb-e6ae220e59c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298350142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2298350142
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3084257332
Short name T655
Test name
Test status
Simulation time 1862282210 ps
CPU time 4.95 seconds
Started May 16 03:15:29 PM PDT 24
Finished May 16 03:15:43 PM PDT 24
Peak memory 208536 kb
Host smart-22a71bab-c9d5-489f-a122-2ecfce0d85ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084257332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3084257332
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.511393922
Short name T820
Test name
Test status
Simulation time 381485542 ps
CPU time 3.57 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:34 PM PDT 24
Peak memory 206848 kb
Host smart-5197207d-e655-4adc-98c4-a173cdd9d8a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511393922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.511393922
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.445294309
Short name T279
Test name
Test status
Simulation time 101143190 ps
CPU time 3.63 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:34 PM PDT 24
Peak memory 209024 kb
Host smart-5dcff906-5861-4639-9e88-24f7ebfb0c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445294309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.445294309
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.128228561
Short name T769
Test name
Test status
Simulation time 48756390 ps
CPU time 2.44 seconds
Started May 16 03:15:28 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 206936 kb
Host smart-d2332b65-42da-4a9c-ab90-301f925f90c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128228561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.128228561
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3919501150
Short name T712
Test name
Test status
Simulation time 95063792 ps
CPU time 0.8 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:31 PM PDT 24
Peak memory 206008 kb
Host smart-10aa7975-85d3-443b-a4e5-dffd38c98d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919501150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3919501150
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.346324525
Short name T805
Test name
Test status
Simulation time 489760065 ps
CPU time 5.13 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:39 PM PDT 24
Peak memory 218364 kb
Host smart-99086aa5-8115-449b-b276-3574c7086cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346324525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.346324525
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1300418072
Short name T203
Test name
Test status
Simulation time 425241172 ps
CPU time 2.4 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 210900 kb
Host smart-30640b4d-df98-4bb8-9699-8cf62471526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300418072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1300418072
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2732586545
Short name T900
Test name
Test status
Simulation time 43933506 ps
CPU time 0.76 seconds
Started May 16 03:15:42 PM PDT 24
Finished May 16 03:15:48 PM PDT 24
Peak memory 206000 kb
Host smart-102c839b-46c7-4203-b467-ca803d7c583f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732586545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2732586545
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3225953544
Short name T430
Test name
Test status
Simulation time 201105137 ps
CPU time 3.63 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:15:50 PM PDT 24
Peak memory 215112 kb
Host smart-bcbca99b-db73-499c-91a8-8a30485f5c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225953544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3225953544
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3448957402
Short name T528
Test name
Test status
Simulation time 55182870 ps
CPU time 2.3 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:15:48 PM PDT 24
Peak memory 207732 kb
Host smart-a6581cb6-837e-439f-8695-cd7b8876f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448957402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3448957402
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1467866324
Short name T773
Test name
Test status
Simulation time 1191580459 ps
CPU time 3.29 seconds
Started May 16 03:15:43 PM PDT 24
Finished May 16 03:15:52 PM PDT 24
Peak memory 221908 kb
Host smart-9acccaed-4fe3-47f3-ab35-a0dcbf8aa384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467866324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1467866324
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.1532617669
Short name T776
Test name
Test status
Simulation time 530662550 ps
CPU time 14.88 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:16:01 PM PDT 24
Peak memory 214352 kb
Host smart-686f842b-71b6-44ac-913d-049578ec20aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532617669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1532617669
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4073558746
Short name T588
Test name
Test status
Simulation time 1952400918 ps
CPU time 51.64 seconds
Started May 16 03:15:27 PM PDT 24
Finished May 16 03:16:27 PM PDT 24
Peak memory 209148 kb
Host smart-dfe80ef5-2bc0-4513-ad68-c7e014b0df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073558746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4073558746
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1482673348
Short name T568
Test name
Test status
Simulation time 58011229 ps
CPU time 3.22 seconds
Started May 16 03:15:41 PM PDT 24
Finished May 16 03:15:50 PM PDT 24
Peak memory 208812 kb
Host smart-38bec223-b25d-4702-b348-0aab9440e6c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482673348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1482673348
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1765100267
Short name T451
Test name
Test status
Simulation time 223999062 ps
CPU time 7.41 seconds
Started May 16 03:15:25 PM PDT 24
Finished May 16 03:15:37 PM PDT 24
Peak memory 207936 kb
Host smart-6c35da26-f5bf-4b52-86d0-e448c076ec5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765100267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1765100267
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3541549340
Short name T625
Test name
Test status
Simulation time 810206657 ps
CPU time 28.47 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:16:14 PM PDT 24
Peak memory 208952 kb
Host smart-67f51c45-3b42-42b3-8479-d461047abd8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541549340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3541549340
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2891688255
Short name T358
Test name
Test status
Simulation time 85258005 ps
CPU time 2.74 seconds
Started May 16 03:15:41 PM PDT 24
Finished May 16 03:15:50 PM PDT 24
Peak memory 215668 kb
Host smart-4848af17-0c20-4a3c-a47d-97108ffb6a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891688255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2891688255
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.325771448
Short name T742
Test name
Test status
Simulation time 161590392 ps
CPU time 2.16 seconds
Started May 16 03:15:30 PM PDT 24
Finished May 16 03:15:41 PM PDT 24
Peak memory 206980 kb
Host smart-885942d5-2341-4759-9f34-9478c15bf791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325771448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.325771448
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.295886757
Short name T897
Test name
Test status
Simulation time 1536513932 ps
CPU time 34.93 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:16:21 PM PDT 24
Peak memory 215252 kb
Host smart-a59dfbb1-06bb-4b40-a0aa-78794787a6c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295886757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.295886757
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1600006124
Short name T338
Test name
Test status
Simulation time 721874061 ps
CPU time 7.76 seconds
Started May 16 03:15:40 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 208476 kb
Host smart-cdc065d5-abce-4884-a340-5ed4052e95d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600006124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1600006124
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3800875370
Short name T410
Test name
Test status
Simulation time 72311343 ps
CPU time 2.81 seconds
Started May 16 03:15:39 PM PDT 24
Finished May 16 03:15:49 PM PDT 24
Peak memory 210212 kb
Host smart-e6d872cc-60c5-4183-8a8d-27ce32788c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800875370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3800875370
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4290262203
Short name T833
Test name
Test status
Simulation time 144316920 ps
CPU time 4.84 seconds
Started May 16 03:15:36 PM PDT 24
Finished May 16 03:15:48 PM PDT 24
Peak memory 222564 kb
Host smart-3728e69f-c194-45b4-bd91-b835dd87268b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290262203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4290262203
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.335957440
Short name T644
Test name
Test status
Simulation time 87391607 ps
CPU time 4.29 seconds
Started May 16 03:15:45 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 210064 kb
Host smart-656edc3b-a295-4df3-9fe4-8a07f4e1e015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335957440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.335957440
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.142926772
Short name T73
Test name
Test status
Simulation time 538882273 ps
CPU time 4.14 seconds
Started May 16 03:15:45 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 218476 kb
Host smart-a56cd670-6c92-4e57-a6da-390a2e15da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142926772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.142926772
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.958153553
Short name T647
Test name
Test status
Simulation time 320510219 ps
CPU time 2.86 seconds
Started May 16 03:15:45 PM PDT 24
Finished May 16 03:15:53 PM PDT 24
Peak memory 214384 kb
Host smart-23e4b28e-401e-406a-bc8d-c14f79b8acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958153553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.958153553
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3906816162
Short name T583
Test name
Test status
Simulation time 35373784 ps
CPU time 1.39 seconds
Started May 16 03:15:42 PM PDT 24
Finished May 16 03:15:49 PM PDT 24
Peak memory 214340 kb
Host smart-38d05031-c070-4051-a6e1-261d51749e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906816162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3906816162
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1792864816
Short name T433
Test name
Test status
Simulation time 57439781 ps
CPU time 2.94 seconds
Started May 16 03:15:42 PM PDT 24
Finished May 16 03:15:51 PM PDT 24
Peak memory 214400 kb
Host smart-5af96551-f58a-4a03-9986-143d1325094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792864816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1792864816
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.597893397
Short name T774
Test name
Test status
Simulation time 68275022 ps
CPU time 3.46 seconds
Started May 16 03:15:41 PM PDT 24
Finished May 16 03:15:51 PM PDT 24
Peak memory 208924 kb
Host smart-441be5d7-ee96-4572-8c2e-03bef26dfefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597893397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.597893397
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1505340711
Short name T288
Test name
Test status
Simulation time 282943473 ps
CPU time 3.27 seconds
Started May 16 03:15:44 PM PDT 24
Finished May 16 03:15:52 PM PDT 24
Peak memory 208420 kb
Host smart-8789410f-e14a-4d54-baff-0995e7403bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505340711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1505340711
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3218878073
Short name T453
Test name
Test status
Simulation time 119958237 ps
CPU time 3.11 seconds
Started May 16 03:15:44 PM PDT 24
Finished May 16 03:15:52 PM PDT 24
Peak memory 207056 kb
Host smart-55afe025-7db8-48a8-a264-c6d0e1d8d059
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218878073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3218878073
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1641990737
Short name T482
Test name
Test status
Simulation time 246282160 ps
CPU time 3.43 seconds
Started May 16 03:15:40 PM PDT 24
Finished May 16 03:15:50 PM PDT 24
Peak memory 206964 kb
Host smart-f9ef6274-6a4e-46b9-aa46-54d7e87f86d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641990737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1641990737
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3109686403
Short name T299
Test name
Test status
Simulation time 59698639 ps
CPU time 2.86 seconds
Started May 16 03:15:51 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 214396 kb
Host smart-e5b13dbc-4ee0-4043-8ac0-5a99b8d16213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109686403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3109686403
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3364545401
Short name T861
Test name
Test status
Simulation time 3165092089 ps
CPU time 18.05 seconds
Started May 16 03:15:41 PM PDT 24
Finished May 16 03:16:05 PM PDT 24
Peak memory 208076 kb
Host smart-c4991ca5-4bba-4476-bbe3-f2dc647111b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364545401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3364545401
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2345627652
Short name T357
Test name
Test status
Simulation time 1166976068 ps
CPU time 9.35 seconds
Started May 16 03:15:49 PM PDT 24
Finished May 16 03:16:03 PM PDT 24
Peak memory 216364 kb
Host smart-592405a0-b944-4c9d-af3e-3dbe3aee3c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345627652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2345627652
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.193536174
Short name T916
Test name
Test status
Simulation time 1612064890 ps
CPU time 11.11 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:07 PM PDT 24
Peak memory 222700 kb
Host smart-11d3fe6a-797d-4249-b889-1482bdacb99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193536174 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.193536174
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3133630105
Short name T689
Test name
Test status
Simulation time 102815242 ps
CPU time 4.54 seconds
Started May 16 03:15:45 PM PDT 24
Finished May 16 03:15:55 PM PDT 24
Peak memory 208804 kb
Host smart-b021b084-b09c-478e-a438-0f58413938d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133630105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3133630105
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3267201165
Short name T695
Test name
Test status
Simulation time 133666693 ps
CPU time 2.62 seconds
Started May 16 03:15:49 PM PDT 24
Finished May 16 03:15:57 PM PDT 24
Peak memory 210260 kb
Host smart-4af9508b-69d8-4348-9c2d-5f12fa82a6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267201165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3267201165
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2705916984
Short name T520
Test name
Test status
Simulation time 40464084 ps
CPU time 0.79 seconds
Started May 16 03:13:21 PM PDT 24
Finished May 16 03:13:27 PM PDT 24
Peak memory 205988 kb
Host smart-fe475141-c207-47f6-9753-63ece8e97814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705916984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2705916984
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2042425508
Short name T738
Test name
Test status
Simulation time 58275409 ps
CPU time 2.24 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:13:26 PM PDT 24
Peak memory 215412 kb
Host smart-48693e95-8b08-4452-a67f-3068ad7463c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042425508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2042425508
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4169603895
Short name T810
Test name
Test status
Simulation time 339617021 ps
CPU time 3.31 seconds
Started May 16 03:13:18 PM PDT 24
Finished May 16 03:13:25 PM PDT 24
Peak memory 210056 kb
Host smart-d59ee9a5-b28e-4791-8b87-480ee2bdaa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169603895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4169603895
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.239825633
Short name T225
Test name
Test status
Simulation time 30686409 ps
CPU time 2.24 seconds
Started May 16 03:13:22 PM PDT 24
Finished May 16 03:13:29 PM PDT 24
Peak memory 214408 kb
Host smart-455088a2-3fb9-44d0-aa7c-5f40d061b5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239825633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.239825633
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1015607384
Short name T241
Test name
Test status
Simulation time 64696324 ps
CPU time 2.57 seconds
Started May 16 03:13:22 PM PDT 24
Finished May 16 03:13:29 PM PDT 24
Peak memory 220252 kb
Host smart-c1d1cb77-a941-4caa-b2f3-40cf8e26bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015607384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1015607384
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2700639516
Short name T624
Test name
Test status
Simulation time 186932963 ps
CPU time 4.74 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:13:28 PM PDT 24
Peak memory 208772 kb
Host smart-94ba695f-cfbb-4980-9158-b589160cd828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700639516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2700639516
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.674166414
Short name T654
Test name
Test status
Simulation time 677560041 ps
CPU time 15.25 seconds
Started May 16 03:13:12 PM PDT 24
Finished May 16 03:13:30 PM PDT 24
Peak memory 208004 kb
Host smart-f2de6cdd-d9ad-4d27-9797-767df37aba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674166414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.674166414
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.889609229
Short name T211
Test name
Test status
Simulation time 509118287 ps
CPU time 16.94 seconds
Started May 16 03:13:22 PM PDT 24
Finished May 16 03:13:45 PM PDT 24
Peak memory 208052 kb
Host smart-2504e753-3456-4f43-9f56-6fae8dc387ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889609229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.889609229
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2972506140
Short name T670
Test name
Test status
Simulation time 87837614 ps
CPU time 4.02 seconds
Started May 16 03:13:20 PM PDT 24
Finished May 16 03:13:29 PM PDT 24
Peak memory 208548 kb
Host smart-1a44290e-2905-4d10-b0fa-d99430a650bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972506140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2972506140
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.212260198
Short name T889
Test name
Test status
Simulation time 2488318959 ps
CPU time 68.35 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:14:32 PM PDT 24
Peak memory 209372 kb
Host smart-cbb38a4b-700d-4842-b815-079290b0a0e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212260198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.212260198
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2783739259
Short name T233
Test name
Test status
Simulation time 112456650 ps
CPU time 4.02 seconds
Started May 16 03:13:20 PM PDT 24
Finished May 16 03:13:29 PM PDT 24
Peak memory 207408 kb
Host smart-dd32807b-333a-4e56-a111-743f17464b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783739259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2783739259
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1465633116
Short name T519
Test name
Test status
Simulation time 112401094 ps
CPU time 1.72 seconds
Started May 16 03:13:11 PM PDT 24
Finished May 16 03:13:16 PM PDT 24
Peak memory 206776 kb
Host smart-866e8011-d34e-4849-99d5-f8b74bee7d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465633116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1465633116
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.894276987
Short name T424
Test name
Test status
Simulation time 31161520 ps
CPU time 2.43 seconds
Started May 16 03:13:20 PM PDT 24
Finished May 16 03:13:27 PM PDT 24
Peak memory 208096 kb
Host smart-e0d9c44a-0f3f-4579-a11b-96ce6e027a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894276987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.894276987
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3486209544
Short name T103
Test name
Test status
Simulation time 19333035 ps
CPU time 0.81 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:08 PM PDT 24
Peak memory 205996 kb
Host smart-f437859f-6056-4c4e-8eb3-7b708920d98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486209544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3486209544
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.969257591
Short name T198
Test name
Test status
Simulation time 401505686 ps
CPU time 3.82 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:00 PM PDT 24
Peak memory 214452 kb
Host smart-71d304ae-d3be-40bc-9e24-59b1a385235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969257591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.969257591
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.792906498
Short name T366
Test name
Test status
Simulation time 119593047 ps
CPU time 2.12 seconds
Started May 16 03:15:51 PM PDT 24
Finished May 16 03:15:58 PM PDT 24
Peak memory 222484 kb
Host smart-0335cca0-e58e-40ae-a652-07f891b0a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792906498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.792906498
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2720147891
Short name T677
Test name
Test status
Simulation time 103944784 ps
CPU time 1.84 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:15:57 PM PDT 24
Peak memory 214344 kb
Host smart-7ce4b5b5-dbd9-402c-b8b8-759a0f7ab764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720147891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2720147891
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2196720685
Short name T530
Test name
Test status
Simulation time 473561799 ps
CPU time 4.23 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:00 PM PDT 24
Peak memory 220104 kb
Host smart-fa0ad42d-4ba5-40dc-a5d4-8c097d38f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196720685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2196720685
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1175769227
Short name T14
Test name
Test status
Simulation time 356950832 ps
CPU time 4.36 seconds
Started May 16 03:15:49 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 209860 kb
Host smart-adfc96e6-c7b4-4823-9065-dde46652f2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175769227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1175769227
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2744828705
Short name T317
Test name
Test status
Simulation time 501026729 ps
CPU time 7.97 seconds
Started May 16 03:15:51 PM PDT 24
Finished May 16 03:16:04 PM PDT 24
Peak memory 208504 kb
Host smart-370de612-c106-4c39-add2-721707675286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744828705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2744828705
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1364143589
Short name T550
Test name
Test status
Simulation time 165811416 ps
CPU time 3.28 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 206972 kb
Host smart-50589312-5ebc-462e-8f12-d837fe4eb38d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364143589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1364143589
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2345862785
Short name T606
Test name
Test status
Simulation time 655126092 ps
CPU time 2.98 seconds
Started May 16 03:15:53 PM PDT 24
Finished May 16 03:16:01 PM PDT 24
Peak memory 206980 kb
Host smart-23774e91-f486-495f-9b84-d6a22c1db252
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345862785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2345862785
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2654220646
Short name T714
Test name
Test status
Simulation time 124766583 ps
CPU time 3.68 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:15:59 PM PDT 24
Peak memory 208912 kb
Host smart-ab9d6c80-03ee-4c0a-9aae-27dd2ab32067
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654220646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2654220646
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3671045376
Short name T818
Test name
Test status
Simulation time 275402753 ps
CPU time 5.78 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:02 PM PDT 24
Peak memory 214428 kb
Host smart-350308d6-0506-4569-88f1-f0db564bc81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671045376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3671045376
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.807813712
Short name T870
Test name
Test status
Simulation time 21728622 ps
CPU time 1.66 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:15:57 PM PDT 24
Peak memory 206824 kb
Host smart-599e20ec-8aa0-444f-a314-3a89a12a4a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807813712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.807813712
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1889029269
Short name T306
Test name
Test status
Simulation time 830020985 ps
CPU time 36.37 seconds
Started May 16 03:15:50 PM PDT 24
Finished May 16 03:16:32 PM PDT 24
Peak memory 216384 kb
Host smart-dad55445-78e2-4d98-8236-83b31aa8ea71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889029269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1889029269
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.100632112
Short name T251
Test name
Test status
Simulation time 1241348813 ps
CPU time 18.92 seconds
Started May 16 03:15:49 PM PDT 24
Finished May 16 03:16:13 PM PDT 24
Peak memory 221304 kb
Host smart-64212beb-24ea-4eef-b9a0-436402d4c41e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100632112 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.100632112
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.581082483
Short name T363
Test name
Test status
Simulation time 2410775701 ps
CPU time 22.33 seconds
Started May 16 03:15:52 PM PDT 24
Finished May 16 03:16:20 PM PDT 24
Peak memory 209876 kb
Host smart-b3da5185-ac70-47f7-94aa-34b2fef538e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581082483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.581082483
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1236790231
Short name T169
Test name
Test status
Simulation time 167666263 ps
CPU time 2.8 seconds
Started May 16 03:15:52 PM PDT 24
Finished May 16 03:16:00 PM PDT 24
Peak memory 210972 kb
Host smart-d658d1f4-2326-4c78-8395-624666ac0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236790231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1236790231
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.926824336
Short name T443
Test name
Test status
Simulation time 16560446 ps
CPU time 0.73 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:08 PM PDT 24
Peak memory 205980 kb
Host smart-e139f374-e8d9-4ff0-8b8e-aae5802dfb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926824336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.926824336
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.837745335
Short name T432
Test name
Test status
Simulation time 55786935 ps
CPU time 4.1 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:12 PM PDT 24
Peak memory 214400 kb
Host smart-7328fc4b-534a-4124-bee3-172b5192fde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837745335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.837745335
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2902642151
Short name T189
Test name
Test status
Simulation time 5703160941 ps
CPU time 26.07 seconds
Started May 16 03:16:04 PM PDT 24
Finished May 16 03:16:36 PM PDT 24
Peak memory 222900 kb
Host smart-448f45fe-36e9-49d2-87d5-a48616b67957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902642151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2902642151
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.43543097
Short name T852
Test name
Test status
Simulation time 92669675 ps
CPU time 2.65 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:08 PM PDT 24
Peak memory 214400 kb
Host smart-4720ae70-14d8-4c6f-be2e-24f9f5fbf2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43543097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.43543097
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1653843791
Short name T623
Test name
Test status
Simulation time 381202266 ps
CPU time 3.45 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:10 PM PDT 24
Peak memory 214244 kb
Host smart-d9f9728a-7024-4667-945a-2d978d816f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653843791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1653843791
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3253952758
Short name T57
Test name
Test status
Simulation time 193850191 ps
CPU time 4.58 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:10 PM PDT 24
Peak memory 208972 kb
Host smart-ddc0eff7-77c9-4e75-a339-defb97fdeace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253952758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3253952758
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.992252838
Short name T589
Test name
Test status
Simulation time 3254516913 ps
CPU time 34.6 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 209596 kb
Host smart-284dccfb-4cb2-43aa-8f01-0cc001d1f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992252838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.992252838
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2606328138
Short name T379
Test name
Test status
Simulation time 804750024 ps
CPU time 21.68 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:29 PM PDT 24
Peak memory 208120 kb
Host smart-6c25e597-a079-484e-b31f-3f35daddd187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606328138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2606328138
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4124220611
Short name T659
Test name
Test status
Simulation time 272914757 ps
CPU time 3.59 seconds
Started May 16 03:16:03 PM PDT 24
Finished May 16 03:16:13 PM PDT 24
Peak memory 209040 kb
Host smart-87445b2e-a879-4596-8838-4c8dfbdcd260
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124220611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4124220611
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3549398575
Short name T522
Test name
Test status
Simulation time 4047226753 ps
CPU time 44.24 seconds
Started May 16 03:16:04 PM PDT 24
Finished May 16 03:16:54 PM PDT 24
Peak memory 208780 kb
Host smart-8a0e8372-096e-4a05-a50c-5bdbaf1726e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549398575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3549398575
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.810509324
Short name T683
Test name
Test status
Simulation time 55591890 ps
CPU time 3.04 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:10 PM PDT 24
Peak memory 207044 kb
Host smart-379214e2-2126-4dd7-aa98-894c3624181d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810509324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.810509324
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3809992570
Short name T479
Test name
Test status
Simulation time 147829863 ps
CPU time 2.13 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:08 PM PDT 24
Peak memory 208336 kb
Host smart-47158592-e56f-466f-bb49-3a122cd80e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809992570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3809992570
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.809690582
Short name T514
Test name
Test status
Simulation time 704885011 ps
CPU time 12.37 seconds
Started May 16 03:16:00 PM PDT 24
Finished May 16 03:16:17 PM PDT 24
Peak memory 208780 kb
Host smart-41dde422-f096-47fa-aaa7-bbdd9089e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809690582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.809690582
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1219474597
Short name T512
Test name
Test status
Simulation time 1012309335 ps
CPU time 11.22 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:17 PM PDT 24
Peak memory 208972 kb
Host smart-ee22bbb1-2726-4277-b6d4-6b4c8f0e0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219474597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1219474597
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3129412859
Short name T480
Test name
Test status
Simulation time 56558064 ps
CPU time 1.99 seconds
Started May 16 03:16:00 PM PDT 24
Finished May 16 03:16:05 PM PDT 24
Peak memory 210688 kb
Host smart-210519b9-bf07-4c9f-a137-005036ce1523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129412859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3129412859
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1932021099
Short name T628
Test name
Test status
Simulation time 75566416 ps
CPU time 0.75 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:20 PM PDT 24
Peak memory 205944 kb
Host smart-84f0990d-a4dc-4e74-b7e4-f3f2dba9907f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932021099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1932021099
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2652261563
Short name T71
Test name
Test status
Simulation time 169486727 ps
CPU time 2.04 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:22 PM PDT 24
Peak memory 207556 kb
Host smart-3224516e-23ad-4b5d-b9d2-93ed40cfd09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652261563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2652261563
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1484722296
Short name T268
Test name
Test status
Simulation time 140217227 ps
CPU time 3.1 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:16:23 PM PDT 24
Peak memory 214664 kb
Host smart-e7edee4f-76f1-4583-9d44-20c0ebd3140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484722296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1484722296
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1948151484
Short name T686
Test name
Test status
Simulation time 85615039 ps
CPU time 3.95 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:24 PM PDT 24
Peak memory 222448 kb
Host smart-9728fa4b-719e-42a7-a572-80d8d6c0d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948151484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1948151484
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.3647568266
Short name T845
Test name
Test status
Simulation time 319622086 ps
CPU time 6.4 seconds
Started May 16 03:16:12 PM PDT 24
Finished May 16 03:16:25 PM PDT 24
Peak memory 214388 kb
Host smart-1546d0d2-e9fc-402f-9806-7034ec355465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647568266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3647568266
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3419873014
Short name T787
Test name
Test status
Simulation time 335052176 ps
CPU time 12.27 seconds
Started May 16 03:16:03 PM PDT 24
Finished May 16 03:16:22 PM PDT 24
Peak memory 209000 kb
Host smart-d1fcfafe-b6a1-45c5-bf80-06bb184765ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419873014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3419873014
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3875312519
Short name T323
Test name
Test status
Simulation time 491443660 ps
CPU time 7.02 seconds
Started May 16 03:16:03 PM PDT 24
Finished May 16 03:16:15 PM PDT 24
Peak memory 208984 kb
Host smart-c35dafb4-9d26-4189-8706-78750cfbf7da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875312519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3875312519
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3627241471
Short name T688
Test name
Test status
Simulation time 118849557 ps
CPU time 2.36 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:10 PM PDT 24
Peak memory 207032 kb
Host smart-cf0ff067-3ea0-4167-9c42-ea072bd24419
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627241471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3627241471
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2573522821
Short name T921
Test name
Test status
Simulation time 744910000 ps
CPU time 5.74 seconds
Started May 16 03:16:02 PM PDT 24
Finished May 16 03:16:13 PM PDT 24
Peak memory 208720 kb
Host smart-3028bbd7-457b-4f67-9475-9dbbe43e2f22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573522821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2573522821
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.462773544
Short name T259
Test name
Test status
Simulation time 36084983 ps
CPU time 2.04 seconds
Started May 16 03:16:15 PM PDT 24
Finished May 16 03:16:23 PM PDT 24
Peak memory 210096 kb
Host smart-90eb0b8b-239c-4ce3-8597-e7dc5e8d5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462773544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.462773544
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.176618825
Short name T457
Test name
Test status
Simulation time 301124082 ps
CPU time 5.87 seconds
Started May 16 03:16:01 PM PDT 24
Finished May 16 03:16:12 PM PDT 24
Peak memory 208396 kb
Host smart-038b2921-64f1-4641-b38a-c8f5791192f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176618825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.176618825
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1455508516
Short name T3
Test name
Test status
Simulation time 2227963029 ps
CPU time 39.27 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:17:00 PM PDT 24
Peak memory 218700 kb
Host smart-39c799f2-1387-4b60-85f6-fdf17cec9b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455508516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1455508516
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2490673954
Short name T700
Test name
Test status
Simulation time 309409203 ps
CPU time 12.55 seconds
Started May 16 03:16:12 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 220840 kb
Host smart-415feed9-634d-440d-b762-1afc1d306479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490673954 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2490673954
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.940786352
Short name T648
Test name
Test status
Simulation time 462901909 ps
CPU time 7.32 seconds
Started May 16 03:16:15 PM PDT 24
Finished May 16 03:16:28 PM PDT 24
Peak memory 209768 kb
Host smart-09668693-a4f7-4482-af12-99e1f58dd747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940786352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.940786352
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1523153262
Short name T840
Test name
Test status
Simulation time 171197291 ps
CPU time 3.4 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:16:24 PM PDT 24
Peak memory 210264 kb
Host smart-6e603948-c5c6-4e51-bded-7393c3e1a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523153262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1523153262
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.134166289
Short name T209
Test name
Test status
Simulation time 85782772 ps
CPU time 0.78 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:38 PM PDT 24
Peak memory 205984 kb
Host smart-f73e10a6-abe0-4152-aa4d-9976afe18a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134166289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.134166289
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1959802411
Short name T350
Test name
Test status
Simulation time 1314863348 ps
CPU time 9.19 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:16:29 PM PDT 24
Peak memory 219696 kb
Host smart-6e96857a-54b6-4f5f-a128-ab70626e02be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959802411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1959802411
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3732570296
Short name T309
Test name
Test status
Simulation time 116516700 ps
CPU time 3.7 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:23 PM PDT 24
Peak memory 214368 kb
Host smart-02942a2b-e70e-49bd-8f70-96093df65f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732570296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3732570296
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1534640248
Short name T308
Test name
Test status
Simulation time 143843937 ps
CPU time 4.18 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:16:25 PM PDT 24
Peak memory 221476 kb
Host smart-f4679d6b-4c50-4086-9f48-213abb88b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534640248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1534640248
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3621365273
Short name T56
Test name
Test status
Simulation time 91101269 ps
CPU time 4.16 seconds
Started May 16 03:16:15 PM PDT 24
Finished May 16 03:16:25 PM PDT 24
Peak memory 216660 kb
Host smart-636b9557-e551-4418-85b2-59befe533980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621365273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3621365273
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3495969841
Short name T557
Test name
Test status
Simulation time 187540614 ps
CPU time 3.42 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:23 PM PDT 24
Peak memory 218428 kb
Host smart-57c5924c-c966-44d7-aa98-c135a618e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495969841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3495969841
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1429506284
Short name T278
Test name
Test status
Simulation time 655117095 ps
CPU time 8.13 seconds
Started May 16 03:16:12 PM PDT 24
Finished May 16 03:16:26 PM PDT 24
Peak memory 208788 kb
Host smart-1a6f42cc-e3c5-428d-ac04-b47e89e86294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429506284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1429506284
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1027099476
Short name T498
Test name
Test status
Simulation time 180630815 ps
CPU time 6.24 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:26 PM PDT 24
Peak memory 208208 kb
Host smart-8b1d3982-9fb9-4837-8161-7a43d606005d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027099476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1027099476
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2280712258
Short name T571
Test name
Test status
Simulation time 57529747 ps
CPU time 3 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:16:22 PM PDT 24
Peak memory 208568 kb
Host smart-5fa46a6a-effa-4f8c-848b-53a86851da7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280712258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2280712258
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1260460375
Short name T762
Test name
Test status
Simulation time 7146416898 ps
CPU time 44.92 seconds
Started May 16 03:16:16 PM PDT 24
Finished May 16 03:17:07 PM PDT 24
Peak memory 208360 kb
Host smart-e0fca041-1c7d-48f6-9a55-d151c35e53ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260460375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1260460375
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2934274604
Short name T542
Test name
Test status
Simulation time 287134521 ps
CPU time 2.5 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:36 PM PDT 24
Peak memory 208144 kb
Host smart-1f762451-1044-4254-89e6-062cdd6b9a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934274604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2934274604
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1891884008
Short name T549
Test name
Test status
Simulation time 72167290 ps
CPU time 1.73 seconds
Started May 16 03:16:14 PM PDT 24
Finished May 16 03:16:22 PM PDT 24
Peak memory 206820 kb
Host smart-f8e43b84-96d1-4aff-a191-a3ba10c6cfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891884008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1891884008
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4140371659
Short name T835
Test name
Test status
Simulation time 522624435 ps
CPU time 25.4 seconds
Started May 16 03:16:29 PM PDT 24
Finished May 16 03:17:01 PM PDT 24
Peak memory 215008 kb
Host smart-17338125-5173-4e26-b7e2-a511ee943c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140371659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4140371659
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.189338418
Short name T105
Test name
Test status
Simulation time 18537074463 ps
CPU time 114.86 seconds
Started May 16 03:16:13 PM PDT 24
Finished May 16 03:18:14 PM PDT 24
Peak memory 220900 kb
Host smart-eb23268a-eb51-440c-9f09-d127baaefa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189338418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.189338418
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2884778856
Short name T698
Test name
Test status
Simulation time 2063455365 ps
CPU time 25.08 seconds
Started May 16 03:16:30 PM PDT 24
Finished May 16 03:17:01 PM PDT 24
Peak memory 210552 kb
Host smart-6d637d5d-7591-4611-ad4d-7d3ea96e5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884778856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2884778856
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.339742925
Short name T445
Test name
Test status
Simulation time 19468262 ps
CPU time 0.71 seconds
Started May 16 03:16:22 PM PDT 24
Finished May 16 03:16:27 PM PDT 24
Peak memory 206024 kb
Host smart-fc7b9959-d9d3-49f7-bfda-65131a3416e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339742925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.339742925
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3192206540
Short name T242
Test name
Test status
Simulation time 80600805 ps
CPU time 1.49 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:16:35 PM PDT 24
Peak memory 214376 kb
Host smart-9eaf3dfe-d542-4b75-8a98-e66b3ae54f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192206540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3192206540
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2876501522
Short name T265
Test name
Test status
Simulation time 83244143 ps
CPU time 3.78 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 209920 kb
Host smart-db0854e1-49bc-4291-b852-c23bc977255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876501522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2876501522
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3063476280
Short name T91
Test name
Test status
Simulation time 108591242 ps
CPU time 2.89 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:30 PM PDT 24
Peak memory 215608 kb
Host smart-62039b82-4091-4ce7-ae4f-c4e2cce29723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063476280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3063476280
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3405156234
Short name T369
Test name
Test status
Simulation time 313641956 ps
CPU time 5.92 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:16:36 PM PDT 24
Peak memory 214648 kb
Host smart-64c36dcb-18d6-440f-8c65-b1fc714fe266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405156234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3405156234
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1139642575
Short name T466
Test name
Test status
Simulation time 34214412 ps
CPU time 2 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:16:32 PM PDT 24
Peak memory 216328 kb
Host smart-26e46ef3-db83-4847-9841-6b02adea9342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139642575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1139642575
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3324358473
Short name T682
Test name
Test status
Simulation time 6250619054 ps
CPU time 31.65 seconds
Started May 16 03:16:24 PM PDT 24
Finished May 16 03:17:00 PM PDT 24
Peak memory 208984 kb
Host smart-82126849-5701-490f-a858-774fd9e8d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324358473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3324358473
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3359002827
Short name T597
Test name
Test status
Simulation time 196735519 ps
CPU time 4.5 seconds
Started May 16 03:16:24 PM PDT 24
Finished May 16 03:16:33 PM PDT 24
Peak memory 206188 kb
Host smart-b653dd9c-9d1b-4006-a70c-8385483c2a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359002827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3359002827
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.228423823
Short name T786
Test name
Test status
Simulation time 39395382 ps
CPU time 2.4 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:29 PM PDT 24
Peak memory 207036 kb
Host smart-546c7495-3564-4aa9-90bd-d7074ddd38fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228423823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.228423823
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.721095975
Short name T604
Test name
Test status
Simulation time 277301272 ps
CPU time 3.5 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 208184 kb
Host smart-4d9191b4-9768-40d6-ad3e-b429fccbcccb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721095975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.721095975
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.210608206
Short name T639
Test name
Test status
Simulation time 490512166 ps
CPU time 4.3 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:38 PM PDT 24
Peak memory 208732 kb
Host smart-7e1d29e8-1405-4fb6-a52a-883ae7347f9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210608206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.210608206
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1789287563
Short name T724
Test name
Test status
Simulation time 274141726 ps
CPU time 2.15 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:36 PM PDT 24
Peak memory 209576 kb
Host smart-437dcb41-7334-4191-84f6-47d92f524234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789287563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1789287563
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2780685935
Short name T455
Test name
Test status
Simulation time 721184682 ps
CPU time 4.93 seconds
Started May 16 03:16:26 PM PDT 24
Finished May 16 03:16:35 PM PDT 24
Peak memory 208424 kb
Host smart-f772f3dd-4c6d-440e-b9ee-50c95c710309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780685935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2780685935
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1294537051
Short name T876
Test name
Test status
Simulation time 476600489 ps
CPU time 17.86 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:16:50 PM PDT 24
Peak memory 222412 kb
Host smart-b68ffc11-f88e-4756-88bd-2da69cfacbfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294537051 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1294537051
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1453223671
Short name T499
Test name
Test status
Simulation time 239187612 ps
CPU time 7.35 seconds
Started May 16 03:16:30 PM PDT 24
Finished May 16 03:16:44 PM PDT 24
Peak memory 210196 kb
Host smart-8337e8c0-d73c-4b0f-8164-e3a57f313bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453223671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1453223671
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2930330214
Short name T872
Test name
Test status
Simulation time 79471472 ps
CPU time 2.2 seconds
Started May 16 03:16:29 PM PDT 24
Finished May 16 03:16:37 PM PDT 24
Peak memory 210440 kb
Host smart-620b912f-7db3-4c83-96cc-958c52cd1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930330214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2930330214
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3387212612
Short name T459
Test name
Test status
Simulation time 38041281 ps
CPU time 0.83 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:34 PM PDT 24
Peak memory 206000 kb
Host smart-6b7c15a4-b624-4999-a877-c85935d5ba44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387212612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3387212612
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2818699157
Short name T409
Test name
Test status
Simulation time 781493895 ps
CPU time 9.22 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:16:39 PM PDT 24
Peak memory 222552 kb
Host smart-1a7b59a0-c5a7-4235-8e06-d04daac39afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818699157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2818699157
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2369143720
Short name T277
Test name
Test status
Simulation time 212729005 ps
CPU time 2.59 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:30 PM PDT 24
Peak memory 220600 kb
Host smart-d10e631a-9fea-4f37-a8e8-ff4822e047b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369143720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2369143720
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3476050183
Short name T627
Test name
Test status
Simulation time 328277918 ps
CPU time 4.15 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:16:34 PM PDT 24
Peak memory 207484 kb
Host smart-f06a32cb-a826-4836-9205-a60020c4d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476050183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3476050183
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1801616149
Short name T94
Test name
Test status
Simulation time 514139813 ps
CPU time 6.09 seconds
Started May 16 03:16:26 PM PDT 24
Finished May 16 03:16:37 PM PDT 24
Peak memory 214344 kb
Host smart-6f3826e2-4ee8-4b8a-adde-890969fb60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801616149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1801616149
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1895534010
Short name T292
Test name
Test status
Simulation time 42030902 ps
CPU time 1.95 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:29 PM PDT 24
Peak memory 219460 kb
Host smart-24952f8a-96e8-49b8-b0bf-e6e47928eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895534010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1895534010
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1787549753
Short name T284
Test name
Test status
Simulation time 113912128 ps
CPU time 2.91 seconds
Started May 16 03:16:24 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 220344 kb
Host smart-6f68b00b-af79-413e-b22b-c9fd440afecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787549753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1787549753
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.778133023
Short name T685
Test name
Test status
Simulation time 1383109277 ps
CPU time 38.15 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:17:08 PM PDT 24
Peak memory 208920 kb
Host smart-d1b80877-2414-4ff1-9e86-44cc592936dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778133023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.778133023
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2107581415
Short name T186
Test name
Test status
Simulation time 94532758 ps
CPU time 3.88 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:41 PM PDT 24
Peak memory 207640 kb
Host smart-9715b046-57c5-4b28-bfe1-ca64a2a61601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107581415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2107581415
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2066306481
Short name T188
Test name
Test status
Simulation time 4162480778 ps
CPU time 28.61 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:56 PM PDT 24
Peak memory 208392 kb
Host smart-c9976e64-97e2-48c7-bef4-76fd502bef23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066306481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2066306481
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2955082728
Short name T922
Test name
Test status
Simulation time 1070148475 ps
CPU time 27.15 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:17:00 PM PDT 24
Peak memory 208808 kb
Host smart-f686ae63-599b-495f-896f-111fcc17b0e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955082728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2955082728
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1599096745
Short name T573
Test name
Test status
Simulation time 977453503 ps
CPU time 24.1 seconds
Started May 16 03:16:24 PM PDT 24
Finished May 16 03:16:52 PM PDT 24
Peak memory 208024 kb
Host smart-1f82119e-fb7e-457c-94e9-e8f1abe22e2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599096745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1599096745
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3695765846
Short name T478
Test name
Test status
Simulation time 153444388 ps
CPU time 3.54 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:37 PM PDT 24
Peak memory 210060 kb
Host smart-db98fef4-b986-4c1f-a305-37a8e1b74f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695765846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3695765846
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2536492580
Short name T423
Test name
Test status
Simulation time 704559509 ps
CPU time 3.72 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:37 PM PDT 24
Peak memory 206852 kb
Host smart-66dd7b85-9dce-47fe-a6a7-2a9824b245e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536492580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2536492580
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1768792441
Short name T865
Test name
Test status
Simulation time 2376321853 ps
CPU time 12.93 seconds
Started May 16 03:16:25 PM PDT 24
Finished May 16 03:16:43 PM PDT 24
Peak memory 209328 kb
Host smart-3499bc81-799f-4693-8655-af4a79155367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768792441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1768792441
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2191005019
Short name T128
Test name
Test status
Simulation time 203534976 ps
CPU time 3.42 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:16:35 PM PDT 24
Peak memory 218668 kb
Host smart-18c4f0af-3a1a-46e0-9469-fe2fddca4691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191005019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2191005019
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2612163365
Short name T164
Test name
Test status
Simulation time 127403209 ps
CPU time 1.37 seconds
Started May 16 03:16:28 PM PDT 24
Finished May 16 03:16:35 PM PDT 24
Peak memory 208688 kb
Host smart-c17c91e7-00f3-42da-946b-c2a1698ab247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612163365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2612163365
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3004272436
Short name T531
Test name
Test status
Simulation time 55739189 ps
CPU time 0.76 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:38 PM PDT 24
Peak memory 205976 kb
Host smart-4328a767-23e7-4ad3-8fb6-68ef1047cb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004272436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3004272436
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3876164945
Short name T902
Test name
Test status
Simulation time 83275930 ps
CPU time 4.81 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:43 PM PDT 24
Peak memory 215836 kb
Host smart-8e644a68-29ef-48d5-9294-c483cb10bd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876164945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3876164945
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1153749740
Short name T9
Test name
Test status
Simulation time 355867677 ps
CPU time 5.59 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:45 PM PDT 24
Peak memory 210268 kb
Host smart-44b295c3-8c85-4d80-8be7-bad9443c553e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153749740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1153749740
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.448988754
Short name T53
Test name
Test status
Simulation time 76557197 ps
CPU time 2.54 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 207760 kb
Host smart-9714ceda-ce5d-49bc-9df0-7ea1abcea1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448988754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.448988754
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2851413874
Short name T84
Test name
Test status
Simulation time 661726423 ps
CPU time 3.78 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:45 PM PDT 24
Peak memory 222528 kb
Host smart-631529f1-979c-4d8c-bb35-a77580f87cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851413874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2851413874
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1893887968
Short name T678
Test name
Test status
Simulation time 93193468 ps
CPU time 2.36 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 208192 kb
Host smart-c7b15bca-e28c-4903-b1ef-b9a35e781e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893887968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1893887968
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2326029907
Short name T291
Test name
Test status
Simulation time 1340882773 ps
CPU time 9.65 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 208224 kb
Host smart-576eedba-9930-46c5-922a-d2a857302997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326029907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2326029907
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1516338339
Short name T513
Test name
Test status
Simulation time 469255758 ps
CPU time 5.89 seconds
Started May 16 03:16:21 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 208076 kb
Host smart-9a49dee8-03bb-4d1b-820a-9e9a873f4a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516338339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1516338339
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3914825782
Short name T497
Test name
Test status
Simulation time 847808439 ps
CPU time 21.3 seconds
Started May 16 03:16:23 PM PDT 24
Finished May 16 03:16:47 PM PDT 24
Peak memory 208920 kb
Host smart-f22b38b4-b9e3-4a96-aad5-591f726b8006
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914825782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3914825782
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1443747232
Short name T452
Test name
Test status
Simulation time 84579516 ps
CPU time 2.65 seconds
Started May 16 03:16:27 PM PDT 24
Finished May 16 03:16:34 PM PDT 24
Peak memory 207040 kb
Host smart-7d0d6ac5-deac-401c-a2d1-a4fe6b8693df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443747232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1443747232
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3593897987
Short name T887
Test name
Test status
Simulation time 27117596 ps
CPU time 2.28 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:41 PM PDT 24
Peak memory 208992 kb
Host smart-ab7f7eee-e299-40a1-89bd-6567badff02b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593897987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3593897987
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1630106102
Short name T564
Test name
Test status
Simulation time 238306769 ps
CPU time 3.39 seconds
Started May 16 03:16:36 PM PDT 24
Finished May 16 03:16:45 PM PDT 24
Peak memory 218252 kb
Host smart-85074944-322c-4fcd-af20-939322bd14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630106102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1630106102
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2958105614
Short name T470
Test name
Test status
Simulation time 127289197 ps
CPU time 3.32 seconds
Started May 16 03:16:30 PM PDT 24
Finished May 16 03:16:39 PM PDT 24
Peak memory 208648 kb
Host smart-29f2e3d1-03a8-4695-a3e6-f86a8e307ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958105614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2958105614
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3758634625
Short name T72
Test name
Test status
Simulation time 275093330 ps
CPU time 14.76 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:53 PM PDT 24
Peak memory 215372 kb
Host smart-9faec379-7a67-4bff-a32e-4ef84de3f5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758634625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3758634625
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.267240130
Short name T863
Test name
Test status
Simulation time 114893168 ps
CPU time 8.26 seconds
Started May 16 03:16:34 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 222624 kb
Host smart-8a749bf5-984c-4ef3-9216-aa6afba67296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267240130 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.267240130
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2772798036
Short name T831
Test name
Test status
Simulation time 118763407 ps
CPU time 5.06 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:46 PM PDT 24
Peak memory 208084 kb
Host smart-4e4ff2a6-ac29-496f-a21e-d06928b026f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772798036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2772798036
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2283243621
Short name T492
Test name
Test status
Simulation time 30595913 ps
CPU time 0.75 seconds
Started May 16 03:16:39 PM PDT 24
Finished May 16 03:16:45 PM PDT 24
Peak memory 205984 kb
Host smart-58e9cd28-e4ab-4c03-a5ac-3a8bc808f7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283243621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2283243621
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1310721074
Short name T285
Test name
Test status
Simulation time 72345602 ps
CPU time 4.32 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:44 PM PDT 24
Peak memory 215384 kb
Host smart-8a53e331-8d3f-4d79-96e7-eb34bb0b49fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310721074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1310721074
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.995983951
Short name T31
Test name
Test status
Simulation time 66213555 ps
CPU time 2.37 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:44 PM PDT 24
Peak memory 221420 kb
Host smart-6cc417f8-c026-4388-b2f8-59407f67270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995983951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.995983951
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3126911377
Short name T739
Test name
Test status
Simulation time 109719058 ps
CPU time 2.01 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:43 PM PDT 24
Peak memory 208880 kb
Host smart-18e37c32-847b-4a58-9293-21143943f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126911377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3126911377
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2719315492
Short name T96
Test name
Test status
Simulation time 726822609 ps
CPU time 10.29 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:48 PM PDT 24
Peak memory 209360 kb
Host smart-40a8cfb5-849a-4bff-ab17-5bf0280e7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719315492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2719315492
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.734667090
Short name T880
Test name
Test status
Simulation time 122215608 ps
CPU time 2.58 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 214344 kb
Host smart-b678f687-e396-475f-b098-b9bdde2dd7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734667090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.734667090
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2698080021
Short name T487
Test name
Test status
Simulation time 794997887 ps
CPU time 5.45 seconds
Started May 16 03:16:31 PM PDT 24
Finished May 16 03:16:43 PM PDT 24
Peak memory 222524 kb
Host smart-9f03c0ec-8522-4e6a-b7b7-3bfb3cd8ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698080021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2698080021
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2191590526
Short name T400
Test name
Test status
Simulation time 381786489 ps
CPU time 5.22 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:46 PM PDT 24
Peak memory 206836 kb
Host smart-852be593-0cbd-4983-88ed-b7efd815238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191590526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2191590526
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.264054611
Short name T383
Test name
Test status
Simulation time 38700687 ps
CPU time 2.51 seconds
Started May 16 03:16:35 PM PDT 24
Finished May 16 03:16:43 PM PDT 24
Peak memory 207308 kb
Host smart-d8fee90e-10ae-44b2-8606-93daa19d2247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264054611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.264054611
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2635113423
Short name T109
Test name
Test status
Simulation time 1246782580 ps
CPU time 3.52 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:42 PM PDT 24
Peak memory 207688 kb
Host smart-a6c291e3-0e67-40ac-9570-1894ebb992cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635113423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2635113423
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.774719432
Short name T866
Test name
Test status
Simulation time 65836958 ps
CPU time 2.46 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:42 PM PDT 24
Peak memory 206800 kb
Host smart-21bd8f29-c385-42e9-b44c-5be4ea02db48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774719432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.774719432
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3608872924
Short name T185
Test name
Test status
Simulation time 59227515 ps
CPU time 2.53 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:42 PM PDT 24
Peak memory 208360 kb
Host smart-90ff360f-8587-40ab-8ec5-952fa9b183c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608872924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3608872924
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2588387673
Short name T704
Test name
Test status
Simulation time 1161474427 ps
CPU time 3.1 seconds
Started May 16 03:16:37 PM PDT 24
Finished May 16 03:16:46 PM PDT 24
Peak memory 206860 kb
Host smart-8f547db3-b3d7-4930-b160-2471cfe911ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588387673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2588387673
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1559582308
Short name T420
Test name
Test status
Simulation time 5241911508 ps
CPU time 130.23 seconds
Started May 16 03:16:40 PM PDT 24
Finished May 16 03:18:55 PM PDT 24
Peak memory 215660 kb
Host smart-803fd650-21db-4054-b0a6-fdfc2d4d5763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559582308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1559582308
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2223264667
Short name T124
Test name
Test status
Simulation time 2189522349 ps
CPU time 25.75 seconds
Started May 16 03:16:47 PM PDT 24
Finished May 16 03:17:15 PM PDT 24
Peak memory 222648 kb
Host smart-dfbeecf9-8c47-478e-afdf-de73efedd7b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223264667 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2223264667
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1481862494
Short name T687
Test name
Test status
Simulation time 465637049 ps
CPU time 5.34 seconds
Started May 16 03:16:33 PM PDT 24
Finished May 16 03:16:44 PM PDT 24
Peak memory 209920 kb
Host smart-8dc6892a-4ee7-4e19-a34d-989d5fb98dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481862494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1481862494
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3910218440
Short name T885
Test name
Test status
Simulation time 164784720 ps
CPU time 1.29 seconds
Started May 16 03:16:32 PM PDT 24
Finished May 16 03:16:40 PM PDT 24
Peak memory 209836 kb
Host smart-220affd5-088b-4391-8a57-00558f48f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910218440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3910218440
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1934210364
Short name T607
Test name
Test status
Simulation time 39369242 ps
CPU time 0.82 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:47 PM PDT 24
Peak memory 206000 kb
Host smart-5e13b5f3-e679-4e9b-b5e7-ffab8686fc4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934210364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1934210364
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2080611721
Short name T402
Test name
Test status
Simulation time 45844054 ps
CPU time 3.41 seconds
Started May 16 03:16:43 PM PDT 24
Finished May 16 03:16:50 PM PDT 24
Peak memory 214392 kb
Host smart-80b5196a-fd54-457d-8239-692f468eb4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080611721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2080611721
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2523032818
Short name T509
Test name
Test status
Simulation time 56008640 ps
CPU time 2.52 seconds
Started May 16 03:16:47 PM PDT 24
Finished May 16 03:16:52 PM PDT 24
Peak memory 214672 kb
Host smart-7c3edf18-c1de-49da-95b9-09ee13448b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523032818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2523032818
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2411047131
Short name T296
Test name
Test status
Simulation time 103647817 ps
CPU time 3.43 seconds
Started May 16 03:16:40 PM PDT 24
Finished May 16 03:16:48 PM PDT 24
Peak memory 214420 kb
Host smart-489c513c-7adb-4481-8c61-55d3776f5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411047131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2411047131
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2219658771
Short name T255
Test name
Test status
Simulation time 180976410 ps
CPU time 4.82 seconds
Started May 16 03:16:39 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 222436 kb
Host smart-119cfa40-b112-4932-b6bb-9d9072e96507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219658771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2219658771
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2360281926
Short name T62
Test name
Test status
Simulation time 52795368 ps
CPU time 4.03 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:50 PM PDT 24
Peak memory 209080 kb
Host smart-9f033b84-df4d-4932-a136-adc90425ac47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360281926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2360281926
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3841759188
Short name T307
Test name
Test status
Simulation time 418873266 ps
CPU time 6.02 seconds
Started May 16 03:16:39 PM PDT 24
Finished May 16 03:16:50 PM PDT 24
Peak memory 208800 kb
Host smart-a5a58db4-10b8-448f-9155-beb87870fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841759188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3841759188
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2672392299
Short name T844
Test name
Test status
Simulation time 81270288 ps
CPU time 3.71 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 208548 kb
Host smart-934d81b1-6d8e-4961-852d-308ad52b90b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672392299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2672392299
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1094803244
Short name T697
Test name
Test status
Simulation time 145341400 ps
CPU time 3.02 seconds
Started May 16 03:16:44 PM PDT 24
Finished May 16 03:16:50 PM PDT 24
Peak memory 209000 kb
Host smart-fe9324b7-24e8-4849-9389-839dabc91d04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094803244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1094803244
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.422427504
Short name T825
Test name
Test status
Simulation time 148017969 ps
CPU time 5.39 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:51 PM PDT 24
Peak memory 207888 kb
Host smart-40350677-5dc3-4c49-bf59-1d9de119f29f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422427504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.422427504
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.693488319
Short name T322
Test name
Test status
Simulation time 189091788 ps
CPU time 4.21 seconds
Started May 16 03:16:43 PM PDT 24
Finished May 16 03:16:51 PM PDT 24
Peak memory 216232 kb
Host smart-6a7d6912-ff74-42db-8dd3-1de595e183b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693488319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.693488319
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3184518197
Short name T780
Test name
Test status
Simulation time 1674435726 ps
CPU time 3.25 seconds
Started May 16 03:16:42 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 208400 kb
Host smart-45aaa447-fe7f-437b-af2f-158445d29a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184518197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3184518197
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.127887787
Short name T920
Test name
Test status
Simulation time 942870893 ps
CPU time 9.55 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:16:55 PM PDT 24
Peak memory 214412 kb
Host smart-1dc2172f-89e8-4f05-9b82-b2ae2f5d663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127887787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.127887787
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1899703622
Short name T61
Test name
Test status
Simulation time 283355128 ps
CPU time 5.08 seconds
Started May 16 03:16:39 PM PDT 24
Finished May 16 03:16:49 PM PDT 24
Peak memory 209980 kb
Host smart-1ef109e0-b7cb-4030-b61a-f8608b34389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899703622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1899703622
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2047300282
Short name T748
Test name
Test status
Simulation time 49492141 ps
CPU time 0.82 seconds
Started May 16 03:16:50 PM PDT 24
Finished May 16 03:16:56 PM PDT 24
Peak memory 205980 kb
Host smart-d26c80e0-5323-454b-b1a8-79dbb06adb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047300282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2047300282
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1210554238
Short name T586
Test name
Test status
Simulation time 158969511 ps
CPU time 2.35 seconds
Started May 16 03:16:48 PM PDT 24
Finished May 16 03:16:55 PM PDT 24
Peak memory 214356 kb
Host smart-358f60e2-da2a-4615-a618-789f99d76655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210554238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1210554238
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2817524742
Short name T570
Test name
Test status
Simulation time 318340404 ps
CPU time 9.15 seconds
Started May 16 03:16:48 PM PDT 24
Finished May 16 03:17:01 PM PDT 24
Peak memory 208308 kb
Host smart-562481b1-54c2-4c79-91f7-29a6bf8709ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817524742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2817524742
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.281267937
Short name T613
Test name
Test status
Simulation time 145820142 ps
CPU time 2.82 seconds
Started May 16 03:16:48 PM PDT 24
Finished May 16 03:16:54 PM PDT 24
Peak memory 214368 kb
Host smart-85b1f896-e2fc-4f4a-8e8b-54fbba2ba991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281267937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.281267937
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.621922745
Short name T858
Test name
Test status
Simulation time 131769126 ps
CPU time 2.37 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:16:56 PM PDT 24
Peak memory 214336 kb
Host smart-57178ba1-663c-423a-9d11-3d204c4eb54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621922745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.621922745
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_random.4174202762
Short name T691
Test name
Test status
Simulation time 285775501 ps
CPU time 3.58 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:16:57 PM PDT 24
Peak memory 207520 kb
Host smart-19e1ff9e-2719-47c5-9ce7-554d7829a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174202762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4174202762
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2542166281
Short name T539
Test name
Test status
Simulation time 441188746 ps
CPU time 5.52 seconds
Started May 16 03:16:40 PM PDT 24
Finished May 16 03:16:51 PM PDT 24
Peak memory 206936 kb
Host smart-4c1eccde-d5f5-400d-8a47-fbf0860978ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542166281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2542166281
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3524962732
Short name T881
Test name
Test status
Simulation time 2209314353 ps
CPU time 24.15 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:17:18 PM PDT 24
Peak memory 208512 kb
Host smart-e8c4ac3f-7237-4964-99f4-56987b980718
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524962732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3524962732
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1240839636
Short name T529
Test name
Test status
Simulation time 1929497822 ps
CPU time 43.46 seconds
Started May 16 03:16:41 PM PDT 24
Finished May 16 03:17:29 PM PDT 24
Peak memory 208200 kb
Host smart-4065ad8d-e3d0-4a57-be14-1a7171f0b208
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240839636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1240839636
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1357575995
Short name T741
Test name
Test status
Simulation time 380974738 ps
CPU time 6.45 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:17:00 PM PDT 24
Peak memory 208252 kb
Host smart-33878953-9cf0-495c-bd5b-7bd56d3b5d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357575995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1357575995
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3967071619
Short name T79
Test name
Test status
Simulation time 7463497639 ps
CPU time 39.54 seconds
Started May 16 03:16:44 PM PDT 24
Finished May 16 03:17:27 PM PDT 24
Peak memory 208408 kb
Host smart-5aa32905-4134-49aa-b577-1b9bc8e1a497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967071619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3967071619
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1425990105
Short name T38
Test name
Test status
Simulation time 173290961 ps
CPU time 6.91 seconds
Started May 16 03:16:50 PM PDT 24
Finished May 16 03:17:01 PM PDT 24
Peak memory 209228 kb
Host smart-61cb1a4f-b03f-43db-946a-b8df531ae013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425990105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1425990105
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.853781059
Short name T36
Test name
Test status
Simulation time 43587938 ps
CPU time 2.2 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:16:56 PM PDT 24
Peak memory 210292 kb
Host smart-35fcf5bb-873a-4f90-97db-c05699fc5667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853781059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.853781059
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.360882879
Short name T664
Test name
Test status
Simulation time 32055139 ps
CPU time 0.77 seconds
Started May 16 03:13:38 PM PDT 24
Finished May 16 03:13:43 PM PDT 24
Peak memory 205908 kb
Host smart-bbf3aeba-ef33-41f7-a030-cbca35f3800f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360882879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.360882879
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.559860999
Short name T40
Test name
Test status
Simulation time 851667444 ps
CPU time 4.62 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:39 PM PDT 24
Peak memory 209196 kb
Host smart-1591596f-7200-40fd-82db-e76b20617524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559860999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.559860999
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1040888401
Short name T506
Test name
Test status
Simulation time 263469731 ps
CPU time 10.02 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:44 PM PDT 24
Peak memory 210488 kb
Host smart-189dce1d-4366-497d-b7ae-9c22f039d047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040888401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1040888401
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1473313424
Short name T89
Test name
Test status
Simulation time 183372507 ps
CPU time 2.2 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:36 PM PDT 24
Peak memory 214384 kb
Host smart-37f809cf-8a57-43b6-bf3a-bc8742bdfe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473313424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1473313424
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1842543477
Short name T224
Test name
Test status
Simulation time 242556332 ps
CPU time 2.77 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:37 PM PDT 24
Peak memory 217220 kb
Host smart-8d7ede17-e777-432c-9948-871510c9371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842543477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1842543477
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.450858583
Short name T490
Test name
Test status
Simulation time 1083049254 ps
CPU time 2.65 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:36 PM PDT 24
Peak memory 208400 kb
Host smart-a5c14b92-2b30-4950-a7ea-e1ac1be9ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450858583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.450858583
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3621742176
Short name T909
Test name
Test status
Simulation time 748870271 ps
CPU time 6.45 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:40 PM PDT 24
Peak memory 214384 kb
Host smart-f1a57650-4897-443e-ab17-0129ee6ae99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621742176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3621742176
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4051418716
Short name T12
Test name
Test status
Simulation time 402280920 ps
CPU time 6.94 seconds
Started May 16 03:13:36 PM PDT 24
Finished May 16 03:13:48 PM PDT 24
Peak memory 237504 kb
Host smart-fc876f94-c9d1-438a-a858-0b248ae7b020
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051418716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4051418716
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1812926468
Short name T501
Test name
Test status
Simulation time 22835109 ps
CPU time 1.93 seconds
Started May 16 03:13:20 PM PDT 24
Finished May 16 03:13:27 PM PDT 24
Peak memory 206824 kb
Host smart-2a1553cc-97df-4d0f-8337-b84f2edf2e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812926468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1812926468
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1013142130
Short name T817
Test name
Test status
Simulation time 184941863 ps
CPU time 3.05 seconds
Started May 16 03:13:29 PM PDT 24
Finished May 16 03:13:38 PM PDT 24
Peak memory 206872 kb
Host smart-6cf9e62c-e019-47ce-b532-7683c1436595
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013142130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1013142130
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3322488345
Short name T467
Test name
Test status
Simulation time 180571766 ps
CPU time 2.67 seconds
Started May 16 03:13:19 PM PDT 24
Finished May 16 03:13:26 PM PDT 24
Peak memory 206816 kb
Host smart-78716c9c-8e4e-4ef9-9882-1ec248761649
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322488345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3322488345
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3201217246
Short name T620
Test name
Test status
Simulation time 333244021 ps
CPU time 2.4 seconds
Started May 16 03:13:29 PM PDT 24
Finished May 16 03:13:38 PM PDT 24
Peak memory 207080 kb
Host smart-615ceb26-78c2-4745-a78e-92e34de0e4b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201217246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3201217246
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4102039641
Short name T540
Test name
Test status
Simulation time 567757679 ps
CPU time 9.27 seconds
Started May 16 03:13:28 PM PDT 24
Finished May 16 03:13:43 PM PDT 24
Peak memory 207984 kb
Host smart-3650b92e-a3dc-425a-91e6-943a2dd2f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102039641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4102039641
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1976603125
Short name T725
Test name
Test status
Simulation time 465427665 ps
CPU time 3.75 seconds
Started May 16 03:13:22 PM PDT 24
Finished May 16 03:13:31 PM PDT 24
Peak memory 208576 kb
Host smart-7fc875ce-8fc5-46b1-8cdf-85afaf78c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976603125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1976603125
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1151402892
Short name T821
Test name
Test status
Simulation time 259932289 ps
CPU time 5.36 seconds
Started May 16 03:13:26 PM PDT 24
Finished May 16 03:13:38 PM PDT 24
Peak memory 214392 kb
Host smart-55a40c01-9432-434c-b510-81053c4717c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151402892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1151402892
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.195765062
Short name T906
Test name
Test status
Simulation time 239469015 ps
CPU time 2.91 seconds
Started May 16 03:13:29 PM PDT 24
Finished May 16 03:13:38 PM PDT 24
Peak memory 209932 kb
Host smart-cb3d0f17-8855-4e7a-98b0-d1a9c0836d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195765062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.195765062
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1926856171
Short name T616
Test name
Test status
Simulation time 19555343 ps
CPU time 0.76 seconds
Started May 16 03:17:01 PM PDT 24
Finished May 16 03:17:07 PM PDT 24
Peak memory 205984 kb
Host smart-739d019a-7073-44b3-ad26-69b795dad874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926856171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1926856171
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1494033801
Short name T896
Test name
Test status
Simulation time 88901487 ps
CPU time 3.55 seconds
Started May 16 03:17:02 PM PDT 24
Finished May 16 03:17:11 PM PDT 24
Peak memory 215724 kb
Host smart-a6dda1ec-e0ae-4a80-a6af-2c2768444405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494033801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1494033801
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3952044238
Short name T245
Test name
Test status
Simulation time 563838116 ps
CPU time 3.2 seconds
Started May 16 03:16:57 PM PDT 24
Finished May 16 03:17:06 PM PDT 24
Peak memory 221520 kb
Host smart-d10db26a-5bf4-4481-bb92-d66a8ea2d3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952044238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3952044238
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3882424624
Short name T673
Test name
Test status
Simulation time 299000085 ps
CPU time 2.99 seconds
Started May 16 03:16:57 PM PDT 24
Finished May 16 03:17:06 PM PDT 24
Peak memory 207604 kb
Host smart-a6e57c34-eae0-431a-91e8-7d2d6051705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882424624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3882424624
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2253632736
Short name T312
Test name
Test status
Simulation time 394472690 ps
CPU time 3.59 seconds
Started May 16 03:16:56 PM PDT 24
Finished May 16 03:17:05 PM PDT 24
Peak memory 214416 kb
Host smart-fa0fdd10-c67b-4963-a821-83370383ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253632736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2253632736
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.908151611
Short name T365
Test name
Test status
Simulation time 653240159 ps
CPU time 8.58 seconds
Started May 16 03:16:58 PM PDT 24
Finished May 16 03:17:12 PM PDT 24
Peak memory 222588 kb
Host smart-f9abd2c6-4b90-49ab-a4ed-243483cccf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908151611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.908151611
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.549583090
Short name T243
Test name
Test status
Simulation time 165133973 ps
CPU time 2.43 seconds
Started May 16 03:16:58 PM PDT 24
Finished May 16 03:17:06 PM PDT 24
Peak memory 214520 kb
Host smart-fb561ff1-8ee5-498a-9496-166807e7988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549583090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.549583090
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3004150869
Short name T106
Test name
Test status
Simulation time 5794567025 ps
CPU time 32.64 seconds
Started May 16 03:16:55 PM PDT 24
Finished May 16 03:17:32 PM PDT 24
Peak memory 218412 kb
Host smart-6175c84c-7584-43d1-baa5-f0bb97c7d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004150869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3004150869
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3585295212
Short name T713
Test name
Test status
Simulation time 1534435918 ps
CPU time 33.51 seconds
Started May 16 03:16:50 PM PDT 24
Finished May 16 03:17:28 PM PDT 24
Peak memory 208316 kb
Host smart-5f169b90-ff3c-4dc2-8d13-8efba58b275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585295212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3585295212
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3035243883
Short name T702
Test name
Test status
Simulation time 38811490 ps
CPU time 2.67 seconds
Started May 16 03:16:52 PM PDT 24
Finished May 16 03:16:58 PM PDT 24
Peak memory 208976 kb
Host smart-c41b616f-7d55-46cd-b816-924ffa6fdf76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035243883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3035243883
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1430577822
Short name T768
Test name
Test status
Simulation time 194257362 ps
CPU time 5.05 seconds
Started May 16 03:16:49 PM PDT 24
Finished May 16 03:16:59 PM PDT 24
Peak memory 208356 kb
Host smart-a54fcffd-6617-45b6-88c8-d1da8b10b9db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430577822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1430577822
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3206115769
Short name T524
Test name
Test status
Simulation time 47748685 ps
CPU time 2.74 seconds
Started May 16 03:16:56 PM PDT 24
Finished May 16 03:17:04 PM PDT 24
Peak memory 207024 kb
Host smart-2e419b1c-67a1-49af-8747-31d68c44c956
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206115769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3206115769
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2650085227
Short name T334
Test name
Test status
Simulation time 110298438 ps
CPU time 4.46 seconds
Started May 16 03:17:00 PM PDT 24
Finished May 16 03:17:10 PM PDT 24
Peak memory 210116 kb
Host smart-7b615d04-737c-4a33-98b9-0866da4f63b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650085227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2650085227
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3198615496
Short name T815
Test name
Test status
Simulation time 462287548 ps
CPU time 5.48 seconds
Started May 16 03:16:48 PM PDT 24
Finished May 16 03:16:57 PM PDT 24
Peak memory 208008 kb
Host smart-920bd802-9424-45e5-a950-72223cc29e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198615496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3198615496
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3842886764
Short name T823
Test name
Test status
Simulation time 2495532812 ps
CPU time 9.37 seconds
Started May 16 03:16:55 PM PDT 24
Finished May 16 03:17:08 PM PDT 24
Peak memory 216524 kb
Host smart-90ae2f85-3227-41fa-b8b1-1ce0646d8011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842886764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3842886764
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2111294402
Short name T74
Test name
Test status
Simulation time 112505847 ps
CPU time 7.34 seconds
Started May 16 03:16:56 PM PDT 24
Finished May 16 03:17:08 PM PDT 24
Peak memory 219640 kb
Host smart-6a35a341-da0f-44d3-862a-26591c928fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111294402 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2111294402
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.762571200
Short name T362
Test name
Test status
Simulation time 255104306 ps
CPU time 6.96 seconds
Started May 16 03:17:00 PM PDT 24
Finished May 16 03:17:12 PM PDT 24
Peak memory 214364 kb
Host smart-369bb615-2dad-4efb-8f96-4d0d3f2f667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762571200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.762571200
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1165512501
Short name T127
Test name
Test status
Simulation time 56965329 ps
CPU time 1.88 seconds
Started May 16 03:17:02 PM PDT 24
Finished May 16 03:17:09 PM PDT 24
Peak memory 210396 kb
Host smart-52585d62-f49a-44a7-91bd-6d6b5500b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165512501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1165512501
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.27672076
Short name T17
Test name
Test status
Simulation time 13434432 ps
CPU time 0.74 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:12 PM PDT 24
Peak memory 205976 kb
Host smart-4cd85966-cac2-47b1-9ae9-70ec12ccc52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.27672076
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3348464088
Short name T142
Test name
Test status
Simulation time 195048002 ps
CPU time 3.79 seconds
Started May 16 03:17:01 PM PDT 24
Finished May 16 03:17:10 PM PDT 24
Peak memory 215524 kb
Host smart-cb002ae4-25d1-433c-938c-ccbe74277532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348464088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3348464088
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3975137844
Short name T603
Test name
Test status
Simulation time 8410114530 ps
CPU time 28.07 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:41 PM PDT 24
Peak memory 209304 kb
Host smart-75aa32fa-d619-4215-b355-b1bce1e97125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975137844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3975137844
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.136644398
Short name T76
Test name
Test status
Simulation time 55606735 ps
CPU time 2.16 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:13 PM PDT 24
Peak memory 207908 kb
Host smart-6d603aaf-b4df-4055-b257-426b92e7345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136644398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.136644398
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2751050685
Short name T893
Test name
Test status
Simulation time 37292953 ps
CPU time 2.78 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:15 PM PDT 24
Peak memory 220792 kb
Host smart-66020c1f-cca9-43f3-aea7-977f447b5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751050685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2751050685
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1547571476
Short name T60
Test name
Test status
Simulation time 418680940 ps
CPU time 6.23 seconds
Started May 16 03:17:08 PM PDT 24
Finished May 16 03:17:20 PM PDT 24
Peak memory 220372 kb
Host smart-d7b74335-74f5-47ed-93a8-11b67748ea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547571476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1547571476
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.510100604
Short name T456
Test name
Test status
Simulation time 459555024 ps
CPU time 6.3 seconds
Started May 16 03:16:57 PM PDT 24
Finished May 16 03:17:09 PM PDT 24
Peak memory 208384 kb
Host smart-d5c497e3-db21-4a53-a5ac-372b015ae910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510100604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.510100604
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4100166224
Short name T841
Test name
Test status
Simulation time 72760261 ps
CPU time 3.14 seconds
Started May 16 03:16:59 PM PDT 24
Finished May 16 03:17:07 PM PDT 24
Peak memory 208808 kb
Host smart-fa8dee3d-8671-4f09-af3a-ed757c5c24b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100166224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4100166224
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.773968732
Short name T662
Test name
Test status
Simulation time 334429078 ps
CPU time 3.01 seconds
Started May 16 03:16:56 PM PDT 24
Finished May 16 03:17:04 PM PDT 24
Peak memory 208872 kb
Host smart-c41ecba1-e9da-4fa4-9b53-bcc2c73f88c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773968732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.773968732
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3229243614
Short name T882
Test name
Test status
Simulation time 1413561249 ps
CPU time 6.42 seconds
Started May 16 03:16:57 PM PDT 24
Finished May 16 03:17:09 PM PDT 24
Peak memory 208164 kb
Host smart-9b891118-ebcb-4338-af01-36d85ab29b2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229243614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3229243614
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.771012250
Short name T230
Test name
Test status
Simulation time 89866015 ps
CPU time 3.71 seconds
Started May 16 03:16:56 PM PDT 24
Finished May 16 03:17:05 PM PDT 24
Peak memory 209028 kb
Host smart-f8975fd9-4149-4708-adea-d67b850e9f85
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771012250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.771012250
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.475280893
Short name T592
Test name
Test status
Simulation time 585333687 ps
CPU time 6.76 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:18 PM PDT 24
Peak memory 209460 kb
Host smart-cc919671-871b-4a1c-bd62-1c895b0123a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475280893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.475280893
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1576900013
Short name T518
Test name
Test status
Simulation time 192661457 ps
CPU time 2.83 seconds
Started May 16 03:16:58 PM PDT 24
Finished May 16 03:17:06 PM PDT 24
Peak memory 207192 kb
Host smart-f4ae9018-d0ac-4d0a-9f87-0f586cf779a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576900013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1576900013
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1821618535
Short name T797
Test name
Test status
Simulation time 4686833407 ps
CPU time 28.22 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:41 PM PDT 24
Peak memory 216320 kb
Host smart-b0ed4df3-3694-49f3-82c0-7841e8160072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821618535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1821618535
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.342812002
Short name T191
Test name
Test status
Simulation time 285625526 ps
CPU time 15.39 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:27 PM PDT 24
Peak memory 222684 kb
Host smart-8138a73f-9d76-4f71-9d0f-15d05708534d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342812002 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.342812002
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1126272902
Short name T262
Test name
Test status
Simulation time 1624735851 ps
CPU time 22.17 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:35 PM PDT 24
Peak memory 214356 kb
Host smart-cd2d41ac-2a58-4227-b98f-1f3614d09f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126272902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1126272902
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1306579488
Short name T223
Test name
Test status
Simulation time 591525498 ps
CPU time 2.46 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 210280 kb
Host smart-07b43c5a-6778-4d2e-b5a1-102b8c6f81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306579488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1306579488
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1306360188
Short name T813
Test name
Test status
Simulation time 19399563 ps
CPU time 0.79 seconds
Started May 16 03:17:20 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 205976 kb
Host smart-e950445b-3011-4317-ad08-b0655248a049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306360188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1306360188
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.174699685
Short name T67
Test name
Test status
Simulation time 145713170 ps
CPU time 2.11 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:13 PM PDT 24
Peak memory 209524 kb
Host smart-0b58d133-0d1b-4920-b702-db2865cc1282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174699685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.174699685
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4007441634
Short name T491
Test name
Test status
Simulation time 1866394775 ps
CPU time 28.91 seconds
Started May 16 03:17:05 PM PDT 24
Finished May 16 03:17:40 PM PDT 24
Peak memory 209588 kb
Host smart-82c63420-8852-492b-9d6d-ec5b06ff5d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007441634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4007441634
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3749778564
Short name T46
Test name
Test status
Simulation time 236114654 ps
CPU time 4.25 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:17 PM PDT 24
Peak memory 219760 kb
Host smart-e06ec714-50e2-4157-8661-836f222f7fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749778564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3749778564
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.656580923
Short name T802
Test name
Test status
Simulation time 1376639856 ps
CPU time 9.85 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:22 PM PDT 24
Peak memory 218432 kb
Host smart-49fd567b-abf4-4d1c-ab29-b23eafb69d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656580923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.656580923
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3382827353
Short name T496
Test name
Test status
Simulation time 342574818 ps
CPU time 5.62 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:18 PM PDT 24
Peak memory 208624 kb
Host smart-b74a2079-2d57-4871-93a1-c9457eb4f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382827353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3382827353
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3630269273
Short name T771
Test name
Test status
Simulation time 2330446748 ps
CPU time 29.38 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:43 PM PDT 24
Peak memory 208604 kb
Host smart-7b181a32-c29d-4bd3-b25b-e980f16df39a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630269273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3630269273
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2909362755
Short name T877
Test name
Test status
Simulation time 97435258 ps
CPU time 2.97 seconds
Started May 16 03:17:08 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 209008 kb
Host smart-b6d81bb6-c6e8-46fa-a3da-d7c669cc7d09
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909362755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2909362755
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2077413468
Short name T517
Test name
Test status
Simulation time 67916022 ps
CPU time 2.94 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 208592 kb
Host smart-0c0df2aa-9926-41df-b69b-4736dee48186
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077413468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2077413468
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2640775001
Short name T303
Test name
Test status
Simulation time 223904193 ps
CPU time 3.04 seconds
Started May 16 03:17:07 PM PDT 24
Finished May 16 03:17:16 PM PDT 24
Peak memory 208660 kb
Host smart-77111e5c-8c4d-4d72-8479-8097c866af28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640775001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2640775001
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1679185080
Short name T751
Test name
Test status
Simulation time 36325716 ps
CPU time 2.27 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:15 PM PDT 24
Peak memory 206712 kb
Host smart-97cc8206-e673-41ea-ac84-01b65a2ebb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679185080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1679185080
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.608963846
Short name T638
Test name
Test status
Simulation time 1049875473 ps
CPU time 8.1 seconds
Started May 16 03:17:06 PM PDT 24
Finished May 16 03:17:20 PM PDT 24
Peak memory 209300 kb
Host smart-61062c5c-ddd9-45a7-8c6b-e1da53730491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608963846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.608963846
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.811329376
Short name T668
Test name
Test status
Simulation time 92002859 ps
CPU time 1.79 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 210352 kb
Host smart-54c92eb4-43a2-4b11-9c83-da54a93e0da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811329376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.811329376
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.750306693
Short name T444
Test name
Test status
Simulation time 17057212 ps
CPU time 0.79 seconds
Started May 16 03:17:20 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 206060 kb
Host smart-415e83c5-4068-49bf-85e5-851a4a928641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750306693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.750306693
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.743461877
Short name T418
Test name
Test status
Simulation time 144354965 ps
CPU time 3.2 seconds
Started May 16 03:17:17 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 214324 kb
Host smart-00ce3eb8-32ca-40ff-b104-290a6236b072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743461877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.743461877
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3654887412
Short name T25
Test name
Test status
Simulation time 283749736 ps
CPU time 8.43 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:30 PM PDT 24
Peak memory 221360 kb
Host smart-65fc1974-55fc-4b75-a31a-df6a76b8c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654887412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3654887412
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2660351781
Short name T715
Test name
Test status
Simulation time 484684971 ps
CPU time 3.42 seconds
Started May 16 03:17:17 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 218492 kb
Host smart-b766af73-5311-46f6-9a82-3c1e1aa011d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660351781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2660351781
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2358319956
Short name T86
Test name
Test status
Simulation time 37078371 ps
CPU time 2.53 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 214372 kb
Host smart-95b83b42-e7e2-4f9c-982e-18b1f634209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358319956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2358319956
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1591646829
Short name T295
Test name
Test status
Simulation time 116237433 ps
CPU time 4.06 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 214320 kb
Host smart-e0fad3ce-ab00-4183-b813-64497d19d5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591646829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1591646829
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2162495256
Short name T914
Test name
Test status
Simulation time 52815309 ps
CPU time 2.04 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 208664 kb
Host smart-db1206bf-a69d-43b6-88c2-04b1b43c7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162495256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2162495256
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1208946488
Short name T129
Test name
Test status
Simulation time 4006056258 ps
CPU time 26.79 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:49 PM PDT 24
Peak memory 214440 kb
Host smart-d65403bb-4493-4552-8048-c987a32bc393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208946488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1208946488
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3629379275
Short name T471
Test name
Test status
Simulation time 68411529 ps
CPU time 2.47 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 207444 kb
Host smart-e61a5b97-a1b1-4185-8331-f82b0456cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629379275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3629379275
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3884312302
Short name T82
Test name
Test status
Simulation time 422484374 ps
CPU time 4.98 seconds
Started May 16 03:17:17 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 209132 kb
Host smart-b9f84ecc-b10c-4072-a7a9-c3a0f70e1777
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884312302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3884312302
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1285840804
Short name T600
Test name
Test status
Simulation time 121699927 ps
CPU time 4.58 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 208568 kb
Host smart-802c075d-684a-4ec7-ae28-2196cd35a8a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285840804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1285840804
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2724690944
Short name T426
Test name
Test status
Simulation time 88592083 ps
CPU time 3.94 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 208732 kb
Host smart-28de35cf-2296-4f3c-b589-ca4242ab4dc1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724690944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2724690944
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3226262774
Short name T500
Test name
Test status
Simulation time 124785668 ps
CPU time 2.06 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 207992 kb
Host smart-a9dd175b-46c4-4f97-a230-293cb143b5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226262774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3226262774
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1905558083
Short name T525
Test name
Test status
Simulation time 57793554 ps
CPU time 2.6 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 206888 kb
Host smart-5def1650-863b-42b5-9081-990e572b0ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905558083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1905558083
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2185111879
Short name T254
Test name
Test status
Simulation time 1818619579 ps
CPU time 21.76 seconds
Started May 16 03:17:20 PM PDT 24
Finished May 16 03:17:45 PM PDT 24
Peak memory 222736 kb
Host smart-e1a6fb8b-e45c-47a9-b639-ada9587925c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185111879 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2185111879
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1205582420
Short name T868
Test name
Test status
Simulation time 548179587 ps
CPU time 6.21 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:29 PM PDT 24
Peak memory 214412 kb
Host smart-494bd1a5-3f34-4934-a713-69b64f00702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205582420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1205582420
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3580781292
Short name T165
Test name
Test status
Simulation time 229580122 ps
CPU time 2.24 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 210164 kb
Host smart-66ecdf68-ac57-4d81-b7b1-753ff425c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580781292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3580781292
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3782142902
Short name T755
Test name
Test status
Simulation time 52398192 ps
CPU time 0.74 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:38 PM PDT 24
Peak memory 205968 kb
Host smart-09493832-7d0d-4683-b9ad-cf89d0ee93dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782142902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3782142902
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.734174465
Short name T385
Test name
Test status
Simulation time 4593552728 ps
CPU time 102 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:19:05 PM PDT 24
Peak memory 222556 kb
Host smart-ae10d8d4-f00d-44f3-a92a-07e1acd0bfe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734174465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.734174465
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.690412366
Short name T394
Test name
Test status
Simulation time 880182789 ps
CPU time 2.6 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 214680 kb
Host smart-516652f0-aeea-4305-8fde-0466e50de6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690412366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.690412366
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4185453118
Short name T331
Test name
Test status
Simulation time 678010386 ps
CPU time 4.65 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:27 PM PDT 24
Peak memory 209832 kb
Host smart-eb6f243d-2173-462c-a54d-9d5c075c886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185453118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4185453118
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.372155379
Short name T22
Test name
Test status
Simulation time 416125009 ps
CPU time 8.64 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:31 PM PDT 24
Peak memory 221176 kb
Host smart-d62f58a4-c0f5-460d-bad9-19b829cdd3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372155379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.372155379
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4197977353
Short name T910
Test name
Test status
Simulation time 80365965 ps
CPU time 2.01 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 217140 kb
Host smart-b5541e32-28cc-4c9e-b23d-3631c45eeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197977353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4197977353
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.302416176
Short name T527
Test name
Test status
Simulation time 316324693 ps
CPU time 3.07 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:25 PM PDT 24
Peak memory 214356 kb
Host smart-921a7b09-c3be-403e-9c8e-065a0c01956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302416176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.302416176
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3065037120
Short name T663
Test name
Test status
Simulation time 3171455418 ps
CPU time 10.85 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:32 PM PDT 24
Peak memory 214396 kb
Host smart-a6110c4f-2418-4a15-adf3-b0c6d27c3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065037120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3065037120
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1158595899
Short name T545
Test name
Test status
Simulation time 243911669 ps
CPU time 5.9 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:28 PM PDT 24
Peak memory 208636 kb
Host smart-4a9e6e18-f515-4cd7-b65e-b837547e287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158595899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1158595899
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1675707443
Short name T359
Test name
Test status
Simulation time 117307637 ps
CPU time 3.22 seconds
Started May 16 03:17:23 PM PDT 24
Finished May 16 03:17:29 PM PDT 24
Peak memory 207032 kb
Host smart-e92717a4-75e1-4f0b-a7f7-7bb0bad408eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675707443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1675707443
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4163338469
Short name T602
Test name
Test status
Simulation time 3845112311 ps
CPU time 36.89 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:18:00 PM PDT 24
Peak memory 208500 kb
Host smart-e6e44fcd-d55e-475d-b0db-6c115f9481e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163338469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4163338469
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2173847502
Short name T494
Test name
Test status
Simulation time 5149343126 ps
CPU time 38.01 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:18:01 PM PDT 24
Peak memory 208244 kb
Host smart-ecf3175f-c7b1-4beb-916f-149438d68032
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173847502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2173847502
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4172542252
Short name T353
Test name
Test status
Simulation time 459485815 ps
CPU time 3.62 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 209596 kb
Host smart-eb5d243d-fad7-49d9-b550-1b7f658d287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172542252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4172542252
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.40341781
Short name T190
Test name
Test status
Simulation time 234842826 ps
CPU time 2.68 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:26 PM PDT 24
Peak memory 208364 kb
Host smart-3c1964da-f717-4d2c-9393-9f04765f072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40341781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.40341781
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.877271734
Short name T746
Test name
Test status
Simulation time 794764306 ps
CPU time 4.33 seconds
Started May 16 03:17:19 PM PDT 24
Finished May 16 03:17:27 PM PDT 24
Peak memory 208408 kb
Host smart-140037cd-ad56-466b-b9e9-67bf5dcddb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877271734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.877271734
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1360608206
Short name T867
Test name
Test status
Simulation time 396361740 ps
CPU time 2.78 seconds
Started May 16 03:17:18 PM PDT 24
Finished May 16 03:17:24 PM PDT 24
Peak memory 210288 kb
Host smart-c2662b15-9ad3-49ed-b458-85be8046e7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360608206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1360608206
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3400541105
Short name T535
Test name
Test status
Simulation time 49026048 ps
CPU time 0.84 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 205996 kb
Host smart-0f063df2-5371-4977-8f4d-75b33e1e0630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400541105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3400541105
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1930057325
Short name T196
Test name
Test status
Simulation time 100567617 ps
CPU time 4.08 seconds
Started May 16 03:17:26 PM PDT 24
Finished May 16 03:17:35 PM PDT 24
Peak memory 214332 kb
Host smart-ef271f86-0be5-4102-95a7-3eb398f59015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930057325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1930057325
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1019884601
Short name T24
Test name
Test status
Simulation time 89158287 ps
CPU time 4.01 seconds
Started May 16 03:17:32 PM PDT 24
Finished May 16 03:17:45 PM PDT 24
Peak memory 209564 kb
Host smart-5b04d947-0750-4f7c-ad17-645fcc10a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019884601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1019884601
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3739405548
Short name T526
Test name
Test status
Simulation time 2878328519 ps
CPU time 28.64 seconds
Started May 16 03:17:30 PM PDT 24
Finished May 16 03:18:06 PM PDT 24
Peak memory 214424 kb
Host smart-d0a2c748-af9a-4f7e-a040-f52c57c61021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739405548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3739405548
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4169266549
Short name T546
Test name
Test status
Simulation time 697098458 ps
CPU time 3.32 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 214356 kb
Host smart-9c49b2e1-ddfd-4622-8f28-46c7c1b66d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169266549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4169266549
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4097243182
Short name T740
Test name
Test status
Simulation time 93419070 ps
CPU time 2.2 seconds
Started May 16 03:17:24 PM PDT 24
Finished May 16 03:17:29 PM PDT 24
Peak memory 214272 kb
Host smart-be1df58b-40f9-4e2d-a8b5-92caa68b4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097243182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4097243182
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1754510977
Short name T329
Test name
Test status
Simulation time 61197107 ps
CPU time 3.08 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 208104 kb
Host smart-d6096cb3-a7ff-4a56-a72a-5d0262a2a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754510977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1754510977
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2151780392
Short name T110
Test name
Test status
Simulation time 372320435 ps
CPU time 11.74 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:46 PM PDT 24
Peak memory 219900 kb
Host smart-a18e9758-2932-4ef9-8f82-c9d306fdee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151780392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2151780392
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3999716714
Short name T422
Test name
Test status
Simulation time 50108715 ps
CPU time 2.57 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 206748 kb
Host smart-ab9d82c3-d3ec-4ed9-bfd1-1ec5ebd90b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999716714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3999716714
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2666465498
Short name T504
Test name
Test status
Simulation time 55473522 ps
CPU time 2.31 seconds
Started May 16 03:17:24 PM PDT 24
Finished May 16 03:17:30 PM PDT 24
Peak memory 207048 kb
Host smart-95a8507a-33bb-4658-90a5-4ceb075de625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666465498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2666465498
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3071630316
Short name T468
Test name
Test status
Simulation time 465595178 ps
CPU time 7.21 seconds
Started May 16 03:17:26 PM PDT 24
Finished May 16 03:17:38 PM PDT 24
Peak memory 208344 kb
Host smart-21e1e098-52d2-4346-81a3-a86af3f45da0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071630316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3071630316
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3605206326
Short name T924
Test name
Test status
Simulation time 214915308 ps
CPU time 7.34 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:42 PM PDT 24
Peak memory 208660 kb
Host smart-297bda36-df51-449d-96d1-30980e748faa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605206326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3605206326
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2557015104
Short name T641
Test name
Test status
Simulation time 59503283 ps
CPU time 2.4 seconds
Started May 16 03:17:32 PM PDT 24
Finished May 16 03:17:44 PM PDT 24
Peak memory 208556 kb
Host smart-35044294-3901-490b-a451-824653c3c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557015104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2557015104
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1252879548
Short name T201
Test name
Test status
Simulation time 1114708798 ps
CPU time 2.66 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:36 PM PDT 24
Peak memory 206872 kb
Host smart-45b663ab-c80f-4016-8c43-3bcd354b91c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252879548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1252879548
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3396309868
Short name T204
Test name
Test status
Simulation time 491833989 ps
CPU time 19.6 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:53 PM PDT 24
Peak memory 222548 kb
Host smart-81966050-9484-477c-b347-d82361d957d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396309868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3396309868
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1192205178
Short name T658
Test name
Test status
Simulation time 1084845498 ps
CPU time 11.68 seconds
Started May 16 03:17:26 PM PDT 24
Finished May 16 03:17:44 PM PDT 24
Peak memory 222660 kb
Host smart-e854a5f8-64e6-47b6-9a49-2d26c506772d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192205178 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1192205178
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3677432690
Short name T264
Test name
Test status
Simulation time 613182081 ps
CPU time 3.36 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:40 PM PDT 24
Peak memory 208392 kb
Host smart-49957a0b-e5aa-41f5-9070-179b72205252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677432690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3677432690
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.134109934
Short name T732
Test name
Test status
Simulation time 109565140 ps
CPU time 4.07 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:40 PM PDT 24
Peak memory 210832 kb
Host smart-23e0331e-7dd0-4754-8e25-d3463e23d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134109934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.134109934
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3892649199
Short name T890
Test name
Test status
Simulation time 12697716 ps
CPU time 0.93 seconds
Started May 16 03:17:33 PM PDT 24
Finished May 16 03:17:44 PM PDT 24
Peak memory 205992 kb
Host smart-2335e6de-7f0f-4fba-961e-6701ac47e41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892649199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3892649199
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2279690222
Short name T417
Test name
Test status
Simulation time 67747477 ps
CPU time 2.5 seconds
Started May 16 03:17:31 PM PDT 24
Finished May 16 03:17:43 PM PDT 24
Peak memory 214612 kb
Host smart-817c01f4-2299-44ae-b03d-1d1d19ae326a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279690222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2279690222
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2544551788
Short name T346
Test name
Test status
Simulation time 1229228633 ps
CPU time 5.02 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:40 PM PDT 24
Peak memory 218620 kb
Host smart-b5d67c6d-734f-443e-b500-910705271101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544551788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2544551788
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2370882726
Short name T745
Test name
Test status
Simulation time 204771175 ps
CPU time 2.39 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:38 PM PDT 24
Peak memory 214408 kb
Host smart-a65e4f65-ae92-47ae-a24b-b8795b5e77c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370882726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2370882726
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2143176367
Short name T333
Test name
Test status
Simulation time 44350275 ps
CPU time 3.07 seconds
Started May 16 03:17:30 PM PDT 24
Finished May 16 03:17:42 PM PDT 24
Peak memory 220588 kb
Host smart-b9286b80-5bea-4ccd-a9fc-324cb38e1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143176367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2143176367
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4245294779
Short name T65
Test name
Test status
Simulation time 213263173 ps
CPU time 3.29 seconds
Started May 16 03:17:33 PM PDT 24
Finished May 16 03:17:47 PM PDT 24
Peak memory 208656 kb
Host smart-5fa7daea-5cc3-4c5d-8bde-1ed9e991ab94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245294779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4245294779
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.976008611
Short name T300
Test name
Test status
Simulation time 582861003 ps
CPU time 5.95 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:43 PM PDT 24
Peak memory 208180 kb
Host smart-6d062587-8d35-4fb1-9632-7ac24c6ed191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976008611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.976008611
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1913719043
Short name T290
Test name
Test status
Simulation time 184283574 ps
CPU time 3.58 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 206936 kb
Host smart-bc69bffa-45a2-4a0d-904e-20e24842e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913719043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1913719043
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.549465958
Short name T827
Test name
Test status
Simulation time 20414804 ps
CPU time 1.77 seconds
Started May 16 03:17:30 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 206792 kb
Host smart-40a736b0-51ca-4ebe-939b-4c30fed07b5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549465958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.549465958
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2984880357
Short name T388
Test name
Test status
Simulation time 243047341 ps
CPU time 3.93 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:38 PM PDT 24
Peak memory 206912 kb
Host smart-b966c69b-60a2-48fc-a6d5-da342db54811
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984880357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2984880357
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1048011394
Short name T643
Test name
Test status
Simulation time 1741848692 ps
CPU time 23.74 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 208592 kb
Host smart-3b98dbab-6dc2-47e7-a4b8-f01012fe077f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048011394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1048011394
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1507710735
Short name T485
Test name
Test status
Simulation time 161792582 ps
CPU time 2.28 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 215516 kb
Host smart-b70a9d13-24b4-4f7c-b5f1-3e32c05c4b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507710735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1507710735
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2486308694
Short name T770
Test name
Test status
Simulation time 136696638 ps
CPU time 3.22 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:36 PM PDT 24
Peak memory 208420 kb
Host smart-08402d33-6882-4655-9c70-27154eb111e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486308694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2486308694
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2423045113
Short name T372
Test name
Test status
Simulation time 6434953349 ps
CPU time 61.58 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:18:37 PM PDT 24
Peak memory 215208 kb
Host smart-a6c91058-c4be-427d-a03b-d942de64ee7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423045113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2423045113
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.468605904
Short name T764
Test name
Test status
Simulation time 363935271 ps
CPU time 4.26 seconds
Started May 16 03:17:31 PM PDT 24
Finished May 16 03:17:43 PM PDT 24
Peak memory 218396 kb
Host smart-16fe915d-f230-446e-bd95-07ff01ec4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468605904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.468605904
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3814687781
Short name T163
Test name
Test status
Simulation time 208666577 ps
CPU time 2.26 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:37 PM PDT 24
Peak memory 210004 kb
Host smart-1fca7cef-2914-4d0b-a912-f72ff3cdba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814687781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3814687781
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.858551321
Short name T790
Test name
Test status
Simulation time 50316779 ps
CPU time 0.83 seconds
Started May 16 03:17:37 PM PDT 24
Finished May 16 03:17:49 PM PDT 24
Peak memory 205988 kb
Host smart-a8a0a93b-cd6e-460f-a33f-a5d55298b396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858551321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.858551321
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2824088123
Short name T429
Test name
Test status
Simulation time 316696190 ps
CPU time 4.61 seconds
Started May 16 03:17:27 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 215780 kb
Host smart-6904c5e1-9f1f-46f2-82f5-104650791928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824088123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2824088123
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1228164883
Short name T849
Test name
Test status
Simulation time 394260075 ps
CPU time 3.3 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:41 PM PDT 24
Peak memory 214428 kb
Host smart-2b17a287-a1f4-4406-bdbd-5b7fa8c9b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228164883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1228164883
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1969441307
Short name T386
Test name
Test status
Simulation time 179314757 ps
CPU time 6.48 seconds
Started May 16 03:17:35 PM PDT 24
Finished May 16 03:17:52 PM PDT 24
Peak memory 222516 kb
Host smart-51a784be-03ae-428d-bc05-134240f6fcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969441307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1969441307
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1911306179
Short name T756
Test name
Test status
Simulation time 45674282 ps
CPU time 2.48 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:49 PM PDT 24
Peak memory 214308 kb
Host smart-fed040db-6e1c-4bff-b242-2b91cdf91a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911306179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1911306179
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3931356992
Short name T132
Test name
Test status
Simulation time 611678850 ps
CPU time 6.24 seconds
Started May 16 03:17:41 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 222424 kb
Host smart-8993cdef-3585-468f-9682-5b8d2f8b184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931356992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3931356992
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2562265702
Short name T4
Test name
Test status
Simulation time 248260770 ps
CPU time 5.62 seconds
Started May 16 03:17:32 PM PDT 24
Finished May 16 03:17:47 PM PDT 24
Peak memory 214212 kb
Host smart-593f995c-21a9-4503-9e8e-57bbf0167586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562265702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2562265702
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3277271405
Short name T462
Test name
Test status
Simulation time 127286115 ps
CPU time 3.83 seconds
Started May 16 03:17:28 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 207044 kb
Host smart-d1e735e0-ab7b-4687-8c21-36c75d8551ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277271405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3277271405
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3611225655
Short name T463
Test name
Test status
Simulation time 11565744768 ps
CPU time 54.73 seconds
Started May 16 03:17:33 PM PDT 24
Finished May 16 03:18:38 PM PDT 24
Peak memory 208328 kb
Host smart-ae8dc505-f45b-42b3-9cc7-3aba4977e08a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611225655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3611225655
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.904316958
Short name T650
Test name
Test status
Simulation time 2281294761 ps
CPU time 5.8 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:42 PM PDT 24
Peak memory 207992 kb
Host smart-7dd2ae3b-94fc-418f-954c-15f8418d581e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904316958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.904316958
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1339803781
Short name T399
Test name
Test status
Simulation time 716238244 ps
CPU time 8.14 seconds
Started May 16 03:17:31 PM PDT 24
Finished May 16 03:17:47 PM PDT 24
Peak memory 207032 kb
Host smart-65df0742-fff7-4496-9362-5157359152ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339803781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1339803781
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3673369901
Short name T584
Test name
Test status
Simulation time 93680109 ps
CPU time 2.47 seconds
Started May 16 03:17:40 PM PDT 24
Finished May 16 03:17:54 PM PDT 24
Peak memory 207560 kb
Host smart-04b58286-66cf-4f50-9533-6ccf1e42b312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673369901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3673369901
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3711680562
Short name T464
Test name
Test status
Simulation time 83897179 ps
CPU time 2.39 seconds
Started May 16 03:17:29 PM PDT 24
Finished May 16 03:17:39 PM PDT 24
Peak memory 206812 kb
Host smart-b8c7a55a-71b7-453a-9ff4-85728afbbe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711680562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3711680562
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2759193924
Short name T6
Test name
Test status
Simulation time 1040677185 ps
CPU time 7.67 seconds
Started May 16 03:17:35 PM PDT 24
Finished May 16 03:17:54 PM PDT 24
Peak memory 215512 kb
Host smart-95379964-bd3d-4ef3-940d-498682ce13c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759193924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2759193924
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.588951256
Short name T795
Test name
Test status
Simulation time 967664577 ps
CPU time 12.03 seconds
Started May 16 03:17:37 PM PDT 24
Finished May 16 03:18:00 PM PDT 24
Peak memory 220380 kb
Host smart-8e34c476-9005-4c7f-9f31-76cf2084af67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588951256 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.588951256
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2012333351
Short name T594
Test name
Test status
Simulation time 184226575 ps
CPU time 5.95 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:53 PM PDT 24
Peak memory 218556 kb
Host smart-0cb20085-5e37-41d8-ae14-1a5990954733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012333351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2012333351
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1680512839
Short name T460
Test name
Test status
Simulation time 47843764 ps
CPU time 0.83 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:57 PM PDT 24
Peak memory 205944 kb
Host smart-0ca01d6e-3dbe-414c-9c07-175a8f1054d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680512839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1680512839
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4053917712
Short name T75
Test name
Test status
Simulation time 42419543 ps
CPU time 2.24 seconds
Started May 16 03:17:40 PM PDT 24
Finished May 16 03:17:53 PM PDT 24
Peak memory 207604 kb
Host smart-e3618112-972c-4c97-acf7-aa89d6e8030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053917712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4053917712
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2034638916
Short name T100
Test name
Test status
Simulation time 171682010 ps
CPU time 6.05 seconds
Started May 16 03:17:35 PM PDT 24
Finished May 16 03:17:52 PM PDT 24
Peak memory 222436 kb
Host smart-b2aced10-4f44-4414-a8b5-5476e4c5f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034638916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2034638916
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.120460975
Short name T270
Test name
Test status
Simulation time 85688166 ps
CPU time 1.87 seconds
Started May 16 03:17:34 PM PDT 24
Finished May 16 03:17:46 PM PDT 24
Peak memory 214312 kb
Host smart-1f7c4d16-e950-41d4-82ea-08df4d6ed0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120460975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.120460975
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.615540480
Short name T206
Test name
Test status
Simulation time 337239143 ps
CPU time 3.3 seconds
Started May 16 03:17:35 PM PDT 24
Finished May 16 03:17:49 PM PDT 24
Peak memory 209604 kb
Host smart-5d46dd66-eef6-4b6e-8d22-822e94eb2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615540480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.615540480
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3761103200
Short name T629
Test name
Test status
Simulation time 1616310934 ps
CPU time 51.57 seconds
Started May 16 03:17:37 PM PDT 24
Finished May 16 03:18:39 PM PDT 24
Peak memory 214372 kb
Host smart-d4f5b7ad-3869-4590-adf3-bf136cfc3916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761103200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3761103200
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.441635924
Short name T706
Test name
Test status
Simulation time 3233021247 ps
CPU time 22.71 seconds
Started May 16 03:17:34 PM PDT 24
Finished May 16 03:18:08 PM PDT 24
Peak memory 208032 kb
Host smart-c9177f0b-b9ac-4348-80d2-d39e85e776cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441635924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.441635924
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3145536347
Short name T493
Test name
Test status
Simulation time 2289274105 ps
CPU time 44.57 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:18:31 PM PDT 24
Peak memory 208368 kb
Host smart-9a4690fe-3f41-45ac-a40c-b34a09193b0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145536347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3145536347
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1893714517
Short name T611
Test name
Test status
Simulation time 416500676 ps
CPU time 3 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:49 PM PDT 24
Peak memory 208792 kb
Host smart-6fb36924-2e1f-46e5-b503-2f59b4a85b57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893714517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1893714517
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2586707131
Short name T563
Test name
Test status
Simulation time 65380434 ps
CPU time 2.42 seconds
Started May 16 03:17:41 PM PDT 24
Finished May 16 03:17:54 PM PDT 24
Peak memory 206812 kb
Host smart-c0787100-fc93-4d6e-b4e9-6721a097fb94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586707131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2586707131
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3916457770
Short name T335
Test name
Test status
Simulation time 135677556 ps
CPU time 3.08 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:17:50 PM PDT 24
Peak memory 218448 kb
Host smart-aed6349a-7b35-4a5b-aebc-6b2d5abb7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916457770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3916457770
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1207171014
Short name T749
Test name
Test status
Simulation time 32287901 ps
CPU time 2.16 seconds
Started May 16 03:17:38 PM PDT 24
Finished May 16 03:17:52 PM PDT 24
Peak memory 206944 kb
Host smart-09b8adac-41bd-49bb-9135-f7bf4d00c2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207171014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1207171014
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1111614106
Short name T63
Test name
Test status
Simulation time 1298275863 ps
CPU time 25.58 seconds
Started May 16 03:17:36 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 217092 kb
Host smart-b9cb22c4-91ba-4ea2-9c7c-b70b2d752c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111614106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1111614106
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4163741823
Short name T327
Test name
Test status
Simulation time 976909625 ps
CPU time 5.57 seconds
Started May 16 03:17:35 PM PDT 24
Finished May 16 03:17:51 PM PDT 24
Peak memory 209556 kb
Host smart-d4f8a2c0-0a6a-4c9c-b023-4c47a7342a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163741823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4163741823
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2112643357
Short name T860
Test name
Test status
Simulation time 92165806 ps
CPU time 1.62 seconds
Started May 16 03:17:37 PM PDT 24
Finished May 16 03:17:50 PM PDT 24
Peak memory 209952 kb
Host smart-d3451c24-385c-4a08-b940-518ffabec952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112643357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2112643357
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1864542902
Short name T439
Test name
Test status
Simulation time 25314776 ps
CPU time 0.86 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:57 PM PDT 24
Peak memory 206008 kb
Host smart-9a1cd7a7-b7cf-4111-b18c-b1a06cf9a540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864542902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1864542902
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.234418867
Short name T66
Test name
Test status
Simulation time 224997921 ps
CPU time 4.01 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:18:00 PM PDT 24
Peak memory 214692 kb
Host smart-b0caf659-1cee-4f8e-afb2-9cabba12f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234418867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.234418867
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2262310387
Short name T757
Test name
Test status
Simulation time 71449038 ps
CPU time 2.47 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 214420 kb
Host smart-5ed1eb4e-092c-4cec-8fb8-b96ded3e68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262310387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2262310387
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2882612469
Short name T809
Test name
Test status
Simulation time 403706899 ps
CPU time 3.43 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 214384 kb
Host smart-585f44be-a3f9-4890-ace4-a75ae414ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882612469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2882612469
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.993956102
Short name T49
Test name
Test status
Simulation time 88344081 ps
CPU time 1.67 seconds
Started May 16 03:17:45 PM PDT 24
Finished May 16 03:17:56 PM PDT 24
Peak memory 214376 kb
Host smart-62049a9b-ef9f-4a06-af11-aa309b8da518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993956102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.993956102
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2941568840
Short name T811
Test name
Test status
Simulation time 127963685 ps
CPU time 3.47 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 209708 kb
Host smart-6711690c-1deb-48d9-bf3b-32847391fc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941568840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2941568840
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3430769254
Short name T915
Test name
Test status
Simulation time 275623102 ps
CPU time 3.59 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 214348 kb
Host smart-cb30dc1f-e721-4ff6-a5b7-67192e9109c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430769254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3430769254
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3463318354
Short name T609
Test name
Test status
Simulation time 22947381 ps
CPU time 2.12 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:57 PM PDT 24
Peak memory 208516 kb
Host smart-898b8f4a-9cfe-4dee-b26c-741a8ff1fa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463318354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3463318354
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2266112148
Short name T657
Test name
Test status
Simulation time 1080119119 ps
CPU time 20.14 seconds
Started May 16 03:17:50 PM PDT 24
Finished May 16 03:18:18 PM PDT 24
Peak memory 208488 kb
Host smart-d0440ef5-88e5-487a-b020-ffa1f2b434f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266112148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2266112148
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3273152647
Short name T237
Test name
Test status
Simulation time 343680530 ps
CPU time 4.15 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 208764 kb
Host smart-0015e122-7bdf-49e6-aba3-9ef93e7bf09f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273152647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3273152647
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1107403897
Short name T489
Test name
Test status
Simulation time 206144407 ps
CPU time 2.96 seconds
Started May 16 03:17:47 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 209080 kb
Host smart-7253e609-08a8-4230-b741-8911efc295d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107403897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1107403897
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2452602858
Short name T615
Test name
Test status
Simulation time 240559904 ps
CPU time 3.69 seconds
Started May 16 03:17:49 PM PDT 24
Finished May 16 03:18:01 PM PDT 24
Peak memory 210148 kb
Host smart-ab066543-b71b-4ca3-a258-e4416d2ac0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452602858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2452602858
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4027504751
Short name T653
Test name
Test status
Simulation time 47619742 ps
CPU time 2.42 seconds
Started May 16 03:17:45 PM PDT 24
Finished May 16 03:17:56 PM PDT 24
Peak memory 208360 kb
Host smart-ac080267-4c62-492f-b9b0-dfd82f866714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027504751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4027504751
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2025473284
Short name T580
Test name
Test status
Simulation time 659356998 ps
CPU time 16.23 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 221620 kb
Host smart-72f00d11-8d22-4839-b21a-0ee02cc925e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025473284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2025473284
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3014638168
Short name T68
Test name
Test status
Simulation time 1416455079 ps
CPU time 14.64 seconds
Started May 16 03:17:48 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 220876 kb
Host smart-05268112-04f8-4abe-911e-25d7a9383bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014638168 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3014638168
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3409349798
Short name T344
Test name
Test status
Simulation time 141442960 ps
CPU time 3.74 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 209896 kb
Host smart-6f778de9-5a98-47fe-b127-b8b0a70e3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409349798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3409349798
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2564340654
Short name T617
Test name
Test status
Simulation time 155420241 ps
CPU time 1.98 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:57 PM PDT 24
Peak memory 209952 kb
Host smart-e99150f3-f3fb-484f-a234-4910beda49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564340654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2564340654
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1207525713
Short name T855
Test name
Test status
Simulation time 22081315 ps
CPU time 0.8 seconds
Started May 16 03:13:49 PM PDT 24
Finished May 16 03:13:53 PM PDT 24
Peak memory 206008 kb
Host smart-3c954973-1c42-4769-9f2c-6e9d253939c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207525713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1207525713
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1040000773
Short name T716
Test name
Test status
Simulation time 110686723 ps
CPU time 3.91 seconds
Started May 16 03:13:38 PM PDT 24
Finished May 16 03:13:46 PM PDT 24
Peak memory 214376 kb
Host smart-cd19c2b5-6880-43fd-8940-fd906d88a247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040000773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1040000773
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2464353531
Short name T27
Test name
Test status
Simulation time 233047402 ps
CPU time 3.03 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:50 PM PDT 24
Peak memory 217328 kb
Host smart-1c153e13-1ccf-468d-9b7d-84b77430ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464353531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2464353531
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.354119154
Short name T585
Test name
Test status
Simulation time 1355660699 ps
CPU time 7.11 seconds
Started May 16 03:13:37 PM PDT 24
Finished May 16 03:13:49 PM PDT 24
Peak memory 209308 kb
Host smart-78018066-a891-4ca6-8569-5c231ba1c1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354119154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.354119154
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1018596876
Short name T391
Test name
Test status
Simulation time 120113615 ps
CPU time 2.21 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:52 PM PDT 24
Peak memory 222496 kb
Host smart-8c74c025-e08e-4ce4-a21c-b2d7503d080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018596876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1018596876
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2795699242
Short name T348
Test name
Test status
Simulation time 118986836 ps
CPU time 1.74 seconds
Started May 16 03:13:49 PM PDT 24
Finished May 16 03:13:54 PM PDT 24
Peak memory 220528 kb
Host smart-26eb1a57-fad7-42a3-a5d7-20a21b2461c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795699242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2795699242
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2992552738
Short name T408
Test name
Test status
Simulation time 325066965 ps
CPU time 2.9 seconds
Started May 16 03:13:48 PM PDT 24
Finished May 16 03:13:55 PM PDT 24
Peak memory 210396 kb
Host smart-3cb27692-53f1-46e5-97f7-780d52108293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992552738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2992552738
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4082432630
Short name T819
Test name
Test status
Simulation time 134429835 ps
CPU time 4.1 seconds
Started May 16 03:13:37 PM PDT 24
Finished May 16 03:13:46 PM PDT 24
Peak memory 214448 kb
Host smart-6676bdd9-a67a-4cee-a24c-b01a2fa1357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082432630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4082432630
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2014188606
Short name T35
Test name
Test status
Simulation time 840245221 ps
CPU time 6.98 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:55 PM PDT 24
Peak memory 230608 kb
Host smart-f7327a9b-a052-4ccb-be5b-dafcb8de4fd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014188606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2014188606
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3659346331
Short name T667
Test name
Test status
Simulation time 121640635 ps
CPU time 3.16 seconds
Started May 16 03:13:36 PM PDT 24
Finished May 16 03:13:44 PM PDT 24
Peak memory 208368 kb
Host smart-de524b5e-4466-4466-a4b4-1983f4c0b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659346331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3659346331
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2512177549
Short name T559
Test name
Test status
Simulation time 1564077285 ps
CPU time 31 seconds
Started May 16 03:13:37 PM PDT 24
Finished May 16 03:14:13 PM PDT 24
Peak memory 208428 kb
Host smart-9a9d81d1-ed72-4e07-8037-4bccd940e04a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512177549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2512177549
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3824835430
Short name T505
Test name
Test status
Simulation time 620972159 ps
CPU time 4.08 seconds
Started May 16 03:13:38 PM PDT 24
Finished May 16 03:13:46 PM PDT 24
Peak memory 206876 kb
Host smart-f73ef73b-9d2e-44a4-8713-258b692bc206
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824835430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3824835430
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4156102427
Short name T851
Test name
Test status
Simulation time 551173959 ps
CPU time 3.68 seconds
Started May 16 03:13:36 PM PDT 24
Finished May 16 03:13:44 PM PDT 24
Peak memory 208680 kb
Host smart-8ed59418-9b7d-4d20-bd8b-dbb26545e190
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156102427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4156102427
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3665812303
Short name T556
Test name
Test status
Simulation time 191266778 ps
CPU time 4.71 seconds
Started May 16 03:13:48 PM PDT 24
Finished May 16 03:13:57 PM PDT 24
Peak memory 209908 kb
Host smart-72e3377a-73dd-4316-8527-fd994a7eab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665812303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3665812303
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4127891471
Short name T766
Test name
Test status
Simulation time 220055598 ps
CPU time 5.52 seconds
Started May 16 03:13:38 PM PDT 24
Finished May 16 03:13:48 PM PDT 24
Peak memory 208024 kb
Host smart-77b3c1b0-77dd-4bf9-bed4-8d3ac5965619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127891471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4127891471
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4272996055
Short name T352
Test name
Test status
Simulation time 2224072884 ps
CPU time 30.94 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:14:20 PM PDT 24
Peak memory 216672 kb
Host smart-84473f17-4c99-42ae-b03e-b1defd86f7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272996055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4272996055
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.174111735
Short name T112
Test name
Test status
Simulation time 152494628 ps
CPU time 9.11 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:57 PM PDT 24
Peak memory 222696 kb
Host smart-2e722548-41b9-4b9e-a9ce-3949cfda2799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174111735 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.174111735
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.655790690
Short name T553
Test name
Test status
Simulation time 114817882 ps
CPU time 3.61 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:53 PM PDT 24
Peak memory 210092 kb
Host smart-863637d0-6e19-4fb6-a833-98e7438636c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655790690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.655790690
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.560458686
Short name T412
Test name
Test status
Simulation time 589299120 ps
CPU time 4.8 seconds
Started May 16 03:13:46 PM PDT 24
Finished May 16 03:13:55 PM PDT 24
Peak memory 209976 kb
Host smart-a78cca1d-aebd-4684-b302-b6b38ce51d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560458686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.560458686
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3410706887
Short name T440
Test name
Test status
Simulation time 24759055 ps
CPU time 0.89 seconds
Started May 16 03:17:56 PM PDT 24
Finished May 16 03:18:03 PM PDT 24
Peak memory 205988 kb
Host smart-2ca02795-5c63-4607-a80d-330f90776ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410706887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3410706887
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3460224377
Short name T656
Test name
Test status
Simulation time 85283830 ps
CPU time 4.07 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:05 PM PDT 24
Peak memory 209772 kb
Host smart-b73290f2-cfa2-44da-a997-22d8dbd7215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460224377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3460224377
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2419472220
Short name T690
Test name
Test status
Simulation time 338333529 ps
CPU time 3.46 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:59 PM PDT 24
Peak memory 209124 kb
Host smart-8facf815-77dd-41a2-95fd-da327e2f3861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419472220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2419472220
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1224717455
Short name T646
Test name
Test status
Simulation time 203067957 ps
CPU time 4.17 seconds
Started May 16 03:17:57 PM PDT 24
Finished May 16 03:18:07 PM PDT 24
Peak memory 220624 kb
Host smart-337f394c-1a52-4a40-b2fe-979559c82830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224717455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1224717455
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3125028246
Short name T903
Test name
Test status
Simulation time 56253069 ps
CPU time 2.9 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:09 PM PDT 24
Peak memory 215256 kb
Host smart-f0e184f8-247c-425f-a618-6e4d0092e37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125028246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3125028246
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1276485060
Short name T192
Test name
Test status
Simulation time 337509817 ps
CPU time 2.33 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:04 PM PDT 24
Peak memory 220220 kb
Host smart-b7fed2c7-a18b-4a5b-a5a4-f7fbda0897dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276485060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1276485060
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3501938436
Short name T516
Test name
Test status
Simulation time 78864201 ps
CPU time 3.4 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 207400 kb
Host smart-0877050c-64cc-4778-9d11-10e68202e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501938436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3501938436
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2864399939
Short name T551
Test name
Test status
Simulation time 2376059423 ps
CPU time 6.53 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:18:02 PM PDT 24
Peak memory 208348 kb
Host smart-254c781e-b3af-4bec-ae77-395ff76ffcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864399939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2864399939
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3104562154
Short name T599
Test name
Test status
Simulation time 685721974 ps
CPU time 4.29 seconds
Started May 16 03:17:50 PM PDT 24
Finished May 16 03:18:02 PM PDT 24
Peak memory 208708 kb
Host smart-8aa09236-6b57-4428-bb09-6e3d310c06f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104562154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3104562154
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.434115919
Short name T696
Test name
Test status
Simulation time 232537651 ps
CPU time 3.26 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 207104 kb
Host smart-e77086c9-e5c2-4224-8bd1-8051f927d0a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434115919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.434115919
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.730522456
Short name T785
Test name
Test status
Simulation time 114198763 ps
CPU time 3.04 seconds
Started May 16 03:17:46 PM PDT 24
Finished May 16 03:17:58 PM PDT 24
Peak memory 208736 kb
Host smart-c09710c4-486a-4e29-b2a1-ad67431d208d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730522456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.730522456
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2895614168
Short name T302
Test name
Test status
Simulation time 54870034 ps
CPU time 1.67 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:09 PM PDT 24
Peak memory 207596 kb
Host smart-ccec2df8-f85d-4ed5-a4dc-0d528ed79c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895614168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2895614168
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2272388079
Short name T184
Test name
Test status
Simulation time 179901117 ps
CPU time 2.23 seconds
Started May 16 03:17:45 PM PDT 24
Finished May 16 03:17:57 PM PDT 24
Peak memory 206852 kb
Host smart-dc5828c7-f65a-4cf2-b81c-d41b6a13e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272388079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2272388079
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.70778032
Short name T370
Test name
Test status
Simulation time 2789077510 ps
CPU time 27.83 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:35 PM PDT 24
Peak memory 215900 kb
Host smart-3a2f7cf8-e2c3-4739-ad3f-2ef72227fc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70778032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.70778032
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3814344340
Short name T199
Test name
Test status
Simulation time 550725807 ps
CPU time 20.89 seconds
Started May 16 03:17:54 PM PDT 24
Finished May 16 03:18:21 PM PDT 24
Peak memory 222968 kb
Host smart-90712d10-45c4-4ac0-bf32-0964a3179dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814344340 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3814344340
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3904414231
Short name T328
Test name
Test status
Simulation time 1818872898 ps
CPU time 7.39 seconds
Started May 16 03:17:56 PM PDT 24
Finished May 16 03:18:09 PM PDT 24
Peak memory 214364 kb
Host smart-d00d6399-0f74-41a0-93a8-db20a00cfee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904414231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3904414231
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2241977135
Short name T413
Test name
Test status
Simulation time 34521863 ps
CPU time 2.06 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:08 PM PDT 24
Peak memory 210312 kb
Host smart-b68b105e-65da-41a5-ba95-2b05c5edc945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241977135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2241977135
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1040528295
Short name T752
Test name
Test status
Simulation time 11200981 ps
CPU time 0.85 seconds
Started May 16 03:17:57 PM PDT 24
Finished May 16 03:18:04 PM PDT 24
Peak memory 206012 kb
Host smart-eb4a684e-56eb-4ebf-85ac-0282dfbc3c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040528295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1040528295
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3266263780
Short name T227
Test name
Test status
Simulation time 282881650 ps
CPU time 14.35 seconds
Started May 16 03:17:54 PM PDT 24
Finished May 16 03:18:15 PM PDT 24
Peak memory 214764 kb
Host smart-f2678fe4-7ac6-45da-a735-f6bf6547040a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266263780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3266263780
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3345597885
Short name T405
Test name
Test status
Simulation time 95142125 ps
CPU time 3.44 seconds
Started May 16 03:17:58 PM PDT 24
Finished May 16 03:18:06 PM PDT 24
Peak memory 218220 kb
Host smart-549cba76-6598-4447-9810-9464a762ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345597885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3345597885
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2334438532
Short name T828
Test name
Test status
Simulation time 156866834 ps
CPU time 2.85 seconds
Started May 16 03:17:57 PM PDT 24
Finished May 16 03:18:05 PM PDT 24
Peak memory 220924 kb
Host smart-3d09bd28-b763-4c8e-be5b-7a41170b11b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334438532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2334438532
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3561205395
Short name T332
Test name
Test status
Simulation time 114693824 ps
CPU time 3.41 seconds
Started May 16 03:17:56 PM PDT 24
Finished May 16 03:18:05 PM PDT 24
Peak memory 214304 kb
Host smart-5d9a09be-045a-45c2-9046-6a8bf138aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561205395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3561205395
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1862469466
Short name T543
Test name
Test status
Simulation time 212414698 ps
CPU time 4.67 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:06 PM PDT 24
Peak memory 206360 kb
Host smart-353009d8-af80-4c7e-8c3f-768f33cc6bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862469466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1862469466
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2054901498
Short name T632
Test name
Test status
Simulation time 368024909 ps
CPU time 4.37 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 207312 kb
Host smart-d325b86d-f578-43df-8910-8499fcccfc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054901498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2054901498
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.163204856
Short name T472
Test name
Test status
Simulation time 63521396 ps
CPU time 2.31 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:04 PM PDT 24
Peak memory 206852 kb
Host smart-92d314cf-6c58-4dad-b231-2fbc98a7ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163204856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.163204856
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.451841818
Short name T856
Test name
Test status
Simulation time 76135908 ps
CPU time 1.88 seconds
Started May 16 03:17:53 PM PDT 24
Finished May 16 03:18:02 PM PDT 24
Peak memory 206972 kb
Host smart-887365ed-b13d-431c-bb60-959ac94394d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451841818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.451841818
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4077795079
Short name T736
Test name
Test status
Simulation time 373610745 ps
CPU time 6.16 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:07 PM PDT 24
Peak memory 208604 kb
Host smart-81aba890-2159-42e0-bdba-1e9882e5c712
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077795079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4077795079
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2184747444
Short name T791
Test name
Test status
Simulation time 1093446727 ps
CPU time 22.12 seconds
Started May 16 03:17:54 PM PDT 24
Finished May 16 03:18:23 PM PDT 24
Peak memory 208224 kb
Host smart-fb094736-4e1b-4e32-a068-aae6e7ef5027
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184747444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2184747444
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3591335291
Short name T619
Test name
Test status
Simulation time 419743541 ps
CPU time 8.99 seconds
Started May 16 03:17:55 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 209780 kb
Host smart-a4ac80e6-1014-4dfa-a758-c9e4fea08f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591335291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3591335291
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1793891264
Short name T566
Test name
Test status
Simulation time 1911119676 ps
CPU time 19.82 seconds
Started May 16 03:17:56 PM PDT 24
Finished May 16 03:18:22 PM PDT 24
Peak memory 208464 kb
Host smart-a3af3347-d6b7-4738-8647-859c3426abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793891264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1793891264
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1185275616
Short name T728
Test name
Test status
Simulation time 372591957 ps
CPU time 10.49 seconds
Started May 16 03:17:54 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 220384 kb
Host smart-e048897e-a316-4780-bf05-a20148e3bd5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185275616 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1185275616
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.762735746
Short name T508
Test name
Test status
Simulation time 407749463 ps
CPU time 4.17 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 207556 kb
Host smart-d03520cf-4a92-4f21-b05a-6f9911e6fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762735746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.762735746
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3476479493
Short name T693
Test name
Test status
Simulation time 122077613 ps
CPU time 2.94 seconds
Started May 16 03:17:54 PM PDT 24
Finished May 16 03:18:04 PM PDT 24
Peak memory 210068 kb
Host smart-750336fb-b6e7-4200-bd66-097a6f0b4145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476479493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3476479493
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1088231613
Short name T649
Test name
Test status
Simulation time 52011980 ps
CPU time 0.88 seconds
Started May 16 03:18:06 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 205996 kb
Host smart-3e3ab0b4-c27e-483a-8583-1ca89af3407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088231613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1088231613
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.832346972
Short name T671
Test name
Test status
Simulation time 108125365 ps
CPU time 3.93 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 214904 kb
Host smart-2ee62dd3-9308-43d9-929a-513b87a6dbf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832346972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.832346972
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3559198984
Short name T873
Test name
Test status
Simulation time 126560737 ps
CPU time 2.48 seconds
Started May 16 03:18:10 PM PDT 24
Finished May 16 03:18:15 PM PDT 24
Peak memory 210576 kb
Host smart-97eb41a6-bc0f-4a2b-a31b-e258133f7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559198984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3559198984
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.458915156
Short name T47
Test name
Test status
Simulation time 888186178 ps
CPU time 4.13 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 218584 kb
Host smart-51646853-6528-4c97-b203-20a97ebb524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458915156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.458915156
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3497920601
Short name T792
Test name
Test status
Simulation time 273179577 ps
CPU time 6.05 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 220556 kb
Host smart-5a4be64e-4aa6-449f-b6f1-fa7d17b1d93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497920601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3497920601
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3206593695
Short name T727
Test name
Test status
Simulation time 58340520 ps
CPU time 3.07 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:10 PM PDT 24
Peak memory 214332 kb
Host smart-908d5626-c7d5-4c28-8fed-01126e4544fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206593695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3206593695
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2725474264
Short name T812
Test name
Test status
Simulation time 37809048 ps
CPU time 2.68 seconds
Started May 16 03:18:11 PM PDT 24
Finished May 16 03:18:16 PM PDT 24
Peak memory 209704 kb
Host smart-825dd393-315c-4ddd-b299-135842fb4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725474264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2725474264
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2592401693
Short name T660
Test name
Test status
Simulation time 2275699592 ps
CPU time 50.49 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:57 PM PDT 24
Peak memory 208600 kb
Host smart-c9b998a2-3045-44b0-897f-bcf4e7cf4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592401693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2592401693
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1601603661
Short name T210
Test name
Test status
Simulation time 31665815 ps
CPU time 2.42 seconds
Started May 16 03:17:57 PM PDT 24
Finished May 16 03:18:05 PM PDT 24
Peak memory 208720 kb
Host smart-2e0f20a2-8cb7-48da-96ba-447f1403caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601603661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1601603661
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.949868120
Short name T221
Test name
Test status
Simulation time 176782299 ps
CPU time 4.91 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 208752 kb
Host smart-ddbe1eb6-9cbb-4232-b9f9-68d03be7952d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949868120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.949868120
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.347085177
Short name T878
Test name
Test status
Simulation time 896844711 ps
CPU time 9.58 seconds
Started May 16 03:17:58 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 208896 kb
Host smart-9dbe5913-b601-455e-a16c-eeeed0533743
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347085177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.347085177
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3527075225
Short name T384
Test name
Test status
Simulation time 514257535 ps
CPU time 2.92 seconds
Started May 16 03:18:08 PM PDT 24
Finished May 16 03:18:13 PM PDT 24
Peak memory 207136 kb
Host smart-467e7589-8f91-42b6-a736-84f75091c74c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527075225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3527075225
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4016174726
Short name T371
Test name
Test status
Simulation time 745697551 ps
CPU time 2.38 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:08 PM PDT 24
Peak memory 209916 kb
Host smart-ff008575-fe52-46ed-a62e-fd202910b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016174726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4016174726
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2029767580
Short name T511
Test name
Test status
Simulation time 200943458 ps
CPU time 2.71 seconds
Started May 16 03:17:59 PM PDT 24
Finished May 16 03:18:06 PM PDT 24
Peak memory 207516 kb
Host smart-ac6ff1c5-5e60-4d64-8190-08eff9b9c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029767580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2029767580
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3836826096
Short name T337
Test name
Test status
Simulation time 467381981 ps
CPU time 15.88 seconds
Started May 16 03:18:06 PM PDT 24
Finished May 16 03:18:25 PM PDT 24
Peak memory 222568 kb
Host smart-d5985c60-db0c-4ec2-9ef7-6a15fa2232bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836826096 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3836826096
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.406596994
Short name T796
Test name
Test status
Simulation time 159758673 ps
CPU time 4.9 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 209064 kb
Host smart-110e8cd8-372d-4efe-9bfc-cc72653f4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406596994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.406596994
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3883145026
Short name T622
Test name
Test status
Simulation time 357312689 ps
CPU time 3.7 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 210152 kb
Host smart-43ff4a91-6001-4185-8568-6b0818fb562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883145026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3883145026
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3662084167
Short name T104
Test name
Test status
Simulation time 18678765 ps
CPU time 0.97 seconds
Started May 16 03:18:14 PM PDT 24
Finished May 16 03:18:17 PM PDT 24
Peak memory 206152 kb
Host smart-9e1aa274-bec0-4c40-8c24-7060845d3cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662084167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3662084167
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.736944940
Short name T416
Test name
Test status
Simulation time 63526199 ps
CPU time 4.28 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 214360 kb
Host smart-72612540-5a90-4142-9ab2-f841d60f1f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736944940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.736944940
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2641513479
Short name T591
Test name
Test status
Simulation time 105558182 ps
CPU time 3.04 seconds
Started May 16 03:18:06 PM PDT 24
Finished May 16 03:18:12 PM PDT 24
Peak memory 214740 kb
Host smart-092c7ab8-ed4d-4735-9311-25a36f4369c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641513479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2641513479
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1898153702
Short name T48
Test name
Test status
Simulation time 174590610 ps
CPU time 2.43 seconds
Started May 16 03:18:10 PM PDT 24
Finished May 16 03:18:15 PM PDT 24
Peak memory 207852 kb
Host smart-7a3a9ff7-7c90-42f1-ad85-f47a768782b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898153702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1898153702
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4224119522
Short name T719
Test name
Test status
Simulation time 294871716 ps
CPU time 3.72 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 214400 kb
Host smart-6a91a12e-8fed-4c8c-af59-c8ea7426c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224119522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4224119522
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2805915514
Short name T789
Test name
Test status
Simulation time 69161788 ps
CPU time 3.52 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 214312 kb
Host smart-0fc54e99-ba9e-4a0c-917f-b0e55293c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805915514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2805915514
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1579993577
Short name T7
Test name
Test status
Simulation time 1399658555 ps
CPU time 12.31 seconds
Started May 16 03:18:03 PM PDT 24
Finished May 16 03:18:19 PM PDT 24
Peak memory 214528 kb
Host smart-b63a8730-4b78-4296-9ae4-fc94eb58b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579993577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1579993577
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2991564266
Short name T536
Test name
Test status
Simulation time 5170119177 ps
CPU time 18.31 seconds
Started May 16 03:18:02 PM PDT 24
Finished May 16 03:18:25 PM PDT 24
Peak memory 207988 kb
Host smart-58be550b-3bc7-411a-96b1-ae4ac37b1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991564266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2991564266
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2581608681
Short name T552
Test name
Test status
Simulation time 17704055337 ps
CPU time 63.65 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:19:11 PM PDT 24
Peak memory 208200 kb
Host smart-0e61a0d9-58e7-48d8-b2de-3b5341867fb8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581608681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2581608681
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2274184140
Short name T342
Test name
Test status
Simulation time 208532734 ps
CPU time 5.66 seconds
Started May 16 03:18:06 PM PDT 24
Finished May 16 03:18:15 PM PDT 24
Peak memory 209080 kb
Host smart-06c997d7-1125-49f0-9b75-10154fa7cd47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274184140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2274184140
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1747242353
Short name T918
Test name
Test status
Simulation time 21146283 ps
CPU time 1.92 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:09 PM PDT 24
Peak memory 206888 kb
Host smart-995d401e-4533-4c4d-8cd3-575daaed3c60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747242353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1747242353
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1989253779
Short name T558
Test name
Test status
Simulation time 120284416 ps
CPU time 2.83 seconds
Started May 16 03:18:10 PM PDT 24
Finished May 16 03:18:15 PM PDT 24
Peak memory 208944 kb
Host smart-f9b62c06-3285-4d5f-b17e-e188e983578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989253779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1989253779
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.386697892
Short name T923
Test name
Test status
Simulation time 4998683704 ps
CPU time 35.57 seconds
Started May 16 03:18:07 PM PDT 24
Finished May 16 03:18:45 PM PDT 24
Peak memory 209100 kb
Host smart-3d5e5ffc-3ce8-478f-a8eb-546bd553b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386697892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.386697892
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4133181258
Short name T218
Test name
Test status
Simulation time 482467219 ps
CPU time 10.09 seconds
Started May 16 03:18:12 PM PDT 24
Finished May 16 03:18:24 PM PDT 24
Peak memory 210464 kb
Host smart-a6e4e1af-4a67-40a1-ac82-de87d502235f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133181258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4133181258
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1976982489
Short name T281
Test name
Test status
Simulation time 116293565 ps
CPU time 3.95 seconds
Started May 16 03:18:04 PM PDT 24
Finished May 16 03:18:11 PM PDT 24
Peak memory 207668 kb
Host smart-d7c7bd89-3d6b-4e18-ac06-6909b740067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976982489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1976982489
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1949725808
Short name T839
Test name
Test status
Simulation time 101206107 ps
CPU time 2.63 seconds
Started May 16 03:18:09 PM PDT 24
Finished May 16 03:18:14 PM PDT 24
Peak memory 210440 kb
Host smart-a3d296d2-36a6-4d32-af7b-049d254a89f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949725808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1949725808
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.35613870
Short name T723
Test name
Test status
Simulation time 248853066 ps
CPU time 0.88 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:27 PM PDT 24
Peak memory 205992 kb
Host smart-41db9142-e1be-43e6-bb66-28d3d158f637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.35613870
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2905142984
Short name T263
Test name
Test status
Simulation time 241947595 ps
CPU time 12.22 seconds
Started May 16 03:18:15 PM PDT 24
Finished May 16 03:18:28 PM PDT 24
Peak memory 215400 kb
Host smart-e91f322c-2d2c-4f7a-819c-526c03701b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905142984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2905142984
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1436454723
Short name T39
Test name
Test status
Simulation time 160040596 ps
CPU time 1.57 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:17 PM PDT 24
Peak memory 218240 kb
Host smart-f04e1f57-d5dc-40e1-8884-bc8c7d3943b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436454723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1436454723
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3202165980
Short name T547
Test name
Test status
Simulation time 365813570 ps
CPU time 3.5 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:18 PM PDT 24
Peak memory 214412 kb
Host smart-ddd7e8e6-1d89-4abc-8d8e-85e9e820a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202165980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3202165980
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2743839238
Short name T913
Test name
Test status
Simulation time 109842938 ps
CPU time 2.41 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:17 PM PDT 24
Peak memory 214360 kb
Host smart-29ea686b-6c47-4450-9df3-dca33bca1bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743839238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2743839238
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4174198005
Short name T595
Test name
Test status
Simulation time 73164226 ps
CPU time 3 seconds
Started May 16 03:18:15 PM PDT 24
Finished May 16 03:18:20 PM PDT 24
Peak memory 220612 kb
Host smart-4c6014ac-c49d-4b81-8a5d-9f7e1b397479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174198005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4174198005
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2687875838
Short name T200
Test name
Test status
Simulation time 353874534 ps
CPU time 3.17 seconds
Started May 16 03:18:15 PM PDT 24
Finished May 16 03:18:20 PM PDT 24
Peak memory 220716 kb
Host smart-f033ace4-4b10-423d-90d8-57e0b493d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687875838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2687875838
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3302290952
Short name T729
Test name
Test status
Simulation time 39364046 ps
CPU time 2.9 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:18 PM PDT 24
Peak memory 214496 kb
Host smart-30efe458-58cf-42a8-b428-ce97e2d92732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302290952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3302290952
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1332773936
Short name T442
Test name
Test status
Simulation time 147487660 ps
CPU time 2.33 seconds
Started May 16 03:18:14 PM PDT 24
Finished May 16 03:18:18 PM PDT 24
Peak memory 206880 kb
Host smart-3eec73b4-a722-4d70-8c4c-3720ec5cf13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332773936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1332773936
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4187652112
Short name T747
Test name
Test status
Simulation time 260473388 ps
CPU time 7.42 seconds
Started May 16 03:18:12 PM PDT 24
Finished May 16 03:18:22 PM PDT 24
Peak memory 208108 kb
Host smart-3e4e58f1-b630-4920-bebe-ce6e2ed8a970
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187652112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4187652112
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1532601626
Short name T361
Test name
Test status
Simulation time 6209237994 ps
CPU time 63.99 seconds
Started May 16 03:18:12 PM PDT 24
Finished May 16 03:19:18 PM PDT 24
Peak memory 208752 kb
Host smart-1d3936f0-dc6d-45a1-a6ae-e29b4fcb67c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532601626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1532601626
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3952298268
Short name T484
Test name
Test status
Simulation time 254060830 ps
CPU time 6.79 seconds
Started May 16 03:18:12 PM PDT 24
Finished May 16 03:18:21 PM PDT 24
Peak memory 207992 kb
Host smart-ffd73a8e-229e-493a-b145-490be5956aca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952298268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3952298268
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2258657885
Short name T275
Test name
Test status
Simulation time 21789275 ps
CPU time 1.77 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:16 PM PDT 24
Peak memory 209284 kb
Host smart-91d1257f-dcc7-49f4-a376-e436b519b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258657885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2258657885
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.4033118834
Short name T642
Test name
Test status
Simulation time 192107059 ps
CPU time 4.89 seconds
Started May 16 03:18:13 PM PDT 24
Finished May 16 03:18:20 PM PDT 24
Peak memory 208036 kb
Host smart-aa29fc3d-f6df-46bc-9054-9cc00df1cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033118834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.4033118834
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1263379649
Short name T304
Test name
Test status
Simulation time 1901546448 ps
CPU time 46.37 seconds
Started May 16 03:18:15 PM PDT 24
Finished May 16 03:19:03 PM PDT 24
Peak memory 219764 kb
Host smart-523b55f0-c086-4970-a659-5190a3c0fb8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263379649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1263379649
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1120394510
Short name T801
Test name
Test status
Simulation time 120783771 ps
CPU time 5.9 seconds
Started May 16 03:18:12 PM PDT 24
Finished May 16 03:18:20 PM PDT 24
Peak memory 209844 kb
Host smart-f78cb13e-6226-4d94-8b81-4e17b98b796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120394510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1120394510
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1832218244
Short name T411
Test name
Test status
Simulation time 224998836 ps
CPU time 1.54 seconds
Started May 16 03:18:16 PM PDT 24
Finished May 16 03:18:19 PM PDT 24
Peak memory 210128 kb
Host smart-bfd8abee-fd2c-4532-8958-ecb4b941f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832218244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1832218244
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1049341058
Short name T565
Test name
Test status
Simulation time 142913713 ps
CPU time 0.83 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:27 PM PDT 24
Peak memory 205988 kb
Host smart-5b4e4121-094a-4a1f-a1d8-69d1b265c0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049341058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1049341058
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1239216823
Short name T70
Test name
Test status
Simulation time 176804535 ps
CPU time 4.26 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:31 PM PDT 24
Peak memory 214376 kb
Host smart-14cbb61e-da9f-43df-9336-d3f33eb44809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239216823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1239216823
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.935746153
Short name T92
Test name
Test status
Simulation time 2071115306 ps
CPU time 14.78 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:41 PM PDT 24
Peak memory 220608 kb
Host smart-8dcedcde-ff03-4db9-8027-ce8b58bc5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935746153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.935746153
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2440284624
Short name T266
Test name
Test status
Simulation time 83256837 ps
CPU time 2.33 seconds
Started May 16 03:18:25 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 206284 kb
Host smart-0975a80e-309f-4f3a-9bf3-8ae9edb0fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440284624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2440284624
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4090902050
Short name T783
Test name
Test status
Simulation time 145135100 ps
CPU time 4.17 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 218496 kb
Host smart-9a201a62-2919-4cf1-9da4-a1a63fb85acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090902050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4090902050
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.452797351
Short name T907
Test name
Test status
Simulation time 473135251 ps
CPU time 4.84 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:34 PM PDT 24
Peak memory 214340 kb
Host smart-b08f1c89-f448-4ca8-9a7a-f9d5a798a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452797351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.452797351
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2850544352
Short name T387
Test name
Test status
Simulation time 292277338 ps
CPU time 2.83 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 207020 kb
Host smart-d226ec14-d73d-4c2d-aff9-235f153bc619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850544352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2850544352
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.196922822
Short name T730
Test name
Test status
Simulation time 6376625140 ps
CPU time 42.77 seconds
Started May 16 03:18:22 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 207980 kb
Host smart-f0fac4f6-5fe2-44f9-b707-4dfdf453cd99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196922822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.196922822
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.656712847
Short name T814
Test name
Test status
Simulation time 196854257 ps
CPU time 2.43 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:29 PM PDT 24
Peak memory 207096 kb
Host smart-d2d0eca0-edf0-422f-8724-c425e9922091
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656712847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.656712847
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1297376001
Short name T458
Test name
Test status
Simulation time 142697733 ps
CPU time 3.72 seconds
Started May 16 03:18:25 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 206852 kb
Host smart-1dcad218-5e78-4a1a-ba99-d59a352ac2f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297376001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1297376001
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1835616942
Short name T325
Test name
Test status
Simulation time 90046575 ps
CPU time 4.17 seconds
Started May 16 03:18:22 PM PDT 24
Finished May 16 03:18:29 PM PDT 24
Peak memory 209264 kb
Host smart-650aba3d-e032-4a0f-a25a-dbc2c159e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835616942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1835616942
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.399305321
Short name T854
Test name
Test status
Simulation time 84938282 ps
CPU time 3.33 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 208748 kb
Host smart-1d9b3b81-790d-46f5-a4e0-6304a3e23d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399305321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.399305321
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3625706064
Short name T126
Test name
Test status
Simulation time 365532652 ps
CPU time 13.15 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:39 PM PDT 24
Peak memory 222788 kb
Host smart-89559adc-df8d-4b2a-bdeb-7452df33ed61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625706064 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3625706064
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1464964216
Short name T474
Test name
Test status
Simulation time 151641664 ps
CPU time 3.04 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 207852 kb
Host smart-d68a00c2-35c8-481c-bbad-0fe59221a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464964216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1464964216
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1796838173
Short name T680
Test name
Test status
Simulation time 210508451 ps
CPU time 1.76 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:28 PM PDT 24
Peak memory 210100 kb
Host smart-f97a5647-0b29-4fa6-9e18-502ed929fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796838173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1796838173
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2612372256
Short name T581
Test name
Test status
Simulation time 19215881 ps
CPU time 0.74 seconds
Started May 16 03:18:25 PM PDT 24
Finished May 16 03:18:29 PM PDT 24
Peak memory 205992 kb
Host smart-1dc6790b-394b-4ab6-ab29-77edaa2baabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612372256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2612372256
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1427862649
Short name T850
Test name
Test status
Simulation time 144585822 ps
CPU time 8.03 seconds
Started May 16 03:18:22 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 214436 kb
Host smart-e3881380-2546-4e96-95c5-6d3c573acf75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427862649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1427862649
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.85815288
Short name T32
Test name
Test status
Simulation time 106782658 ps
CPU time 4.31 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:34 PM PDT 24
Peak memory 209488 kb
Host smart-472f259a-1194-4f58-af96-b6df7aa05bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85815288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.85815288
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4935375
Short name T666
Test name
Test status
Simulation time 46923026 ps
CPU time 2.46 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 209028 kb
Host smart-589b6bb6-20a8-4b5f-b31e-6dee15663c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4935375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4935375
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3537127031
Short name T390
Test name
Test status
Simulation time 67246747 ps
CPU time 2.9 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 214444 kb
Host smart-b5acac90-f7df-4913-abd9-b3dfe99dd14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537127031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3537127031
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1863804055
Short name T240
Test name
Test status
Simulation time 120273154 ps
CPU time 5.37 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:31 PM PDT 24
Peak memory 220516 kb
Host smart-173b4a1f-19a3-4c5a-ab9a-5121a123be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863804055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1863804055
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.571948670
Short name T377
Test name
Test status
Simulation time 265627394 ps
CPU time 4.59 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:32 PM PDT 24
Peak memory 214372 kb
Host smart-eae03a0b-6051-46d9-a22e-68643ce6e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571948670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.571948670
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1058783143
Short name T703
Test name
Test status
Simulation time 186834789 ps
CPU time 3.23 seconds
Started May 16 03:18:22 PM PDT 24
Finished May 16 03:18:26 PM PDT 24
Peak memory 208556 kb
Host smart-0cc4571c-ef17-4070-8766-3654bf785496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058783143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1058783143
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1868836636
Short name T707
Test name
Test status
Simulation time 335630537 ps
CPU time 5.53 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:35 PM PDT 24
Peak memory 208064 kb
Host smart-522d6ccf-126e-43e8-b8df-562848d85e44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868836636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1868836636
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3634570834
Short name T898
Test name
Test status
Simulation time 121618923 ps
CPU time 4.91 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:31 PM PDT 24
Peak memory 208876 kb
Host smart-1a36421e-2d9a-4211-abda-5f527defab84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634570834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3634570834
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3399039832
Short name T319
Test name
Test status
Simulation time 359579066 ps
CPU time 7.32 seconds
Started May 16 03:18:27 PM PDT 24
Finished May 16 03:18:37 PM PDT 24
Peak memory 209004 kb
Host smart-d6024435-a40b-4899-ad86-312a42866d62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399039832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3399039832
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2349641676
Short name T743
Test name
Test status
Simulation time 48447481 ps
CPU time 2.45 seconds
Started May 16 03:18:24 PM PDT 24
Finished May 16 03:18:30 PM PDT 24
Peak memory 218228 kb
Host smart-a26e5957-535f-4260-87e7-9446a99ac533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349641676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2349641676
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3319484719
Short name T428
Test name
Test status
Simulation time 228041111 ps
CPU time 5.05 seconds
Started May 16 03:18:25 PM PDT 24
Finished May 16 03:18:33 PM PDT 24
Peak memory 206728 kb
Host smart-80abb1fd-6e63-4ac5-ba8a-9a50652865a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319484719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3319484719
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1787766383
Short name T180
Test name
Test status
Simulation time 1033207705 ps
CPU time 15.65 seconds
Started May 16 03:18:25 PM PDT 24
Finished May 16 03:18:44 PM PDT 24
Peak memory 220312 kb
Host smart-cc85ca17-0204-48db-b241-c3078bdd75d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787766383 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1787766383
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3002134371
Short name T582
Test name
Test status
Simulation time 325190574 ps
CPU time 8.5 seconds
Started May 16 03:18:23 PM PDT 24
Finished May 16 03:18:34 PM PDT 24
Peak memory 214396 kb
Host smart-017644b3-de2a-42c5-ab25-3427bfce5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002134371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3002134371
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.65750826
Short name T415
Test name
Test status
Simulation time 55327517 ps
CPU time 2.16 seconds
Started May 16 03:18:26 PM PDT 24
Finished May 16 03:18:31 PM PDT 24
Peak memory 210140 kb
Host smart-84520259-a206-4f18-81c1-929e4649c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65750826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.65750826
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1697955345
Short name T672
Test name
Test status
Simulation time 19046452 ps
CPU time 1.05 seconds
Started May 16 03:18:35 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 206180 kb
Host smart-c9c35a6a-d91c-4a05-812b-6293a92d39e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697955345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1697955345
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3138281945
Short name T131
Test name
Test status
Simulation time 131257593 ps
CPU time 4.94 seconds
Started May 16 03:18:31 PM PDT 24
Finished May 16 03:18:41 PM PDT 24
Peak memory 214368 kb
Host smart-19acfd6e-913a-45d5-b521-586bd06f33b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138281945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3138281945
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1311896021
Short name T19
Test name
Test status
Simulation time 68913020 ps
CPU time 1.74 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:41 PM PDT 24
Peak memory 217688 kb
Host smart-0726a166-428b-4f95-859a-e547c3b16813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311896021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1311896021
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2302792846
Short name T777
Test name
Test status
Simulation time 54834919 ps
CPU time 3.16 seconds
Started May 16 03:18:33 PM PDT 24
Finished May 16 03:18:41 PM PDT 24
Peak memory 207520 kb
Host smart-e57d27aa-357a-4c3c-ab63-2ae3ca7a288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302792846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2302792846
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2626511889
Short name T256
Test name
Test status
Simulation time 296976804 ps
CPU time 6.13 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:45 PM PDT 24
Peak memory 219168 kb
Host smart-4a4f8c8d-0d31-48b8-a929-b0e00a85731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626511889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2626511889
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2359868647
Short name T614
Test name
Test status
Simulation time 643374682 ps
CPU time 6.33 seconds
Started May 16 03:18:33 PM PDT 24
Finished May 16 03:18:44 PM PDT 24
Peak memory 214304 kb
Host smart-8e6f3d8e-22ec-4209-9c3b-1482bef1b780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359868647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2359868647
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.744301211
Short name T618
Test name
Test status
Simulation time 511490129 ps
CPU time 5.21 seconds
Started May 16 03:18:31 PM PDT 24
Finished May 16 03:18:41 PM PDT 24
Peak memory 214484 kb
Host smart-4cadc317-0b7c-4a8e-b420-a9173559c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744301211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.744301211
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1224112553
Short name T421
Test name
Test status
Simulation time 199153601 ps
CPU time 2.61 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 206936 kb
Host smart-ff85b9e5-9607-48c5-baa0-a6d3c5c514d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224112553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1224112553
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3936735786
Short name T326
Test name
Test status
Simulation time 550904136 ps
CPU time 9.63 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:49 PM PDT 24
Peak memory 208772 kb
Host smart-e7b6af0d-661f-434b-9cd1-8cf81ea147e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936735786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3936735786
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2033784717
Short name T778
Test name
Test status
Simulation time 260124924 ps
CPU time 3.2 seconds
Started May 16 03:18:36 PM PDT 24
Finished May 16 03:18:44 PM PDT 24
Peak memory 208992 kb
Host smart-f1621362-e089-4056-b99b-3661a745cac4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033784717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2033784717
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1194165678
Short name T239
Test name
Test status
Simulation time 1460563275 ps
CPU time 3.65 seconds
Started May 16 03:18:36 PM PDT 24
Finished May 16 03:18:45 PM PDT 24
Peak memory 208676 kb
Host smart-46f865d2-9a76-4df9-a6c6-eb144340dce9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194165678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1194165678
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3067788822
Short name T341
Test name
Test status
Simulation time 184447769 ps
CPU time 3.92 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:44 PM PDT 24
Peak memory 209980 kb
Host smart-49b70154-1b94-45ea-ad60-61a2d798b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067788822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3067788822
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1542166623
Short name T555
Test name
Test status
Simulation time 2809557416 ps
CPU time 16.07 seconds
Started May 16 03:18:32 PM PDT 24
Finished May 16 03:18:53 PM PDT 24
Peak memory 208824 kb
Host smart-fb6f8faa-71b5-449f-a9d4-8c8f0a44d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542166623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1542166623
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.803664778
Short name T816
Test name
Test status
Simulation time 2173634647 ps
CPU time 7.34 seconds
Started May 16 03:18:35 PM PDT 24
Finished May 16 03:18:48 PM PDT 24
Peak memory 208416 kb
Host smart-fc1dcc65-8128-410a-aea1-8641a718aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803664778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.803664778
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1927079253
Short name T194
Test name
Test status
Simulation time 2454623367 ps
CPU time 22.38 seconds
Started May 16 03:18:32 PM PDT 24
Finished May 16 03:18:59 PM PDT 24
Peak memory 211216 kb
Host smart-1a94a01e-6d66-4ecc-8837-a931c4dca55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927079253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1927079253
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3063113895
Short name T446
Test name
Test status
Simulation time 106956267 ps
CPU time 0.66 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:46 PM PDT 24
Peak memory 206008 kb
Host smart-737da459-c5db-4df9-bd45-2d319edb08b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063113895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3063113895
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.368027067
Short name T435
Test name
Test status
Simulation time 498068241 ps
CPU time 7.57 seconds
Started May 16 03:18:35 PM PDT 24
Finished May 16 03:18:48 PM PDT 24
Peak memory 215484 kb
Host smart-b7aba240-26ad-45ab-b56f-5a3e610bd873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368027067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.368027067
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3690192101
Short name T908
Test name
Test status
Simulation time 234698275 ps
CPU time 3.5 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:51 PM PDT 24
Peak memory 210112 kb
Host smart-98e62f33-653a-492e-8bed-78261d67188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690192101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3690192101
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4154752748
Short name T476
Test name
Test status
Simulation time 620921269 ps
CPU time 17.99 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:58 PM PDT 24
Peak memory 214268 kb
Host smart-360a8c48-ee2b-405f-8958-2138a408b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154752748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4154752748
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.593270809
Short name T694
Test name
Test status
Simulation time 74153009 ps
CPU time 3.64 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:43 PM PDT 24
Peak memory 214404 kb
Host smart-cf7a65e4-1b21-43bb-ae86-b4074ed2920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593270809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.593270809
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2790233001
Short name T891
Test name
Test status
Simulation time 196020901 ps
CPU time 3.78 seconds
Started May 16 03:18:33 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 222588 kb
Host smart-e32e005e-a383-4911-9bfc-39d5a9cbaac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790233001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2790233001
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.4176564011
Short name T473
Test name
Test status
Simulation time 616920589 ps
CPU time 14.91 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:54 PM PDT 24
Peak memory 208404 kb
Host smart-c42a2414-ded2-403d-90c7-1df8b1593500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176564011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.4176564011
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1812571416
Short name T754
Test name
Test status
Simulation time 22888271 ps
CPU time 1.86 seconds
Started May 16 03:18:35 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 206792 kb
Host smart-600fd99b-c142-4c43-9ee9-7eaf2ae2b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812571416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1812571416
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4132611756
Short name T562
Test name
Test status
Simulation time 282387611 ps
CPU time 2.07 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 208672 kb
Host smart-699e5a44-0619-41d9-885c-357a22684ddb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132611756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4132611756
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2502513594
Short name T271
Test name
Test status
Simulation time 5408513664 ps
CPU time 39.63 seconds
Started May 16 03:18:36 PM PDT 24
Finished May 16 03:19:21 PM PDT 24
Peak memory 208808 kb
Host smart-3da20765-1247-4dd8-aa42-3ccae6cdf969
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502513594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2502513594
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2316825152
Short name T78
Test name
Test status
Simulation time 300808661 ps
CPU time 3.16 seconds
Started May 16 03:18:35 PM PDT 24
Finished May 16 03:18:43 PM PDT 24
Peak memory 206972 kb
Host smart-57b23544-9ee6-4a1c-9fdf-763e4f5eb942
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316825152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2316825152
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4004160103
Short name T232
Test name
Test status
Simulation time 68111769 ps
CPU time 2.42 seconds
Started May 16 03:18:34 PM PDT 24
Finished May 16 03:18:42 PM PDT 24
Peak memory 215636 kb
Host smart-82fb1253-1b01-4cf1-ac64-973413bcdb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004160103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4004160103
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3392952502
Short name T824
Test name
Test status
Simulation time 317144324 ps
CPU time 3.16 seconds
Started May 16 03:18:32 PM PDT 24
Finished May 16 03:18:39 PM PDT 24
Peak memory 208624 kb
Host smart-11a6ce13-e095-45e9-a77b-157a9b5fae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392952502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3392952502
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2760512757
Short name T847
Test name
Test status
Simulation time 481090421 ps
CPU time 8.4 seconds
Started May 16 03:18:40 PM PDT 24
Finished May 16 03:18:53 PM PDT 24
Peak memory 222688 kb
Host smart-ba86ddb2-b6ca-43f8-b5aa-837a6a527fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760512757 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2760512757
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2708660112
Short name T842
Test name
Test status
Simulation time 386959331 ps
CPU time 3.47 seconds
Started May 16 03:18:32 PM PDT 24
Finished May 16 03:18:40 PM PDT 24
Peak memory 208280 kb
Host smart-a3072b3a-a1e3-450b-9afd-93602960dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708660112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2708660112
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1282244714
Short name T626
Test name
Test status
Simulation time 81802157 ps
CPU time 3.21 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:18:53 PM PDT 24
Peak memory 210056 kb
Host smart-f207f4d7-39e4-480d-ba1d-7533492fb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282244714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1282244714
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.304323168
Short name T488
Test name
Test status
Simulation time 13249721 ps
CPU time 0.85 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:49 PM PDT 24
Peak memory 206024 kb
Host smart-949c9a5a-8c1c-4afa-865e-19fe2d08fcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304323168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.304323168
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3156852943
Short name T343
Test name
Test status
Simulation time 109712909 ps
CPU time 4.01 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:50 PM PDT 24
Peak memory 222628 kb
Host smart-e252075f-4699-4a94-90c4-1fc2eeb13ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156852943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3156852943
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3501226426
Short name T661
Test name
Test status
Simulation time 273149649 ps
CPU time 3.02 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:18:52 PM PDT 24
Peak memory 207192 kb
Host smart-48d45085-94f6-46f6-a7a9-6c262644e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501226426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3501226426
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3345180874
Short name T269
Test name
Test status
Simulation time 138710066 ps
CPU time 3.91 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:51 PM PDT 24
Peak memory 222516 kb
Host smart-5198e81d-3e53-4400-b804-2d562d015913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345180874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3345180874
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1085386906
Short name T784
Test name
Test status
Simulation time 175278190 ps
CPU time 4.39 seconds
Started May 16 03:18:40 PM PDT 24
Finished May 16 03:18:49 PM PDT 24
Peak memory 214396 kb
Host smart-250a23ba-cfd0-4551-a090-352843c6822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085386906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1085386906
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2193670940
Short name T806
Test name
Test status
Simulation time 196821315 ps
CPU time 3.49 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:18:53 PM PDT 24
Peak memory 218328 kb
Host smart-f426b8b6-a78b-4ed3-bca0-e14211768bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193670940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2193670940
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2721052516
Short name T289
Test name
Test status
Simulation time 1422369269 ps
CPU time 19.03 seconds
Started May 16 03:18:40 PM PDT 24
Finished May 16 03:19:04 PM PDT 24
Peak memory 207920 kb
Host smart-94dbf9f1-7b8c-45d7-8c6e-f4d09d83cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721052516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2721052516
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.299052123
Short name T355
Test name
Test status
Simulation time 65244165 ps
CPU time 1.95 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:48 PM PDT 24
Peak memory 207412 kb
Host smart-32a3ff54-701b-4b1b-9ab0-96726892cf4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299052123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.299052123
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2334624012
Short name T593
Test name
Test status
Simulation time 254689376 ps
CPU time 3.32 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:51 PM PDT 24
Peak memory 208772 kb
Host smart-4ca20013-dacf-4e01-bd98-5d272185e4a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334624012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2334624012
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2927501248
Short name T836
Test name
Test status
Simulation time 193979681 ps
CPU time 5.93 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:51 PM PDT 24
Peak memory 208156 kb
Host smart-beec2c68-2c34-4850-872b-9f46a550ca88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927501248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2927501248
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.367463214
Short name T578
Test name
Test status
Simulation time 43470004 ps
CPU time 1.64 seconds
Started May 16 03:18:47 PM PDT 24
Finished May 16 03:18:54 PM PDT 24
Peak memory 207600 kb
Host smart-168cf173-3ffa-4780-ada6-976e78bcc000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367463214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.367463214
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1628555466
Short name T598
Test name
Test status
Simulation time 96145669 ps
CPU time 2.55 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:49 PM PDT 24
Peak memory 206900 kb
Host smart-739a7f10-2b29-48e5-8a23-7fbeb8ddd267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628555466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1628555466
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.466024638
Short name T857
Test name
Test status
Simulation time 6027888718 ps
CPU time 57.61 seconds
Started May 16 03:18:47 PM PDT 24
Finished May 16 03:19:50 PM PDT 24
Peak memory 216056 kb
Host smart-f45a280c-8f32-4b46-8216-392a2943ecc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466024638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.466024638
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.543238227
Short name T590
Test name
Test status
Simulation time 336528890 ps
CPU time 13.23 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:19:03 PM PDT 24
Peak memory 222632 kb
Host smart-dd003657-0404-4e62-b9bb-9131691feaf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543238227 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.543238227
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2353013484
Short name T576
Test name
Test status
Simulation time 561373172 ps
CPU time 4.12 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:18:52 PM PDT 24
Peak memory 207348 kb
Host smart-7f37ab83-6baf-4979-a484-f550827aeabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353013484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2353013484
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2326287260
Short name T708
Test name
Test status
Simulation time 74521183 ps
CPU time 2.37 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:18:51 PM PDT 24
Peak memory 209796 kb
Host smart-20239bcb-d075-4923-b7cb-15e3f93ac81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326287260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2326287260
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2604012802
Short name T537
Test name
Test status
Simulation time 174899875 ps
CPU time 0.81 seconds
Started May 16 03:13:57 PM PDT 24
Finished May 16 03:14:00 PM PDT 24
Peak memory 205988 kb
Host smart-756c141f-eb75-4939-b3a9-a41d82ace99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604012802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2604012802
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2302865971
Short name T28
Test name
Test status
Simulation time 79003127 ps
CPU time 2.67 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:51 PM PDT 24
Peak memory 208660 kb
Host smart-668fb347-a0ae-4549-99a7-60354b6a4e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302865971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2302865971
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.616105701
Short name T761
Test name
Test status
Simulation time 6471738290 ps
CPU time 31.34 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:14:20 PM PDT 24
Peak memory 218228 kb
Host smart-af0cf998-71be-4598-8b55-4a571860bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616105701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.616105701
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1239398879
Short name T102
Test name
Test status
Simulation time 491231358 ps
CPU time 5.61 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:56 PM PDT 24
Peak memory 208768 kb
Host smart-fd49d8c3-017b-4081-96a3-46c560d2dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239398879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1239398879
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4172520214
Short name T368
Test name
Test status
Simulation time 127802312 ps
CPU time 2.72 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:53 PM PDT 24
Peak memory 214300 kb
Host smart-0e6f3435-31ca-4a63-86be-2f4873b22715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172520214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4172520214
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2669315620
Short name T834
Test name
Test status
Simulation time 138732300 ps
CPU time 2.46 seconds
Started May 16 03:13:46 PM PDT 24
Finished May 16 03:13:53 PM PDT 24
Peak memory 209840 kb
Host smart-8f245afb-8964-4c5c-9813-4a50aa42d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669315620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2669315620
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2296409679
Short name T207
Test name
Test status
Simulation time 360294607 ps
CPU time 6.11 seconds
Started May 16 03:13:47 PM PDT 24
Finished May 16 03:13:57 PM PDT 24
Peak memory 214460 kb
Host smart-d35a2545-7583-4b16-ad68-6cd93835d231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296409679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2296409679
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.841188732
Short name T502
Test name
Test status
Simulation time 22608770 ps
CPU time 1.83 seconds
Started May 16 03:13:48 PM PDT 24
Finished May 16 03:13:54 PM PDT 24
Peak memory 207376 kb
Host smart-1687c65c-03a8-4277-a055-85777dd7ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841188732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.841188732
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.257411829
Short name T360
Test name
Test status
Simulation time 100566486 ps
CPU time 3.25 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:51 PM PDT 24
Peak memory 206856 kb
Host smart-b66d6fb2-4d5e-4454-a1da-b57c969ddb5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257411829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.257411829
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2215776928
Short name T886
Test name
Test status
Simulation time 279783104 ps
CPU time 7.7 seconds
Started May 16 03:13:44 PM PDT 24
Finished May 16 03:13:55 PM PDT 24
Peak memory 208032 kb
Host smart-4fe4e9ad-4083-480b-91a8-3a786bd38c23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215776928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2215776928
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3152523482
Short name T301
Test name
Test status
Simulation time 1937832533 ps
CPU time 15.02 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:14:04 PM PDT 24
Peak memory 208856 kb
Host smart-fe535bf7-7f34-4044-ba77-f00245ad1401
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152523482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3152523482
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3272107815
Short name T862
Test name
Test status
Simulation time 474799778 ps
CPU time 6.35 seconds
Started May 16 03:13:43 PM PDT 24
Finished May 16 03:13:52 PM PDT 24
Peak memory 218444 kb
Host smart-192a84ab-f4da-4e84-a0f5-fa42aaa1fcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272107815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3272107815
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3591947750
Short name T596
Test name
Test status
Simulation time 33312132 ps
CPU time 2.08 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:52 PM PDT 24
Peak memory 206892 kb
Host smart-79afc938-f672-4ad5-86ae-c852b20ef361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591947750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3591947750
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1930008080
Short name T717
Test name
Test status
Simulation time 5326997815 ps
CPU time 40.5 seconds
Started May 16 03:13:58 PM PDT 24
Finished May 16 03:14:40 PM PDT 24
Peak memory 221416 kb
Host smart-20f552c0-0aa9-4b03-98ba-1dd4fc5f35da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930008080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1930008080
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4224957140
Short name T758
Test name
Test status
Simulation time 737886353 ps
CPU time 11.07 seconds
Started May 16 03:13:46 PM PDT 24
Finished May 16 03:14:01 PM PDT 24
Peak memory 214360 kb
Host smart-1c2c9a46-7dde-441d-ad37-f29e356c2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224957140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4224957140
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.409908620
Short name T905
Test name
Test status
Simulation time 45599842 ps
CPU time 2.48 seconds
Started May 16 03:13:45 PM PDT 24
Finished May 16 03:13:52 PM PDT 24
Peak memory 209860 kb
Host smart-100a3d64-e977-4e73-a450-35c37a53e336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409908620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.409908620
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.206073672
Short name T448
Test name
Test status
Simulation time 17321827 ps
CPU time 0.71 seconds
Started May 16 03:14:13 PM PDT 24
Finished May 16 03:14:15 PM PDT 24
Peak memory 206000 kb
Host smart-c1b8417b-d15e-4a8e-ac6d-75bb20b112ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206073672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.206073672
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.754790066
Short name T431
Test name
Test status
Simulation time 34334720 ps
CPU time 2.75 seconds
Started May 16 03:14:00 PM PDT 24
Finished May 16 03:14:05 PM PDT 24
Peak memory 214788 kb
Host smart-5c6d4fd6-21a7-4bbe-8df2-56c353610296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754790066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.754790066
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.392997616
Short name T560
Test name
Test status
Simulation time 1598150198 ps
CPU time 6.44 seconds
Started May 16 03:13:59 PM PDT 24
Finished May 16 03:14:07 PM PDT 24
Peak memory 210484 kb
Host smart-99f10347-a63a-4d4d-84a6-70d0e2e61faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392997616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.392997616
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.31513577
Short name T569
Test name
Test status
Simulation time 105953452 ps
CPU time 2.03 seconds
Started May 16 03:14:02 PM PDT 24
Finished May 16 03:14:06 PM PDT 24
Peak memory 207500 kb
Host smart-1712f219-2256-49ee-ba50-880e370a71a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31513577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.31513577
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2301296529
Short name T895
Test name
Test status
Simulation time 125876793 ps
CPU time 6.03 seconds
Started May 16 03:14:01 PM PDT 24
Finished May 16 03:14:09 PM PDT 24
Peak memory 220716 kb
Host smart-0accdae7-42f5-4620-b298-67caf62877f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301296529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2301296529
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.628911160
Short name T51
Test name
Test status
Simulation time 92219219 ps
CPU time 2.24 seconds
Started May 16 03:14:00 PM PDT 24
Finished May 16 03:14:04 PM PDT 24
Peak memory 214272 kb
Host smart-264d276a-712f-4ed8-9862-1e102cbc9e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628911160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.628911160
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.657367035
Short name T252
Test name
Test status
Simulation time 374595317 ps
CPU time 5.03 seconds
Started May 16 03:14:02 PM PDT 24
Finished May 16 03:14:09 PM PDT 24
Peak memory 210148 kb
Host smart-e7c331a1-91bc-44cc-9548-c302a626ae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657367035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.657367035
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2997869061
Short name T235
Test name
Test status
Simulation time 87122284 ps
CPU time 4.35 seconds
Started May 16 03:14:01 PM PDT 24
Finished May 16 03:14:08 PM PDT 24
Peak memory 208216 kb
Host smart-f9e02698-c4d1-4a52-be9a-1ecae791ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997869061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2997869061
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2525587021
Short name T495
Test name
Test status
Simulation time 289172247 ps
CPU time 2.82 seconds
Started May 16 03:13:53 PM PDT 24
Finished May 16 03:13:58 PM PDT 24
Peak memory 206892 kb
Host smart-74e00a47-97ba-473f-b417-bd0ac8ccdaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525587021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2525587021
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.652539875
Short name T843
Test name
Test status
Simulation time 131178420 ps
CPU time 2.37 seconds
Started May 16 03:13:53 PM PDT 24
Finished May 16 03:13:58 PM PDT 24
Peak memory 206912 kb
Host smart-b90993d9-3e55-45c8-b2df-56d4f545c421
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652539875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.652539875
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2861046713
Short name T759
Test name
Test status
Simulation time 72777409 ps
CPU time 3.39 seconds
Started May 16 03:13:52 PM PDT 24
Finished May 16 03:13:58 PM PDT 24
Peak memory 208908 kb
Host smart-e65588bb-8688-4ba6-b1ca-7a692a4999d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861046713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2861046713
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2116846427
Short name T608
Test name
Test status
Simulation time 223904916 ps
CPU time 2.92 seconds
Started May 16 03:14:02 PM PDT 24
Finished May 16 03:14:07 PM PDT 24
Peak memory 208792 kb
Host smart-69325ad8-2f7e-4aaf-9ab5-037d2cd2c4f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116846427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2116846427
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1478289083
Short name T234
Test name
Test status
Simulation time 433450953 ps
CPU time 2.8 seconds
Started May 16 03:14:02 PM PDT 24
Finished May 16 03:14:07 PM PDT 24
Peak memory 208636 kb
Host smart-1d30bc15-3131-4545-ab06-9e8969086054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478289083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1478289083
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4073281781
Short name T486
Test name
Test status
Simulation time 117488875 ps
CPU time 3.69 seconds
Started May 16 03:13:53 PM PDT 24
Finished May 16 03:13:59 PM PDT 24
Peak memory 206844 kb
Host smart-6e5177b1-4eb2-48f3-b050-06caef708bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073281781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4073281781
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.93266918
Short name T219
Test name
Test status
Simulation time 43840787017 ps
CPU time 264.53 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:18:37 PM PDT 24
Peak memory 216764 kb
Host smart-d98e3bb1-c211-4a63-9983-913eb2851ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93266918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.93266918
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2139298473
Short name T425
Test name
Test status
Simulation time 147685455 ps
CPU time 4.16 seconds
Started May 16 03:14:02 PM PDT 24
Finished May 16 03:14:08 PM PDT 24
Peak memory 207364 kb
Host smart-b34e4fbf-6d17-4b62-a2f2-9af9dad8b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139298473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2139298473
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1094951966
Short name T58
Test name
Test status
Simulation time 93588692 ps
CPU time 2.6 seconds
Started May 16 03:14:13 PM PDT 24
Finished May 16 03:14:17 PM PDT 24
Peak memory 210120 kb
Host smart-2f70661a-3d65-409e-8c22-af103a23f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094951966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1094951966
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3901273223
Short name T450
Test name
Test status
Simulation time 26965113 ps
CPU time 0.79 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:24 PM PDT 24
Peak memory 205884 kb
Host smart-1a129d50-ed1b-4374-951f-bb1799bfa7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901273223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3901273223
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2875854042
Short name T381
Test name
Test status
Simulation time 174702106 ps
CPU time 3.65 seconds
Started May 16 03:14:10 PM PDT 24
Finished May 16 03:14:16 PM PDT 24
Peak memory 215060 kb
Host smart-e949805b-4e2d-4d0e-ac82-21bc06a8ac59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875854042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2875854042
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3762778995
Short name T26
Test name
Test status
Simulation time 438455189 ps
CPU time 13.05 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:14:25 PM PDT 24
Peak memory 214688 kb
Host smart-c63ae129-e423-4782-8edd-49d982e0c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762778995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3762778995
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2333960040
Short name T469
Test name
Test status
Simulation time 45165028 ps
CPU time 1.96 seconds
Started May 16 03:14:12 PM PDT 24
Finished May 16 03:14:16 PM PDT 24
Peak memory 207728 kb
Host smart-483ff47e-2a24-4a3b-ab04-ad6999510f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333960040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2333960040
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2436016285
Short name T101
Test name
Test status
Simulation time 159733119 ps
CPU time 5.4 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:14:18 PM PDT 24
Peak memory 215048 kb
Host smart-95665985-9a1f-420d-a6c6-6a6ec6954aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436016285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2436016285
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3318947978
Short name T621
Test name
Test status
Simulation time 87708657 ps
CPU time 4.07 seconds
Started May 16 03:14:13 PM PDT 24
Finished May 16 03:14:20 PM PDT 24
Peak memory 210408 kb
Host smart-f79d4cc3-256f-4c03-b278-1bc4218efbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318947978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3318947978
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2711437265
Short name T765
Test name
Test status
Simulation time 788206814 ps
CPU time 3.86 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:14:17 PM PDT 24
Peak memory 209932 kb
Host smart-541f82c9-0a1c-48f2-988a-95ef3dbdc619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711437265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2711437265
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3657274264
Short name T375
Test name
Test status
Simulation time 4043167943 ps
CPU time 40.23 seconds
Started May 16 03:14:13 PM PDT 24
Finished May 16 03:14:55 PM PDT 24
Peak memory 220600 kb
Host smart-da4856f1-b8e4-40b2-8b8f-ab477c7d2994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657274264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3657274264
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3984804806
Short name T803
Test name
Test status
Simulation time 2337368862 ps
CPU time 16.02 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:14:29 PM PDT 24
Peak memory 207156 kb
Host smart-e02e7e39-68f0-4a23-bd25-c251136aa54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984804806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3984804806
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.333944385
Short name T753
Test name
Test status
Simulation time 1810233144 ps
CPU time 20.46 seconds
Started May 16 03:14:14 PM PDT 24
Finished May 16 03:14:37 PM PDT 24
Peak memory 208400 kb
Host smart-121188b8-d949-4290-8f32-1f6ea972996e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333944385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.333944385
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.943369152
Short name T427
Test name
Test status
Simulation time 43979047 ps
CPU time 2.63 seconds
Started May 16 03:14:11 PM PDT 24
Finished May 16 03:14:15 PM PDT 24
Peak memory 208628 kb
Host smart-3e5f56a8-3b58-4d3e-93be-222832f94469
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943369152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.943369152
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1403666620
Short name T80
Test name
Test status
Simulation time 41380965 ps
CPU time 1.85 seconds
Started May 16 03:14:10 PM PDT 24
Finished May 16 03:14:14 PM PDT 24
Peak memory 206992 kb
Host smart-afef9139-8e33-49ab-997a-2a60cd5bf70a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403666620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1403666620
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2245391262
Short name T800
Test name
Test status
Simulation time 121216168 ps
CPU time 3.27 seconds
Started May 16 03:14:14 PM PDT 24
Finished May 16 03:14:20 PM PDT 24
Peak memory 209252 kb
Host smart-6abb4c5e-35c4-42a4-b6b7-665ec2ac4b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245391262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2245391262
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1625971225
Short name T772
Test name
Test status
Simulation time 897556502 ps
CPU time 15.87 seconds
Started May 16 03:14:12 PM PDT 24
Finished May 16 03:14:30 PM PDT 24
Peak memory 208452 kb
Host smart-9ebb27d5-6df6-48ad-b62d-e30d02a12840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625971225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1625971225
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2893489919
Short name T793
Test name
Test status
Simulation time 2230312064 ps
CPU time 15.01 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:38 PM PDT 24
Peak memory 220320 kb
Host smart-3d358546-36e8-43e4-a518-3b4f827242ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893489919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2893489919
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4128620369
Short name T726
Test name
Test status
Simulation time 531735412 ps
CPU time 9.75 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:33 PM PDT 24
Peak memory 221012 kb
Host smart-ecf6f1e6-c578-43af-8cd7-0b9d564d3595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128620369 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4128620369
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.710310515
Short name T888
Test name
Test status
Simulation time 529246566 ps
CPU time 7.8 seconds
Started May 16 03:14:12 PM PDT 24
Finished May 16 03:14:22 PM PDT 24
Peak memory 208956 kb
Host smart-9426f900-994c-4f96-b5d3-78f1aa5d2de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710310515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.710310515
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2872168913
Short name T721
Test name
Test status
Simulation time 571648417 ps
CPU time 2.81 seconds
Started May 16 03:14:22 PM PDT 24
Finished May 16 03:14:27 PM PDT 24
Peak memory 210028 kb
Host smart-77bb7003-8662-49ff-99cf-f8ecc61e0666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872168913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2872168913
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2539176570
Short name T731
Test name
Test status
Simulation time 9747295 ps
CPU time 0.82 seconds
Started May 16 03:14:29 PM PDT 24
Finished May 16 03:14:31 PM PDT 24
Peak memory 205984 kb
Host smart-0eae6a42-533f-4463-bfe0-63764ecfee31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539176570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2539176570
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2414616946
Short name T437
Test name
Test status
Simulation time 61537556 ps
CPU time 4.61 seconds
Started May 16 03:14:18 PM PDT 24
Finished May 16 03:14:26 PM PDT 24
Peak memory 214420 kb
Host smart-9a542d8c-61dd-4597-8bb5-807c4c8de3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414616946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2414616946
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.519894555
Short name T393
Test name
Test status
Simulation time 874618641 ps
CPU time 5.96 seconds
Started May 16 03:14:19 PM PDT 24
Finished May 16 03:14:28 PM PDT 24
Peak memory 221652 kb
Host smart-291773e1-dbd1-4576-a72b-ac4cceb7c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519894555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.519894555
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2702619078
Short name T767
Test name
Test status
Simulation time 68686884 ps
CPU time 1.59 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:24 PM PDT 24
Peak memory 207496 kb
Host smart-bcd75f02-502c-41e5-bab7-0350c856ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702619078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2702619078
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.355233432
Short name T799
Test name
Test status
Simulation time 2958255673 ps
CPU time 20.71 seconds
Started May 16 03:14:19 PM PDT 24
Finished May 16 03:14:43 PM PDT 24
Peak memory 209864 kb
Host smart-07f28b3f-2e52-4aba-92de-1890c6ba8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355233432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.355233432
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3461475214
Short name T710
Test name
Test status
Simulation time 51649638 ps
CPU time 2.96 seconds
Started May 16 03:14:21 PM PDT 24
Finished May 16 03:14:27 PM PDT 24
Peak memory 208592 kb
Host smart-36612082-f7c8-4388-9d1e-c31b122b57ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461475214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3461475214
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2495096168
Short name T750
Test name
Test status
Simulation time 176043601 ps
CPU time 3.98 seconds
Started May 16 03:14:23 PM PDT 24
Finished May 16 03:14:29 PM PDT 24
Peak memory 208848 kb
Host smart-5c53315d-84b5-452a-b54a-b28d2c669b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495096168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2495096168
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1458415819
Short name T636
Test name
Test status
Simulation time 1863402621 ps
CPU time 7.93 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:31 PM PDT 24
Peak memory 208804 kb
Host smart-0bbf39d6-c33b-4ddc-a07b-0f684ea61a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458415819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1458415819
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.347505068
Short name T601
Test name
Test status
Simulation time 92781999 ps
CPU time 3.96 seconds
Started May 16 03:14:22 PM PDT 24
Finished May 16 03:14:29 PM PDT 24
Peak memory 209080 kb
Host smart-6f6566c1-c98b-4053-8afd-e36c5f827cb4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347505068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.347505068
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1899182229
Short name T538
Test name
Test status
Simulation time 280477652 ps
CPU time 3.47 seconds
Started May 16 03:14:19 PM PDT 24
Finished May 16 03:14:25 PM PDT 24
Peak memory 208872 kb
Host smart-821c8bf7-8704-4869-8109-19ce3de74849
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899182229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1899182229
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.775367593
Short name T899
Test name
Test status
Simulation time 51606674 ps
CPU time 2.96 seconds
Started May 16 03:14:21 PM PDT 24
Finished May 16 03:14:27 PM PDT 24
Peak memory 206992 kb
Host smart-0d5f5bfe-1663-4e99-873b-3857e884cc2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775367593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.775367593
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1224199308
Short name T286
Test name
Test status
Simulation time 5006677421 ps
CPU time 37.48 seconds
Started May 16 03:14:24 PM PDT 24
Finished May 16 03:15:03 PM PDT 24
Peak memory 214484 kb
Host smart-4981ea42-0233-4378-a7c7-da21ca00d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224199308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1224199308
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3920439007
Short name T481
Test name
Test status
Simulation time 771297434 ps
CPU time 4.48 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:28 PM PDT 24
Peak memory 206708 kb
Host smart-578be40d-2175-434b-bf1a-1416a28ce8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920439007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3920439007
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1899268406
Short name T216
Test name
Test status
Simulation time 594595038 ps
CPU time 21.09 seconds
Started May 16 03:14:24 PM PDT 24
Finished May 16 03:14:47 PM PDT 24
Peak memory 222476 kb
Host smart-e7d89a8c-3ca2-43ce-b6be-07d2fed7355c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899268406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1899268406
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.300780346
Short name T202
Test name
Test status
Simulation time 302678410 ps
CPU time 8.77 seconds
Started May 16 03:14:20 PM PDT 24
Finished May 16 03:14:32 PM PDT 24
Peak memory 214372 kb
Host smart-c62a3ee6-d6ce-4647-8727-7b6a2a5eb793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300780346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.300780346
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1929662861
Short name T171
Test name
Test status
Simulation time 5266849162 ps
CPU time 14.77 seconds
Started May 16 03:14:23 PM PDT 24
Finished May 16 03:14:40 PM PDT 24
Peak memory 211936 kb
Host smart-0700fbf4-720b-45ab-b53b-b8bea664c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929662861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1929662861
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2195917769
Short name T541
Test name
Test status
Simulation time 38396190 ps
CPU time 0.72 seconds
Started May 16 03:14:32 PM PDT 24
Finished May 16 03:14:35 PM PDT 24
Peak memory 205988 kb
Host smart-13b76279-350f-466d-b989-c23426dfa1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195917769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2195917769
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2602780971
Short name T781
Test name
Test status
Simulation time 172027885 ps
CPU time 9.83 seconds
Started May 16 03:14:31 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 214380 kb
Host smart-9ceac467-18c5-4f5b-9ce2-9a7fc2f0de40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602780971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2602780971
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1442222949
Short name T871
Test name
Test status
Simulation time 251843154 ps
CPU time 3.35 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:14:37 PM PDT 24
Peak memory 214604 kb
Host smart-a97ee44e-bef1-4c17-8ee1-5f0235d634f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442222949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1442222949
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3444828272
Short name T830
Test name
Test status
Simulation time 1909395820 ps
CPU time 33.29 seconds
Started May 16 03:14:32 PM PDT 24
Finished May 16 03:15:08 PM PDT 24
Peak memory 208676 kb
Host smart-4f5b16d1-a6bc-4232-bddb-81a2d236c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444828272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3444828272
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.87133720
Short name T267
Test name
Test status
Simulation time 125084926 ps
CPU time 2.54 seconds
Started May 16 03:14:28 PM PDT 24
Finished May 16 03:14:32 PM PDT 24
Peak memory 214372 kb
Host smart-7960007b-f5c1-4328-a5b7-25a6630dba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87133720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.87133720
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.26015436
Short name T737
Test name
Test status
Simulation time 62904321 ps
CPU time 3.06 seconds
Started May 16 03:14:29 PM PDT 24
Finished May 16 03:14:34 PM PDT 24
Peak memory 220192 kb
Host smart-ef2136fe-0460-4658-a5e4-dcfbf0cde6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26015436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.26015436
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3548525604
Short name T321
Test name
Test status
Simulation time 294181404 ps
CPU time 11.28 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:14:44 PM PDT 24
Peak memory 209288 kb
Host smart-659c6d94-0089-4312-9573-aa4992f5c1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548525604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3548525604
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2617820154
Short name T567
Test name
Test status
Simulation time 131156717 ps
CPU time 2.12 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:14:35 PM PDT 24
Peak memory 206764 kb
Host smart-74405457-2fdf-49ee-ad3b-a3243d961a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617820154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2617820154
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3871001297
Short name T298
Test name
Test status
Simulation time 1600093398 ps
CPU time 23.49 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:14:56 PM PDT 24
Peak memory 208404 kb
Host smart-2dabdea8-7415-4047-9c77-4898670252c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871001297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3871001297
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2637152877
Short name T684
Test name
Test status
Simulation time 363432206 ps
CPU time 2.9 seconds
Started May 16 03:14:28 PM PDT 24
Finished May 16 03:14:32 PM PDT 24
Peak memory 207068 kb
Host smart-32e05453-e998-47b3-86b8-f1571158fcaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637152877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2637152877
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2266421753
Short name T2
Test name
Test status
Simulation time 46920556 ps
CPU time 2.69 seconds
Started May 16 03:14:28 PM PDT 24
Finished May 16 03:14:33 PM PDT 24
Peak memory 206988 kb
Host smart-ab1ca465-e767-4839-a5ea-74db8a49664d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266421753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2266421753
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1917298993
Short name T351
Test name
Test status
Simulation time 327110952 ps
CPU time 2.26 seconds
Started May 16 03:14:30 PM PDT 24
Finished May 16 03:14:35 PM PDT 24
Peak memory 214520 kb
Host smart-65597e9d-fba9-4cb5-bc41-24d83dc2a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917298993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1917298993
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.174628754
Short name T475
Test name
Test status
Simulation time 479950886 ps
CPU time 2.77 seconds
Started May 16 03:14:29 PM PDT 24
Finished May 16 03:14:34 PM PDT 24
Peak memory 208760 kb
Host smart-2fa84947-9147-433a-b5ca-714b54961bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174628754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.174628754
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3947023806
Short name T378
Test name
Test status
Simulation time 366143689 ps
CPU time 13.3 seconds
Started May 16 03:14:32 PM PDT 24
Finished May 16 03:14:48 PM PDT 24
Peak memory 222644 kb
Host smart-0768b9b9-c54a-434a-9d82-5f65abe5b3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947023806 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3947023806
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1257966056
Short name T282
Test name
Test status
Simulation time 787312724 ps
CPU time 9.37 seconds
Started May 16 03:14:29 PM PDT 24
Finished May 16 03:14:40 PM PDT 24
Peak memory 214368 kb
Host smart-8907bb0a-08e1-4cc0-9f5c-61c2119273e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257966056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1257966056
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1096505280
Short name T521
Test name
Test status
Simulation time 1103114973 ps
CPU time 5.82 seconds
Started May 16 03:14:28 PM PDT 24
Finished May 16 03:14:36 PM PDT 24
Peak memory 210516 kb
Host smart-fb234edf-f335-4a97-8d3a-10ed65645a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096505280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1096505280
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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