SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OtpRootKeyValidLow] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 2 | 1 | T65 | 1 | T131 | 1 | - | - | ||||
auto[LcStateInvalid] | 72 | 1 | T27 | 12 | T372 | 12 | T322 | 36 | ||||
auto[OtpDevIdInvalid] | 108 | 1 | T102 | 36 | T373 | 12 | T374 | 36 | ||||
auto[RomDigestInvalid] | 60 | 1 | T25 | 12 | T372 | 24 | T321 | 12 | ||||
auto[RomDigestValidLow] | 108 | 1 | T372 | 36 | T373 | 24 | T322 | 36 | ||||
auto[FlashCreatorSeedInvalid] | 24 | 1 | T99 | 24 | - | - | - | - | ||||
auto[FlashOwnerSeedInvalid] | 156 | 1 | T26 | 12 | T27 | 36 | T100 | 24 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |