Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

10

T2

5

T14

7

auto[1]

565

1

T1

2

T2

10

T3

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

10

T2

5

T14

7

auto[1]

565

1

T1

2

T2

10

T3

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4770

1

T1

12

T2

10

T3

1

auto[1]

511

1

T2

5

T14

1

T15

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4770

1

T1

12

T2

10

T3

1

auto[1]

511

1

T2

5

T14

1

T15

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T2	3		T3	1		T14	2
auto[OpGenId]	1119	1			T2	2		T14	3		T15	1
auto[OpGenSwOut]	1104	1			T2	4		T14	1		T15	1
auto[OpGenHwOut]	2551	1			T1	12		T2	6		T14	2
auto[OpDisable]	73	1			T28	2		T29	1		T30	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	434	1			T2	3		T3	1		T14	2
auto[OpGenId]	1119	1			T2	2		T14	3		T15	1
auto[OpGenSwOut]	1104	1			T2	4		T14	1		T15	1
auto[OpGenHwOut]	2551	1			T1	12		T2	6		T14	2
auto[OpDisable]	73	1			T28	2		T29	1		T30	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701

1

T1

12

T2

12

T3

1

auto[1]

580

1

T2

3

T18

2

T37

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701

1

T1

12

T2

12

T3

1

auto[1]

580

1

T2

3

T18

2

T37

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4974

1

T1

12

T2

3

T3

1

auto[1]

307

1

T2

12

T119

14

T134

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1813	1			T1	2		T2	4		T3	1
auto[1]	690	1			T1	1		T14	2		T15	1
auto[2]	693	1			T1	1		T2	2		T15	3
auto[3]	687	1			T1	1		T2	9		T14	2
auto[4]	340	1			T1	3		T14	1		T37	1
auto[5]	340	1			T1	3		T14	1		T37	1
auto[6]	348	1			T16	1		T18	1		T88	1
auto[7]	370	1			T1	1		T14	1		T16	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1398	1			T1	7		T14	3		T16	2
clear_one[1]	690	1			T1	1		T14	2		T15	1
clear_one[2]	693	1			T1	1		T2	2		T15	3
clear_one[3]	687	1			T1	1		T2	9		T14	2
clear_none	1813	1			T1	2		T2	4		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T1	4		T14	2		T15	1
auto[StInit]	624	1			T1	1		T2	1		T14	1
auto[StCreatorRootKey]	568	1			T1	1		T2	4		T14	1
auto[StOwnerIntKey]	501	1			T1	1		T3	1		T18	1
auto[StOwnerKey]	491	1			T1	1		T2	3		T14	1
auto[StDisabled]	1878	1			T1	4		T2	7		T14	3
auto[StInvalid]	282	1			T16	4		T40	3		T50	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T1	4		T14	2		T15	1
auto[StInit]	624	1			T1	1		T2	1		T14	1
auto[StCreatorRootKey]	568	1			T1	1		T2	4		T14	1
auto[StOwnerIntKey]	501	1			T1	1		T3	1		T18	1
auto[StOwnerKey]	491	1			T1	1		T2	3		T14	1
auto[StDisabled]	1878	1			T1	4		T2	7		T14	3
auto[StInvalid]	282	1			T16	4		T40	3		T50	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[2] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[2] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[2] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled] , auto[StInvalid]]	[auto[OpDisable]]	--	--	6
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T134	1		T220	1		T221	1
auto[0]	auto[StReset]	auto[OpGenId]	145	1			T29	2		T30	2		T92	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	145	1			T16	1		T17	1		T18	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	253	1			T1	1		T14	1		T15	1
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T28	1		T133	1		T64	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T2	1		T127	1		T61	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	108	1			T29	3		T32	1		T30	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	187	1			T28	1		T89	1		T29	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T19	1		T222	1		T223	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	55	1			T18	1		T107	1		T224	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	46	1			T88	1		T28	1		T64	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	78	1			T2	3		T30	2		T137	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T3	1		T29	1		T30	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T29	1		T30	1		T225	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T29	1		T54	1		T226	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T89	1		T198	1		T108	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T19	1		T61	1		T25	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	27	1			T29	1		T30	1		T64	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T29	1		T54	1		T5	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T29	1		T200	1		T199	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	33	1			T61	1		T64	1		T224	3
auto[0]	auto[StDisabled]	auto[OpGenId]	58	1			T136	1		T64	3		T54	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T114	1		T29	2		T64	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T1	1		T15	1		T19	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T30	1		T54	1		T227	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T51	1		T93	1		T91	1
auto[0]	auto[StInvalid]	auto[OpGenId]	29	1			T40	1		T228	1		T229	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T40	1		T94	1		T228	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	26	1			T40	1		T50	1		T230	2
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T231	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T232	1		T233	1		T203	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T19	1		T41	1		T61	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T234	1		T235	1		T71	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T14	1		T55	1		T236	2
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T73	1		T237	1		T69	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T238	1		T239	1		T76	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	14	1			T240	1		T241	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T119	1		T243	3		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T245	1		T188	1		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T72	1		T132	1		T247	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T200	1		T199	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T59	1		T249	1		T77	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T64	1		T68	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T64	1		T74	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T29	1		T248	1		T128	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T252	1		T193	1		T215	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	7	1			T54	1		T188	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T243	1		T249	1		T188	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T88	1		T89	1		T29	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T64	1		T224	1		T71	1
auto[1]	auto[StDisabled]	auto[OpGenId]	63	1			T14	1		T15	1		T29	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T29	2		T64	1		T97	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T1	1		T37	1		T89	2
auto[1]	auto[StDisabled]	auto[OpDisable]	14	1			T28	1		T29	1		T71	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	9	1			T50	1		T230	1		T45	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T16	1		T254	1		T255	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T230	1		T95	1		T254	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T95	1		T256	1		T257	1
auto[2]	auto[StReset]	auto[OpGenId]	25	1			T41	1		T258	1		T95	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T259	1		T239	1		T95	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	35	1			T37	1		T200	1		T64	2
auto[2]	auto[StInit]	auto[OpAdvance]	12	1			T260	1		T27	1		T189	1
auto[2]	auto[StInit]	auto[OpGenId]	6	1			T191	1		T79	1		T261	2
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T74	1		T262	1		T188	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T1	1		T15	1		T37	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T2	1		T263	1		T264	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	23	1			T66	1		T54	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T15	1		T60	1		T203	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T37	1		T30	1		T198	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T32	1		T64	1		T260	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T29	1		T61	2		T64	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T30	1		T266	1		T246	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T267	1		T260	1		T268	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T64	1		T90	1		T269	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T18	1		T30	1		T131	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T2	1		T30	1		T265	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T28	1		T127	1		T270	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	15	1			T61	1		T271	1		T79	1
auto[2]	auto[StDisabled]	auto[OpGenId]	54	1			T19	1		T29	1		T30	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T19	1		T29	1		T83	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T15	1		T37	2		T30	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T74	1		T191	1		T77	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T272	2		T273	1		T274	1
auto[2]	auto[StInvalid]	auto[OpGenId]	13	1			T16	1		T275	2		T276	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T93	1		T229	1		T277	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T16	1		T51	1		T230	1
auto[3]	auto[StReset]	auto[OpGenId]	23	1			T17	1		T30	1		T64	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T30	1		T119	1		T278	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	35	1			T37	1		T279	1		T280	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T83	1		T281	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	7	1			T282	1		T79	1		T283	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	7	1			T284	1		T79	1		T261	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T28	1		T248	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T55	1		T232	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T109	1		T97	1		T128	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T14	1		T59	2		T287	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T29	2		T109	1		T112	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T136	1		T288	1		T77	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T30	1		T289	1		T189	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T28	1		T29	1		T61	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T290	1		T66	1		T291	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T2	2		T29	1		T136	2
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T28	1		T136	2		T69	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T136	2		T65	1		T258	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T37	1		T29	1		T112	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T30	1		T119	1		T136	2
auto[3]	auto[StDisabled]	auto[OpGenId]	54	1			T2	1		T88	1		T28	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T2	3		T28	1		T30	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T1	1		T2	3		T14	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T28	1		T69	1		T188	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T92	1		T228	1		T256	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T92	1		T292	1		T293	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T96	1		T293	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T295	1		T296	1		T297	1
auto[4]	auto[StReset]	auto[OpGenId]	18	1			T29	2		T61	1		T298	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	7	1			T74	1		T204	1		T299	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	24	1			T1	2		T37	1		T29	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T300	1		T301	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T74	1		T76	1		T203	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T128	1		T193	1		T302	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T198	1		T200	1		T287	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T189	1		T303	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T30	1		T74	1		T69	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T29	1		T192	1		T304	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T270	1		T54	1		T305	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T64	1		T306	1		T236	2
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T134	1		T69	1		T132	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T71	1		T307	1		T308	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T114	1		T30	1		T71	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T222	1		T59	1		T309	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T14	1		T188	1		T75	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T64	1		T310	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T1	1		T137	1		T225	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T134	2		T111	1		T312	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T29	1		T54	1		T226	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T28	1		T29	1		T30	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T127	1		T198	2		T199	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T313	1		T314	1		T315	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T257	1		T272	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T92	1		T94	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T93	1		T276	1		T277	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T91	1		T254	1		T275	1
auto[5]	auto[StReset]	auto[OpGenId]	5	1			T75	1		T318	1		T77	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	5	1			T319	1		T318	1		T52	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	30	1			T1	1		T290	1		T84	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T128	1		T186	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T189	1		T320	1		T207	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T321	1		T322	1		T323	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T61	1		T324	1		T192	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T119	1		T311	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T325	1		T189	1		T76	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T74	1		T76	1		T326	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T1	1		T89	1		T267	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T119	1		T60	1		T204	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T327	1		T328	1		T306	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T29	1		T239	1		T181	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T37	1		T119	3		T64	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T119	2		T298	1		T103	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T109	1		T74	1		T329	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T330	1		T331	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T198	1		T64	1		T54	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	9	1			T14	1		T250	1		T243	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T114	1		T119	1		T332	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T28	1		T87	1		T29	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T1	1		T89	1		T199	1
auto[5]	auto[StDisabled]	auto[OpDisable]	9	1			T54	1		T284	1		T320	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T333	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T93	1		T334	1		T274	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T335	1		T336	1		T337	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T95	1		T335	1		T333	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T74	1		T338	1		T339	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T30	1		T77	1		T141	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	17	1			T29	1		T198	1		T280	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T26	1		T340	1		T341	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T342	1		T69	1		T233	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T76	1		T78	1		T215	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T54	1		T343	1		T280	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T250	1		T341	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T136	1		T344	1		T220	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T114	1		T136	2		T35	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	8	1			T84	1		T345	1		T203	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T18	1		T340	2		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T190	1		T346	1		T347	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T247	1		T348	1		T315	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T200	1		T199	1		T137	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T35	1		T261	1		T349	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T113	1		T271	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T29	1		T59	1		T271	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T290	1		T54	1		T280	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	26	1			T101	1		T222	1		T59	1
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T127	1		T29	3		T197	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T30	3		T64	1		T54	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T88	1		T127	1		T30	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T50	1		T230	1		T45	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T273	1		T351	1		T352	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T353	1		T274	1		T354	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T16	1		T230	1		T276	1
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T14	1		T16	1		T188	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T59	1		T252	1		T355	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	20	1			T270	1		T108	1		T235	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T188	1		T338	1		T102	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T119	1		T193	1		T141	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T30	1		T356	4		T357	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	7	1			T234	1		T358	1		T350	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T359	1		T347	1		T360	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	2	1			T361	1		T362	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T54	1		T203	1		T363	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T291	1		T279	1		T65	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T332	1		T75	1		T311	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T90	1		T338	1		T213	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T223	1		T250	1		T364	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T1	1		T234	1		T54	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T29	1		T30	1		T288	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T342	1		T250	1		T76	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T30	1		T64	1		T250	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T114	1		T61	1		T291	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T30	1		T312	1		T252	1
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T28	1		T64	2		T260	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T30	1		T54	1		T5	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T89	1		T30	1		T198	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T61	1		T54	1		T365	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	7	1			T50	1		T317	1		T366	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T229	1		T255	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T367	1		T368	1		T369	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T91	1		T319	1		T274	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1398

1

T1

7

T14

3

T16

2

clear_one[1]

auto[0]

auto[0]

auto[0]

387

1

T1

1

T14

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

160

1

T37

1

T89

3

T29

3

clear_one[1]

auto[0]

auto[1]

auto[0]

109

1

T88

1

T29

2

T200

2

clear_one[1]

auto[0]

auto[1]

auto[1]

34

1

T29

2

T54

1

T97

1

clear_one[2]

auto[0]

auto[0]

auto[0]

383

1

T1

1

T15

3

T16

2

clear_one[2]

auto[0]

auto[0]

auto[1]

143

1

T2

1

T18

1

T37

3

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T19

2

T28

1

T127

1

clear_one[2]

auto[1]

auto[0]

auto[1]

38

1

T2

1

T30

2

T61

1

clear_one[3]

auto[0]

auto[0]

auto[0]

379

1

T17

1

T37

3

T28

4

clear_one[3]

auto[0]

auto[1]

auto[0]

132

1

T14

1

T29

1

T30

2

clear_one[3]

auto[1]

auto[0]

auto[0]

135

1

T1

1

T2

5

T14

1

clear_one[3]

auto[1]

auto[1]

auto[0]

41

1

T2

4

T136

1

T64

1

clear_none

auto[0]

auto[0]

auto[0]

1313

1

T1

1

T2

3

T14

1

clear_none

auto[0]

auto[0]

auto[1]

127

1

T18

1

T89

1

T30

1

clear_none

auto[0]

auto[1]

auto[0]

126

1

T15

1

T200

2

T199

1

clear_none

auto[0]

auto[1]

auto[1]

25

1

T2

1

T54

1

T188

1

clear_none

auto[1]

auto[0]

auto[0]

143

1

T1

1

T3

1

T19

1

clear_none

auto[1]

auto[0]

auto[1]

35

1

T87

1

T61

1

T225

1

clear_none

auto[1]

auto[1]

auto[0]

26

1

T136

1

T64

2

T111

1

clear_none

auto[1]

auto[1]

auto[1]

18

1

T29

1

T197

1

T54

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1323	1			T1	7		T14	3		T16	2
clear_all	auto[1]	75	1			T119	7		T134	1		T136	2
clear_one[1]	auto[0]	632	1			T1	1		T14	2		T15	1
clear_one[1]	auto[1]	58	1			T243	6		T364	1		T370	3
clear_one[2]	auto[0]	668	1			T1	1		T2	1		T15	3
clear_one[2]	auto[1]	25	1			T2	1		T260	5		T271	2
clear_one[3]	auto[0]	632	1			T1	1		T2	1		T14	2
clear_one[3]	auto[1]	55	1			T2	8		T119	7		T136	7
clear_none	auto[0]	1719	1			T1	2		T2	1		T3	1
clear_none	auto[1]	94	1			T2	3		T134	1		T224	4