Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10896

1

T1

17

T2

12

T3

4

auto[Attestation]

7559

1

T1

3

T2

8

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2640	1			T2	2		T4	1		T14	6
auto[Aes]	3263	1			T1	20		T2	4		T3	3
auto[Kmac]	3315	1			T2	5		T4	2		T14	4
auto[Otbn]	3316	1			T2	5		T3	1		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7695	1			T1	8		T2	8		T3	3
auto[OpGenId]	5921	1			T2	4		T3	1		T4	3
auto[OpGenSwOut]	5742	1			T2	6		T14	8		T15	5
auto[OpGenHwOut]	6792	1			T1	20		T2	10		T3	4
auto[OpDisable]	139	1			T28	2		T29	2		T30	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10704

1

T1

8

T2

15

T3

7

auto[OpDoneFail]

15585

1

T1

20

T2

13

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6239	1			T1	13		T2	1		T3	1
auto[StInit]	3679	1			T1	2		T2	4		T3	2
auto[StCreatorRootKey]	3209	1			T1	2		T2	3		T3	2
auto[StOwnerIntKey]	2796	1			T1	2		T2	4		T3	3
auto[StOwnerKey]	2483	1			T1	2		T2	6		T14	2
auto[StDisabled]	7883	1			T1	7		T2	10		T14	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T14	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T28	1		T29	2		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T29	1		T61	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T127	1		T29	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T2	1		T29	5		T196	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	201	1			T2	1		T14	2		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	343	1			T14	1		T15	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	105	1			T28	1		T87	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	94	1			T15	1		T114	1		T29	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T2	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	69	1			T18	1		T30	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	207	1			T28	5		T114	2		T29	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	316	1			T15	1		T16	2		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	101	1			T29	1		T30	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T14	1		T28	1		T29	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T28	1		T87	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	50	1			T29	1		T196	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	214	1			T2	1		T14	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	278	1			T38	1		T29	3		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T29	1		T30	2		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T14	1		T28	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T87	1		T29	3		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T29	1		T196	1		T54	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	211	1			T19	1		T88	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	69	1			T28	1		T29	4		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T114	1		T32	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T29	2		T61	2		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T15	1		T28	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T29	1		T30	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	212	1			T14	1		T28	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T29	3		T30	1		T61	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	79	1			T29	3		T196	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T29	1		T61	2		T64	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	59	1			T28	1		T61	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T2	1		T29	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	210	1			T28	1		T87	2		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	93	1			T29	3		T30	2		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T29	2		T30	2		T61	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T87	1		T114	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T29	1		T30	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T29	1		T30	1		T64	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	230	1			T19	1		T28	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T29	1		T61	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	84	1			T29	2		T30	2		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T88	1		T28	2		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T29	1		T30	2		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T29	1		T30	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T2	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	256	1			T14	1		T18	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T114	1		T30	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T87	1		T29	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T88	1		T64	3		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T88	1		T28	1		T29	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	179	1			T14	1		T19	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	399	1			T1	12		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T1	1		T4	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T1	1		T3	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T1	1		T3	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T28	1		T114	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	276	1			T1	2		T2	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	448	1			T38	1		T29	4		T30	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T38	1		T28	2		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T30	1		T61	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T2	1		T14	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T2	1		T18	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	253	1			T2	1		T15	1		T29	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	465	1			T14	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T2	2		T29	3		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T2	1		T89	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T37	1		T87	2		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	100	1			T18	1		T30	1		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	292	1			T37	3		T88	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T29	1		T64	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	92	1			T29	1		T30	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T4	1		T28	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T61	1		T64	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T29	1		T61	2		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T19	2		T28	2		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T29	3		T30	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T15	1		T29	2		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T32	1		T30	2		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	85	1			T87	1		T29	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	95	1			T1	1		T2	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	262	1			T1	2		T14	4		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T29	1		T30	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	102	1			T4	1		T199	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	120	1			T2	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T29	3		T200	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	79	1			T18	3		T28	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	288	1			T15	1		T29	7		T30	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T29	2		T61	2		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T4	1		T37	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T18	1		T37	1		T29	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T3	1		T114	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	81	1			T18	2		T37	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	279	1			T2	1		T37	1		T88	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	195	1			T2	1		T127	1		T29	6
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	631	1			T2	1		T14	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T2	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	674	1			T14	1		T15	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	199	1			T14	1		T28	2		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	646	1			T2	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T14	1		T28	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	607	1			T19	1		T38	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T15	1		T28	1		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	394	1			T14	1		T28	3		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	189	1			T2	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	381	1			T28	1		T87	2		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	187	1			T87	1		T114	1		T29	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	444	1			T19	1		T28	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	201	1			T88	1		T28	2		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	378	1			T2	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T88	2		T28	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	544	1			T14	2		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	258	1			T1	2		T3	3		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	816	1			T1	15		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T2	2		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	818	1			T2	1		T15	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	302	1			T2	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	884	1			T2	2		T14	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	183	1			T4	1		T28	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	335	1			T19	2		T28	2		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	282	1			T1	1		T2	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	447	1			T1	2		T14	4		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T2	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	462	1			T4	1		T15	1		T29	9
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T3	1		T18	3		T37	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	470	1			T2	1		T4	1		T37	2