Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32458

1

T1

33

T2

32

T3

9

auto[1]

301

1

T2

6

T119

10

T134

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32468	1			T1	33		T2	32		T3	9
auto[134217728:268435455]	12	1			T2	1		T109	1		T220	2
auto[268435456:402653183]	8	1			T364	1		T231	1		T363	2
auto[402653184:536870911]	13	1			T2	3		T136	1		T298	1
auto[536870912:671088639]	10	1			T220	1		T399	1		T400	1
auto[671088640:805306367]	8	1			T2	1		T400	1		T386	2
auto[805306368:939524095]	10	1			T288	1		T338	1		T401	1
auto[939524096:1073741823]	14	1			T119	1		T136	1		T356	1
auto[1073741824:1207959551]	6	1			T271	1		T400	1		T231	1
auto[1207959552:1342177279]	10	1			T119	2		T356	1		T338	1
auto[1342177280:1476395007]	13	1			T119	1		T356	1		T387	1
auto[1476395008:1610612735]	15	1			T119	1		T136	1		T260	1
auto[1610612736:1744830463]	6	1			T136	1		T400	1		T402	1
auto[1744830464:1879048191]	11	1			T119	1		T134	1		T356	1
auto[1879048192:2013265919]	6	1			T136	1		T364	1		T400	2
auto[2013265920:2147483647]	6	1			T288	1		T338	1		T399	1
auto[2147483648:2281701375]	9	1			T288	1		T387	1		T386	1
auto[2281701376:2415919103]	9	1			T136	1		T400	1		T244	2
auto[2415919104:2550136831]	7	1			T260	1		T325	1		T340	1
auto[2550136832:2684354559]	10	1			T260	1		T364	1		T400	1
auto[2684354560:2818572287]	5	1			T119	1		T136	1		T401	1
auto[2818572288:2952790015]	11	1			T400	2		T387	1		T402	1
auto[2952790016:3087007743]	9	1			T119	1		T260	1		T220	1
auto[3087007744:3221225471]	10	1			T243	1		T387	1		T402	1
auto[3221225472:3355443199]	11	1			T224	1		T243	1		T220	1
auto[3355443200:3489660927]	5	1			T2	1		T243	1		T356	1
auto[3489660928:3623878655]	9	1			T136	1		T260	1		T356	2
auto[3623878656:3758096383]	10	1			T400	2		T387	1		T244	1
auto[3758096384:3892314111]	12	1			T119	1		T243	3		T400	1
auto[3892314112:4026531839]	9	1			T243	1		T356	1		T271	2
auto[4026531840:4160749567]	5	1			T119	1		T401	1		T340	1
auto[4160749568:4294967295]	12	1			T224	1		T243	1		T356	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32458	1			T1	33		T2	32		T3	9
auto[0:134217727]	auto[1]	10	1			T220	1		T266	1		T370	1
auto[134217728:268435455]	auto[1]	12	1			T2	1		T109	1		T220	2
auto[268435456:402653183]	auto[1]	8	1			T364	1		T231	1		T363	2
auto[402653184:536870911]	auto[1]	13	1			T2	3		T136	1		T298	1
auto[536870912:671088639]	auto[1]	10	1			T220	1		T399	1		T400	1
auto[671088640:805306367]	auto[1]	8	1			T2	1		T400	1		T386	2
auto[805306368:939524095]	auto[1]	10	1			T288	1		T338	1		T401	1
auto[939524096:1073741823]	auto[1]	14	1			T119	1		T136	1		T356	1
auto[1073741824:1207959551]	auto[1]	6	1			T271	1		T400	1		T231	1
auto[1207959552:1342177279]	auto[1]	10	1			T119	2		T356	1		T338	1
auto[1342177280:1476395007]	auto[1]	13	1			T119	1		T356	1		T387	1
auto[1476395008:1610612735]	auto[1]	15	1			T119	1		T136	1		T260	1
auto[1610612736:1744830463]	auto[1]	6	1			T136	1		T400	1		T402	1
auto[1744830464:1879048191]	auto[1]	11	1			T119	1		T134	1		T356	1
auto[1879048192:2013265919]	auto[1]	6	1			T136	1		T364	1		T400	2
auto[2013265920:2147483647]	auto[1]	6	1			T288	1		T338	1		T399	1
auto[2147483648:2281701375]	auto[1]	9	1			T288	1		T387	1		T386	1
auto[2281701376:2415919103]	auto[1]	9	1			T136	1		T400	1		T244	2
auto[2415919104:2550136831]	auto[1]	7	1			T260	1		T325	1		T340	1
auto[2550136832:2684354559]	auto[1]	10	1			T260	1		T364	1		T400	1
auto[2684354560:2818572287]	auto[1]	5	1			T119	1		T136	1		T401	1
auto[2818572288:2952790015]	auto[1]	11	1			T400	2		T387	1		T402	1
auto[2952790016:3087007743]	auto[1]	9	1			T119	1		T260	1		T220	1
auto[3087007744:3221225471]	auto[1]	10	1			T243	1		T387	1		T402	1
auto[3221225472:3355443199]	auto[1]	11	1			T224	1		T243	1		T220	1
auto[3355443200:3489660927]	auto[1]	5	1			T2	1		T243	1		T356	1
auto[3489660928:3623878655]	auto[1]	9	1			T136	1		T260	1		T356	2
auto[3623878656:3758096383]	auto[1]	10	1			T400	2		T387	1		T244	1
auto[3758096384:3892314111]	auto[1]	12	1			T119	1		T243	3		T400	1
auto[3892314112:4026531839]	auto[1]	9	1			T243	1		T356	1		T271	2
auto[4026531840:4160749567]	auto[1]	5	1			T119	1		T401	1		T340	1
auto[4160749568:4294967295]	auto[1]	12	1			T224	1		T243	1		T356	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1562

1

T2

2

T3

1

T16

5

auto[1]

1842

1

T2

2

T3

1

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T14	1		T88	1		T92	1
auto[134217728:268435455]	110	1			T3	1		T28	2		T29	2
auto[268435456:402653183]	116	1			T16	1		T17	1		T29	2
auto[402653184:536870911]	112	1			T14	1		T30	1		T92	1
auto[536870912:671088639]	106	1			T2	1		T3	1		T28	1
auto[671088640:805306367]	107	1			T29	3		T53	1		T30	1
auto[805306368:939524095]	94	1			T29	1		T53	1		T30	1
auto[939524096:1073741823]	110	1			T2	1		T17	1		T88	1
auto[1073741824:1207959551]	104	1			T18	1		T30	2		T33	1
auto[1207959552:1342177279]	91	1			T16	1		T19	1		T28	1
auto[1342177280:1476395007]	112	1			T114	1		T29	1		T61	1
auto[1476395008:1610612735]	127	1			T50	1		T29	3		T30	2
auto[1610612736:1744830463]	103	1			T16	1		T18	1		T29	3
auto[1744830464:1879048191]	122	1			T28	1		T40	1		T29	1
auto[1879048192:2013265919]	100	1			T18	1		T88	1		T30	1
auto[2013265920:2147483647]	99	1			T30	1		T92	1		T61	3
auto[2147483648:2281701375]	104	1			T18	1		T114	1		T29	2
auto[2281701376:2415919103]	120	1			T32	1		T30	1		T196	1
auto[2415919104:2550136831]	102	1			T2	1		T28	1		T87	1
auto[2550136832:2684354559]	106	1			T17	1		T29	2		T30	1
auto[2684354560:2818572287]	118	1			T16	1		T87	1		T114	1
auto[2818572288:2952790015]	112	1			T16	1		T40	1		T29	2
auto[2952790016:3087007743]	95	1			T18	1		T30	2		T196	1
auto[3087007744:3221225471]	96	1			T19	1		T40	1		T29	2
auto[3221225472:3355443199]	101	1			T19	1		T64	2		T224	1
auto[3355443200:3489660927]	105	1			T19	1		T40	1		T29	5
auto[3489660928:3623878655]	111	1			T29	1		T51	1		T119	1
auto[3623878656:3758096383]	95	1			T17	1		T88	1		T28	1
auto[3758096384:3892314111]	109	1			T2	1		T88	1		T87	1
auto[3892314112:4026531839]	106	1			T16	1		T19	1		T28	2
auto[4026531840:4160749567]	104	1			T17	1		T87	1		T29	1
auto[4160749568:4294967295]	118	1			T50	1		T114	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29	1			T92	1		T64	2		T278	1
auto[0:134217727]	auto[1]	60	1			T14	1		T88	1		T119	1
auto[134217728:268435455]	auto[0]	49	1			T3	1		T28	1		T29	1
auto[134217728:268435455]	auto[1]	61	1			T28	1		T29	1		T61	1
auto[268435456:402653183]	auto[0]	56	1			T17	1		T61	1		T64	2
auto[268435456:402653183]	auto[1]	60	1			T16	1		T29	2		T353	1
auto[402653184:536870911]	auto[0]	62	1			T30	1		T92	1		T64	1
auto[402653184:536870911]	auto[1]	50	1			T14	1		T119	1		T133	1
auto[536870912:671088639]	auto[0]	57	1			T2	1		T50	1		T29	1
auto[536870912:671088639]	auto[1]	49	1			T3	1		T28	1		T29	1
auto[671088640:805306367]	auto[0]	54	1			T29	1		T53	1		T30	1
auto[671088640:805306367]	auto[1]	53	1			T29	2		T61	1		T64	2
auto[805306368:939524095]	auto[0]	38	1			T30	1		T64	1		T5	1
auto[805306368:939524095]	auto[1]	56	1			T29	1		T53	1		T134	1
auto[939524096:1073741823]	auto[0]	43	1			T17	1		T88	1		T50	1
auto[939524096:1073741823]	auto[1]	67	1			T2	1		T29	1		T64	3
auto[1073741824:1207959551]	auto[0]	44	1			T30	1		T64	2		T109	1
auto[1073741824:1207959551]	auto[1]	60	1			T18	1		T30	1		T33	1
auto[1207959552:1342177279]	auto[0]	42	1			T16	1		T28	1		T29	2
auto[1207959552:1342177279]	auto[1]	49	1			T19	1		T30	1		T61	1
auto[1342177280:1476395007]	auto[0]	47	1			T114	1		T29	1		T64	1
auto[1342177280:1476395007]	auto[1]	65	1			T61	1		T64	1		T101	2
auto[1476395008:1610612735]	auto[0]	58	1			T50	1		T29	2		T30	1
auto[1476395008:1610612735]	auto[1]	69	1			T29	1		T30	1		T196	1
auto[1610612736:1744830463]	auto[0]	46	1			T16	1		T18	1		T29	1
auto[1610612736:1744830463]	auto[1]	57	1			T29	2		T30	1		T196	1
auto[1744830464:1879048191]	auto[0]	57	1			T28	1		T40	1		T29	1
auto[1744830464:1879048191]	auto[1]	65	1			T51	1		T41	1		T65	2
auto[1879048192:2013265919]	auto[0]	45	1			T30	1		T51	1		T64	3
auto[1879048192:2013265919]	auto[1]	55	1			T18	1		T88	1		T61	1
auto[2013265920:2147483647]	auto[0]	55	1			T92	1		T61	1		T64	1
auto[2013265920:2147483647]	auto[1]	44	1			T30	1		T61	2		T230	1
auto[2147483648:2281701375]	auto[0]	43	1			T114	1		T29	1		T248	1
auto[2147483648:2281701375]	auto[1]	61	1			T18	1		T29	1		T64	2
auto[2281701376:2415919103]	auto[0]	50	1			T32	1		T30	1		T92	1
auto[2281701376:2415919103]	auto[1]	70	1			T196	1		T134	1		T49	1
auto[2415919104:2550136831]	auto[0]	52	1			T2	1		T28	1		T29	1
auto[2415919104:2550136831]	auto[1]	50	1			T87	1		T29	1		T30	1
auto[2550136832:2684354559]	auto[0]	47	1			T17	1		T29	2		T30	1
auto[2550136832:2684354559]	auto[1]	59	1			T54	1		T5	1		T128	1
auto[2684354560:2818572287]	auto[0]	53	1			T16	1		T114	1		T29	1
auto[2684354560:2818572287]	auto[1]	65	1			T87	1		T29	1		T61	1
auto[2818572288:2952790015]	auto[0]	53	1			T16	1		T29	1		T30	1
auto[2818572288:2952790015]	auto[1]	59	1			T40	1		T29	1		T196	1
auto[2952790016:3087007743]	auto[0]	39	1			T196	1		T61	1		T109	1
auto[2952790016:3087007743]	auto[1]	56	1			T18	1		T30	2		T64	1
auto[3087007744:3221225471]	auto[0]	46	1			T19	1		T40	1		T30	1
auto[3087007744:3221225471]	auto[1]	50	1			T29	2		T196	1		T248	1
auto[3221225472:3355443199]	auto[0]	44	1			T6	1		T97	1		T59	1
auto[3221225472:3355443199]	auto[1]	57	1			T19	1		T64	2		T224	1
auto[3355443200:3489660927]	auto[0]	54	1			T29	3		T30	2		T92	1
auto[3355443200:3489660927]	auto[1]	51	1			T19	1		T40	1		T29	2
auto[3489660928:3623878655]	auto[0]	44	1			T29	1		T51	1		T119	1
auto[3489660928:3623878655]	auto[1]	67	1			T64	2		T101	1		T5	1
auto[3623878656:3758096383]	auto[0]	39	1			T17	1		T88	1		T28	1
auto[3623878656:3758096383]	auto[1]	56	1			T93	1		T64	2		T5	2
auto[3758096384:3892314111]	auto[0]	50	1			T30	3		T64	1		T54	1
auto[3758096384:3892314111]	auto[1]	59	1			T2	1		T88	1		T87	1
auto[3892314112:4026531839]	auto[0]	64	1			T16	1		T28	1		T119	1
auto[3892314112:4026531839]	auto[1]	42	1			T19	1		T28	1		T197	1
auto[4026531840:4160749567]	auto[0]	51	1			T17	1		T53	1		T54	1
auto[4026531840:4160749567]	auto[1]	53	1			T87	1		T29	1		T30	1
auto[4160749568:4294967295]	auto[0]	51	1			T64	1		T54	1		T59	1
auto[4160749568:4294967295]	auto[1]	67	1			T50	1		T114	1		T29	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1576

1

T2

2

T16

5

T17

4

auto[1]

1827

1

T2

2

T3

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T87	1		T29	2		T32	1
auto[134217728:268435455]	111	1			T29	4		T196	2		T51	1
auto[268435456:402653183]	110	1			T16	1		T28	1		T87	1
auto[402653184:536870911]	95	1			T30	3		T196	1		T51	1
auto[536870912:671088639]	127	1			T2	2		T88	1		T40	1
auto[671088640:805306367]	123	1			T2	1		T29	4		T61	1
auto[805306368:939524095]	107	1			T18	1		T19	1		T88	1
auto[939524096:1073741823]	102	1			T50	1		T29	1		T30	1
auto[1073741824:1207959551]	100	1			T18	1		T29	1		T119	1
auto[1207959552:1342177279]	89	1			T29	1		T32	1		T30	3
auto[1342177280:1476395007]	110	1			T16	1		T17	1		T18	1
auto[1476395008:1610612735]	131	1			T16	1		T17	1		T88	1
auto[1610612736:1744830463]	120	1			T29	2		T30	1		T54	1
auto[1744830464:1879048191]	92	1			T3	1		T16	1		T50	1
auto[1879048192:2013265919]	105	1			T29	1		T30	1		T92	2
auto[2013265920:2147483647]	108	1			T2	1		T19	1		T29	1
auto[2147483648:2281701375]	100	1			T14	1		T17	1		T87	1
auto[2281701376:2415919103]	94	1			T19	1		T28	1		T29	1
auto[2415919104:2550136831]	100	1			T28	1		T50	1		T30	1
auto[2550136832:2684354559]	99	1			T3	1		T29	3		T53	1
auto[2684354560:2818572287]	106	1			T50	1		T114	1		T32	1
auto[2818572288:2952790015]	94	1			T29	1		T119	1		T64	2
auto[2952790016:3087007743]	99	1			T16	1		T88	1		T28	1
auto[3087007744:3221225471]	104	1			T114	1		T29	1		T41	1
auto[3221225472:3355443199]	107	1			T20	1		T222	1		T5	1
auto[3355443200:3489660927]	111	1			T17	1		T87	1		T30	2
auto[3489660928:3623878655]	112	1			T14	1		T28	2		T29	5
auto[3623878656:3758096383]	106	1			T88	1		T29	1		T30	1
auto[3758096384:3892314111]	104	1			T114	2		T29	2		T196	1
auto[3892314112:4026531839]	100	1			T16	1		T18	1		T28	1
auto[4026531840:4160749567]	113	1			T18	1		T19	1		T29	1
auto[4160749568:4294967295]	111	1			T17	1		T19	1		T29	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T29	1		T32	1		T30	1
auto[0:134217727]	auto[1]	59	1			T87	1		T29	1		T30	1
auto[134217728:268435455]	auto[0]	57	1			T29	2		T51	1		T64	1
auto[134217728:268435455]	auto[1]	54	1			T29	2		T196	2		T133	1
auto[268435456:402653183]	auto[0]	57	1			T16	1		T29	1		T30	1
auto[268435456:402653183]	auto[1]	53	1			T28	1		T87	1		T54	1
auto[402653184:536870911]	auto[0]	46	1			T30	1		T196	1		T51	1
auto[402653184:536870911]	auto[1]	49	1			T30	2		T64	2		T223	1
auto[536870912:671088639]	auto[0]	55	1			T2	2		T40	1		T30	1
auto[536870912:671088639]	auto[1]	72	1			T88	1		T30	1		T33	1
auto[671088640:805306367]	auto[0]	56	1			T29	1		T61	1		T64	1
auto[671088640:805306367]	auto[1]	67	1			T2	1		T29	3		T353	1
auto[805306368:939524095]	auto[0]	46	1			T28	1		T53	1		T30	1
auto[805306368:939524095]	auto[1]	61	1			T18	1		T19	1		T88	1
auto[939524096:1073741823]	auto[0]	46	1			T50	1		T30	1		T92	1
auto[939524096:1073741823]	auto[1]	56	1			T29	1		T5	1		T71	2
auto[1073741824:1207959551]	auto[0]	45	1			T18	1		T119	1		T288	1
auto[1073741824:1207959551]	auto[1]	55	1			T29	1		T61	1		T20	1
auto[1207959552:1342177279]	auto[0]	41	1			T32	1		T61	1		T64	1
auto[1207959552:1342177279]	auto[1]	48	1			T29	1		T30	3		T197	2
auto[1342177280:1476395007]	auto[0]	55	1			T16	1		T53	1		T64	2
auto[1342177280:1476395007]	auto[1]	55	1			T17	1		T18	1		T136	1
auto[1476395008:1610612735]	auto[0]	61	1			T17	1		T28	1		T29	1
auto[1476395008:1610612735]	auto[1]	70	1			T16	1		T88	1		T53	1
auto[1610612736:1744830463]	auto[0]	61	1			T29	1		T54	1		T224	1
auto[1610612736:1744830463]	auto[1]	59	1			T29	1		T30	1		T5	1
auto[1744830464:1879048191]	auto[0]	45	1			T16	1		T50	1		T29	1
auto[1744830464:1879048191]	auto[1]	47	1			T3	1		T61	1		T64	1
auto[1879048192:2013265919]	auto[0]	51	1			T29	1		T30	1		T92	2
auto[1879048192:2013265919]	auto[1]	54	1			T61	1		T134	1		T54	1
auto[2013265920:2147483647]	auto[0]	50	1			T29	1		T92	1		T61	1
auto[2013265920:2147483647]	auto[1]	58	1			T2	1		T19	1		T64	2
auto[2147483648:2281701375]	auto[0]	42	1			T17	1		T40	1		T29	1
auto[2147483648:2281701375]	auto[1]	58	1			T14	1		T87	1		T133	1
auto[2281701376:2415919103]	auto[0]	49	1			T19	1		T28	1		T29	1
auto[2281701376:2415919103]	auto[1]	45	1			T136	1		T101	1		T111	1
auto[2415919104:2550136831]	auto[0]	48	1			T28	1		T50	1		T30	1
auto[2415919104:2550136831]	auto[1]	52	1			T196	1		T64	2		T71	1
auto[2550136832:2684354559]	auto[0]	44	1			T30	1		T64	1		T49	1
auto[2550136832:2684354559]	auto[1]	55	1			T3	1		T29	3		T53	1
auto[2684354560:2818572287]	auto[0]	41	1			T32	1		T136	1		T224	1
auto[2684354560:2818572287]	auto[1]	65	1			T50	1		T114	1		T41	1
auto[2818572288:2952790015]	auto[0]	40	1			T64	1		T107	1		T109	1
auto[2818572288:2952790015]	auto[1]	54	1			T29	1		T119	1		T64	1
auto[2952790016:3087007743]	auto[0]	48	1			T16	1		T88	1		T28	1
auto[2952790016:3087007743]	auto[1]	51	1			T40	1		T29	1		T61	2
auto[3087007744:3221225471]	auto[0]	54	1			T114	1		T92	1		T64	1
auto[3087007744:3221225471]	auto[1]	50	1			T29	1		T41	1		T64	1
auto[3221225472:3355443199]	auto[0]	42	1			T20	1		T5	1		T278	1
auto[3221225472:3355443199]	auto[1]	65	1			T222	1		T278	1		T65	1
auto[3355443200:3489660927]	auto[0]	58	1			T17	1		T30	1		T61	1
auto[3355443200:3489660927]	auto[1]	53	1			T87	1		T30	1		T119	1
auto[3489660928:3623878655]	auto[0]	49	1			T28	1		T29	3		T30	2
auto[3489660928:3623878655]	auto[1]	63	1			T14	1		T28	1		T29	2
auto[3623878656:3758096383]	auto[0]	44	1			T88	1		T64	1		T128	1
auto[3623878656:3758096383]	auto[1]	62	1			T29	1		T30	1		T51	2
auto[3758096384:3892314111]	auto[0]	53	1			T114	1		T29	2		T288	1
auto[3758096384:3892314111]	auto[1]	51	1			T114	1		T196	1		T54	1
auto[3892314112:4026531839]	auto[0]	46	1			T16	1		T28	1		T64	2
auto[3892314112:4026531839]	auto[1]	54	1			T18	1		T29	1		T61	1
auto[4026531840:4160749567]	auto[0]	45	1			T196	1		T61	1		T64	3
auto[4026531840:4160749567]	auto[1]	68	1			T18	1		T19	1		T29	1
auto[4160749568:4294967295]	auto[0]	47	1			T17	1		T29	1		T64	1
auto[4160749568:4294967295]	auto[1]	64	1			T19	1		T29	1		T61	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1591

1

T2

2

T14

1

T16

5

auto[1]

1812

1

T2

2

T3

2

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T29	2		T30	1		T196	1
auto[134217728:268435455]	101	1			T88	1		T32	1		T53	1
auto[268435456:402653183]	110	1			T92	1		T134	1		T64	2
auto[402653184:536870911]	108	1			T2	1		T14	1		T18	1
auto[536870912:671088639]	110	1			T50	1		T61	1		T136	1
auto[671088640:805306367]	101	1			T17	1		T18	1		T87	1
auto[805306368:939524095]	114	1			T16	1		T17	1		T29	3
auto[939524096:1073741823]	114	1			T28	1		T29	2		T30	1
auto[1073741824:1207959551]	98	1			T88	1		T28	1		T29	1
auto[1207959552:1342177279]	95	1			T29	2		T51	1		T64	7
auto[1342177280:1476395007]	98	1			T87	1		T53	1		T30	1
auto[1476395008:1610612735]	98	1			T18	1		T28	1		T87	1
auto[1610612736:1744830463]	115	1			T28	1		T114	1		T29	1
auto[1744830464:1879048191]	92	1			T2	1		T16	1		T28	1
auto[1879048192:2013265919]	106	1			T2	1		T16	1		T28	1
auto[2013265920:2147483647]	100	1			T3	1		T28	1		T29	1
auto[2147483648:2281701375]	111	1			T19	1		T40	1		T29	2
auto[2281701376:2415919103]	118	1			T29	1		T30	2		T92	1
auto[2415919104:2550136831]	116	1			T19	1		T29	2		T30	2
auto[2550136832:2684354559]	108	1			T19	2		T114	1		T29	3
auto[2684354560:2818572287]	102	1			T18	1		T88	1		T50	1
auto[2818572288:2952790015]	117	1			T29	2		T92	1		T119	1
auto[2952790016:3087007743]	113	1			T17	1		T29	2		T30	2
auto[3087007744:3221225471]	106	1			T29	1		T41	1		T64	2
auto[3221225472:3355443199]	112	1			T16	1		T19	1		T29	1
auto[3355443200:3489660927]	100	1			T87	1		T119	1		T64	2
auto[3489660928:3623878655]	96	1			T16	1		T17	1		T32	1
auto[3623878656:3758096383]	109	1			T14	1		T28	1		T30	2
auto[3758096384:3892314111]	96	1			T3	1		T16	1		T17	1
auto[3892314112:4026531839]	103	1			T2	1		T114	1		T29	1
auto[4026531840:4160749567]	107	1			T18	1		T88	1		T28	1
auto[4160749568:4294967295]	124	1			T88	1		T40	1		T29	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T30	1		T61	1		T109	1
auto[0:134217727]	auto[1]	52	1			T29	2		T196	1		T64	1
auto[134217728:268435455]	auto[0]	53	1			T88	1		T32	1		T53	1
auto[134217728:268435455]	auto[1]	48	1			T5	1		T223	1		T71	1
auto[268435456:402653183]	auto[0]	52	1			T92	1		T64	1		T20	1
auto[268435456:402653183]	auto[1]	58	1			T134	1		T64	1		T66	1
auto[402653184:536870911]	auto[0]	52	1			T2	1		T18	1		T29	1
auto[402653184:536870911]	auto[1]	56	1			T14	1		T50	1		T29	1
auto[536870912:671088639]	auto[0]	51	1			T50	1		T61	1		T136	1
auto[536870912:671088639]	auto[1]	59	1			T64	1		T20	1		T65	1
auto[671088640:805306367]	auto[0]	47	1			T17	1		T50	1		T51	1
auto[671088640:805306367]	auto[1]	54	1			T18	1		T87	1		T114	1
auto[805306368:939524095]	auto[0]	62	1			T16	1		T29	2		T30	1
auto[805306368:939524095]	auto[1]	52	1			T17	1		T29	1		T41	1
auto[939524096:1073741823]	auto[0]	60	1			T28	1		T29	1		T30	1
auto[939524096:1073741823]	auto[1]	54	1			T29	1		T94	1		T5	1
auto[1073741824:1207959551]	auto[0]	47	1			T88	1		T28	1		T29	1
auto[1073741824:1207959551]	auto[1]	51	1			T61	1		T133	1		T136	1
auto[1207959552:1342177279]	auto[0]	36	1			T64	3		T197	1		T73	1
auto[1207959552:1342177279]	auto[1]	59	1			T29	2		T51	1		T64	4
auto[1342177280:1476395007]	auto[0]	47	1			T64	1		T54	1		T353	1
auto[1342177280:1476395007]	auto[1]	51	1			T87	1		T53	1		T30	1
auto[1476395008:1610612735]	auto[0]	47	1			T28	1		T29	1		T32	1
auto[1476395008:1610612735]	auto[1]	51	1			T18	1		T87	1		T29	1
auto[1610612736:1744830463]	auto[0]	54	1			T114	1		T30	1		T51	1
auto[1610612736:1744830463]	auto[1]	61	1			T28	1		T29	1		T64	1
auto[1744830464:1879048191]	auto[0]	38	1			T16	1		T29	1		T61	1
auto[1744830464:1879048191]	auto[1]	54	1			T2	1		T28	1		T196	1
auto[1879048192:2013265919]	auto[0]	52	1			T16	1		T28	1		T29	1
auto[1879048192:2013265919]	auto[1]	54	1			T2	1		T196	1		T61	2
auto[2013265920:2147483647]	auto[0]	38	1			T28	1		T29	1		T5	1
auto[2013265920:2147483647]	auto[1]	62	1			T3	1		T30	1		T64	3
auto[2147483648:2281701375]	auto[0]	51	1			T29	2		T92	1		T64	3
auto[2147483648:2281701375]	auto[1]	60	1			T19	1		T40	1		T51	1
auto[2281701376:2415919103]	auto[0]	45	1			T29	1		T30	1		T92	1
auto[2281701376:2415919103]	auto[1]	73	1			T30	1		T61	1		T133	1
auto[2415919104:2550136831]	auto[0]	44	1			T30	1		T64	1		T109	1
auto[2415919104:2550136831]	auto[1]	72	1			T19	1		T29	2		T30	1
auto[2550136832:2684354559]	auto[0]	43	1			T19	1		T114	1		T29	2
auto[2550136832:2684354559]	auto[1]	65	1			T19	1		T29	1		T30	2
auto[2684354560:2818572287]	auto[0]	44	1			T50	1		T29	1		T30	1
auto[2684354560:2818572287]	auto[1]	58	1			T18	1		T88	1		T29	1
auto[2818572288:2952790015]	auto[0]	63	1			T29	1		T92	1		T64	2
auto[2818572288:2952790015]	auto[1]	54	1			T29	1		T119	1		T93	1
auto[2952790016:3087007743]	auto[0]	58	1			T17	1		T29	1		T30	1
auto[2952790016:3087007743]	auto[1]	55	1			T29	1		T30	1		T119	1
auto[3087007744:3221225471]	auto[0]	49	1			T29	1		T64	2		T260	1
auto[3087007744:3221225471]	auto[1]	57	1			T41	1		T222	1		T55	1
auto[3221225472:3355443199]	auto[0]	52	1			T30	1		T61	1		T54	1
auto[3221225472:3355443199]	auto[1]	60	1			T16	1		T19	1		T29	1
auto[3355443200:3489660927]	auto[0]	41	1			T64	1		T222	1		T288	1
auto[3355443200:3489660927]	auto[1]	59	1			T87	1		T119	1		T64	1
auto[3489660928:3623878655]	auto[0]	42	1			T16	1		T17	1		T32	1
auto[3489660928:3623878655]	auto[1]	54	1			T64	1		T101	2		T65	1
auto[3623878656:3758096383]	auto[0]	53	1			T14	1		T28	1		T30	1
auto[3623878656:3758096383]	auto[1]	56	1			T30	1		T134	1		T248	1
auto[3758096384:3892314111]	auto[0]	53	1			T16	1		T17	1		T40	1
auto[3758096384:3892314111]	auto[1]	43	1			T3	1		T40	1		T30	1
auto[3892314112:4026531839]	auto[0]	53	1			T2	1		T114	1		T64	1
auto[3892314112:4026531839]	auto[1]	50	1			T29	1		T196	1		T64	1
auto[4026531840:4160749567]	auto[0]	54	1			T88	1		T29	1		T53	1
auto[4026531840:4160749567]	auto[1]	53	1			T18	1		T28	1		T29	2
auto[4160749568:4294967295]	auto[0]	57	1			T64	1		T6	1		T152	1
auto[4160749568:4294967295]	auto[1]	67	1			T88	1		T40	1		T29	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1584

1

T16

5

T17

5

T18

1

auto[1]

1819

1

T2

4

T3

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T87	1		T40	1		T114	1
auto[134217728:268435455]	100	1			T17	1		T28	1		T29	1
auto[268435456:402653183]	109	1			T14	1		T16	1		T19	1
auto[402653184:536870911]	103	1			T2	1		T18	1		T40	1
auto[536870912:671088639]	116	1			T16	1		T19	1		T87	1
auto[671088640:805306367]	91	1			T28	1		T64	2		T230	1
auto[805306368:939524095]	94	1			T3	1		T50	1		T196	1
auto[939524096:1073741823]	103	1			T29	1		T30	1		T196	1
auto[1073741824:1207959551]	109	1			T18	1		T88	1		T28	1
auto[1207959552:1342177279]	101	1			T2	1		T18	1		T40	1
auto[1342177280:1476395007]	97	1			T28	1		T29	1		T30	1
auto[1476395008:1610612735]	123	1			T16	1		T28	1		T30	1
auto[1610612736:1744830463]	123	1			T114	1		T29	2		T53	1
auto[1744830464:1879048191]	105	1			T29	1		T30	1		T33	1
auto[1879048192:2013265919]	105	1			T17	1		T29	2		T222	1
auto[2013265920:2147483647]	117	1			T2	1		T3	1		T16	1
auto[2147483648:2281701375]	88	1			T29	2		T30	1		T64	1
auto[2281701376:2415919103]	121	1			T50	1		T29	3		T30	1
auto[2415919104:2550136831]	96	1			T16	1		T18	1		T28	1
auto[2550136832:2684354559]	94	1			T29	1		T30	2		T51	1
auto[2684354560:2818572287]	104	1			T17	1		T87	1		T29	1
auto[2818572288:2952790015]	93	1			T2	1		T28	1		T29	3
auto[2952790016:3087007743]	110	1			T14	1		T114	1		T29	2
auto[3087007744:3221225471]	100	1			T17	1		T88	1		T50	1
auto[3221225472:3355443199]	104	1			T88	1		T40	1		T29	3
auto[3355443200:3489660927]	111	1			T19	1		T29	2		T64	1
auto[3489660928:3623878655]	98	1			T87	1		T30	1		T61	1
auto[3623878656:3758096383]	97	1			T16	1		T114	1		T29	2
auto[3758096384:3892314111]	111	1			T19	1		T53	1		T30	1
auto[3892314112:4026531839]	118	1			T19	1		T29	3		T41	1
auto[4026531840:4160749567]	132	1			T17	1		T18	1		T88	2
auto[4160749568:4294967295]	111	1			T29	1		T53	1		T30	1