Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4662

1

T2

4

T14

2

T16

8

auto[1]

2144

1

T2

4

T3

4

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	210	1			T19	2		T29	4		T61	4
auto[134217728:268435455]	222	1			T87	2		T29	2		T196	2
auto[268435456:402653183]	232	1			T87	2		T30	2		T133	2
auto[402653184:536870911]	176	1			T17	2		T29	8		T53	2
auto[536870912:671088639]	216	1			T29	4		T32	2		T196	2
auto[671088640:805306367]	192	1			T40	2		T119	2		T136	2
auto[805306368:939524095]	236	1			T16	2		T29	6		T30	2
auto[939524096:1073741823]	240	1			T16	2		T19	2		T50	2
auto[1073741824:1207959551]	194	1			T40	2		T29	2		T30	2
auto[1207959552:1342177279]	214	1			T17	2		T114	2		T29	2
auto[1342177280:1476395007]	192	1			T17	2		T87	2		T29	4
auto[1476395008:1610612735]	198	1			T29	2		T196	2		T61	2
auto[1610612736:1744830463]	220	1			T14	2		T18	2		T88	4
auto[1744830464:1879048191]	206	1			T3	2		T16	2		T18	2
auto[1879048192:2013265919]	240	1			T18	2		T88	2		T28	2
auto[2013265920:2147483647]	230	1			T28	2		T87	2		T29	2
auto[2147483648:2281701375]	194	1			T19	2		T29	6		T30	8
auto[2281701376:2415919103]	234	1			T29	2		T53	2		T30	2
auto[2415919104:2550136831]	224	1			T29	2		T41	4		T61	2
auto[2550136832:2684354559]	210	1			T2	2		T28	2		T29	4
auto[2684354560:2818572287]	180	1			T28	2		T92	4		T54	2
auto[2818572288:2952790015]	180	1			T30	4		T92	2		T197	2
auto[2952790016:3087007743]	230	1			T28	2		T40	2		T114	2
auto[3087007744:3221225471]	232	1			T16	2		T17	2		T30	2
auto[3221225472:3355443199]	224	1			T14	2		T114	2		T29	8
auto[3355443200:3489660927]	224	1			T3	2		T29	2		T51	2
auto[3489660928:3623878655]	194	1			T18	2		T29	4		T30	2
auto[3623878656:3758096383]	186	1			T2	2		T16	2		T18	2
auto[3758096384:3892314111]	238	1			T19	2		T88	2		T29	2
auto[3892314112:4026531839]	216	1			T2	2		T16	2		T28	4
auto[4026531840:4160749567]	228	1			T2	2		T17	2		T19	2
auto[4160749568:4294967295]	194	1			T29	2		T64	2		T226	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	140	1			T29	4		T61	2		T133	2
auto[0:134217727]	auto[1]	70	1			T19	2		T61	2		T128	2
auto[134217728:268435455]	auto[0]	150	1			T87	2		T29	2		T196	2
auto[134217728:268435455]	auto[1]	72	1			T92	2		T61	2		T248	2
auto[268435456:402653183]	auto[0]	176	1			T87	2		T30	2		T64	8
auto[268435456:402653183]	auto[1]	56	1			T133	2		T64	2		T403	2
auto[402653184:536870911]	auto[0]	114	1			T17	2		T29	4		T196	2
auto[402653184:536870911]	auto[1]	62	1			T29	4		T53	2		T64	2
auto[536870912:671088639]	auto[0]	150	1			T29	2		T32	2		T196	2
auto[536870912:671088639]	auto[1]	66	1			T29	2		T93	2		T64	2
auto[671088640:805306367]	auto[0]	132	1			T40	2		T119	2		T136	2
auto[671088640:805306367]	auto[1]	60	1			T6	2		T59	2		T408	2
auto[805306368:939524095]	auto[0]	162	1			T16	2		T29	6		T30	2
auto[805306368:939524095]	auto[1]	74	1			T64	2		T101	2		T90	2
auto[939524096:1073741823]	auto[0]	170	1			T16	2		T19	2		T29	2
auto[939524096:1073741823]	auto[1]	70	1			T50	2		T29	2		T32	2
auto[1073741824:1207959551]	auto[0]	134	1			T119	2		T134	2		T64	2
auto[1073741824:1207959551]	auto[1]	60	1			T40	2		T29	2		T30	2
auto[1207959552:1342177279]	auto[0]	164	1			T17	2		T30	2		T41	2
auto[1207959552:1342177279]	auto[1]	50	1			T114	2		T29	2		T53	2
auto[1342177280:1476395007]	auto[0]	138	1			T17	2		T87	2		T29	2
auto[1342177280:1476395007]	auto[1]	54	1			T29	2		T92	2		T74	2
auto[1476395008:1610612735]	auto[0]	106	1			T196	2		T107	2		T101	2
auto[1476395008:1610612735]	auto[1]	92	1			T29	2		T61	2		T5	2
auto[1610612736:1744830463]	auto[0]	154	1			T14	2		T18	2		T40	2
auto[1610612736:1744830463]	auto[1]	66	1			T88	4		T30	2		T92	2
auto[1744830464:1879048191]	auto[0]	156	1			T18	2		T29	2		T51	2
auto[1744830464:1879048191]	auto[1]	50	1			T3	2		T16	2		T64	2
auto[1879048192:2013265919]	auto[0]	152	1			T28	2		T30	2		T64	4
auto[1879048192:2013265919]	auto[1]	88	1			T18	2		T88	2		T50	2
auto[2013265920:2147483647]	auto[0]	142	1			T28	2		T87	2		T29	2
auto[2013265920:2147483647]	auto[1]	88	1			T30	4		T197	2		T224	2
auto[2147483648:2281701375]	auto[0]	134	1			T19	2		T29	2		T30	6
auto[2147483648:2281701375]	auto[1]	60	1			T29	4		T30	2		T33	2
auto[2281701376:2415919103]	auto[0]	166	1			T29	2		T30	2		T51	2
auto[2281701376:2415919103]	auto[1]	68	1			T53	2		T61	2		T93	2
auto[2415919104:2550136831]	auto[0]	158	1			T29	2		T41	4		T64	6
auto[2415919104:2550136831]	auto[1]	66	1			T61	2		T278	2		T97	2
auto[2550136832:2684354559]	auto[0]	136	1			T2	2		T30	2		T119	2
auto[2550136832:2684354559]	auto[1]	74	1			T28	2		T29	4		T222	2
auto[2684354560:2818572287]	auto[0]	110	1			T28	2		T92	2		T54	2
auto[2684354560:2818572287]	auto[1]	70	1			T92	2		T109	2		T6	2
auto[2818572288:2952790015]	auto[0]	114	1			T224	2		T71	2		T260	2
auto[2818572288:2952790015]	auto[1]	66	1			T30	4		T92	2		T197	2
auto[2952790016:3087007743]	auto[0]	156	1			T28	2		T40	2		T114	2
auto[2952790016:3087007743]	auto[1]	74	1			T92	2		T134	2		T64	2
auto[3087007744:3221225471]	auto[0]	158	1			T17	2		T30	2		T64	6
auto[3087007744:3221225471]	auto[1]	74	1			T16	2		T61	2		T128	2
auto[3221225472:3355443199]	auto[0]	142	1			T29	6		T30	2		T49	2
auto[3221225472:3355443199]	auto[1]	82	1			T14	2		T114	2		T29	2
auto[3355443200:3489660927]	auto[0]	166	1			T29	2		T51	2		T133	2
auto[3355443200:3489660927]	auto[1]	58	1			T3	2		T248	2		T197	2
auto[3489660928:3623878655]	auto[0]	146	1			T18	2		T29	2		T30	2
auto[3489660928:3623878655]	auto[1]	48	1			T29	2		T61	2		T152	2
auto[3623878656:3758096383]	auto[0]	128	1			T16	2		T18	2		T28	2
auto[3623878656:3758096383]	auto[1]	58	1			T2	2		T29	4		T30	2
auto[3758096384:3892314111]	auto[0]	168	1			T19	2		T196	2		T61	2
auto[3758096384:3892314111]	auto[1]	70	1			T88	2		T29	2		T225	2
auto[3892314112:4026531839]	auto[0]	152	1			T16	2		T28	2		T29	4
auto[3892314112:4026531839]	auto[1]	64	1			T2	2		T28	2		T50	2
auto[4026531840:4160749567]	auto[0]	150	1			T2	2		T19	2		T28	2
auto[4026531840:4160749567]	auto[1]	78	1			T17	2		T88	2		T50	2
auto[4160749568:4294967295]	auto[0]	138	1			T29	2		T64	2		T226	2
auto[4160749568:4294967295]	auto[1]	56	1			T65	2		T97	2		T128	2