Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.04 97.99 98.61 100.00 99.02 98.41 91.19


Total test records in report: 1084
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T1009 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3021735333 May 19 01:48:54 PM PDT 24 May 19 01:49:00 PM PDT 24 123844451 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.471215193 May 19 01:48:48 PM PDT 24 May 19 01:48:51 PM PDT 24 11195547 ps
T1011 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.104039759 May 19 01:48:51 PM PDT 24 May 19 01:48:58 PM PDT 24 162020524 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2143448616 May 19 01:48:51 PM PDT 24 May 19 01:48:57 PM PDT 24 227610319 ps
T170 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3020143534 May 19 01:48:46 PM PDT 24 May 19 01:48:52 PM PDT 24 146083109 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3829690420 May 19 01:48:36 PM PDT 24 May 19 01:48:41 PM PDT 24 23179757 ps
T1014 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4109245465 May 19 01:48:59 PM PDT 24 May 19 01:49:01 PM PDT 24 138271328 ps
T1015 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.205565169 May 19 01:48:39 PM PDT 24 May 19 01:48:46 PM PDT 24 131137326 ps
T1016 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2242153768 May 19 01:49:02 PM PDT 24 May 19 01:49:04 PM PDT 24 23691802 ps
T169 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1860548166 May 19 01:49:00 PM PDT 24 May 19 01:49:05 PM PDT 24 185798178 ps
T158 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3764509206 May 19 01:48:54 PM PDT 24 May 19 01:49:01 PM PDT 24 178458738 ps
T1017 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2622367532 May 19 01:48:52 PM PDT 24 May 19 01:48:57 PM PDT 24 67379621 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2935066834 May 19 01:48:39 PM PDT 24 May 19 01:48:59 PM PDT 24 1294130566 ps
T179 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1313125842 May 19 01:48:44 PM PDT 24 May 19 01:48:49 PM PDT 24 146574939 ps
T1019 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1789756736 May 19 01:49:22 PM PDT 24 May 19 01:49:24 PM PDT 24 11786868 ps
T1020 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1465683110 May 19 01:48:45 PM PDT 24 May 19 01:48:49 PM PDT 24 204442274 ps
T1021 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.945219478 May 19 01:48:54 PM PDT 24 May 19 01:48:59 PM PDT 24 199223557 ps
T1022 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3877393007 May 19 01:48:54 PM PDT 24 May 19 01:48:59 PM PDT 24 78669503 ps
T1023 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1152286696 May 19 01:49:16 PM PDT 24 May 19 01:49:17 PM PDT 24 35834867 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.552508739 May 19 01:48:46 PM PDT 24 May 19 01:48:49 PM PDT 24 437530708 ps
T1025 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4106003510 May 19 01:48:38 PM PDT 24 May 19 01:48:42 PM PDT 24 15344925 ps
T1026 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1184507773 May 19 01:48:51 PM PDT 24 May 19 01:49:03 PM PDT 24 870253796 ps
T1027 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2121521893 May 19 01:48:59 PM PDT 24 May 19 01:49:01 PM PDT 24 32082811 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1388115658 May 19 01:48:41 PM PDT 24 May 19 01:49:16 PM PDT 24 4754981940 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2178923039 May 19 01:48:40 PM PDT 24 May 19 01:48:46 PM PDT 24 38593003 ps
T1030 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1110583041 May 19 01:48:53 PM PDT 24 May 19 01:48:58 PM PDT 24 391513776 ps
T1031 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2401915329 May 19 01:49:07 PM PDT 24 May 19 01:49:09 PM PDT 24 57639302 ps
T1032 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.254967566 May 19 01:48:54 PM PDT 24 May 19 01:48:59 PM PDT 24 322133403 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.420617980 May 19 01:48:48 PM PDT 24 May 19 01:48:50 PM PDT 24 12016957 ps
T1034 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1123099719 May 19 01:48:59 PM PDT 24 May 19 01:49:01 PM PDT 24 14722209 ps
T1035 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.636227688 May 19 01:48:52 PM PDT 24 May 19 01:48:56 PM PDT 24 22854859 ps
T1036 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.412730092 May 19 01:48:58 PM PDT 24 May 19 01:49:05 PM PDT 24 493806824 ps
T1037 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1493729377 May 19 01:49:03 PM PDT 24 May 19 01:49:05 PM PDT 24 90055283 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3197264668 May 19 01:48:50 PM PDT 24 May 19 01:48:56 PM PDT 24 92062372 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2198990437 May 19 01:48:51 PM PDT 24 May 19 01:48:56 PM PDT 24 97267221 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1982255110 May 19 01:48:35 PM PDT 24 May 19 01:48:39 PM PDT 24 143034618 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3111749540 May 19 01:48:38 PM PDT 24 May 19 01:48:43 PM PDT 24 102799121 ps
T1042 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3337682662 May 19 01:49:01 PM PDT 24 May 19 01:49:08 PM PDT 24 123703937 ps
T1043 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3419128374 May 19 01:49:11 PM PDT 24 May 19 01:49:13 PM PDT 24 35262583 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1292254354 May 19 01:48:43 PM PDT 24 May 19 01:48:50 PM PDT 24 816983646 ps
T1045 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.904062872 May 19 01:49:02 PM PDT 24 May 19 01:49:11 PM PDT 24 295017515 ps
T1046 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3832767574 May 19 01:48:59 PM PDT 24 May 19 01:49:02 PM PDT 24 647539408 ps
T1047 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1207213561 May 19 01:48:54 PM PDT 24 May 19 01:48:59 PM PDT 24 45045811 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.747733834 May 19 01:48:31 PM PDT 24 May 19 01:48:36 PM PDT 24 134578375 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.662690269 May 19 01:48:47 PM PDT 24 May 19 01:48:50 PM PDT 24 25635443 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3049087921 May 19 01:48:34 PM PDT 24 May 19 01:49:02 PM PDT 24 3588521543 ps
T1051 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3305915053 May 19 01:48:42 PM PDT 24 May 19 01:48:45 PM PDT 24 21725738 ps
T1052 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3864970868 May 19 01:48:51 PM PDT 24 May 19 01:48:55 PM PDT 24 13668586 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3680107043 May 19 01:48:41 PM PDT 24 May 19 01:49:00 PM PDT 24 510928160 ps
T1054 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3017270475 May 19 01:49:05 PM PDT 24 May 19 01:49:07 PM PDT 24 44062181 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2601256572 May 19 01:48:47 PM PDT 24 May 19 01:48:50 PM PDT 24 86439680 ps
T166 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.887444624 May 19 01:48:36 PM PDT 24 May 19 01:48:48 PM PDT 24 268504769 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1303805491 May 19 01:48:58 PM PDT 24 May 19 01:49:01 PM PDT 24 69104393 ps
T1057 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2225753460 May 19 01:48:45 PM PDT 24 May 19 01:48:49 PM PDT 24 58078007 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3028131000 May 19 01:49:01 PM PDT 24 May 19 01:49:06 PM PDT 24 1386770902 ps
T1059 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1543758588 May 19 01:48:47 PM PDT 24 May 19 01:48:51 PM PDT 24 98345654 ps
T1060 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4265731404 May 19 01:48:57 PM PDT 24 May 19 01:49:01 PM PDT 24 67557769 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3472073885 May 19 01:49:03 PM PDT 24 May 19 01:49:18 PM PDT 24 1589230236 ps
T1062 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.315465879 May 19 01:49:00 PM PDT 24 May 19 01:49:02 PM PDT 24 36300105 ps
T1063 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1276566161 May 19 01:48:40 PM PDT 24 May 19 01:48:46 PM PDT 24 717678329 ps
T1064 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3086054829 May 19 01:48:44 PM PDT 24 May 19 01:48:47 PM PDT 24 128707344 ps
T159 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4143362813 May 19 01:48:50 PM PDT 24 May 19 01:49:03 PM PDT 24 3516118671 ps
T176 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.210920917 May 19 01:48:49 PM PDT 24 May 19 01:48:55 PM PDT 24 839411022 ps
T1065 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3417130195 May 19 01:48:43 PM PDT 24 May 19 01:48:46 PM PDT 24 60675425 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1354146316 May 19 01:48:50 PM PDT 24 May 19 01:48:55 PM PDT 24 383828207 ps
T1067 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2683726490 May 19 01:48:50 PM PDT 24 May 19 01:48:54 PM PDT 24 97462692 ps
T163 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3655702190 May 19 01:48:51 PM PDT 24 May 19 01:48:58 PM PDT 24 495707927 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3439825576 May 19 01:48:35 PM PDT 24 May 19 01:48:38 PM PDT 24 69482770 ps
T1069 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1630662303 May 19 01:48:49 PM PDT 24 May 19 01:48:53 PM PDT 24 348756591 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1043647604 May 19 01:48:41 PM PDT 24 May 19 01:48:46 PM PDT 24 137917869 ps
T1071 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2967323548 May 19 01:49:22 PM PDT 24 May 19 01:49:26 PM PDT 24 77516897 ps
T1072 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2792941073 May 19 01:48:48 PM PDT 24 May 19 01:48:51 PM PDT 24 13720903 ps
T1073 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2320084838 May 19 01:49:01 PM PDT 24 May 19 01:49:03 PM PDT 24 42979534 ps
T1074 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4080290021 May 19 01:48:51 PM PDT 24 May 19 01:48:57 PM PDT 24 162165568 ps
T1075 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.973806644 May 19 01:48:55 PM PDT 24 May 19 01:48:59 PM PDT 24 31556049 ps
T1076 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1593136610 May 19 01:48:55 PM PDT 24 May 19 01:48:59 PM PDT 24 222423503 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3673126889 May 19 01:48:40 PM PDT 24 May 19 01:48:49 PM PDT 24 268398900 ps
T1078 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3102903505 May 19 01:49:02 PM PDT 24 May 19 01:49:04 PM PDT 24 9671083 ps
T1079 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2720290655 May 19 01:48:38 PM PDT 24 May 19 01:48:46 PM PDT 24 196695687 ps
T1080 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1781470389 May 19 01:48:38 PM PDT 24 May 19 01:48:45 PM PDT 24 427509166 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1567402185 May 19 01:48:54 PM PDT 24 May 19 01:48:57 PM PDT 24 11134508 ps
T1082 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3832547648 May 19 01:48:41 PM PDT 24 May 19 01:48:45 PM PDT 24 29776808 ps
T1083 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1897862724 May 19 01:49:01 PM PDT 24 May 19 01:49:03 PM PDT 24 370768399 ps
T1084 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1062457262 May 19 01:48:53 PM PDT 24 May 19 01:48:58 PM PDT 24 71588620 ps

Test location /workspace/coverage/default/44.keymgr_sideload_protect.516521648
Short name T18
Test name
Test status
Simulation time 2744119473 ps
CPU time 19 seconds
Started May 19 01:51:25 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 218312 kb
Host smart-dea557a7-23da-4ab7-a02f-c11be28929b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516521648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.516521648
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4098791085
Short name T29
Test name
Test status
Simulation time 32675916842 ps
CPU time 336.63 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 217476 kb
Host smart-d534095d-57ec-425f-925e-8ab540e77cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098791085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4098791085
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3313931876
Short name T61
Test name
Test status
Simulation time 2922234794 ps
CPU time 22.33 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:46 PM PDT 24
Peak memory 223340 kb
Host smart-751c541b-8112-451d-88b7-ab22fc3a8fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313931876 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3313931876
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1204381308
Short name T11
Test name
Test status
Simulation time 1169525322 ps
CPU time 9.19 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:51 PM PDT 24
Peak memory 238272 kb
Host smart-fda46aa7-368a-4e2d-969f-c3907559352c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204381308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1204381308
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1146284711
Short name T59
Test name
Test status
Simulation time 5296710937 ps
CPU time 157.64 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:54:09 PM PDT 24
Peak memory 222388 kb
Host smart-1222e19a-038b-4b7b-818b-c6382483e443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146284711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1146284711
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3868239463
Short name T2
Test name
Test status
Simulation time 231954469 ps
CPU time 11.79 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 222428 kb
Host smart-950bfb07-4d2c-4d6f-ba96-797201ff0364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868239463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3868239463
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2001734107
Short name T117
Test name
Test status
Simulation time 1080827201 ps
CPU time 16.53 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:49:09 PM PDT 24
Peak memory 214252 kb
Host smart-5962faa4-a22f-45fa-ae63-22d5908b1cfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001734107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2001734107
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3288434399
Short name T64
Test name
Test status
Simulation time 445585617 ps
CPU time 21.84 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 222456 kb
Host smart-bd49adb0-60d5-4eb0-8093-86460e31ee75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288434399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3288434399
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.977036025
Short name T74
Test name
Test status
Simulation time 16720431457 ps
CPU time 30.44 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 217828 kb
Host smart-181efce0-5154-488a-b1b2-81b4024753ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977036025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.977036025
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1127389905
Short name T16
Test name
Test status
Simulation time 168195805 ps
CPU time 3.19 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 214320 kb
Host smart-a0e3ec2d-d39b-429a-8d68-d32d9aa67673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127389905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1127389905
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.207241534
Short name T8
Test name
Test status
Simulation time 107663030 ps
CPU time 3 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 214708 kb
Host smart-26fdb4b5-ec26-4552-945d-93f20bb31156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207241534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.207241534
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1826538234
Short name T400
Test name
Test status
Simulation time 7620156636 ps
CPU time 99.83 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:52:58 PM PDT 24
Peak memory 222600 kb
Host smart-e5772084-af54-4eeb-9469-4c28e67cf844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826538234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1826538234
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2514491957
Short name T119
Test name
Test status
Simulation time 442482891 ps
CPU time 12.1 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 215260 kb
Host smart-d8e6d60e-1f7a-4d13-a96b-7120bc17294c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514491957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2514491957
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2305364587
Short name T26
Test name
Test status
Simulation time 162047013 ps
CPU time 4.46 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 219188 kb
Host smart-996420e0-187d-420d-b3e0-484fd9d5e4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305364587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2305364587
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3798824345
Short name T128
Test name
Test status
Simulation time 2411424135 ps
CPU time 25.49 seconds
Started May 19 01:49:55 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 222640 kb
Host smart-50520beb-5cb2-45cc-922c-ed2a92d4429f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798824345 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3798824345
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3682451636
Short name T410
Test name
Test status
Simulation time 948313262 ps
CPU time 14.01 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:48 PM PDT 24
Peak memory 215888 kb
Host smart-0aedc3ee-c883-495b-8c1f-154f38280189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682451636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3682451636
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2436218799
Short name T41
Test name
Test status
Simulation time 813667164 ps
CPU time 5.64 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:45 PM PDT 24
Peak memory 214332 kb
Host smart-063ae18e-b436-47d1-be84-12bc4804fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436218799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2436218799
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.929919967
Short name T360
Test name
Test status
Simulation time 213169862 ps
CPU time 11.76 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 214592 kb
Host smart-f4b85d05-8641-40cd-8615-5026b445458b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929919967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.929919967
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1982291801
Short name T30
Test name
Test status
Simulation time 1763269775 ps
CPU time 51.71 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:50:45 PM PDT 24
Peak memory 222404 kb
Host smart-2a500357-8bc9-4db4-89a0-f980b67a5423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982291801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1982291801
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3797187051
Short name T4
Test name
Test status
Simulation time 299555322 ps
CPU time 3.15 seconds
Started May 19 01:51:32 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 210380 kb
Host smart-c885866c-0d59-4366-819e-18313c126856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797187051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3797187051
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2467438300
Short name T24
Test name
Test status
Simulation time 72213340 ps
CPU time 2.96 seconds
Started May 19 01:51:41 PM PDT 24
Finished May 19 01:51:44 PM PDT 24
Peak memory 214768 kb
Host smart-092968a6-690d-4ede-b06d-30f8c0f6de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467438300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2467438300
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1361994785
Short name T356
Test name
Test status
Simulation time 1864459689 ps
CPU time 91.15 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 222512 kb
Host smart-ec92f768-9b5c-4fb8-a4fe-2b49c7089323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361994785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1361994785
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2266869843
Short name T152
Test name
Test status
Simulation time 302648045 ps
CPU time 3.32 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 217860 kb
Host smart-3ceebf26-7306-435a-a030-698f292a1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266869843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2266869843
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1730865909
Short name T121
Test name
Test status
Simulation time 286452038 ps
CPU time 2.91 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 214344 kb
Host smart-aad3005b-70b9-4a8b-a705-d2edacc594d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730865909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1730865909
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1182729479
Short name T212
Test name
Test status
Simulation time 236000351 ps
CPU time 3.36 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 214328 kb
Host smart-41e67201-c1a6-4ce0-9138-1b15c4421fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182729479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1182729479
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.352613036
Short name T136
Test name
Test status
Simulation time 548653389 ps
CPU time 6.48 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 215272 kb
Host smart-e6692462-0832-4303-8723-b46727bd0676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352613036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.352613036
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4093616135
Short name T188
Test name
Test status
Simulation time 9167790948 ps
CPU time 55.26 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 216972 kb
Host smart-629fc24c-5317-4659-a90d-e020797121f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093616135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4093616135
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1431495535
Short name T106
Test name
Test status
Simulation time 16726102 ps
CPU time 0.94 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 206116 kb
Host smart-6fccf593-061f-4883-8ce1-78fbe70229ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431495535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1431495535
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1814262289
Short name T243
Test name
Test status
Simulation time 6720965856 ps
CPU time 48.12 seconds
Started May 19 01:49:49 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 214980 kb
Host smart-f05a5f8f-850d-4376-b6c8-4ab33c22a274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814262289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1814262289
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2203786571
Short name T162
Test name
Test status
Simulation time 482855871 ps
CPU time 8.08 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 214192 kb
Host smart-800fb2e9-04e8-4ec0-b7f7-b844c46b3ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203786571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2203786571
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2224400270
Short name T69
Test name
Test status
Simulation time 948311130 ps
CPU time 34.27 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 222472 kb
Host smart-c6b7bca0-40c3-4855-a341-673db6a64194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224400270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2224400270
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1503319722
Short name T54
Test name
Test status
Simulation time 5198151224 ps
CPU time 18.79 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 217160 kb
Host smart-80114d58-561f-452c-ad35-60eae43880a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503319722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1503319722
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.477239070
Short name T341
Test name
Test status
Simulation time 292990522 ps
CPU time 4.08 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 214352 kb
Host smart-82e817e6-ff92-486e-afde-30c62bcecbb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477239070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.477239070
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1199675326
Short name T319
Test name
Test status
Simulation time 110201659 ps
CPU time 5.61 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 207744 kb
Host smart-06ca172a-25cd-4706-a98f-6b2d45f4ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199675326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1199675326
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1420482533
Short name T154
Test name
Test status
Simulation time 177803180 ps
CPU time 3.42 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 222992 kb
Host smart-2e02f6a5-2c18-494a-b8c8-7e8ec1070b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420482533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1420482533
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3500076948
Short name T189
Test name
Test status
Simulation time 8732838352 ps
CPU time 49.05 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 216748 kb
Host smart-44be2a82-d619-4199-b4c8-b07ff2945184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500076948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3500076948
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.402215401
Short name T153
Test name
Test status
Simulation time 291401571 ps
CPU time 3.79 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 218668 kb
Host smart-42d127c8-befc-417e-920e-0dcb1f0af61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402215401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.402215401
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3606756771
Short name T95
Test name
Test status
Simulation time 571730596 ps
CPU time 4.93 seconds
Started May 19 01:50:01 PM PDT 24
Finished May 19 01:50:06 PM PDT 24
Peak memory 222204 kb
Host smart-84680671-d38a-498d-a047-dfde569ef22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606756771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3606756771
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3372364498
Short name T231
Test name
Test status
Simulation time 8792003830 ps
CPU time 47.98 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 215464 kb
Host smart-130e9f6d-3297-4699-a206-13fb9ae066d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372364498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3372364498
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3702829790
Short name T192
Test name
Test status
Simulation time 1845971587 ps
CPU time 40.36 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 216164 kb
Host smart-b7615245-9e37-4bfe-8fb0-f71987f93cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702829790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3702829790
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.684312609
Short name T12
Test name
Test status
Simulation time 1830109955 ps
CPU time 15.91 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 239020 kb
Host smart-5c367def-9165-41d8-b5c3-64e893a692a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684312609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.684312609
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1866722554
Short name T150
Test name
Test status
Simulation time 515616249 ps
CPU time 4.31 seconds
Started May 19 01:51:11 PM PDT 24
Finished May 19 01:51:17 PM PDT 24
Peak memory 222700 kb
Host smart-d9375874-9f57-4cb1-8705-92323279bf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866722554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1866722554
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3628158416
Short name T322
Test name
Test status
Simulation time 5769393680 ps
CPU time 92.34 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 222536 kb
Host smart-69008f38-2962-43fe-ad62-7201576b3450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628158416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3628158416
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3752031700
Short name T340
Test name
Test status
Simulation time 227665792 ps
CPU time 11.6 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 222592 kb
Host smart-a1f09e6f-e139-4cde-abc2-9eb1bfd9bb14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752031700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3752031700
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.891039398
Short name T277
Test name
Test status
Simulation time 101790480 ps
CPU time 2.19 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 214388 kb
Host smart-a0392dfe-c5b7-47ca-adef-992b163756c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891039398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.891039398
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2647163005
Short name T160
Test name
Test status
Simulation time 285493858 ps
CPU time 9.53 seconds
Started May 19 01:48:55 PM PDT 24
Finished May 19 01:49:07 PM PDT 24
Peak memory 213964 kb
Host smart-98bea340-1769-47dc-8b3e-65d0aaeac762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647163005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2647163005
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.363716107
Short name T52
Test name
Test status
Simulation time 516511088 ps
CPU time 3.81 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 220012 kb
Host smart-3a997a99-63a5-4f40-b4d4-7a643eb967ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363716107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.363716107
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.768565381
Short name T180
Test name
Test status
Simulation time 43579970 ps
CPU time 2.15 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 209964 kb
Host smart-7d38e38b-5d4c-4316-9be3-1c8d1025c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768565381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.768565381
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3919455513
Short name T151
Test name
Test status
Simulation time 90360539 ps
CPU time 4.39 seconds
Started May 19 01:50:01 PM PDT 24
Finished May 19 01:50:06 PM PDT 24
Peak memory 218008 kb
Host smart-ca676385-3b28-4909-80a1-e886c62824f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919455513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3919455513
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.83432595
Short name T353
Test name
Test status
Simulation time 47395771 ps
CPU time 3.02 seconds
Started May 19 01:50:46 PM PDT 24
Finished May 19 01:50:50 PM PDT 24
Peak memory 214268 kb
Host smart-d23747ca-7232-41c9-9c84-eb99de5d8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83432595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.83432595
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2666263689
Short name T75
Test name
Test status
Simulation time 3780685293 ps
CPU time 36.15 seconds
Started May 19 01:50:45 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 222452 kb
Host smart-5c621db4-cc65-43d1-a94a-59dd421daebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666263689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2666263689
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.266687351
Short name T272
Test name
Test status
Simulation time 168279769 ps
CPU time 3.59 seconds
Started May 19 01:49:49 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 214368 kb
Host smart-c70c431b-208f-4acb-b394-991ca9f6bdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266687351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.266687351
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4143362813
Short name T159
Test name
Test status
Simulation time 3516118671 ps
CPU time 9.83 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 216976 kb
Host smart-4f9063d6-ef5b-47ae-a5fe-e372097238d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143362813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4143362813
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3323119008
Short name T164
Test name
Test status
Simulation time 62759857 ps
CPU time 3.41 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 215040 kb
Host smart-64e9d426-5ab5-4b63-8aee-f3567901389b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323119008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3323119008
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2476925500
Short name T182
Test name
Test status
Simulation time 37200435 ps
CPU time 1.61 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 214684 kb
Host smart-900ee302-d14b-432b-8fa5-e9bf476e2d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476925500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2476925500
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3850988500
Short name T149
Test name
Test status
Simulation time 335218929 ps
CPU time 4.77 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:18 PM PDT 24
Peak memory 222536 kb
Host smart-266eaa6a-46f4-457d-8e72-042da5de012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850988500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3850988500
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1192146934
Short name T5
Test name
Test status
Simulation time 389112941 ps
CPU time 23.82 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 221180 kb
Host smart-9df63200-4680-40d3-bad7-c1ac818ea4f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192146934 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1192146934
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2689144482
Short name T76
Test name
Test status
Simulation time 536838575 ps
CPU time 19.2 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:17 PM PDT 24
Peak memory 215848 kb
Host smart-8befed44-f583-4282-8239-332a31fb8ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689144482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2689144482
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.69318611
Short name T65
Test name
Test status
Simulation time 1143872549 ps
CPU time 11.84 seconds
Started May 19 01:49:38 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 220408 kb
Host smart-39f0d3d6-1767-49b3-a0d4-b82f7c1bf780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69318611 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.69318611
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2936914475
Short name T221
Test name
Test status
Simulation time 5280130769 ps
CPU time 66.47 seconds
Started May 19 01:50:58 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 214596 kb
Host smart-613078e2-2d91-4a4f-a9b9-3567ac5b7c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936914475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2936914475
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3927848978
Short name T337
Test name
Test status
Simulation time 38547857 ps
CPU time 2.33 seconds
Started May 19 01:51:39 PM PDT 24
Finished May 19 01:51:43 PM PDT 24
Peak memory 214396 kb
Host smart-8ec0c2f1-2819-4c25-a286-26c356c54c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927848978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3927848978
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3810299286
Short name T315
Test name
Test status
Simulation time 22806421785 ps
CPU time 98.97 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:53:27 PM PDT 24
Peak memory 215716 kb
Host smart-ad2c101c-3263-46b2-b02b-5551e4ce6ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810299286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3810299286
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2400214164
Short name T50
Test name
Test status
Simulation time 435780596 ps
CPU time 1.78 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 214340 kb
Host smart-93f2cbe0-89bb-400c-8813-b047187e385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400214164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2400214164
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4138162015
Short name T261
Test name
Test status
Simulation time 1706078244 ps
CPU time 32.16 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 220584 kb
Host smart-6dff859a-efb8-4b07-b97e-4b1ec4420749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138162015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4138162015
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2453286835
Short name T25
Test name
Test status
Simulation time 95415925 ps
CPU time 3.94 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 222456 kb
Host smart-76bafb05-186a-4fae-97c7-8228b94db1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453286835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2453286835
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.565311993
Short name T731
Test name
Test status
Simulation time 6925179865 ps
CPU time 75.83 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 216268 kb
Host smart-2972801d-5d4a-46e6-8d93-01217c7a09f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565311993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.565311993
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2902972232
Short name T129
Test name
Test status
Simulation time 72790944 ps
CPU time 2.82 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 210288 kb
Host smart-666f0499-32fe-4a20-ab55-fcbc86cf1037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902972232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2902972232
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1578850840
Short name T275
Test name
Test status
Simulation time 85020853 ps
CPU time 2.15 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 219296 kb
Host smart-7a9eaed1-4225-46c0-9ea6-24e5bdac35e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578850840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1578850840
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1165078663
Short name T281
Test name
Test status
Simulation time 3249163335 ps
CPU time 86.05 seconds
Started May 19 01:50:43 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 215432 kb
Host smart-a0c73a61-3c31-4d45-8746-357acd263795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165078663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1165078663
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2566656069
Short name T575
Test name
Test status
Simulation time 1830888983 ps
CPU time 40.1 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 208880 kb
Host smart-1603721c-5c33-43b7-98ae-22b587bff6e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566656069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2566656069
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.186927463
Short name T405
Test name
Test status
Simulation time 531379991 ps
CPU time 7.62 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 215044 kb
Host smart-a773c434-eecc-426d-afc3-0a41903fdfcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186927463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.186927463
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2020128002
Short name T347
Test name
Test status
Simulation time 3718962931 ps
CPU time 20.52 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:41 PM PDT 24
Peak memory 221804 kb
Host smart-f685e502-ba7e-4548-a6bf-063317107253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020128002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2020128002
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2932597886
Short name T99
Test name
Test status
Simulation time 104301628 ps
CPU time 3.66 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 208172 kb
Host smart-cf89db15-7505-4197-91ec-ea8ae724176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932597886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2932597886
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3805276815
Short name T784
Test name
Test status
Simulation time 1310386561 ps
CPU time 4.47 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 220776 kb
Host smart-27fe5ab3-9c01-4db5-9afc-6d6bf07ee4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805276815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3805276815
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1293513968
Short name T178
Test name
Test status
Simulation time 236657552 ps
CPU time 5.09 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 213932 kb
Host smart-f080994a-6a09-4795-8a34-2714017a2530
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293513968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1293513968
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4223343527
Short name T177
Test name
Test status
Simulation time 758844111 ps
CPU time 3.74 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 215184 kb
Host smart-79d3f04f-09f6-4417-a31e-f9f5e5c27157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223343527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.4223343527
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.210920917
Short name T176
Test name
Test status
Simulation time 839411022 ps
CPU time 4.02 seconds
Started May 19 01:48:49 PM PDT 24
Finished May 19 01:48:55 PM PDT 24
Peak memory 213968 kb
Host smart-ef63bcdd-ddaf-408f-add8-5ff61284c765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210920917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.210920917
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.154016587
Short name T174
Test name
Test status
Simulation time 147537022 ps
CPU time 6.01 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:09 PM PDT 24
Peak memory 213920 kb
Host smart-2bbb787b-eec0-4e1c-a27a-481be002f7d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154016587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.154016587
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1596793731
Short name T167
Test name
Test status
Simulation time 81834124 ps
CPU time 2.25 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 210032 kb
Host smart-54cc238e-66f0-4112-9c43-0bd0666048b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596793731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1596793731
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.108450319
Short name T148
Test name
Test status
Simulation time 151417960 ps
CPU time 4.71 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 218164 kb
Host smart-57473dda-42b8-4f6f-9325-0c0cbec77d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108450319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.108450319
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2862602271
Short name T155
Test name
Test status
Simulation time 254718932 ps
CPU time 2.57 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:15 PM PDT 24
Peak memory 217604 kb
Host smart-67cf8e67-a145-4061-8799-17c9b7213ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862602271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2862602271
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1164340443
Short name T43
Test name
Test status
Simulation time 147897615 ps
CPU time 2.48 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 217148 kb
Host smart-8e5aed50-761e-4299-9f3e-719e7fa0d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164340443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1164340443
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_random.3569151910
Short name T308
Test name
Test status
Simulation time 579251348 ps
CPU time 6.59 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 214312 kb
Host smart-a9052f61-eb43-47f7-a9bb-a2adb3e85234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569151910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3569151910
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1836177057
Short name T813
Test name
Test status
Simulation time 181618018 ps
CPU time 1.45 seconds
Started May 19 01:49:33 PM PDT 24
Finished May 19 01:49:38 PM PDT 24
Peak memory 209804 kb
Host smart-20fa1974-f85f-473f-9c20-b6ccb61b8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836177057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1836177057
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.298092170
Short name T296
Test name
Test status
Simulation time 259363781 ps
CPU time 3.55 seconds
Started May 19 01:50:21 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 214420 kb
Host smart-b7acdd58-f13f-415c-970d-57cae80b22fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298092170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.298092170
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1512555035
Short name T621
Test name
Test status
Simulation time 72992452 ps
CPU time 2.6 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 207588 kb
Host smart-7e04a5ce-78dc-48b0-bc52-eea616354a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512555035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1512555035
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.183778507
Short name T368
Test name
Test status
Simulation time 61558788 ps
CPU time 1.76 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 214272 kb
Host smart-4342ac64-b17c-4020-b808-74bce80c8a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183778507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.183778507
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1704128694
Short name T771
Test name
Test status
Simulation time 124231861 ps
CPU time 4.2 seconds
Started May 19 01:50:20 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 208688 kb
Host smart-6dc5dfed-174b-43fb-9819-c77a0d000716
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704128694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1704128694
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3179412355
Short name T211
Test name
Test status
Simulation time 7890927848 ps
CPU time 128.84 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:52:45 PM PDT 24
Peak memory 217924 kb
Host smart-bc41c121-6f36-4e4a-899b-ada33c402f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179412355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3179412355
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.685558869
Short name T210
Test name
Test status
Simulation time 1235838761 ps
CPU time 23.67 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 210008 kb
Host smart-62799ffd-9838-41af-b072-a8c0253e5331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685558869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.685558869
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.793274950
Short name T386
Test name
Test status
Simulation time 126478073 ps
CPU time 6.13 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 214824 kb
Host smart-deee5b16-39af-4fcc-ac8f-9780ed18bf88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793274950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.793274950
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3907710619
Short name T330
Test name
Test status
Simulation time 39577610 ps
CPU time 3.01 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 207360 kb
Host smart-b9d89913-202d-414a-9e7b-8e220b7eb2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907710619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3907710619
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4067902101
Short name T327
Test name
Test status
Simulation time 97911080 ps
CPU time 3.1 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:50:57 PM PDT 24
Peak memory 214380 kb
Host smart-098d1398-ef00-4e07-a95e-22d6c031acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067902101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4067902101
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.170454787
Short name T362
Test name
Test status
Simulation time 79415290 ps
CPU time 4.1 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:08 PM PDT 24
Peak memory 215732 kb
Host smart-fb95aba5-b125-4e77-b8a7-7bcc705f256f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170454787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.170454787
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.941564783
Short name T301
Test name
Test status
Simulation time 676593140 ps
CPU time 10.79 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 215104 kb
Host smart-a6ac95d0-0188-482b-9aef-d62ed6788283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941564783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.941564783
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1055519369
Short name T333
Test name
Test status
Simulation time 533200057 ps
CPU time 3.38 seconds
Started May 19 01:51:35 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 214560 kb
Host smart-cec12aa5-49aa-4d9c-adf8-92c83c5efe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055519369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1055519369
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3122864908
Short name T988
Test name
Test status
Simulation time 506873473 ps
CPU time 8.7 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 205788 kb
Host smart-9269f310-ae2e-4ae2-9c64-386837e76faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122864908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
122864908
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3049087921
Short name T1050
Test name
Test status
Simulation time 3588521543 ps
CPU time 25.42 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 205784 kb
Host smart-7417499e-9ea4-4ec4-97dd-95de2e29b23d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049087921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
049087921
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.722670633
Short name T937
Test name
Test status
Simulation time 106856174 ps
CPU time 1.19 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 205668 kb
Host smart-94f61cda-f2f2-4d22-8a0f-425c3d2db1fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722670633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.722670633
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3111749540
Short name T1041
Test name
Test status
Simulation time 102799121 ps
CPU time 1.5 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 214048 kb
Host smart-325bd7d3-52ce-4ca1-b21f-f8cc5e60fae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111749540 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3111749540
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1763563331
Short name T143
Test name
Test status
Simulation time 35369549 ps
CPU time 0.98 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 205660 kb
Host smart-ca78bc5b-7378-4668-b464-5cebec69f923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763563331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1763563331
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3439825576
Short name T1068
Test name
Test status
Simulation time 69482770 ps
CPU time 0.81 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 205436 kb
Host smart-de008c04-2dee-44e5-b8cd-780352870696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439825576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3439825576
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3435594666
Short name T998
Test name
Test status
Simulation time 37150333 ps
CPU time 2.18 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 205740 kb
Host smart-2b2aa256-7db5-4adb-9109-1966d012cb4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435594666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3435594666
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.747733834
Short name T1048
Test name
Test status
Simulation time 134578375 ps
CPU time 4.02 seconds
Started May 19 01:48:31 PM PDT 24
Finished May 19 01:48:36 PM PDT 24
Peak memory 214376 kb
Host smart-a04a6537-b925-4fa9-a1e1-756399f44b64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747733834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.747733834
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2028652167
Short name T1000
Test name
Test status
Simulation time 146232578 ps
CPU time 6.81 seconds
Started May 19 01:48:33 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 222468 kb
Host smart-4ed82600-f6b4-4f0a-960b-07787a29d4ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028652167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2028652167
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.548686982
Short name T945
Test name
Test status
Simulation time 115358631 ps
CPU time 2.1 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 213888 kb
Host smart-df3a68a1-5e01-45a4-9aa4-89a2d44e759d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548686982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.548686982
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2019983691
Short name T168
Test name
Test status
Simulation time 335411232 ps
CPU time 4.46 seconds
Started May 19 01:48:32 PM PDT 24
Finished May 19 01:48:37 PM PDT 24
Peak memory 213964 kb
Host smart-994b908f-70f7-4b20-b88a-8d4af964a0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019983691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2019983691
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.109621156
Short name T986
Test name
Test status
Simulation time 1827238327 ps
CPU time 17.17 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205700 kb
Host smart-568a20ae-d1ed-40b7-a9fd-fb723ed3a057
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109621156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.109621156
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1388115658
Short name T1028
Test name
Test status
Simulation time 4754981940 ps
CPU time 32.34 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:49:16 PM PDT 24
Peak memory 205800 kb
Host smart-a7fa2989-f199-489d-b7ca-e5867d123b3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388115658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
388115658
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2755928351
Short name T925
Test name
Test status
Simulation time 82892007 ps
CPU time 1.06 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 206032 kb
Host smart-115804c5-5f3b-4a53-9af9-b2ac61c7bde0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755928351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
755928351
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1045664589
Short name T935
Test name
Test status
Simulation time 128441267 ps
CPU time 1.65 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 205876 kb
Host smart-30fac859-518e-4a91-b9c7-a4988dd0d2e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045664589 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1045664589
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4106003510
Short name T1025
Test name
Test status
Simulation time 15344925 ps
CPU time 1.23 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 205920 kb
Host smart-f3cb3585-d0d3-498d-97eb-b8d37abc1040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106003510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4106003510
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1735467455
Short name T942
Test name
Test status
Simulation time 36403952 ps
CPU time 0.78 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 205524 kb
Host smart-da67c8e6-a0bf-486b-9555-43700dbd4f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735467455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1735467455
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1982255110
Short name T1040
Test name
Test status
Simulation time 143034618 ps
CPU time 1.77 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 206048 kb
Host smart-2270e989-627b-4ef4-a1fc-ba9a6fe65c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982255110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1982255110
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2720290655
Short name T1079
Test name
Test status
Simulation time 196695687 ps
CPU time 5.29 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 214304 kb
Host smart-b123077a-f378-4bb7-8004-6c4a4461eedb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720290655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2720290655
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.529110268
Short name T991
Test name
Test status
Simulation time 57201143 ps
CPU time 2.59 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 213940 kb
Host smart-2cdbc89b-1f78-44a8-9c95-a651ac3bb95e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529110268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.529110268
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.887444624
Short name T166
Test name
Test status
Simulation time 268504769 ps
CPU time 9.67 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:48 PM PDT 24
Peak memory 213988 kb
Host smart-3a779c9a-2d05-4700-83ad-3c71617b2654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887444624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
887444624
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2683726490
Short name T1067
Test name
Test status
Simulation time 97462692 ps
CPU time 2.12 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:54 PM PDT 24
Peak memory 213932 kb
Host smart-a755f15c-8faf-4c18-8bbd-9508f41a69ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683726490 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2683726490
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1370420917
Short name T952
Test name
Test status
Simulation time 24157012 ps
CPU time 1.04 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 205660 kb
Host smart-ad305bd0-9e2a-4948-b1d5-9f288361446b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370420917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1370420917
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2792941073
Short name T1072
Test name
Test status
Simulation time 13720903 ps
CPU time 0.85 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205512 kb
Host smart-262ce412-e5e7-4844-97ef-5ecc1ae62487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792941073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2792941073
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.982648453
Short name T992
Test name
Test status
Simulation time 160291555 ps
CPU time 1.97 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205756 kb
Host smart-c9842a70-48ad-4a37-a7a9-c0cebcd93d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982648453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.982648453
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2793254061
Short name T960
Test name
Test status
Simulation time 152846834 ps
CPU time 3.99 seconds
Started May 19 01:48:44 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 214328 kb
Host smart-13ffb692-dc73-4206-b8b4-61eb78ea2dc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793254061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2793254061
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.492536538
Short name T976
Test name
Test status
Simulation time 82454727 ps
CPU time 3.73 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 214368 kb
Host smart-2cd82b32-c102-45d7-8a3a-3c6571bc2d7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492536538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.492536538
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2860203927
Short name T946
Test name
Test status
Simulation time 350386555 ps
CPU time 3.94 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:54 PM PDT 24
Peak memory 214232 kb
Host smart-12bba6e6-cdac-49ad-9a7d-1ee8b0beae39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860203927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2860203927
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1968279509
Short name T172
Test name
Test status
Simulation time 197075922 ps
CPU time 3.15 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:55 PM PDT 24
Peak memory 205680 kb
Host smart-fefbf5bd-5ec6-4fac-8c75-0282acdd71d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968279509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1968279509
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3332374384
Short name T981
Test name
Test status
Simulation time 64475792 ps
CPU time 1.56 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:54 PM PDT 24
Peak memory 222168 kb
Host smart-c3191362-978e-4244-becd-c33241dd6133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332374384 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3332374384
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1879496961
Short name T1008
Test name
Test status
Simulation time 32900454 ps
CPU time 0.98 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 205628 kb
Host smart-96c0f086-0f7b-4825-9773-778fa0f0e810
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879496961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1879496961
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.400177584
Short name T965
Test name
Test status
Simulation time 20083884 ps
CPU time 0.85 seconds
Started May 19 01:48:53 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 205404 kb
Host smart-268f2764-12ab-4df0-b877-deba69d3294b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400177584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.400177584
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3197264668
Short name T1038
Test name
Test status
Simulation time 92062372 ps
CPU time 3.45 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205728 kb
Host smart-cb7e5e57-a587-4eb0-bece-633f8518690b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197264668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3197264668
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1045084148
Short name T123
Test name
Test status
Simulation time 53831712 ps
CPU time 2.55 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 214304 kb
Host smart-744c8ca8-3b34-45ea-84a8-6fed1cc411be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045084148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1045084148
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3866581188
Short name T953
Test name
Test status
Simulation time 75581069 ps
CPU time 3.09 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 213936 kb
Host smart-abfb861f-f264-4759-a309-98308190ee55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866581188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3866581188
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4176674261
Short name T967
Test name
Test status
Simulation time 43679730 ps
CPU time 1.74 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 219016 kb
Host smart-051ecac9-1d25-4ee3-a9fd-4c5c93fe4b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176674261 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.4176674261
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.636227688
Short name T1035
Test name
Test status
Simulation time 22854859 ps
CPU time 1.07 seconds
Started May 19 01:48:52 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205652 kb
Host smart-e596326c-8326-409b-b7bd-feb6ad9068d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636227688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.636227688
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4188855213
Short name T932
Test name
Test status
Simulation time 31443565 ps
CPU time 0.7 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 205476 kb
Host smart-fdc6ef0c-49e7-4ada-aced-0daa676ab51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188855213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4188855213
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1354146316
Short name T1066
Test name
Test status
Simulation time 383828207 ps
CPU time 2.42 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:55 PM PDT 24
Peak memory 205700 kb
Host smart-67747ee2-60de-416c-bff5-e2ca0427bad7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354146316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1354146316
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1110583041
Short name T1030
Test name
Test status
Simulation time 391513776 ps
CPU time 2.7 seconds
Started May 19 01:48:53 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 214336 kb
Host smart-bb58ba6b-5084-45cf-a902-ff86cbe1f35a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110583041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1110583041
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1184507773
Short name T1026
Test name
Test status
Simulation time 870253796 ps
CPU time 9.21 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 220560 kb
Host smart-356874af-3bcb-41ea-8751-1905d6a05579
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184507773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1184507773
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2198990437
Short name T1039
Test name
Test status
Simulation time 97267221 ps
CPU time 2.45 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 213976 kb
Host smart-90bea740-bf7c-4462-8e76-386a26973d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198990437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2198990437
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3655702190
Short name T163
Test name
Test status
Simulation time 495707927 ps
CPU time 3.79 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 213876 kb
Host smart-63cbc9c5-420c-4400-bac0-2ff3127e3f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655702190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3655702190
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4117806516
Short name T968
Test name
Test status
Simulation time 60265781 ps
CPU time 1.47 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 214008 kb
Host smart-0934f87e-5e89-4ca1-8ba5-c786fd46dd51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117806516 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4117806516
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1291085081
Short name T142
Test name
Test status
Simulation time 27932773 ps
CPU time 1.09 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:55 PM PDT 24
Peak memory 205788 kb
Host smart-1c643234-30b3-4157-83cf-c7dba6ccc375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291085081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1291085081
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3743588229
Short name T930
Test name
Test status
Simulation time 21371276 ps
CPU time 0.88 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:54 PM PDT 24
Peak memory 205784 kb
Host smart-a9225387-778c-479c-8532-7db4146423b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743588229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3743588229
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4294389021
Short name T964
Test name
Test status
Simulation time 101135459 ps
CPU time 1.91 seconds
Started May 19 01:48:52 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205656 kb
Host smart-86ddbc35-c9c2-4e19-b63a-8330e0de2014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294389021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4294389021
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1629589572
Short name T963
Test name
Test status
Simulation time 140634906 ps
CPU time 4.25 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 214332 kb
Host smart-1a8672d2-3384-449a-8058-6698f0d385f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629589572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1629589572
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4218612488
Short name T118
Test name
Test status
Simulation time 197124463 ps
CPU time 3.38 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 214276 kb
Host smart-da78fcf0-ae82-4708-92f0-1cf4408e1839
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218612488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4218612488
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.954191202
Short name T950
Test name
Test status
Simulation time 286508044 ps
CPU time 2.68 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 213900 kb
Host smart-5169f5bf-ac1b-4e53-ac82-ac349d58a9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954191202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.954191202
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1207213561
Short name T1047
Test name
Test status
Simulation time 45045811 ps
CPU time 2.08 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214004 kb
Host smart-b1bf7de5-d6e3-4167-bae0-faca13e4a639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207213561 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1207213561
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.842578287
Short name T954
Test name
Test status
Simulation time 23978186 ps
CPU time 0.98 seconds
Started May 19 01:48:52 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205616 kb
Host smart-391f9fef-ecf0-4da6-9526-215983cfadfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842578287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.842578287
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3864970868
Short name T1052
Test name
Test status
Simulation time 13668586 ps
CPU time 0.9 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:55 PM PDT 24
Peak memory 205400 kb
Host smart-eae5b3ef-c58f-499e-b491-8861c1096a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864970868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3864970868
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2622367532
Short name T1017
Test name
Test status
Simulation time 67379621 ps
CPU time 2.29 seconds
Started May 19 01:48:52 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 205672 kb
Host smart-c9787c1d-3681-413a-af7e-4d2dc95bcd7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622367532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2622367532
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3021735333
Short name T1009
Test name
Test status
Simulation time 123844451 ps
CPU time 3.28 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 218804 kb
Host smart-7f1f6077-2f84-4ab8-b66a-dfd8b967201a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021735333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3021735333
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2104286845
Short name T1001
Test name
Test status
Simulation time 596062255 ps
CPU time 9.21 seconds
Started May 19 01:48:49 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 214268 kb
Host smart-ebe653be-0df0-4624-870c-c3857064c214
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104286845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2104286845
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4080290021
Short name T1074
Test name
Test status
Simulation time 162165568 ps
CPU time 3.39 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 217076 kb
Host smart-fe502fd6-dce8-4cf8-aadd-403f86d165ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080290021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4080290021
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.945219478
Short name T1021
Test name
Test status
Simulation time 199223557 ps
CPU time 2.18 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214020 kb
Host smart-7129f2ac-1d6d-4f89-b064-47b86082a491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945219478 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.945219478
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1031480916
Short name T958
Test name
Test status
Simulation time 22976546 ps
CPU time 0.86 seconds
Started May 19 01:48:53 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205660 kb
Host smart-1dd8a9ba-ebd0-48d5-a153-8df8765408eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031480916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1031480916
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3066061342
Short name T987
Test name
Test status
Simulation time 45789065 ps
CPU time 0.76 seconds
Started May 19 01:48:56 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 205452 kb
Host smart-24a53056-f03d-456f-a776-f5ddc30fffbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066061342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3066061342
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3337682662
Short name T1042
Test name
Test status
Simulation time 123703937 ps
CPU time 4.62 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:08 PM PDT 24
Peak memory 205900 kb
Host smart-1b5c346b-6ce8-4f86-af30-1e716bb585ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337682662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3337682662
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3682360053
Short name T1007
Test name
Test status
Simulation time 344304579 ps
CPU time 2.76 seconds
Started May 19 01:48:52 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 214264 kb
Host smart-94d0dc48-1d9e-422a-ba13-f93883c41238
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682360053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3682360053
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2011238177
Short name T124
Test name
Test status
Simulation time 5989438140 ps
CPU time 11.72 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 222180 kb
Host smart-33760054-629c-4b5d-84c8-e788818c2313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011238177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2011238177
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.254967566
Short name T1032
Test name
Test status
Simulation time 322133403 ps
CPU time 2.59 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214040 kb
Host smart-1d5a977c-200b-4854-a0a2-826dafccde61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254967566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.254967566
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1593136610
Short name T1076
Test name
Test status
Simulation time 222423503 ps
CPU time 1.82 seconds
Started May 19 01:48:55 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 213952 kb
Host smart-5f6e5211-4ab7-4fa7-979c-7db7f21784aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593136610 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1593136610
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.973806644
Short name T1075
Test name
Test status
Simulation time 31556049 ps
CPU time 1.61 seconds
Started May 19 01:48:55 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 205748 kb
Host smart-5e32334e-504d-4eea-9e59-35ddd81b3c9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973806644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.973806644
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3537098109
Short name T922
Test name
Test status
Simulation time 29575905 ps
CPU time 0.71 seconds
Started May 19 01:48:53 PM PDT 24
Finished May 19 01:48:56 PM PDT 24
Peak memory 205524 kb
Host smart-5a908ed0-b345-4dd8-98bc-9368f86c33d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537098109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3537098109
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.24485419
Short name T939
Test name
Test status
Simulation time 146318427 ps
CPU time 1.71 seconds
Started May 19 01:48:55 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 205788 kb
Host smart-d16851c9-e336-4d40-b9c2-b7975c6c837c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sam
e_csr_outstanding.24485419
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2993325723
Short name T1002
Test name
Test status
Simulation time 240387378 ps
CPU time 1.7 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214272 kb
Host smart-e9eeaf5c-3346-42d5-9c3f-53d540d7a2df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993325723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2993325723
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.904062872
Short name T1045
Test name
Test status
Simulation time 295017515 ps
CPU time 7.37 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:11 PM PDT 24
Peak memory 214568 kb
Host smart-a1070114-b49d-49b0-86d2-65aaf280cef5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904062872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.904062872
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2675001626
Short name T969
Test name
Test status
Simulation time 164942933 ps
CPU time 2.15 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 215072 kb
Host smart-0d60f46a-315e-45d8-a1e3-acc6aa2b1aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675001626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2675001626
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1031954350
Short name T383
Test name
Test status
Simulation time 38454405 ps
CPU time 1.16 seconds
Started May 19 01:48:57 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214096 kb
Host smart-d9fc5df8-71f1-41c7-b4bd-52ee0e4292ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031954350 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1031954350
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1123099719
Short name T1034
Test name
Test status
Simulation time 14722209 ps
CPU time 1.21 seconds
Started May 19 01:48:59 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 205804 kb
Host smart-035240cc-6faa-4098-b198-a0abbb9f34a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123099719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1123099719
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.705617149
Short name T970
Test name
Test status
Simulation time 19884046 ps
CPU time 0.76 seconds
Started May 19 01:49:00 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 205492 kb
Host smart-0fabbcce-b329-4940-8ef4-459af870c867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705617149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.705617149
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3028131000
Short name T1058
Test name
Test status
Simulation time 1386770902 ps
CPU time 3.19 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 205756 kb
Host smart-27bf8924-7888-41fb-8e6b-43ee4045c807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028131000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3028131000
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1303805491
Short name T1056
Test name
Test status
Simulation time 69104393 ps
CPU time 2.58 seconds
Started May 19 01:48:58 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 214388 kb
Host smart-80d03de2-4a88-4e4f-9058-d2a1101d41a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303805491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1303805491
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3472073885
Short name T1061
Test name
Test status
Simulation time 1589230236 ps
CPU time 13.59 seconds
Started May 19 01:49:03 PM PDT 24
Finished May 19 01:49:18 PM PDT 24
Peak memory 214540 kb
Host smart-8ae19ead-3d0b-4b73-8418-10ab9b478373
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472073885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3472073885
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4289776818
Short name T1006
Test name
Test status
Simulation time 77337193 ps
CPU time 2.5 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:04 PM PDT 24
Peak memory 214028 kb
Host smart-ebc77198-2747-48dc-a44a-3a721ec2169f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289776818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4289776818
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3877393007
Short name T1022
Test name
Test status
Simulation time 78669503 ps
CPU time 2.11 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214024 kb
Host smart-3bf73882-3225-4044-aac6-8efeb9e91e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877393007 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3877393007
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1756632987
Short name T933
Test name
Test status
Simulation time 29974654 ps
CPU time 0.98 seconds
Started May 19 01:48:55 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 205552 kb
Host smart-6fd5a1e7-9496-415b-8860-41cf873606e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756632987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1756632987
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1567402185
Short name T1081
Test name
Test status
Simulation time 11134508 ps
CPU time 0.85 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 205436 kb
Host smart-1ac7641a-6ec4-432b-b6a4-d552cbfb049d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567402185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1567402185
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1897862724
Short name T1083
Test name
Test status
Simulation time 370768399 ps
CPU time 1.4 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 205780 kb
Host smart-4b99fe52-3e0f-45d3-83ce-a0124196e3a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897862724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1897862724
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1062457262
Short name T1084
Test name
Test status
Simulation time 71588620 ps
CPU time 2.48 seconds
Started May 19 01:48:53 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 222404 kb
Host smart-e28a4981-ae32-4860-a505-024a6b7c8b26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062457262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1062457262
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3428433422
Short name T961
Test name
Test status
Simulation time 720318019 ps
CPU time 4.96 seconds
Started May 19 01:49:00 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 214420 kb
Host smart-1d134661-0cc9-488b-ac40-4836ca22fab1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428433422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3428433422
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3823787163
Short name T999
Test name
Test status
Simulation time 54695869 ps
CPU time 2.03 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 215548 kb
Host smart-dbdd0e89-41ec-41b9-8f8a-8792899ec7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823787163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3823787163
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3764509206
Short name T158
Test name
Test status
Simulation time 178458738 ps
CPU time 4.46 seconds
Started May 19 01:48:54 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 213992 kb
Host smart-f6fdb51a-9dba-4b53-add4-d400a00093da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764509206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3764509206
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2967323548
Short name T1071
Test name
Test status
Simulation time 77516897 ps
CPU time 2.14 seconds
Started May 19 01:49:22 PM PDT 24
Finished May 19 01:49:26 PM PDT 24
Peak memory 213508 kb
Host smart-b9e0a884-9f40-4c41-a952-928f655a8743
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967323548 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2967323548
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2484279168
Short name T146
Test name
Test status
Simulation time 20986866 ps
CPU time 1.17 seconds
Started May 19 01:48:57 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 205844 kb
Host smart-e1983247-5bcd-42fc-bf74-80d5eb837d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484279168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2484279168
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1631456791
Short name T974
Test name
Test status
Simulation time 61663198 ps
CPU time 0.75 seconds
Started May 19 01:48:56 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 205524 kb
Host smart-8d160f99-d928-45a9-af94-7c62f585c4af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631456791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1631456791
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1871701933
Short name T947
Test name
Test status
Simulation time 428251901 ps
CPU time 3.09 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 205760 kb
Host smart-3021729c-aca3-45fb-9a48-f9deaea0829c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871701933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1871701933
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3832767574
Short name T1046
Test name
Test status
Simulation time 647539408 ps
CPU time 1.98 seconds
Started May 19 01:48:59 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 214404 kb
Host smart-41129300-136c-4839-9df5-c01bc86c09d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832767574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3832767574
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.412730092
Short name T1036
Test name
Test status
Simulation time 493806824 ps
CPU time 5.99 seconds
Started May 19 01:48:58 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 214260 kb
Host smart-e718e3e8-1e6c-4d64-8d90-aaf4cafb8bbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412730092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.412730092
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4265731404
Short name T1060
Test name
Test status
Simulation time 67557769 ps
CPU time 2.65 seconds
Started May 19 01:48:57 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 213944 kb
Host smart-ddef1381-7aaa-47fe-9e84-4200209c8362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265731404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4265731404
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1860548166
Short name T169
Test name
Test status
Simulation time 185798178 ps
CPU time 4.56 seconds
Started May 19 01:49:00 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 213980 kb
Host smart-7ed06440-580f-4b80-a366-0d12211ce1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860548166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1860548166
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3680107043
Short name T1053
Test name
Test status
Simulation time 510928160 ps
CPU time 15.93 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 205660 kb
Host smart-4dcf71ac-bb13-45a8-a4b0-3b63fe7c4ef3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680107043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
680107043
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.753851491
Short name T156
Test name
Test status
Simulation time 653234019 ps
CPU time 8.94 seconds
Started May 19 01:48:34 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205836 kb
Host smart-ea10c283-6001-4cad-990d-153be1f7d3ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753851491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.753851491
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.439949030
Short name T995
Test name
Test status
Simulation time 54433880 ps
CPU time 1.42 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:39 PM PDT 24
Peak memory 205764 kb
Host smart-4f4f138f-1f99-49ad-9bf2-f4fd46090bea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439949030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.439949030
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4076806481
Short name T1003
Test name
Test status
Simulation time 45946993 ps
CPU time 2.04 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 214000 kb
Host smart-446625de-1486-440f-a17f-39b64ad8b9dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076806481 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4076806481
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3829690420
Short name T1013
Test name
Test status
Simulation time 23179757 ps
CPU time 1.17 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:41 PM PDT 24
Peak memory 205800 kb
Host smart-18d47116-c9f8-4c9b-ba5a-6780e5127ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829690420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3829690420
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.971607215
Short name T928
Test name
Test status
Simulation time 21528378 ps
CPU time 0.82 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 205448 kb
Host smart-78adf312-aacd-4ecd-9ef4-d38dc45a12a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971607215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.971607215
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2874635459
Short name T938
Test name
Test status
Simulation time 62005940 ps
CPU time 2.4 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 205872 kb
Host smart-50787f33-9632-411d-9bcb-051336457985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874635459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2874635459
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.981041008
Short name T985
Test name
Test status
Simulation time 476987994 ps
CPU time 1.91 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 214240 kb
Host smart-785291f1-e2ca-4015-90f6-98544a97766c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981041008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.981041008
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1781470389
Short name T1080
Test name
Test status
Simulation time 427509166 ps
CPU time 4.2 seconds
Started May 19 01:48:38 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 214368 kb
Host smart-292a1044-fb28-492d-87dd-afccda01c6a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781470389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1781470389
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2060183911
Short name T926
Test name
Test status
Simulation time 33695528 ps
CPU time 2.18 seconds
Started May 19 01:48:37 PM PDT 24
Finished May 19 01:48:43 PM PDT 24
Peak memory 213956 kb
Host smart-56a61af3-e095-4817-8417-b5153befe8ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060183911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2060183911
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3159012707
Short name T161
Test name
Test status
Simulation time 2040430675 ps
CPU time 6.53 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 213972 kb
Host smart-d8a342ae-427f-4e3a-83cd-dfcbc0ca9d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159012707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3159012707
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1538880782
Short name T979
Test name
Test status
Simulation time 41973808 ps
CPU time 0.84 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 205428 kb
Host smart-f98bceae-902a-4c7c-a776-e99cf70a15cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538880782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1538880782
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2295629751
Short name T957
Test name
Test status
Simulation time 8558419 ps
CPU time 0.7 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:04 PM PDT 24
Peak memory 205532 kb
Host smart-2f6d29fa-87a9-4036-986c-f62b72a35d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295629751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2295629751
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2344727999
Short name T977
Test name
Test status
Simulation time 12823016 ps
CPU time 0.85 seconds
Started May 19 01:49:03 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 205660 kb
Host smart-db5f5444-8fb8-4f38-9f0b-46426991fcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344727999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2344727999
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2520500468
Short name T1005
Test name
Test status
Simulation time 29510445 ps
CPU time 0.76 seconds
Started May 19 01:49:05 PM PDT 24
Finished May 19 01:49:08 PM PDT 24
Peak memory 205460 kb
Host smart-8e95db52-e07c-42b9-8d53-b25216957324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520500468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2520500468
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3017270475
Short name T1054
Test name
Test status
Simulation time 44062181 ps
CPU time 0.75 seconds
Started May 19 01:49:05 PM PDT 24
Finished May 19 01:49:07 PM PDT 24
Peak memory 205492 kb
Host smart-9cb5d229-9323-46d7-8141-2de2b36f0d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017270475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3017270475
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2960677309
Short name T990
Test name
Test status
Simulation time 14239955 ps
CPU time 0.86 seconds
Started May 19 01:48:58 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 205580 kb
Host smart-a0dfef64-97aa-4a2b-bba8-aafbe3401ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960677309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2960677309
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1789756736
Short name T1019
Test name
Test status
Simulation time 11786868 ps
CPU time 0.83 seconds
Started May 19 01:49:22 PM PDT 24
Finished May 19 01:49:24 PM PDT 24
Peak memory 205232 kb
Host smart-c8069c95-9713-494c-b2ec-44eb4bf50150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789756736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1789756736
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4161773383
Short name T921
Test name
Test status
Simulation time 18405611 ps
CPU time 0.72 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 205516 kb
Host smart-c1cf4a65-7283-4873-9b04-47569f458ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161773383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4161773383
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3102903505
Short name T1078
Test name
Test status
Simulation time 9671083 ps
CPU time 0.81 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:04 PM PDT 24
Peak memory 205532 kb
Host smart-61ac3088-bbf0-4f20-8895-5ee76798d4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102903505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3102903505
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4109245465
Short name T1014
Test name
Test status
Simulation time 138271328 ps
CPU time 0.85 seconds
Started May 19 01:48:59 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 205400 kb
Host smart-d7895e64-d156-479a-8ffd-f28afb27bb85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109245465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4109245465
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.205565169
Short name T1015
Test name
Test status
Simulation time 131137326 ps
CPU time 3.7 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205776 kb
Host smart-f283c1a0-a7cf-401c-98c8-3cf241a9ed86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205565169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.205565169
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2935066834
Short name T1018
Test name
Test status
Simulation time 1294130566 ps
CPU time 16.08 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 206052 kb
Host smart-a72a49d6-ae4c-4288-830c-ae777dd16522
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935066834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
935066834
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2862230459
Short name T943
Test name
Test status
Simulation time 21420477 ps
CPU time 1.12 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205704 kb
Host smart-1db39e56-7ef8-46e0-98c0-5ebde793de1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862230459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
862230459
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.748209209
Short name T382
Test name
Test status
Simulation time 30865723 ps
CPU time 1.26 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:44 PM PDT 24
Peak memory 205732 kb
Host smart-9c78cf8c-6196-412c-8c98-6d4a1e67115d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748209209 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.748209209
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3305915053
Short name T1051
Test name
Test status
Simulation time 21725738 ps
CPU time 0.96 seconds
Started May 19 01:48:42 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 205480 kb
Host smart-2f7fc848-4fc5-4acb-9619-b771c722c13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305915053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3305915053
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4086419483
Short name T994
Test name
Test status
Simulation time 14377890 ps
CPU time 0.71 seconds
Started May 19 01:48:35 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 205540 kb
Host smart-e58fad0b-201a-4e2c-a7c3-726d0106055b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086419483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4086419483
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3401836179
Short name T147
Test name
Test status
Simulation time 38547497 ps
CPU time 2.49 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205732 kb
Host smart-30df86cc-6cef-4b32-83ea-17c0083e6617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401836179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3401836179
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2256385851
Short name T973
Test name
Test status
Simulation time 73267413 ps
CPU time 2.45 seconds
Started May 19 01:48:36 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 214392 kb
Host smart-28b431ea-7d69-4d95-8a15-c3553881275a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256385851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2256385851
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4228099610
Short name T116
Test name
Test status
Simulation time 2030677719 ps
CPU time 5.19 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:48 PM PDT 24
Peak memory 214316 kb
Host smart-b355ce9a-fe31-41d1-b19e-b417e949ee1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228099610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4228099610
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.268521331
Short name T927
Test name
Test status
Simulation time 142175049 ps
CPU time 2.48 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 216144 kb
Host smart-50bc2410-7b57-4850-8206-99403ff24e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268521331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.268521331
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2668636823
Short name T173
Test name
Test status
Simulation time 252795145 ps
CPU time 3.2 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 213936 kb
Host smart-98bcd923-5242-49f3-9255-d7f484be8f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668636823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2668636823
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2656330283
Short name T923
Test name
Test status
Simulation time 200158544 ps
CPU time 0.84 seconds
Started May 19 01:48:59 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 205436 kb
Host smart-51baa738-1b2b-4a85-9c43-2f4e45a9504d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656330283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2656330283
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2242153768
Short name T1016
Test name
Test status
Simulation time 23691802 ps
CPU time 0.76 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:04 PM PDT 24
Peak memory 205464 kb
Host smart-8523a9f8-a5f6-4253-be3a-f2202c5602c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242153768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2242153768
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2792684078
Short name T948
Test name
Test status
Simulation time 9864714 ps
CPU time 0.85 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:04 PM PDT 24
Peak memory 205452 kb
Host smart-7fe65567-83fa-4a35-81f5-012f2186edd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792684078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2792684078
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1534980163
Short name T993
Test name
Test status
Simulation time 9890926 ps
CPU time 0.81 seconds
Started May 19 01:49:20 PM PDT 24
Finished May 19 01:49:22 PM PDT 24
Peak memory 205380 kb
Host smart-717bec93-9a7b-4b43-8440-f113dfdd88b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534980163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1534980163
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3419128374
Short name T1043
Test name
Test status
Simulation time 35262583 ps
CPU time 0.8 seconds
Started May 19 01:49:11 PM PDT 24
Finished May 19 01:49:13 PM PDT 24
Peak memory 205536 kb
Host smart-fca77613-6975-4287-adb3-0e292942fbef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419128374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3419128374
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4157854485
Short name T931
Test name
Test status
Simulation time 18582361 ps
CPU time 0.75 seconds
Started May 19 01:49:02 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 205496 kb
Host smart-13401525-939f-43a3-b9e6-bf989e9e7c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157854485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4157854485
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2481125120
Short name T984
Test name
Test status
Simulation time 10362543 ps
CPU time 0.84 seconds
Started May 19 01:49:00 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 205524 kb
Host smart-a2f5c6a9-e5f3-45b7-b403-41c5945c5b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481125120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2481125120
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1912734178
Short name T934
Test name
Test status
Simulation time 11080589 ps
CPU time 0.73 seconds
Started May 19 01:49:04 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 205784 kb
Host smart-1ed46924-2681-4d88-b2a0-0bc7ea033a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912734178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1912734178
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2320084838
Short name T1073
Test name
Test status
Simulation time 42979534 ps
CPU time 0.92 seconds
Started May 19 01:49:01 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 205488 kb
Host smart-d1137bed-93db-4565-8a02-7c7e43273d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320084838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2320084838
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.41370220
Short name T975
Test name
Test status
Simulation time 13336577 ps
CPU time 0.81 seconds
Started May 19 01:49:05 PM PDT 24
Finished May 19 01:49:08 PM PDT 24
Peak memory 205540 kb
Host smart-20f64674-7354-4be6-8400-b13ade66d190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.41370220
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3673126889
Short name T1077
Test name
Test status
Simulation time 268398900 ps
CPU time 5.83 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 205756 kb
Host smart-702948ce-be5e-41fe-9f18-30abf39515db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673126889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
673126889
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3544141601
Short name T929
Test name
Test status
Simulation time 542614954 ps
CPU time 6.93 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 205720 kb
Host smart-39563246-87f1-496a-b2d9-3f4487f96b3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544141601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
544141601
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3832547648
Short name T1082
Test name
Test status
Simulation time 29776808 ps
CPU time 0.93 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 205572 kb
Host smart-22bdc731-2f3d-414a-9f45-cf0f34b4bf2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832547648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
832547648
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1543758588
Short name T1059
Test name
Test status
Simulation time 98345654 ps
CPU time 1.81 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 214048 kb
Host smart-b44286b3-ee4b-4638-ad80-b72d3e284167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543758588 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1543758588
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2697230469
Short name T941
Test name
Test status
Simulation time 14573760 ps
CPU time 1.21 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205732 kb
Host smart-a5c7cb09-563b-4eb7-877a-83e20b724fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697230469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2697230469
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3743420480
Short name T919
Test name
Test status
Simulation time 13530062 ps
CPU time 0.74 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 205480 kb
Host smart-814cdaa9-b98a-42a0-91de-22e6064b7a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743420480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3743420480
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.238559908
Short name T951
Test name
Test status
Simulation time 227003441 ps
CPU time 2.71 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 213912 kb
Host smart-c6a342f4-387e-481b-8bad-3eacb572ec51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238559908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.238559908
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2423475969
Short name T126
Test name
Test status
Simulation time 268400881 ps
CPU time 2.78 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:48 PM PDT 24
Peak memory 214272 kb
Host smart-2913d57f-b09b-4405-998a-9a78595beb66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423475969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2423475969
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.734162241
Short name T120
Test name
Test status
Simulation time 589211203 ps
CPU time 6.68 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 214272 kb
Host smart-345e966a-9e0f-4b42-83cd-9f89a2f8a378
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734162241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.734162241
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1043647604
Short name T1070
Test name
Test status
Simulation time 137917869 ps
CPU time 2.49 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 214028 kb
Host smart-ae9508f9-95b5-4f4d-976f-359641a5d440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043647604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1043647604
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.694013613
Short name T924
Test name
Test status
Simulation time 45275378 ps
CPU time 0.83 seconds
Started May 19 01:49:22 PM PDT 24
Finished May 19 01:49:25 PM PDT 24
Peak memory 205384 kb
Host smart-c412b890-dcde-4160-805e-591d7c2d9272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694013613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.694013613
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.315465879
Short name T1062
Test name
Test status
Simulation time 36300105 ps
CPU time 0.81 seconds
Started May 19 01:49:00 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 205500 kb
Host smart-af21dd02-5e9a-49fa-b520-081f91bf05db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315465879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.315465879
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1338386797
Short name T997
Test name
Test status
Simulation time 11333616 ps
CPU time 0.79 seconds
Started May 19 01:49:20 PM PDT 24
Finished May 19 01:49:22 PM PDT 24
Peak memory 205380 kb
Host smart-5cb4f2d5-bc74-4cff-9e85-37f8551dca44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338386797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1338386797
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1152286696
Short name T1023
Test name
Test status
Simulation time 35834867 ps
CPU time 0.81 seconds
Started May 19 01:49:16 PM PDT 24
Finished May 19 01:49:17 PM PDT 24
Peak memory 205536 kb
Host smart-99a70859-ec3b-4fbc-99c7-2dbbc832f726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152286696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1152286696
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2121521893
Short name T1027
Test name
Test status
Simulation time 32082811 ps
CPU time 0.77 seconds
Started May 19 01:48:59 PM PDT 24
Finished May 19 01:49:01 PM PDT 24
Peak memory 205372 kb
Host smart-80c78fbf-ea09-48eb-a0d3-3f17175af40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121521893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2121521893
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2823473640
Short name T920
Test name
Test status
Simulation time 23986646 ps
CPU time 0.8 seconds
Started May 19 01:48:58 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 205404 kb
Host smart-fabb88cb-fe32-4321-b91e-6b01f13ba952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823473640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2823473640
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1493729377
Short name T1037
Test name
Test status
Simulation time 90055283 ps
CPU time 0.87 seconds
Started May 19 01:49:03 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 205492 kb
Host smart-ff73036c-0836-4e64-8d32-8755e0733372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493729377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1493729377
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3470395267
Short name T944
Test name
Test status
Simulation time 39184810 ps
CPU time 0.7 seconds
Started May 19 01:49:04 PM PDT 24
Finished May 19 01:49:06 PM PDT 24
Peak memory 205524 kb
Host smart-18d0866b-44c2-4843-b27d-0afd299225e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470395267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3470395267
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.159570155
Short name T980
Test name
Test status
Simulation time 46784161 ps
CPU time 0.71 seconds
Started May 19 01:49:03 PM PDT 24
Finished May 19 01:49:05 PM PDT 24
Peak memory 205512 kb
Host smart-2d08f392-036f-48a7-a74e-311b9f7e037a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159570155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.159570155
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2401915329
Short name T1031
Test name
Test status
Simulation time 57639302 ps
CPU time 0.71 seconds
Started May 19 01:49:07 PM PDT 24
Finished May 19 01:49:09 PM PDT 24
Peak memory 205492 kb
Host smart-62a8aa9b-7295-409f-b9eb-a0ca537c4b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401915329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2401915329
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3417130195
Short name T1065
Test name
Test status
Simulation time 60675425 ps
CPU time 1.26 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205776 kb
Host smart-1b42cf27-389c-4265-bc05-9672a002bffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417130195 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3417130195
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1358927606
Short name T144
Test name
Test status
Simulation time 14283198 ps
CPU time 1.08 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 205628 kb
Host smart-48aa6898-da2c-4224-984a-2e73a0d1e6c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358927606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1358927606
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3161686834
Short name T962
Test name
Test status
Simulation time 8249887 ps
CPU time 0.8 seconds
Started May 19 01:48:41 PM PDT 24
Finished May 19 01:48:45 PM PDT 24
Peak memory 205520 kb
Host smart-fcb21aae-dc2a-4bb0-8569-e713a05afc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161686834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3161686834
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2178923039
Short name T1029
Test name
Test status
Simulation time 38593003 ps
CPU time 2.56 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 205696 kb
Host smart-c89a15c0-25fb-42a8-a6a7-e5aab388ca3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178923039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2178923039
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1276566161
Short name T1063
Test name
Test status
Simulation time 717678329 ps
CPU time 2.08 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 214336 kb
Host smart-e04519d6-9b13-430d-891a-a4336a4fcb7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276566161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1276566161
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3693984059
Short name T982
Test name
Test status
Simulation time 793617877 ps
CPU time 15.49 seconds
Started May 19 01:48:40 PM PDT 24
Finished May 19 01:48:59 PM PDT 24
Peak memory 214360 kb
Host smart-9c04ccf6-ee81-4746-93b9-14b424a87d29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693984059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3693984059
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.4076807851
Short name T936
Test name
Test status
Simulation time 46900051 ps
CPU time 2.88 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 213976 kb
Host smart-683a8d10-825a-4ab7-bd04-08da95337a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076807851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.4076807851
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2041147640
Short name T1004
Test name
Test status
Simulation time 443362548 ps
CPU time 10.83 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:49:00 PM PDT 24
Peak memory 213928 kb
Host smart-be747c9f-5e4a-4aa1-a415-21bcd865d874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041147640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2041147640
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2601256572
Short name T1055
Test name
Test status
Simulation time 86439680 ps
CPU time 1.46 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 205780 kb
Host smart-4ce8d4fe-d817-40e8-bad7-c30e052741ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601256572 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2601256572
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3404748505
Short name T959
Test name
Test status
Simulation time 81125120 ps
CPU time 1.24 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205764 kb
Host smart-64a50332-99e0-463f-a49c-102ce923f9f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404748505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3404748505
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3832474592
Short name T917
Test name
Test status
Simulation time 42240990 ps
CPU time 0.8 seconds
Started May 19 01:48:45 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 205432 kb
Host smart-d7564615-b2c7-46f9-917c-9935b46fbc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832474592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3832474592
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1115170121
Short name T972
Test name
Test status
Simulation time 83578689 ps
CPU time 1.62 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 205704 kb
Host smart-9b66215d-26aa-4166-ac5f-357f70ff88f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115170121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1115170121
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1041779920
Short name T125
Test name
Test status
Simulation time 619271830 ps
CPU time 3.44 seconds
Started May 19 01:48:39 PM PDT 24
Finished May 19 01:48:46 PM PDT 24
Peak memory 214344 kb
Host smart-74b07777-946a-4fea-b8ca-39a276375ff3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041779920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1041779920
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.925201182
Short name T978
Test name
Test status
Simulation time 89524042 ps
CPU time 3.76 seconds
Started May 19 01:48:42 PM PDT 24
Finished May 19 01:48:48 PM PDT 24
Peak memory 220092 kb
Host smart-e38f9a7d-39bf-44da-8929-559b68dcdfc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925201182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.925201182
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3086054829
Short name T1064
Test name
Test status
Simulation time 128707344 ps
CPU time 1.82 seconds
Started May 19 01:48:44 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 213936 kb
Host smart-a270548f-031c-49d8-941a-1217e97a3143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086054829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3086054829
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.119844494
Short name T989
Test name
Test status
Simulation time 41283660 ps
CPU time 1.64 seconds
Started May 19 01:48:46 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 214020 kb
Host smart-a6de6027-31bb-4ce8-b878-1a05a666c992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119844494 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.119844494
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.420617980
Short name T1033
Test name
Test status
Simulation time 12016957 ps
CPU time 0.88 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 205464 kb
Host smart-7852cce0-524f-41ac-beac-6a5d331a4160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420617980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.420617980
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3512075091
Short name T940
Test name
Test status
Simulation time 19513174 ps
CPU time 0.72 seconds
Started May 19 01:48:50 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 205500 kb
Host smart-a371bc4f-50d7-4f7c-af46-f2cdd92e4453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512075091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3512075091
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.552508739
Short name T1024
Test name
Test status
Simulation time 437530708 ps
CPU time 2.66 seconds
Started May 19 01:48:46 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 205648 kb
Host smart-7f5461fc-51a5-487b-93a5-efb293bb03dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552508739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.552508739
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1630662303
Short name T1069
Test name
Test status
Simulation time 348756591 ps
CPU time 1.8 seconds
Started May 19 01:48:49 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 214288 kb
Host smart-2b344e7c-30eb-4a77-b00b-e9517a951018
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630662303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1630662303
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1292254354
Short name T1044
Test name
Test status
Simulation time 816983646 ps
CPU time 4.65 seconds
Started May 19 01:48:43 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 214392 kb
Host smart-5d3c8070-de52-4334-a75b-cf1762b2c8ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292254354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1292254354
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1297509351
Short name T996
Test name
Test status
Simulation time 104736675 ps
CPU time 4 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 216344 kb
Host smart-d2ffb3c7-4fd8-446d-83e6-6d210c3fabfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297509351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1297509351
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2143448616
Short name T1012
Test name
Test status
Simulation time 227610319 ps
CPU time 2.86 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:57 PM PDT 24
Peak memory 215080 kb
Host smart-62fb59d4-4852-4229-ae1d-e9640de8041f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143448616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2143448616
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.801287964
Short name T956
Test name
Test status
Simulation time 84358260 ps
CPU time 1.48 seconds
Started May 19 01:48:46 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 214008 kb
Host smart-016ec9b3-d102-40f4-a7e0-798a6c604094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801287964 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.801287964
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1257328783
Short name T145
Test name
Test status
Simulation time 29409180 ps
CPU time 1.04 seconds
Started May 19 01:48:45 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 205696 kb
Host smart-5c682dca-a854-4251-af3c-7d552a8ecfee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257328783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1257328783
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2673340041
Short name T949
Test name
Test status
Simulation time 26216516 ps
CPU time 0.79 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 205424 kb
Host smart-f1fb28ea-f997-45a2-ab09-5d25ea1b89e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673340041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2673340041
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2225753460
Short name T1057
Test name
Test status
Simulation time 58078007 ps
CPU time 2.12 seconds
Started May 19 01:48:45 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 205700 kb
Host smart-579446e5-5814-4634-a324-d3843d8b54be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225753460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2225753460
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1542691461
Short name T966
Test name
Test status
Simulation time 260381814 ps
CPU time 3.09 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 219004 kb
Host smart-5f1053ad-342f-4029-8832-e326d710e889
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542691461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1542691461
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.172986574
Short name T122
Test name
Test status
Simulation time 1147422036 ps
CPU time 13.6 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:49:02 PM PDT 24
Peak memory 214360 kb
Host smart-e6561a67-7a7d-453d-b3b6-02ed4cec7a7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172986574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.172986574
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.662690269
Short name T1049
Test name
Test status
Simulation time 25635443 ps
CPU time 1.68 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:50 PM PDT 24
Peak memory 213904 kb
Host smart-59a1cade-1c80-413f-8f21-ade0843766b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662690269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.662690269
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3020143534
Short name T170
Test name
Test status
Simulation time 146083109 ps
CPU time 4.54 seconds
Started May 19 01:48:46 PM PDT 24
Finished May 19 01:48:52 PM PDT 24
Peak memory 206012 kb
Host smart-70c7d4fe-8425-4ec4-9fa0-5f92c4ec11eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020143534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3020143534
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3896744065
Short name T971
Test name
Test status
Simulation time 14624712 ps
CPU time 1.13 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 214092 kb
Host smart-3acb3089-fff1-459d-b1d3-29946a495f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896744065 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3896744065
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.471215193
Short name T1010
Test name
Test status
Simulation time 11195547 ps
CPU time 0.88 seconds
Started May 19 01:48:48 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205496 kb
Host smart-23408b3a-624a-4b88-b95c-c1fde0dc0421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471215193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.471215193
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.637026458
Short name T918
Test name
Test status
Simulation time 44679846 ps
CPU time 0.7 seconds
Started May 19 01:48:49 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 205436 kb
Host smart-612c2899-af43-4a8e-a2b0-05de6791a621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637026458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.637026458
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3576783016
Short name T955
Test name
Test status
Simulation time 772534108 ps
CPU time 2.58 seconds
Started May 19 01:48:47 PM PDT 24
Finished May 19 01:48:51 PM PDT 24
Peak memory 214260 kb
Host smart-060c0b54-f7a3-4293-b71b-2ac1a0525703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576783016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3576783016
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1465683110
Short name T1020
Test name
Test status
Simulation time 204442274 ps
CPU time 2.88 seconds
Started May 19 01:48:45 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 214308 kb
Host smart-f97885f0-9570-4db2-8a59-bc6405c610a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465683110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1465683110
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.104039759
Short name T1011
Test name
Test status
Simulation time 162020524 ps
CPU time 3.75 seconds
Started May 19 01:48:51 PM PDT 24
Finished May 19 01:48:58 PM PDT 24
Peak memory 214252 kb
Host smart-f1871c56-9d26-4131-878a-32b58909579a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104039759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.104039759
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1200454821
Short name T983
Test name
Test status
Simulation time 67910272 ps
CPU time 2.1 seconds
Started May 19 01:48:49 PM PDT 24
Finished May 19 01:48:53 PM PDT 24
Peak memory 216104 kb
Host smart-2c9bef4a-5d7e-45a9-a893-a9258c47fb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200454821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1200454821
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1313125842
Short name T179
Test name
Test status
Simulation time 146574939 ps
CPU time 4.04 seconds
Started May 19 01:48:44 PM PDT 24
Finished May 19 01:48:49 PM PDT 24
Peak memory 205756 kb
Host smart-e0cde974-8a33-4f2f-870b-36e5cfa23518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313125842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1313125842
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2880507045
Short name T465
Test name
Test status
Simulation time 36304926 ps
CPU time 0.86 seconds
Started May 19 01:49:32 PM PDT 24
Finished May 19 01:49:35 PM PDT 24
Peak memory 205972 kb
Host smart-e2c1b4cb-355b-445e-b10b-52753f2f452c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880507045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2880507045
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3685533354
Short name T413
Test name
Test status
Simulation time 437576469 ps
CPU time 3.85 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 214324 kb
Host smart-ae6b53e6-a3ca-454a-8dc5-bf9a705b882a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685533354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3685533354
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2443798144
Short name T70
Test name
Test status
Simulation time 185165158 ps
CPU time 4.62 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 214660 kb
Host smart-3a277877-e161-4e98-ac66-5dfac4697a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443798144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2443798144
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2742700869
Short name T320
Test name
Test status
Simulation time 220532639 ps
CPU time 3.15 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 209432 kb
Host smart-8c3c7fb3-c839-4816-9cf0-de4de34677ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742700869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2742700869
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1139845830
Short name T603
Test name
Test status
Simulation time 370819924 ps
CPU time 2.72 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 222456 kb
Host smart-ac889a03-296c-4a69-a70a-2f5e24a236ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139845830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1139845830
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.514175182
Short name T316
Test name
Test status
Simulation time 100899206 ps
CPU time 3.54 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 214180 kb
Host smart-3fa17bc8-15e6-41a1-817d-5c8100faebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514175182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.514175182
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.873474168
Short name T762
Test name
Test status
Simulation time 45005702 ps
CPU time 2.63 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 209896 kb
Host smart-55f8c63e-0bf7-4f91-81a0-a04539c29649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873474168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.873474168
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.133006809
Short name T857
Test name
Test status
Simulation time 584086774 ps
CPU time 4.21 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 214640 kb
Host smart-bce25c07-3824-40c8-9124-051f2ca9f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133006809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.133006809
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4142074881
Short name T48
Test name
Test status
Simulation time 1021621567 ps
CPU time 23.71 seconds
Started May 19 01:49:32 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 239196 kb
Host smart-50ff84ae-2a2e-450d-ba0a-077902b662bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142074881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4142074881
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1807932122
Short name T279
Test name
Test status
Simulation time 268692679 ps
CPU time 5.39 seconds
Started May 19 01:49:32 PM PDT 24
Finished May 19 01:49:41 PM PDT 24
Peak memory 208712 kb
Host smart-99ea1203-3746-4aaa-bb73-b652ccce68d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807932122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1807932122
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3586439642
Short name T804
Test name
Test status
Simulation time 530337792 ps
CPU time 4.5 seconds
Started May 19 01:49:33 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 206992 kb
Host smart-ecd2c52b-07f3-468f-9bde-7a413d788562
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586439642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3586439642
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1834225569
Short name T910
Test name
Test status
Simulation time 74571402 ps
CPU time 1.75 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 206900 kb
Host smart-19be7bb2-8364-4ab7-8998-0847d66294c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834225569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1834225569
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2682793495
Short name T803
Test name
Test status
Simulation time 212958131 ps
CPU time 3.17 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 207400 kb
Host smart-f198aca2-d5d3-445a-af0f-128ae99e0646
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682793495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2682793495
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2094225094
Short name T472
Test name
Test status
Simulation time 53829788 ps
CPU time 2.36 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:41 PM PDT 24
Peak memory 209992 kb
Host smart-a3ecc204-9fd3-43db-95d4-d63b23d6ec27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094225094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2094225094
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3169710673
Short name T792
Test name
Test status
Simulation time 969716391 ps
CPU time 8.54 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 208616 kb
Host smart-4b4ed7c8-49d9-4a37-a02a-82afb3acdb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169710673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3169710673
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3879743502
Short name T500
Test name
Test status
Simulation time 1748921506 ps
CPU time 42.45 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 208020 kb
Host smart-bb1d9ddb-ed44-4722-9bd9-06f0b6680d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879743502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3879743502
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2057176588
Short name T522
Test name
Test status
Simulation time 427257706 ps
CPU time 3.24 seconds
Started May 19 01:49:31 PM PDT 24
Finished May 19 01:49:37 PM PDT 24
Peak memory 207504 kb
Host smart-edb4301b-6359-4e05-941e-b03e859d9411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057176588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2057176588
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2113323649
Short name T376
Test name
Test status
Simulation time 146609516 ps
CPU time 1.85 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:40 PM PDT 24
Peak memory 210372 kb
Host smart-22a766aa-5619-4502-b039-31a19e9e9bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113323649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2113323649
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3413513037
Short name T776
Test name
Test status
Simulation time 92524541 ps
CPU time 3.11 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 207704 kb
Host smart-f08d063b-c5ad-4d71-9438-5242bc147ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413513037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3413513037
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1605205096
Short name T19
Test name
Test status
Simulation time 134580887 ps
CPU time 2.41 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 221136 kb
Host smart-3ad8161c-5407-40c8-b87f-7f54393d3a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605205096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1605205096
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1996008656
Short name T254
Test name
Test status
Simulation time 66695941 ps
CPU time 2.86 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 214308 kb
Host smart-6c3647b2-e031-4118-98d2-6e5dba307186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996008656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1996008656
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3451516526
Short name T761
Test name
Test status
Simulation time 63733288 ps
CPU time 3.8 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 222516 kb
Host smart-e5416b92-8658-4859-8571-71835300672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451516526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3451516526
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3774047094
Short name T342
Test name
Test status
Simulation time 329870527 ps
CPU time 3.17 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 208604 kb
Host smart-57f54b02-511e-4439-9112-967612e8672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774047094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3774047094
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.953574781
Short name T547
Test name
Test status
Simulation time 672269272 ps
CPU time 6.63 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 208024 kb
Host smart-66ed29d8-9195-42b1-ae8e-b6fc91890943
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953574781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.953574781
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2602529629
Short name T428
Test name
Test status
Simulation time 116568890 ps
CPU time 3.55 seconds
Started May 19 01:49:31 PM PDT 24
Finished May 19 01:49:37 PM PDT 24
Peak memory 206992 kb
Host smart-dc6c22bd-330b-4eba-890a-020dc136d956
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602529629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2602529629
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2031429088
Short name T832
Test name
Test status
Simulation time 59150359 ps
CPU time 2.98 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 208108 kb
Host smart-d738c5ea-1133-4e16-a647-62333d8caae8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031429088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2031429088
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3129842477
Short name T719
Test name
Test status
Simulation time 4376865007 ps
CPU time 34.6 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:50:15 PM PDT 24
Peak memory 208672 kb
Host smart-e298959b-c623-4348-8252-0ea50f808411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129842477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3129842477
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2907319232
Short name T195
Test name
Test status
Simulation time 83304290 ps
CPU time 2.98 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 206836 kb
Host smart-c302daf1-98c5-4cdd-beef-9ebbbcff06b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907319232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2907319232
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1503741575
Short name T481
Test name
Test status
Simulation time 3610513461 ps
CPU time 21.74 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 207924 kb
Host smart-ba283bf6-3a1c-43e1-afef-1d68b76d62cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503741575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1503741575
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.4078266524
Short name T131
Test name
Test status
Simulation time 136952977 ps
CPU time 8.29 seconds
Started May 19 01:49:51 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 220524 kb
Host smart-4b04c46c-5f6d-4aa3-bde2-e097e823ee9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078266524 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.4078266524
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.507085670
Short name T457
Test name
Test status
Simulation time 1871047637 ps
CPU time 11.83 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:56 PM PDT 24
Peak memory 208720 kb
Host smart-56e53929-1f07-4506-85ff-39930b09d1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507085670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.507085670
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4238385896
Short name T564
Test name
Test status
Simulation time 14713653 ps
CPU time 0.82 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 205968 kb
Host smart-b938e50a-00d9-4996-85f9-f971403845dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238385896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4238385896
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3673248857
Short name T563
Test name
Test status
Simulation time 58329307 ps
CPU time 2.06 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 214528 kb
Host smart-d1771f02-d90d-41a2-b91f-b7c3011976a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673248857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3673248857
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2490134481
Short name T255
Test name
Test status
Simulation time 470213407 ps
CPU time 3.22 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 214576 kb
Host smart-793a5eec-73fa-407c-a5c5-0ed5092b538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490134481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2490134481
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3417694336
Short name T878
Test name
Test status
Simulation time 36075659 ps
CPU time 1.69 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 214240 kb
Host smart-b9bdae95-1e57-4033-943c-86286987b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417694336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3417694336
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2592530741
Short name T407
Test name
Test status
Simulation time 2149119297 ps
CPU time 5.5 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 210404 kb
Host smart-4859dbc9-1375-43c6-9730-4765270a75c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592530741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2592530741
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1717212757
Short name T87
Test name
Test status
Simulation time 45814154 ps
CPU time 3.03 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:15 PM PDT 24
Peak memory 214520 kb
Host smart-cb830575-b1b2-4885-b1bb-805ba50952eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717212757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1717212757
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1232001949
Short name T699
Test name
Test status
Simulation time 55293337 ps
CPU time 2.93 seconds
Started May 19 01:50:08 PM PDT 24
Finished May 19 01:50:12 PM PDT 24
Peak memory 206840 kb
Host smart-2cd48b8c-3027-4277-ab9e-69667ba88877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232001949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1232001949
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3846546364
Short name T729
Test name
Test status
Simulation time 765001146 ps
CPU time 7.95 seconds
Started May 19 01:50:07 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 207076 kb
Host smart-fbd6226e-506d-4bfb-b061-1d235111808f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846546364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3846546364
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1028277651
Short name T504
Test name
Test status
Simulation time 4337629041 ps
CPU time 39.6 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 208204 kb
Host smart-07eea7d1-600f-497e-8f76-6516caf40388
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028277651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1028277651
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2107127294
Short name T901
Test name
Test status
Simulation time 219607976 ps
CPU time 6.36 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 208344 kb
Host smart-2836b872-927c-481d-ac14-4db8e6b204bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107127294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2107127294
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1007820615
Short name T578
Test name
Test status
Simulation time 116506157 ps
CPU time 2.7 seconds
Started May 19 01:50:02 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 208676 kb
Host smart-87a93314-eb18-4356-a532-53b3cbac2d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007820615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1007820615
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2583475830
Short name T532
Test name
Test status
Simulation time 1422664220 ps
CPU time 16.61 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 208092 kb
Host smart-ff942b43-050a-44e7-a30a-0cd8974ee6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583475830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2583475830
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.745260784
Short name T781
Test name
Test status
Simulation time 5223374254 ps
CPU time 33.71 seconds
Started May 19 01:50:04 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 222552 kb
Host smart-ffca4c0d-2004-4024-8479-b2d7c68eabd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745260784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.745260784
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2676377025
Short name T282
Test name
Test status
Simulation time 233684748 ps
CPU time 3.71 seconds
Started May 19 01:50:04 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 218600 kb
Host smart-c0602f19-07dd-42aa-8f70-e460c3b72282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676377025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2676377025
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.218462039
Short name T165
Test name
Test status
Simulation time 57831350 ps
CPU time 2.55 seconds
Started May 19 01:50:03 PM PDT 24
Finished May 19 01:50:06 PM PDT 24
Peak memory 210256 kb
Host smart-c59c25dd-53f9-4aa9-85ae-6ac70120d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218462039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.218462039
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1367234813
Short name T466
Test name
Test status
Simulation time 17146937 ps
CPU time 0.76 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 205908 kb
Host smart-8b002f30-cc78-4249-8504-5bf677d21edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367234813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1367234813
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3728468269
Short name T906
Test name
Test status
Simulation time 613428157 ps
CPU time 8.96 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 214324 kb
Host smart-65c5a67b-6907-49af-b84b-f3fa04f9d547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728468269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3728468269
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2198382453
Short name T208
Test name
Test status
Simulation time 194868496 ps
CPU time 4.78 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:11 PM PDT 24
Peak memory 208440 kb
Host smart-884ca17a-8338-4af0-ac67-3e03e8e1ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198382453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2198382453
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3886036232
Short name T72
Test name
Test status
Simulation time 28594546 ps
CPU time 1.96 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 206772 kb
Host smart-b11803ef-e465-4da2-9969-598943a6f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886036232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3886036232
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1314435778
Short name T744
Test name
Test status
Simulation time 423537999 ps
CPU time 4.87 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 214296 kb
Host smart-6fbbe644-1b7a-4279-a59c-40c2120f668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314435778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1314435778
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1623987314
Short name T677
Test name
Test status
Simulation time 1260757522 ps
CPU time 4.04 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 208988 kb
Host smart-287beb26-272a-49f2-8f70-c1f6984f307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623987314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1623987314
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.155810589
Short name T517
Test name
Test status
Simulation time 4564483464 ps
CPU time 28.62 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:47 PM PDT 24
Peak memory 208748 kb
Host smart-0e13ea90-d5c2-457d-b6fb-44bc6a217c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155810589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.155810589
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1270151318
Short name T692
Test name
Test status
Simulation time 65761857 ps
CPU time 3.23 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 208480 kb
Host smart-526c3676-b95c-4b60-9c31-944f2b5519d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270151318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1270151318
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1467212096
Short name T610
Test name
Test status
Simulation time 240333145 ps
CPU time 2.84 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 206844 kb
Host smart-53aa364a-5318-4c14-9bac-88c6b1a817b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467212096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1467212096
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3304041143
Short name T853
Test name
Test status
Simulation time 872079330 ps
CPU time 9.5 seconds
Started May 19 01:50:20 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 207916 kb
Host smart-d0d11853-e449-4db2-a8c1-726c753d704a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304041143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3304041143
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1804339804
Short name T505
Test name
Test status
Simulation time 843785592 ps
CPU time 15.76 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 208304 kb
Host smart-9d27b619-4047-4910-a775-bea484781873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804339804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1804339804
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3108718181
Short name T403
Test name
Test status
Simulation time 3582542221 ps
CPU time 26.94 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 209168 kb
Host smart-3522ce40-a7d9-49e6-9c95-563ce9cfa6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108718181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3108718181
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1569778799
Short name T437
Test name
Test status
Simulation time 365291341 ps
CPU time 3.91 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 208712 kb
Host smart-2fb08a81-8835-443b-a659-79a3000d6676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569778799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1569778799
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2622475417
Short name T602
Test name
Test status
Simulation time 286360603 ps
CPU time 5.86 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 210520 kb
Host smart-49e6c7c6-d1bb-4002-8334-5a53b9e1ec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622475417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2622475417
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4245255250
Short name T777
Test name
Test status
Simulation time 72794716 ps
CPU time 2.58 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 210556 kb
Host smart-b3ac86d7-c52e-4546-aef0-e7393d56108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245255250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4245255250
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3231858106
Short name T417
Test name
Test status
Simulation time 12632326 ps
CPU time 0.83 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 205940 kb
Host smart-782bc144-0ff2-4400-968c-0bd154952da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231858106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3231858106
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.333700984
Short name T592
Test name
Test status
Simulation time 388980595 ps
CPU time 2.4 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 210228 kb
Host smart-eff23b6b-45ab-42f3-bc15-dc639dd10cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333700984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.333700984
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.998270993
Short name T90
Test name
Test status
Simulation time 831892322 ps
CPU time 7.96 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 214288 kb
Host smart-825c97a9-6759-4950-83a6-3facdff36b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998270993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.998270993
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1408104835
Short name T591
Test name
Test status
Simulation time 57835647 ps
CPU time 2.23 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:15 PM PDT 24
Peak memory 214184 kb
Host smart-b1c64c2e-4235-4c14-928c-fa11f97a7bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408104835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1408104835
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.234252470
Short name T788
Test name
Test status
Simulation time 2144591234 ps
CPU time 14 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 209684 kb
Host smart-6df37d3f-3c76-4a5d-a6df-620dedcd81fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234252470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.234252470
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1403769282
Short name T715
Test name
Test status
Simulation time 153953301 ps
CPU time 2.85 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 208184 kb
Host smart-fb9453e6-cb90-4cc6-a3af-ad1ecd296dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403769282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1403769282
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1215227012
Short name T909
Test name
Test status
Simulation time 78308813 ps
CPU time 2.44 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 208840 kb
Host smart-6173c9b9-faf5-41cf-8877-5183bda88c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215227012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1215227012
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3959026674
Short name T691
Test name
Test status
Simulation time 483216096 ps
CPU time 7.63 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 208036 kb
Host smart-9900a3f3-4d3a-4925-bbee-b3ba58c7b15a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959026674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3959026674
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2351850874
Short name T392
Test name
Test status
Simulation time 751401626 ps
CPU time 5.85 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 207072 kb
Host smart-798fd18f-1610-41b5-a0a6-5b438befe06d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351850874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2351850874
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2244845272
Short name T703
Test name
Test status
Simulation time 470327749 ps
CPU time 6.01 seconds
Started May 19 01:50:22 PM PDT 24
Finished May 19 01:50:29 PM PDT 24
Peak memory 208136 kb
Host smart-c1a287ae-7d21-41ce-bdda-ba03e7f03abf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244845272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2244845272
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2661234701
Short name T439
Test name
Test status
Simulation time 69240589 ps
CPU time 2.91 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 208136 kb
Host smart-a43bd7b2-0d82-4fb4-a391-a80c4d932dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661234701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2661234701
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4033744077
Short name T418
Test name
Test status
Simulation time 103152204 ps
CPU time 2.66 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 208364 kb
Host smart-e93b83e1-fd87-44ee-9107-78dc4dccbdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033744077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4033744077
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.425999958
Short name T425
Test name
Test status
Simulation time 150231738 ps
CPU time 5.02 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 207692 kb
Host smart-d2d63306-4b00-477c-9603-536a3dc5a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425999958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.425999958
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2569939264
Short name T62
Test name
Test status
Simulation time 1284211151 ps
CPU time 6.71 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 210968 kb
Host smart-f3053a1f-b96d-457c-965c-5133e3f18eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569939264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2569939264
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1200342634
Short name T743
Test name
Test status
Simulation time 13799257 ps
CPU time 0.88 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:18 PM PDT 24
Peak memory 205948 kb
Host smart-bc018e1b-8121-4a71-bddb-956a788690fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200342634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1200342634
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.450186159
Short name T338
Test name
Test status
Simulation time 1065978284 ps
CPU time 6.25 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 215856 kb
Host smart-27f6819a-7177-4b17-ad31-e93f65f97d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450186159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.450186159
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2823480985
Short name T601
Test name
Test status
Simulation time 839838809 ps
CPU time 4.93 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 210700 kb
Host smart-64b32553-d134-4c92-b55e-171ce39d51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823480985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2823480985
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4185604045
Short name T540
Test name
Test status
Simulation time 27924129 ps
CPU time 2.05 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 207460 kb
Host smart-609a2866-eac6-4d67-a490-a84b9c91b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185604045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4185604045
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2375754712
Short name T294
Test name
Test status
Simulation time 411459229 ps
CPU time 4.61 seconds
Started May 19 01:50:21 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 214380 kb
Host smart-a06282a1-9b67-45b7-9adb-e058a620775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375754712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2375754712
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.844178845
Short name T94
Test name
Test status
Simulation time 644816173 ps
CPU time 5.11 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 222448 kb
Host smart-594890c0-d447-4183-81ec-36fca116704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844178845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.844178845
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4171126203
Short name T209
Test name
Test status
Simulation time 284339572 ps
CPU time 2.69 seconds
Started May 19 01:50:22 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 209764 kb
Host smart-c3a307db-31d6-43c7-b5cf-a942a77ddcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171126203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4171126203
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3021373543
Short name T197
Test name
Test status
Simulation time 981953450 ps
CPU time 5.98 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 208744 kb
Host smart-40b268a2-699a-4682-9026-96bc3d5e4c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021373543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3021373543
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3181648630
Short name T448
Test name
Test status
Simulation time 73232567 ps
CPU time 1.64 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 207076 kb
Host smart-f1d4de1f-d774-45a8-a977-0d9522abcc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181648630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3181648630
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1960269004
Short name T587
Test name
Test status
Simulation time 1174849196 ps
CPU time 7.05 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 208792 kb
Host smart-05efc892-b43c-43d9-aca7-a44025b9e303
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960269004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1960269004
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3542366253
Short name T633
Test name
Test status
Simulation time 3256886653 ps
CPU time 22.7 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 208236 kb
Host smart-fce885ae-bc00-4ab3-98ca-feba95467187
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542366253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3542366253
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.112870166
Short name T544
Test name
Test status
Simulation time 1218802578 ps
CPU time 37.05 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:54 PM PDT 24
Peak memory 207792 kb
Host smart-17bbb216-9d0f-4329-a83b-bcffbf60f124
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112870166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.112870166
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3470568534
Short name T600
Test name
Test status
Simulation time 460175275 ps
CPU time 2.01 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 208372 kb
Host smart-6ddd0ba3-2ad5-4ddd-b993-437408b6a54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470568534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3470568534
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.948874687
Short name T645
Test name
Test status
Simulation time 42307471 ps
CPU time 2.28 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 206676 kb
Host smart-968a3bd5-3bda-4d41-b758-5585aa17df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948874687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.948874687
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.935617002
Short name T289
Test name
Test status
Simulation time 3838101162 ps
CPU time 36.92 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 218176 kb
Host smart-703cca25-4f97-4fdf-8dd2-84ae01a8c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935617002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.935617002
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2554794974
Short name T900
Test name
Test status
Simulation time 49401697 ps
CPU time 0.8 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 205944 kb
Host smart-8ab96b4b-1e8d-4b1e-94cc-7a086eb81c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554794974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2554794974
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2877115364
Short name T406
Test name
Test status
Simulation time 1544994761 ps
CPU time 9.79 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 214312 kb
Host smart-6410d242-6302-4041-9944-d2d8ca0d7182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877115364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2877115364
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1604984473
Short name T548
Test name
Test status
Simulation time 1336049751 ps
CPU time 2.92 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:20 PM PDT 24
Peak memory 214328 kb
Host smart-de0fe6da-fc6e-41b3-a0e9-de100da354aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604984473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1604984473
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2317436876
Short name T274
Test name
Test status
Simulation time 38353420 ps
CPU time 2.86 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 221844 kb
Host smart-2ffca245-4fa1-4d8f-aa53-15e1a849b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317436876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2317436876
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.643252174
Short name T514
Test name
Test status
Simulation time 99223397 ps
CPU time 3.06 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 214564 kb
Host smart-08b80b07-7609-4070-9263-f92e0ca9d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643252174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.643252174
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4171441088
Short name T732
Test name
Test status
Simulation time 1858877058 ps
CPU time 8.7 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 218572 kb
Host smart-33826e35-8a66-4888-90ef-e93195427e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171441088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4171441088
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.523951877
Short name T348
Test name
Test status
Simulation time 227535110 ps
CPU time 2.76 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 206772 kb
Host smart-aa055494-02d0-469a-a0db-0ca0459a1ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523951877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.523951877
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.902949038
Short name T242
Test name
Test status
Simulation time 25444131 ps
CPU time 1.93 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 208860 kb
Host smart-0539ccf7-7921-4886-8fad-f079849e5970
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902949038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.902949038
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.578855496
Short name T721
Test name
Test status
Simulation time 773051613 ps
CPU time 6.03 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 207960 kb
Host smart-f63bda7b-fa95-4218-9fa7-adcae1964e00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578855496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.578855496
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2959371497
Short name T647
Test name
Test status
Simulation time 530931360 ps
CPU time 5.82 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 207104 kb
Host smart-43502f19-7739-4f4e-9a62-d0e46dd44730
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959371497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2959371497
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4274518695
Short name T511
Test name
Test status
Simulation time 429461191 ps
CPU time 4.04 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 210276 kb
Host smart-7f679966-ea7d-4418-b238-dff408401e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274518695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4274518695
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2063849119
Short name T841
Test name
Test status
Simulation time 1840569088 ps
CPU time 14.26 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 208300 kb
Host smart-ade0dad3-0afd-46d3-b7ea-303c3e7257dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063849119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2063849119
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1694118374
Short name T498
Test name
Test status
Simulation time 149657669 ps
CPU time 7.27 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:29 PM PDT 24
Peak memory 220868 kb
Host smart-bf502932-e737-4ff6-81c9-f49164d0262a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694118374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1694118374
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3929044442
Short name T868
Test name
Test status
Simulation time 548795912 ps
CPU time 6.43 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 209224 kb
Host smart-39c2005d-b043-4b87-a43c-8e6c4a5e672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929044442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3929044442
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4233461448
Short name T757
Test name
Test status
Simulation time 150729978 ps
CPU time 2.21 seconds
Started May 19 01:50:12 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 210428 kb
Host smart-4c9a622f-ea10-4002-9003-f05e3e3baf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233461448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4233461448
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3183817628
Short name T652
Test name
Test status
Simulation time 62162873 ps
CPU time 0.83 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 205960 kb
Host smart-de304d9f-0733-4e84-ab43-d364163aa507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183817628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3183817628
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2756537345
Short name T220
Test name
Test status
Simulation time 211582835 ps
CPU time 7.33 seconds
Started May 19 01:50:17 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 214436 kb
Host smart-dfbff60b-7e8c-4818-abe9-cd0ebe8f5aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756537345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2756537345
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2281085009
Short name T67
Test name
Test status
Simulation time 100469671 ps
CPU time 3.52 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 209460 kb
Host smart-23ffc590-3894-482b-a398-f66e71ce43f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281085009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2281085009
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3839692319
Short name T660
Test name
Test status
Simulation time 20055005 ps
CPU time 1.61 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 209508 kb
Host smart-d962abab-4cac-4d17-855b-9eb05b42cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839692319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3839692319
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3115866692
Short name T100
Test name
Test status
Simulation time 321149568 ps
CPU time 6.34 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 208888 kb
Host smart-8499fa61-49a3-4619-b67f-136fa467115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115866692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3115866692
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_random.4084576885
Short name T879
Test name
Test status
Simulation time 67128216 ps
CPU time 4.38 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 218544 kb
Host smart-69037de1-1fe5-4a98-be50-04c28c32189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084576885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4084576885
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3564579204
Short name T127
Test name
Test status
Simulation time 221655309 ps
CPU time 3.01 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 206840 kb
Host smart-ab9b0c32-1465-4f79-8bcd-8561488d1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564579204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3564579204
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1657888997
Short name T235
Test name
Test status
Simulation time 315811694 ps
CPU time 4.76 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 208972 kb
Host smart-6f3e30e9-abce-423b-818d-e1c3d5b18977
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657888997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1657888997
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2585896518
Short name T493
Test name
Test status
Simulation time 89212893 ps
CPU time 3.9 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:14 PM PDT 24
Peak memory 208952 kb
Host smart-311999f1-110a-494e-aa61-37d75222295c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585896518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2585896518
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3028344344
Short name T775
Test name
Test status
Simulation time 129570363 ps
CPU time 2.52 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 207284 kb
Host smart-46348b76-1b4c-4aff-9a69-7730b797d25f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028344344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3028344344
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.98416023
Short name T299
Test name
Test status
Simulation time 258431807 ps
CPU time 3.23 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 209944 kb
Host smart-a86bafc4-1239-44ce-879f-7afc327ac5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98416023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.98416023
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1527580631
Short name T669
Test name
Test status
Simulation time 45438124 ps
CPU time 2.37 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 208072 kb
Host smart-002c3747-b72a-4f24-a5e3-01a259dc34c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527580631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1527580631
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.535681992
Short name T460
Test name
Test status
Simulation time 824819085 ps
CPU time 10.97 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 208176 kb
Host smart-e05d51af-ac4c-4867-9282-f5b71db6a41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535681992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.535681992
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2370482591
Short name T749
Test name
Test status
Simulation time 213101866 ps
CPU time 2.64 seconds
Started May 19 01:50:22 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 210484 kb
Host smart-f9e26609-6ad2-4762-811d-357ca80c7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370482591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2370482591
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3891218916
Short name T470
Test name
Test status
Simulation time 16808216 ps
CPU time 0.72 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 205980 kb
Host smart-6c6df6d3-d2d9-4953-b59c-4ca1c50654f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891218916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3891218916
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1572220776
Short name T271
Test name
Test status
Simulation time 90435429 ps
CPU time 5.75 seconds
Started May 19 01:50:20 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 214344 kb
Host smart-c7122008-c627-4a41-ae23-ad3b16f80ee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572220776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1572220776
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.37109163
Short name T10
Test name
Test status
Simulation time 647880390 ps
CPU time 13.16 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 221828 kb
Host smart-5703f523-5506-413b-a591-3e7d7bfffb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37109163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.37109163
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3202942621
Short name T639
Test name
Test status
Simulation time 318639009 ps
CPU time 3.23 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 208920 kb
Host smart-766e215c-422a-4126-ad43-ac26e432a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202942621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3202942621
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.966746047
Short name T553
Test name
Test status
Simulation time 1155773832 ps
CPU time 12.5 seconds
Started May 19 01:50:20 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 208896 kb
Host smart-6fbc3300-c10f-4a02-bd95-877e06009d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966746047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.966746047
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1683509993
Short name T49
Test name
Test status
Simulation time 71342623 ps
CPU time 2.14 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 214320 kb
Host smart-60e0b69c-1a61-4e5b-b79a-42d3440ac486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683509993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1683509993
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3647698455
Short name T312
Test name
Test status
Simulation time 6804169674 ps
CPU time 33.23 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 209768 kb
Host smart-9b7d36f2-f2fb-42c2-b53f-2ee262ba48a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647698455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3647698455
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3551979980
Short name T650
Test name
Test status
Simulation time 196504115 ps
CPU time 6.72 seconds
Started May 19 01:50:21 PM PDT 24
Finished May 19 01:50:29 PM PDT 24
Peak memory 206868 kb
Host smart-40a3f5ee-496a-43a0-a461-741b96867e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551979980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3551979980
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2943186386
Short name T512
Test name
Test status
Simulation time 39424378 ps
CPU time 2.26 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 206848 kb
Host smart-b237ba54-7935-45f9-af77-67daf5758e36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943186386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2943186386
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2276748417
Short name T718
Test name
Test status
Simulation time 31012924 ps
CPU time 2.31 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 206848 kb
Host smart-4315cafc-24b9-42a2-ac25-33845254a6d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276748417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2276748417
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.438243319
Short name T561
Test name
Test status
Simulation time 200670110 ps
CPU time 3.44 seconds
Started May 19 01:50:17 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 208580 kb
Host smart-5879cee3-429e-48f9-9b65-781a7982f123
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438243319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.438243319
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3647812919
Short name T467
Test name
Test status
Simulation time 243805328 ps
CPU time 4.86 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:16 PM PDT 24
Peak memory 209700 kb
Host smart-506c0ccf-dcd7-460a-88dc-0566c5297ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647812919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3647812919
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1013014047
Short name T681
Test name
Test status
Simulation time 336683628 ps
CPU time 4.62 seconds
Started May 19 01:50:08 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 207488 kb
Host smart-957f2fad-f03f-40c4-9722-70f5520a2739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013014047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1013014047
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3562323555
Short name T213
Test name
Test status
Simulation time 11895189031 ps
CPU time 41.52 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:58 PM PDT 24
Peak memory 215892 kb
Host smart-1067011d-45f7-4025-8b63-22bbc0910674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562323555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3562323555
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.678792766
Short name T259
Test name
Test status
Simulation time 2804421723 ps
CPU time 9.26 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 210444 kb
Host smart-220151c8-6065-4158-96f3-16912509a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678792766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.678792766
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.24725756
Short name T171
Test name
Test status
Simulation time 318552487 ps
CPU time 2.24 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 210420 kb
Host smart-afc745d4-a15f-40ec-ae8c-0e35399ee94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24725756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.24725756
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2510058425
Short name T702
Test name
Test status
Simulation time 15091157 ps
CPU time 0.75 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 205936 kb
Host smart-04c3d94b-0e21-4544-9a9e-0709bbc90a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510058425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2510058425
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.97324908
Short name T363
Test name
Test status
Simulation time 1390279828 ps
CPU time 57.64 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 215200 kb
Host smart-57cc6324-ff11-4a26-825d-4c9bcaf4e283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97324908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.97324908
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1254576314
Short name T810
Test name
Test status
Simulation time 366752284 ps
CPU time 5.88 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 209520 kb
Host smart-89a92e25-9e04-437a-b12e-7a96d80b89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254576314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1254576314
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3034492895
Short name T284
Test name
Test status
Simulation time 403969817 ps
CPU time 3.49 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 214556 kb
Host smart-7d561223-d9dc-4921-8c4d-c09843370051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034492895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3034492895
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2553479362
Short name T354
Test name
Test status
Simulation time 104023825 ps
CPU time 1.96 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 214324 kb
Host smart-6fb5cae8-8951-4b9e-ac1a-db2ca651cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553479362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2553479362
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2167879650
Short name T45
Test name
Test status
Simulation time 48136988 ps
CPU time 3.08 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 214272 kb
Host smart-59dae804-581a-42e6-a072-748cc89efb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167879650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2167879650
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3285237931
Short name T469
Test name
Test status
Simulation time 1228710634 ps
CPU time 2.89 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 214704 kb
Host smart-9529f010-9519-489d-a5a6-5cdd1308abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285237931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3285237931
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3436534942
Short name T269
Test name
Test status
Simulation time 170080901 ps
CPU time 3.14 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:19 PM PDT 24
Peak memory 208216 kb
Host smart-1751752c-60c3-4d47-95a2-f901ff5db9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436534942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3436534942
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3073922102
Short name T501
Test name
Test status
Simulation time 1282090158 ps
CPU time 5.17 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 207972 kb
Host smart-6ec7a222-ff69-4578-a9a2-d38af6eb9731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073922102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3073922102
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4243862339
Short name T477
Test name
Test status
Simulation time 171507330 ps
CPU time 2.6 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 207612 kb
Host smart-7d25836a-35bb-46da-af2f-8a665cadec1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243862339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4243862339
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4059424422
Short name T270
Test name
Test status
Simulation time 173584130 ps
CPU time 2.52 seconds
Started May 19 01:50:22 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 208876 kb
Host smart-73e03891-df7d-4a5f-bdb3-6cfd7235c243
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059424422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4059424422
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2411982555
Short name T268
Test name
Test status
Simulation time 116837069 ps
CPU time 3.83 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 208704 kb
Host smart-23ab59b6-bc57-4455-98e1-50244f09855c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411982555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2411982555
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2405269050
Short name T133
Test name
Test status
Simulation time 42840786 ps
CPU time 2.32 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 209688 kb
Host smart-69357681-34f7-4987-bd66-ad2a51ef41c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405269050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2405269050
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2835510527
Short name T657
Test name
Test status
Simulation time 65352742 ps
CPU time 2.26 seconds
Started May 19 01:50:13 PM PDT 24
Finished May 19 01:50:18 PM PDT 24
Peak memory 206816 kb
Host smart-5ca083e5-9d1b-40c9-a4d4-e6335c9b13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835510527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2835510527
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2947272791
Short name T252
Test name
Test status
Simulation time 287968983 ps
CPU time 8.21 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 210456 kb
Host smart-d36c76d6-7461-4572-a98b-1296d430b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947272791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2947272791
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1298390389
Short name T452
Test name
Test status
Simulation time 339135051 ps
CPU time 3.26 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 209984 kb
Host smart-9369b490-2b81-42af-9fd7-c61ef60f0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298390389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1298390389
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3459072919
Short name T663
Test name
Test status
Simulation time 22124806 ps
CPU time 0.74 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 206004 kb
Host smart-10d51993-1916-4dcd-9ec9-83db1e1d64be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459072919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3459072919
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3676686814
Short name T33
Test name
Test status
Simulation time 1664689866 ps
CPU time 3.85 seconds
Started May 19 01:50:20 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 208656 kb
Host smart-497d5941-e51f-4a61-8f80-38ddd08f8866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676686814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3676686814
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3130364606
Short name T78
Test name
Test status
Simulation time 222158303 ps
CPU time 8.65 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 214300 kb
Host smart-88596263-0e68-41b1-a77c-3a1b9c1f5634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130364606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3130364606
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1570657466
Short name T321
Test name
Test status
Simulation time 286795440 ps
CPU time 6.52 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 214300 kb
Host smart-c7c027c3-90b2-4039-ac15-a5280b292bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570657466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1570657466
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.326691702
Short name T476
Test name
Test status
Simulation time 452195185 ps
CPU time 2.99 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 222432 kb
Host smart-db92c550-26e0-493d-8081-827b63c77695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326691702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.326691702
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1528895126
Short name T214
Test name
Test status
Simulation time 175660219 ps
CPU time 2.78 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 215700 kb
Host smart-33bf3e54-b688-47b8-ae9e-011bc5a05866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528895126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1528895126
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1246570443
Short name T232
Test name
Test status
Simulation time 968623509 ps
CPU time 7.27 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 218348 kb
Host smart-b0602cc0-4cad-4a0e-831d-390a5629f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246570443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1246570443
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3548693558
Short name T456
Test name
Test status
Simulation time 745175156 ps
CPU time 6.43 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 206920 kb
Host smart-33d1713d-731b-4740-8833-d1b72a01238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548693558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3548693558
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3152957462
Short name T596
Test name
Test status
Simulation time 355953375 ps
CPU time 2.93 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 206948 kb
Host smart-48d57514-29b5-4c09-9c0d-42e8148758c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152957462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3152957462
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1622640267
Short name T843
Test name
Test status
Simulation time 66357877 ps
CPU time 2.72 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 208076 kb
Host smart-71420453-bb06-4aa3-8351-29a2c97397c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622640267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1622640267
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4071716171
Short name T438
Test name
Test status
Simulation time 375134476 ps
CPU time 3.32 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 214344 kb
Host smart-4d09173f-28cc-4116-b71b-3ed72c2b7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071716171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4071716171
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.969051045
Short name T81
Test name
Test status
Simulation time 54001270 ps
CPU time 2.73 seconds
Started May 19 01:50:14 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 208576 kb
Host smart-7820f6e2-b459-49a1-9936-32df20e5a37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969051045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.969051045
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.677112344
Short name T311
Test name
Test status
Simulation time 42863857474 ps
CPU time 471.69 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:58:25 PM PDT 24
Peak memory 222656 kb
Host smart-1d595253-054d-49e5-99c1-4bc3b0505633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677112344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.677112344
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2543560007
Short name T656
Test name
Test status
Simulation time 395842597 ps
CPU time 15.1 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:50 PM PDT 24
Peak memory 221048 kb
Host smart-5bf99d75-a954-47f0-9cb8-9f9719ba95d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543560007 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2543560007
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.798977996
Short name T332
Test name
Test status
Simulation time 67714126 ps
CPU time 3.39 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 218220 kb
Host smart-3c66381f-a360-4f80-85a9-06b53e9a8b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798977996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.798977996
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3696104469
Short name T509
Test name
Test status
Simulation time 194868340 ps
CPU time 2.37 seconds
Started May 19 01:50:22 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 210136 kb
Host smart-be9dff4a-273b-40b6-ad98-b0554b6df5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696104469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3696104469
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.309819815
Short name T698
Test name
Test status
Simulation time 9137761 ps
CPU time 0.79 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 205940 kb
Host smart-f3fd92eb-ad8d-4172-8ebc-307524dd5049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309819815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.309819815
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3179910064
Short name T298
Test name
Test status
Simulation time 373999306 ps
CPU time 3.15 seconds
Started May 19 01:50:19 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 215500 kb
Host smart-937b9a28-a864-45b0-b1a8-10790f80f877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179910064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3179910064
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4002896795
Short name T523
Test name
Test status
Simulation time 62548198 ps
CPU time 2.81 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 218692 kb
Host smart-f63f4b4b-8d0c-4439-ab6d-995982a423c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002896795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4002896795
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4243903098
Short name T823
Test name
Test status
Simulation time 31098321 ps
CPU time 2.04 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:26 PM PDT 24
Peak memory 214376 kb
Host smart-699c757d-61ca-4f08-b94d-454f73048fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243903098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4243903098
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1459400599
Short name T831
Test name
Test status
Simulation time 298237951 ps
CPU time 3.76 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 214240 kb
Host smart-23270514-e39b-43ca-a9fc-c825914d8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459400599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1459400599
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.211306787
Short name T492
Test name
Test status
Simulation time 379635898 ps
CPU time 3.73 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 209560 kb
Host smart-ad56e43a-2a8e-4cb9-bdcf-ecdf9cff98b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211306787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.211306787
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1982394336
Short name T860
Test name
Test status
Simulation time 378104348 ps
CPU time 9.89 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:46 PM PDT 24
Peak memory 214280 kb
Host smart-97b8075e-1b07-4c1c-bb1e-f44fcac9afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982394336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1982394336
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1192191123
Short name T86
Test name
Test status
Simulation time 236283815 ps
CPU time 3.37 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 206852 kb
Host smart-e0dfdf4f-b9a1-4784-879f-66fee4785f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192191123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1192191123
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.617825779
Short name T280
Test name
Test status
Simulation time 450698177 ps
CPU time 8.89 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 208528 kb
Host smart-2f448076-fde3-4c30-a677-75d2bea129fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617825779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.617825779
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3463338505
Short name T343
Test name
Test status
Simulation time 237743570 ps
CPU time 9.12 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 208396 kb
Host smart-22d3b613-6d66-47bc-848c-a96a4dedc51e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463338505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3463338505
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3254750891
Short name T877
Test name
Test status
Simulation time 559629955 ps
CPU time 19.34 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 208332 kb
Host smart-30719cc7-5dc8-44c6-b3d7-f8b807d78c94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254750891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3254750891
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1725095731
Short name T604
Test name
Test status
Simulation time 48722198 ps
CPU time 2.36 seconds
Started May 19 01:50:23 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 208968 kb
Host smart-47228b74-f97e-4859-8d5e-ec36152533f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725095731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1725095731
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3075761140
Short name T391
Test name
Test status
Simulation time 989475572 ps
CPU time 3.6 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 208676 kb
Host smart-39c2a7cf-321f-4b1c-afce-5e564925c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075761140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3075761140
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2828805463
Short name T250
Test name
Test status
Simulation time 327304806 ps
CPU time 8.6 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 216736 kb
Host smart-6353a644-35b6-44de-a207-c7255087a589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828805463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2828805463
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2913650855
Short name T486
Test name
Test status
Simulation time 4759434072 ps
CPU time 33.03 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:58 PM PDT 24
Peak memory 218488 kb
Host smart-b47ee9ef-944e-4fb5-b1fb-e35e6f72b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913650855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2913650855
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1925023410
Short name T895
Test name
Test status
Simulation time 168078398 ps
CPU time 2.42 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 210388 kb
Host smart-533db635-a9b0-45c2-83e2-3e868253a899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925023410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1925023410
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.570786829
Short name T443
Test name
Test status
Simulation time 34352021 ps
CPU time 0.69 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 205968 kb
Host smart-ba9e3014-007c-42a6-b9cc-e85149949aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570786829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.570786829
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.29186068
Short name T411
Test name
Test status
Simulation time 226651299 ps
CPU time 4.42 seconds
Started May 19 01:49:34 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 215344 kb
Host smart-9e09a238-b092-4d89-9c08-8c946a630850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29186068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.29186068
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3584207591
Short name T894
Test name
Test status
Simulation time 1040130143 ps
CPU time 6.42 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 217200 kb
Host smart-c9e77d50-7cf3-4d11-b03e-2e9d1f7644f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584207591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3584207591
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3153675833
Short name T262
Test name
Test status
Simulation time 116294154 ps
CPU time 2.25 seconds
Started May 19 01:49:40 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 218436 kb
Host smart-9de32f74-3234-4551-8791-955a9e110928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153675833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3153675833
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.831289144
Short name T372
Test name
Test status
Simulation time 130740726 ps
CPU time 4.98 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:52 PM PDT 24
Peak memory 214384 kb
Host smart-67ca8149-fac8-4100-a6e6-3bea2b34d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831289144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.831289144
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1343691006
Short name T890
Test name
Test status
Simulation time 113032379 ps
CPU time 4.56 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 206084 kb
Host smart-44e95710-3c13-420d-be04-4e1174e839be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343691006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1343691006
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1333373146
Short name T17
Test name
Test status
Simulation time 108038818 ps
CPU time 1.93 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 206636 kb
Host smart-06c4d0ed-0d14-4385-83ed-9e6594ee7cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333373146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1333373146
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.4289217669
Short name T766
Test name
Test status
Simulation time 179686116 ps
CPU time 3.15 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 207644 kb
Host smart-3f0fecb5-7d87-4d60-b789-e8346c1cb777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289217669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4289217669
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3854319179
Short name T13
Test name
Test status
Simulation time 911802888 ps
CPU time 5.7 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:50 PM PDT 24
Peak memory 229344 kb
Host smart-3789761a-0ea7-432e-80be-c76faf25b610
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854319179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3854319179
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3736896082
Short name T245
Test name
Test status
Simulation time 286945659 ps
CPU time 2.74 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 206728 kb
Host smart-b58c1167-14cb-4702-8c89-f8510b4f5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736896082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3736896082
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3697358762
Short name T426
Test name
Test status
Simulation time 65090016 ps
CPU time 1.74 seconds
Started May 19 01:49:33 PM PDT 24
Finished May 19 01:49:39 PM PDT 24
Peak memory 206892 kb
Host smart-8c4b3117-2838-48be-90f0-942b2b787b5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697358762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3697358762
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3788056113
Short name T848
Test name
Test status
Simulation time 51595476 ps
CPU time 2.82 seconds
Started May 19 01:49:59 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 208932 kb
Host smart-5827539e-615f-4cb4-8dcf-63b3f0d9b1ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788056113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3788056113
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1150712688
Short name T84
Test name
Test status
Simulation time 83252134 ps
CPU time 3.79 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 208936 kb
Host smart-67d4edb0-9e2d-4616-b40a-b41acf2d74d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150712688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1150712688
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4124450195
Short name T637
Test name
Test status
Simulation time 436752347 ps
CPU time 4.02 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 208044 kb
Host smart-6f6681b1-92e2-4176-98a7-be6a353888db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124450195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4124450195
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3648744058
Short name T581
Test name
Test status
Simulation time 148357875 ps
CPU time 2.46 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 207004 kb
Host smart-2c4f0a5e-f264-4aff-976e-e75f8f0326e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648744058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3648744058
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1764173033
Short name T77
Test name
Test status
Simulation time 1620056220 ps
CPU time 21.48 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:50:14 PM PDT 24
Peak memory 222400 kb
Host smart-381123b0-5890-475e-aeb7-8c2b1bf017a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764173033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1764173033
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1928670195
Short name T141
Test name
Test status
Simulation time 7995714532 ps
CPU time 23.63 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 222724 kb
Host smart-76c9c2d4-084b-4a28-b421-9a39aac091f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928670195 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1928670195
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1630649207
Short name T571
Test name
Test status
Simulation time 175739717 ps
CPU time 4.06 seconds
Started May 19 01:49:46 PM PDT 24
Finished May 19 01:49:51 PM PDT 24
Peak memory 209736 kb
Host smart-0c63416e-62cf-4e53-a6b1-cf2380abcd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630649207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1630649207
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3740441215
Short name T63
Test name
Test status
Simulation time 1390833795 ps
CPU time 6.33 seconds
Started May 19 01:49:33 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 210788 kb
Host smart-d2d99a34-957a-4269-90f6-799d8493daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740441215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3740441215
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3211895249
Short name T415
Test name
Test status
Simulation time 20373015 ps
CPU time 0.72 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 205900 kb
Host smart-c6277499-d6cc-4bec-9108-dcb57fd94f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211895249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3211895249
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1105007239
Short name T828
Test name
Test status
Simulation time 170228659 ps
CPU time 3.21 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 214348 kb
Host smart-c36df77d-4d01-493d-be19-db05d1de8ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105007239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1105007239
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2361011217
Short name T21
Test name
Test status
Simulation time 170769149 ps
CPU time 4.66 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 209968 kb
Host smart-e977610a-7e96-4f9c-9be5-86cef60e3ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361011217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2361011217
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.955429444
Short name T527
Test name
Test status
Simulation time 27688654 ps
CPU time 1.68 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 208232 kb
Host smart-c2045817-1a15-4879-a5ea-bf58e6fb4b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955429444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.955429444
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2032787850
Short name T97
Test name
Test status
Simulation time 61085809 ps
CPU time 3.58 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 220476 kb
Host smart-df5948a2-0b52-4ada-8361-a8bb7fc213b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032787850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2032787850
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3271866199
Short name T257
Test name
Test status
Simulation time 101663638 ps
CPU time 2.72 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 214288 kb
Host smart-530b3ec2-a28c-43f1-a1d7-c552c3e703c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271866199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3271866199
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3109634762
Short name T513
Test name
Test status
Simulation time 83915512 ps
CPU time 3.64 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:24 PM PDT 24
Peak memory 208000 kb
Host smart-5645fba2-24f4-44c9-89bd-8498e5e7a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109634762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3109634762
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1634094771
Short name T774
Test name
Test status
Simulation time 710170358 ps
CPU time 9.64 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 214340 kb
Host smart-6d661814-dcb6-43c6-b6b0-db72af47c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634094771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1634094771
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3285505426
Short name T583
Test name
Test status
Simulation time 903025696 ps
CPU time 26.53 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 208136 kb
Host smart-abed23d1-e294-45cc-8f34-03a16352f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285505426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3285505426
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2809232291
Short name T874
Test name
Test status
Simulation time 193590332 ps
CPU time 2.89 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 206980 kb
Host smart-db25b25e-eb3e-44c0-af08-3b888b625b73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809232291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2809232291
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1443500627
Short name T720
Test name
Test status
Simulation time 241160022 ps
CPU time 8.53 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 209064 kb
Host smart-0cf57807-0c78-4c9a-ac13-eb3880243524
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443500627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1443500627
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.904607781
Short name T567
Test name
Test status
Simulation time 216267500 ps
CPU time 6.59 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 208600 kb
Host smart-0833f40c-3ac7-41f6-a6f6-5e1fc9a7ca43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904607781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.904607781
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.885759600
Short name T798
Test name
Test status
Simulation time 296034287 ps
CPU time 2.26 seconds
Started May 19 01:50:16 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 215508 kb
Host smart-60e4557e-613b-4ff5-a1f2-66f0ea9bf16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885759600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.885759600
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2129105995
Short name T725
Test name
Test status
Simulation time 281322871 ps
CPU time 1.9 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 208776 kb
Host smart-ede95ff8-226b-4db1-ad9e-df644c407dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129105995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2129105995
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2181555853
Short name T83
Test name
Test status
Simulation time 182770121 ps
CPU time 4.41 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 209828 kb
Host smart-786c97a6-0c9f-4607-b3ec-1c463cd08b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181555853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2181555853
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1520860801
Short name T697
Test name
Test status
Simulation time 233286570 ps
CPU time 2.43 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 209824 kb
Host smart-44bdd22d-c8d9-4db8-b84d-666dba40a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520860801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1520860801
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1062270299
Short name T594
Test name
Test status
Simulation time 33491568 ps
CPU time 0.77 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:33 PM PDT 24
Peak memory 205964 kb
Host smart-eddec447-8cd1-4df0-bab3-7a2a7ee9e364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062270299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1062270299
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.92053610
Short name T412
Test name
Test status
Simulation time 211764258 ps
CPU time 3.76 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 214352 kb
Host smart-14ccd03d-1072-445f-90d6-9aabd9394e3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92053610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.92053610
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1472993143
Short name T35
Test name
Test status
Simulation time 41718817 ps
CPU time 2.35 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 216164 kb
Host smart-9c3c808e-c382-4356-875a-2fe00f70f491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472993143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1472993143
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1888355996
Short name T905
Test name
Test status
Simulation time 611587500 ps
CPU time 4.97 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 214280 kb
Host smart-f1c54fd8-fe15-44c0-9bd8-d18569397cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888355996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1888355996
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.276288924
Short name T96
Test name
Test status
Simulation time 106937908 ps
CPU time 2.02 seconds
Started May 19 01:50:18 PM PDT 24
Finished May 19 01:50:23 PM PDT 24
Peak memory 214380 kb
Host smart-1c9ac6bd-43e0-40b8-b2b3-2a454b7e4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276288924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.276288924
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3441155315
Short name T727
Test name
Test status
Simulation time 258582941 ps
CPU time 2.4 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 214296 kb
Host smart-1ac2dee7-bb9d-44bd-b9a2-e47daa086c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441155315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3441155315
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.3600098500
Short name T867
Test name
Test status
Simulation time 456539161 ps
CPU time 4.7 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 218452 kb
Host smart-0f13abc6-d5b9-4139-8d4c-2caa56591863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600098500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3600098500
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2434757371
Short name T339
Test name
Test status
Simulation time 277193358 ps
CPU time 3.46 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 208900 kb
Host smart-31d45db2-f208-45d7-80c2-1eddfd7c8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434757371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2434757371
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3393850638
Short name T267
Test name
Test status
Simulation time 30518684 ps
CPU time 2.24 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 206852 kb
Host smart-aed8c512-11ec-4c95-9d01-ba3749d45a85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393850638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3393850638
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1500940222
Short name T795
Test name
Test status
Simulation time 74365075 ps
CPU time 3.5 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 208592 kb
Host smart-7b93b7e6-32cd-4083-9ad1-288cf73e499c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500940222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1500940222
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1089203696
Short name T846
Test name
Test status
Simulation time 96341150 ps
CPU time 3.4 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 208656 kb
Host smart-6f351084-38ae-4ec4-ab06-35d34bede621
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089203696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1089203696
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2454727742
Short name T812
Test name
Test status
Simulation time 226313594 ps
CPU time 2.83 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 209860 kb
Host smart-d4d01623-8976-4b5e-ac25-22ef9e3221e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454727742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2454727742
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.232321623
Short name T507
Test name
Test status
Simulation time 23911342 ps
CPU time 1.9 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 208444 kb
Host smart-d68c3546-950e-49ae-aa18-657d2c69852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232321623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.232321623
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4281889766
Short name T286
Test name
Test status
Simulation time 104218206 ps
CPU time 4.47 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 218352 kb
Host smart-9fcdc133-ca79-4511-8bd3-f98850503332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281889766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4281889766
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3988989050
Short name T57
Test name
Test status
Simulation time 156490341 ps
CPU time 1.92 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 210208 kb
Host smart-61dd4e62-da94-47d2-92d0-5fa410e59647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988989050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3988989050
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.91957594
Short name T104
Test name
Test status
Simulation time 44119999 ps
CPU time 0.79 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:50:51 PM PDT 24
Peak memory 205864 kb
Host smart-475a4b9f-bf97-49ae-b0c1-3ddb72381ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91957594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.91957594
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2655210250
Short name T224
Test name
Test status
Simulation time 179719091 ps
CPU time 3.23 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 214392 kb
Host smart-083613aa-22f7-4daa-809b-9f8ad1f2d9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655210250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2655210250
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3556714454
Short name T219
Test name
Test status
Simulation time 477212679 ps
CPU time 7.49 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 210092 kb
Host smart-927c4d40-daa5-49f6-bd00-a3b17e488dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556714454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3556714454
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2138512404
Short name T705
Test name
Test status
Simulation time 153832575 ps
CPU time 2.16 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 207492 kb
Host smart-c6e7fff6-bd51-4668-9ceb-9843193ba8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138512404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2138512404
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.240017928
Short name T317
Test name
Test status
Simulation time 75372974 ps
CPU time 2.7 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 214304 kb
Host smart-c440e5d4-68fb-40d0-88cf-c48802b1afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240017928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.240017928
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1454488422
Short name T589
Test name
Test status
Simulation time 389055047 ps
CPU time 2.67 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 214300 kb
Host smart-66a849ea-644c-4cd5-9387-758bfc6059ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454488422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1454488422
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3655718595
Short name T688
Test name
Test status
Simulation time 307742824 ps
CPU time 7 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 209880 kb
Host smart-0ec5a0be-1148-4067-a58b-87fdd532cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655718595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3655718595
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4291321044
Short name T733
Test name
Test status
Simulation time 284989635 ps
CPU time 1.87 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 206908 kb
Host smart-26e13337-86be-48f1-a973-ca75ed3cd72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291321044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4291321044
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2020198498
Short name T805
Test name
Test status
Simulation time 113497091 ps
CPU time 3.11 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 207352 kb
Host smart-3e91907f-66dc-4dc1-8d3b-9e1a387b53e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020198498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2020198498
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3129394602
Short name T576
Test name
Test status
Simulation time 282100249 ps
CPU time 4.84 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 206888 kb
Host smart-18354e52-bfb1-4acf-a9ea-dbb7eae995c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129394602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3129394602
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2846426752
Short name T624
Test name
Test status
Simulation time 498490133 ps
CPU time 12.53 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:46 PM PDT 24
Peak memory 206888 kb
Host smart-1885a1d6-2d9e-479f-9d5d-48a72e7f34d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846426752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2846426752
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4284421118
Short name T237
Test name
Test status
Simulation time 54974212 ps
CPU time 2.34 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 214592 kb
Host smart-ebeb9521-8f21-4768-864c-632039710d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284421118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4284421118
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.92244645
Short name T445
Test name
Test status
Simulation time 167821295 ps
CPU time 3.33 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 208644 kb
Host smart-2ec2b0c1-65d1-4769-871d-e33aaa2d9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92244645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.92244645
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1670584670
Short name T204
Test name
Test status
Simulation time 11831248091 ps
CPU time 116.34 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:52:29 PM PDT 24
Peak memory 215244 kb
Host smart-a4499c33-c9ed-4314-aef1-c4728fab4056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670584670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1670584670
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2485913887
Short name T636
Test name
Test status
Simulation time 185874684 ps
CPU time 3.3 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 207580 kb
Host smart-60f02ad5-8ad8-4e38-abbb-04acb67dcdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485913887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2485913887
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.192118106
Short name T194
Test name
Test status
Simulation time 87025041 ps
CPU time 3.44 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 210044 kb
Host smart-828efc4d-c0f7-4acc-8112-b7a62c5f2881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192118106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.192118106
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4128537415
Short name T605
Test name
Test status
Simulation time 23019940 ps
CPU time 0.93 seconds
Started May 19 01:50:26 PM PDT 24
Finished May 19 01:50:29 PM PDT 24
Peak memory 205952 kb
Host smart-03d09f68-c670-4272-acb7-814f042acb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128537415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4128537415
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1927161328
Short name T371
Test name
Test status
Simulation time 348209515 ps
CPU time 4.25 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 210808 kb
Host smart-8534478f-c480-4fad-a9ff-a3824fefbf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927161328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1927161328
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3346809155
Short name T887
Test name
Test status
Simulation time 3937099514 ps
CPU time 17.43 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:56 PM PDT 24
Peak memory 219880 kb
Host smart-f1644c8a-6a62-4326-9179-73dc7f4fc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346809155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3346809155
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1275904435
Short name T247
Test name
Test status
Simulation time 234428145 ps
CPU time 3.55 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 208460 kb
Host smart-f458147a-8838-453e-a03e-00e887c8b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275904435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1275904435
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4214848274
Short name T228
Test name
Test status
Simulation time 116004603 ps
CPU time 4.35 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 214832 kb
Host smart-3be5f0ab-c9fc-4547-bd37-249d0d70d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214848274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4214848274
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3068017321
Short name T408
Test name
Test status
Simulation time 395986374 ps
CPU time 2.35 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 214300 kb
Host smart-272b6abf-c8c9-44af-8ccf-2c3f424bc258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068017321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3068017321
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3145137519
Short name T488
Test name
Test status
Simulation time 258368689 ps
CPU time 2.78 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 214300 kb
Host smart-ab976fa0-3c1a-4f52-ba0c-359a6c249c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145137519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3145137519
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2691393294
Short name T346
Test name
Test status
Simulation time 57901480 ps
CPU time 2.21 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:34 PM PDT 24
Peak memory 206748 kb
Host smart-8c7834f3-70d6-4230-850e-9edb8cba4a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691393294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2691393294
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1472484534
Short name T580
Test name
Test status
Simulation time 127447037 ps
CPU time 2.34 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 206948 kb
Host smart-036d13ff-2d17-4ca0-846c-f25bcaed1bdf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472484534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1472484534
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4168283801
Short name T431
Test name
Test status
Simulation time 1104226468 ps
CPU time 2.98 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 209004 kb
Host smart-5e86a5c5-d066-46a3-baa0-8a011c6dde0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168283801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4168283801
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4117793276
Short name T112
Test name
Test status
Simulation time 147913360 ps
CPU time 5.39 seconds
Started May 19 01:50:35 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 206876 kb
Host smart-6c1af07d-d7e1-4920-bb6c-5899a23ac1fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117793276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4117793276
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3579283271
Short name T807
Test name
Test status
Simulation time 76599964 ps
CPU time 3.16 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 207996 kb
Host smart-295e93cf-18cf-4d4a-b325-a73dc2276687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579283271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3579283271
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1321367396
Short name T110
Test name
Test status
Simulation time 20954766 ps
CPU time 1.76 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 206704 kb
Host smart-496cb5f7-4a87-4683-ba16-4fe0045c30b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321367396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1321367396
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1562582737
Short name T717
Test name
Test status
Simulation time 19685640760 ps
CPU time 34.48 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 216364 kb
Host smart-d8007a82-424d-4bdc-a3e7-7d650f1e5503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562582737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1562582737
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.963004107
Short name T760
Test name
Test status
Simulation time 801289548 ps
CPU time 12.32 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 222668 kb
Host smart-5eb9682a-b521-41c6-a488-c7a2985e2372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963004107 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.963004107
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.895923345
Short name T475
Test name
Test status
Simulation time 86186385 ps
CPU time 4.26 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 209152 kb
Host smart-b7ecbeff-fb87-4891-8901-82ac1ba8f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895923345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.895923345
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1598566422
Short name T175
Test name
Test status
Simulation time 97215926 ps
CPU time 1.9 seconds
Started May 19 01:50:35 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 210012 kb
Host smart-fd592c78-51d0-44b1-beb0-345144a4a892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598566422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1598566422
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1412036393
Short name T902
Test name
Test status
Simulation time 23728988 ps
CPU time 0.88 seconds
Started May 19 01:50:50 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 205980 kb
Host smart-d8c03569-ea86-42ec-82b6-e721504c1649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412036393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1412036393
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.250637058
Short name T385
Test name
Test status
Simulation time 36398697 ps
CPU time 2.81 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 214360 kb
Host smart-d8c8e3ce-d82e-4c0f-aef5-da7e2cfb0f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250637058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.250637058
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.744973011
Short name T628
Test name
Test status
Simulation time 1095296180 ps
CPU time 5.55 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 214248 kb
Host smart-3e7802d6-9d1a-4a4a-8477-39ab40aea416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744973011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.744973011
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.779693950
Short name T709
Test name
Test status
Simulation time 344750540 ps
CPU time 10.85 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 208608 kb
Host smart-1811dfb4-55f3-4eb3-9a53-7505221911fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779693950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.779693950
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1024878703
Short name T558
Test name
Test status
Simulation time 168415704 ps
CPU time 3.77 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 209520 kb
Host smart-edc553f6-ed78-4750-8985-777275b47d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024878703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1024878703
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.867777885
Short name T92
Test name
Test status
Simulation time 56775920 ps
CPU time 3.09 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 214260 kb
Host smart-f2ccae99-583b-4788-a42e-6abb371065bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867777885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.867777885
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3356110948
Short name T655
Test name
Test status
Simulation time 634606266 ps
CPU time 4.17 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 215436 kb
Host smart-e1e39e03-0b2f-49bd-9175-82be5b744c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356110948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3356110948
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.252257497
Short name T627
Test name
Test status
Simulation time 118514587 ps
CPU time 5.18 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 209428 kb
Host smart-74d04a50-a625-4b52-b7a9-1698980eb021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252257497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.252257497
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1892593660
Short name T862
Test name
Test status
Simulation time 50653648 ps
CPU time 2.72 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:30 PM PDT 24
Peak memory 206928 kb
Host smart-2c91a958-b1c4-40f1-9c02-ca6a76ef9fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892593660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1892593660
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2239930048
Short name T541
Test name
Test status
Simulation time 794482613 ps
CPU time 6.44 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:37 PM PDT 24
Peak memory 208316 kb
Host smart-37269be9-0e76-441b-9fa2-aefdc5c680d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239930048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2239930048
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3564838871
Short name T199
Test name
Test status
Simulation time 239063492 ps
CPU time 3.89 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 206992 kb
Host smart-6bf1222b-bb0c-49e6-9995-8e9eb2c4a416
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564838871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3564838871
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3958526077
Short name T80
Test name
Test status
Simulation time 1071380538 ps
CPU time 7.05 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 207804 kb
Host smart-5a7b20f9-a0f7-4280-8a69-db71c7b3c484
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958526077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3958526077
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3111736007
Short name T622
Test name
Test status
Simulation time 149335432 ps
CPU time 3.71 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 208548 kb
Host smart-5f6ad4b3-14a0-43eb-8e24-450b01eef569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111736007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3111736007
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3442563746
Short name T611
Test name
Test status
Simulation time 382550247 ps
CPU time 4.29 seconds
Started May 19 01:50:25 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 208404 kb
Host smart-149ed3d0-7182-4d4f-b39a-56d2c00fcd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442563746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3442563746
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4158802259
Short name T28
Test name
Test status
Simulation time 4995953464 ps
CPU time 106.7 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 222404 kb
Host smart-455a5071-3d9e-4719-b9b0-b31e1942d9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158802259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4158802259
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.85023302
Short name T184
Test name
Test status
Simulation time 712227052 ps
CPU time 11.86 seconds
Started May 19 01:50:27 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 222608 kb
Host smart-bf498b4a-93e8-435a-96c3-25ab092237a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85023302 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.85023302
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3739884911
Short name T824
Test name
Test status
Simulation time 269344561 ps
CPU time 7.86 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 208240 kb
Host smart-fc7ce01d-483a-4600-bc8a-9074314dd9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739884911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3739884911
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3679443448
Short name T39
Test name
Test status
Simulation time 51371995 ps
CPU time 2.11 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 210104 kb
Host smart-094fdbe9-1d12-41dc-8364-9b5a33de802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679443448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3679443448
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.271188586
Short name T487
Test name
Test status
Simulation time 75589259 ps
CPU time 0.94 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 205960 kb
Host smart-b2e55380-2a61-468d-a804-919be83be488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271188586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.271188586
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1375873596
Short name T533
Test name
Test status
Simulation time 61626544 ps
CPU time 1.9 seconds
Started May 19 01:50:51 PM PDT 24
Finished May 19 01:50:54 PM PDT 24
Peak memory 210180 kb
Host smart-82c5b8c0-0fd8-4e8f-8444-67a656345297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375873596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1375873596
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.39313064
Short name T365
Test name
Test status
Simulation time 478626328 ps
CPU time 12 seconds
Started May 19 01:50:34 PM PDT 24
Finished May 19 01:50:50 PM PDT 24
Peak memory 207988 kb
Host smart-bfe6e0ff-2f9b-45c0-ad10-20e146e861dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39313064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.39313064
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4281081776
Short name T292
Test name
Test status
Simulation time 84733593 ps
CPU time 2.04 seconds
Started May 19 01:50:43 PM PDT 24
Finished May 19 01:50:46 PM PDT 24
Peak memory 214496 kb
Host smart-a06e3ef1-bc48-4a0d-b53e-1ea0f0e40572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281081776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4281081776
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3607316927
Short name T787
Test name
Test status
Simulation time 383509451 ps
CPU time 2.45 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 206372 kb
Host smart-90c3b638-6a35-4d51-98f9-fd8d8c07e2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607316927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3607316927
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.554518402
Short name T664
Test name
Test status
Simulation time 94381511 ps
CPU time 4.25 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:50:54 PM PDT 24
Peak memory 210284 kb
Host smart-ce5f96d9-4a39-44ff-85ef-b3a24ea6587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554518402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.554518402
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1093671765
Short name T716
Test name
Test status
Simulation time 181566694 ps
CPU time 2.34 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 206136 kb
Host smart-1fc78d96-fb53-410b-9154-312054e5f754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093671765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1093671765
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2350870380
Short name T499
Test name
Test status
Simulation time 147786332 ps
CPU time 3.27 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:35 PM PDT 24
Peak memory 206948 kb
Host smart-53c05e12-15f3-4d48-b6b1-457a60328b22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350870380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2350870380
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1815975586
Short name T679
Test name
Test status
Simulation time 94369618 ps
CPU time 3.91 seconds
Started May 19 01:50:42 PM PDT 24
Finished May 19 01:50:46 PM PDT 24
Peak memory 206840 kb
Host smart-895c892a-5a7e-4f82-94f4-f255688e3919
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815975586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1815975586
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.312989262
Short name T891
Test name
Test status
Simulation time 191120052 ps
CPU time 2.7 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 208764 kb
Host smart-02be50cb-a7e8-4ad7-84d3-14e6c3c1e123
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312989262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.312989262
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2203100796
Short name T521
Test name
Test status
Simulation time 1175607945 ps
CPU time 22.71 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 208400 kb
Host smart-e1d3a7f2-c30e-4fac-b689-940018b1e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203100796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2203100796
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2113913671
Short name T441
Test name
Test status
Simulation time 47273765 ps
CPU time 1.96 seconds
Started May 19 01:50:29 PM PDT 24
Finished May 19 01:50:36 PM PDT 24
Peak memory 208540 kb
Host smart-0a26631b-bf84-48ba-86c1-17cda79a4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113913671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2113913671
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1786847711
Short name T207
Test name
Test status
Simulation time 3903871352 ps
CPU time 47.79 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 222576 kb
Host smart-75a66485-4856-4538-8927-8cd6b67641be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786847711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1786847711
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.4213646162
Short name T863
Test name
Test status
Simulation time 875184400 ps
CPU time 8.87 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 217392 kb
Host smart-a965233b-1d4a-4cab-9fb7-8453ac8ac7dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213646162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.4213646162
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1466666790
Short name T379
Test name
Test status
Simulation time 57538813 ps
CPU time 1.9 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:00 PM PDT 24
Peak memory 209704 kb
Host smart-ef0edbe5-9bd2-4d34-8230-838d3563fbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466666790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1466666790
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1922085305
Short name T429
Test name
Test status
Simulation time 52570001 ps
CPU time 0.86 seconds
Started May 19 01:50:47 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 205984 kb
Host smart-f27d8866-87a9-41d5-a80d-fcdacbfa1546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922085305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1922085305
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.179715848
Short name T384
Test name
Test status
Simulation time 71794174 ps
CPU time 2.63 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 214364 kb
Host smart-cfafc3e1-4108-4835-8072-a85c17001432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179715848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.179715848
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4001914163
Short name T31
Test name
Test status
Simulation time 838826864 ps
CPU time 2.3 seconds
Started May 19 01:50:51 PM PDT 24
Finished May 19 01:50:54 PM PDT 24
Peak memory 214640 kb
Host smart-e6fa1d46-1d75-4418-8f14-73dfc9d231ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001914163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4001914163
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1090663698
Short name T453
Test name
Test status
Simulation time 26478896 ps
CPU time 1.85 seconds
Started May 19 01:50:40 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 208032 kb
Host smart-9b28049a-93a7-435f-8e9f-1fc5e6621a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090663698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1090663698
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2645358841
Short name T27
Test name
Test status
Simulation time 67179049 ps
CPU time 3.33 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 209384 kb
Host smart-4d669afb-8282-408e-959e-942c99636ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645358841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2645358841
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1406736767
Short name T888
Test name
Test status
Simulation time 140199353 ps
CPU time 2.69 seconds
Started May 19 01:50:48 PM PDT 24
Finished May 19 01:50:51 PM PDT 24
Peak memory 214272 kb
Host smart-bc6afe66-4162-4483-8978-57219d62481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406736767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1406736767
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3975150614
Short name T278
Test name
Test status
Simulation time 192100639 ps
CPU time 3.14 seconds
Started May 19 01:50:42 PM PDT 24
Finished May 19 01:50:45 PM PDT 24
Peak memory 220340 kb
Host smart-edd34c24-0931-4b23-b01b-4476de6f0033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975150614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3975150614
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1941841679
Short name T814
Test name
Test status
Simulation time 273726730 ps
CPU time 4.66 seconds
Started May 19 01:50:34 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 207452 kb
Host smart-b87caa07-7343-46bd-abdd-d61c3b07ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941841679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1941841679
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2658895993
Short name T355
Test name
Test status
Simulation time 128993873 ps
CPU time 2.79 seconds
Started May 19 01:50:30 PM PDT 24
Finished May 19 01:50:38 PM PDT 24
Peak memory 208540 kb
Host smart-788ea00e-9759-458b-a830-1f8947459484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658895993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2658895993
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3712318765
Short name T790
Test name
Test status
Simulation time 70458136 ps
CPU time 2.87 seconds
Started May 19 01:50:31 PM PDT 24
Finished May 19 01:50:39 PM PDT 24
Peak memory 207908 kb
Host smart-6008a703-0854-490f-8636-f567bddf3257
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712318765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3712318765
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.50618655
Short name T566
Test name
Test status
Simulation time 548398518 ps
CPU time 5 seconds
Started May 19 01:50:32 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 207048 kb
Host smart-d7531c36-4a36-41b0-87d8-7e9074a381de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50618655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.50618655
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3390705349
Short name T108
Test name
Test status
Simulation time 1521704935 ps
CPU time 9.14 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 208984 kb
Host smart-2b379613-27ce-4790-9ca8-2a5b64f37958
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390705349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3390705349
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3665559883
Short name T618
Test name
Test status
Simulation time 66292591 ps
CPU time 3.17 seconds
Started May 19 01:50:35 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 218280 kb
Host smart-ec2a9750-16dd-4077-b9a4-8b159ac56754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665559883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3665559883
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1756036280
Short name T579
Test name
Test status
Simulation time 170588510 ps
CPU time 2.28 seconds
Started May 19 01:50:28 PM PDT 24
Finished May 19 01:50:40 PM PDT 24
Peak memory 206904 kb
Host smart-674db4db-0b0c-4ea3-9b7c-9f65d45e6012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756036280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1756036280
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2702825227
Short name T6
Test name
Test status
Simulation time 259321423 ps
CPU time 5.02 seconds
Started May 19 01:50:56 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 216500 kb
Host smart-e4f1c446-89a0-4e2e-acb1-05b7026a7377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702825227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2702825227
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3966666772
Short name T140
Test name
Test status
Simulation time 759078285 ps
CPU time 8.79 seconds
Started May 19 01:50:44 PM PDT 24
Finished May 19 01:50:53 PM PDT 24
Peak memory 219968 kb
Host smart-4f3d7cec-7e47-4b14-a888-bcfcb8ca660d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966666772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3966666772
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1960981544
Short name T196
Test name
Test status
Simulation time 10699955289 ps
CPU time 71.49 seconds
Started May 19 01:50:34 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 209276 kb
Host smart-a74a0324-41b3-4124-bf1c-2d04468a71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960981544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1960981544
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2125508477
Short name T380
Test name
Test status
Simulation time 1598815476 ps
CPU time 24.18 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 211220 kb
Host smart-62c4785f-72c0-443e-b694-f5209a64c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125508477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2125508477
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.466315649
Short name T840
Test name
Test status
Simulation time 46708026 ps
CPU time 0.9 seconds
Started May 19 01:50:43 PM PDT 24
Finished May 19 01:50:45 PM PDT 24
Peak memory 205976 kb
Host smart-e4c622e8-a246-438e-9667-3e3e32a0a8bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466315649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.466315649
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4027336560
Short name T387
Test name
Test status
Simulation time 126669594 ps
CPU time 7.08 seconds
Started May 19 01:50:52 PM PDT 24
Finished May 19 01:51:00 PM PDT 24
Peak memory 222532 kb
Host smart-e453e3c0-840a-4bad-bd74-a3b9e7559290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027336560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4027336560
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1760236840
Short name T34
Test name
Test status
Simulation time 97026970 ps
CPU time 1.2 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:50:55 PM PDT 24
Peak memory 214224 kb
Host smart-ed58be8c-d3ab-4903-b728-361b529b0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760236840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1760236840
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.115058049
Short name T98
Test name
Test status
Simulation time 2366857246 ps
CPU time 30.81 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 214312 kb
Host smart-0c8dee1c-6f26-4b4e-8d14-e01642465ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115058049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.115058049
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4088762715
Short name T730
Test name
Test status
Simulation time 295658457 ps
CPU time 2.9 seconds
Started May 19 01:50:45 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 214316 kb
Host smart-3f00641a-0a29-44cb-9218-a5fc50d62b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088762715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4088762715
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.758223634
Short name T763
Test name
Test status
Simulation time 219604499 ps
CPU time 2.87 seconds
Started May 19 01:50:58 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 207604 kb
Host smart-08f03316-4c67-4d4a-9790-fbd56db915ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758223634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.758223634
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3791354384
Short name T833
Test name
Test status
Simulation time 191334318 ps
CPU time 2.86 seconds
Started May 19 01:50:55 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 206152 kb
Host smart-776cd67d-47f5-44f8-b3f4-c68e382728f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791354384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3791354384
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.678204419
Short name T358
Test name
Test status
Simulation time 249541016 ps
CPU time 3.09 seconds
Started May 19 01:50:55 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 208792 kb
Host smart-2d6d452d-6896-4f71-b4db-2db1aa57393b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678204419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.678204419
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2184264528
Short name T485
Test name
Test status
Simulation time 154559266 ps
CPU time 5.52 seconds
Started May 19 01:50:33 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 207016 kb
Host smart-3a8b8854-e867-412e-b64c-0d3fd9be71cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184264528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2184264528
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.324057905
Short name T543
Test name
Test status
Simulation time 31852817 ps
CPU time 2.18 seconds
Started May 19 01:50:59 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 209352 kb
Host smart-96b04fe1-e019-46dc-9a16-691f4c77002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324057905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.324057905
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2143074987
Short name T462
Test name
Test status
Simulation time 260382204 ps
CPU time 3.2 seconds
Started May 19 01:50:37 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 206780 kb
Host smart-1a86c2fe-6482-48a1-be7a-e9d6312d430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143074987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2143074987
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.4172323400
Short name T187
Test name
Test status
Simulation time 1047325150 ps
CPU time 18.63 seconds
Started May 19 01:50:42 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 222532 kb
Host smart-cf5fc3cb-233b-4ea1-a138-9b632919c627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172323400 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.4172323400
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.989116300
Short name T555
Test name
Test status
Simulation time 2776815151 ps
CPU time 28.28 seconds
Started May 19 01:50:58 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 208692 kb
Host smart-c23b41d5-be81-41da-b2b5-3e43a98b356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989116300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.989116300
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3417566649
Short name T855
Test name
Test status
Simulation time 296348862 ps
CPU time 1.68 seconds
Started May 19 01:50:51 PM PDT 24
Finished May 19 01:50:53 PM PDT 24
Peak memory 209624 kb
Host smart-288b7c75-f30f-42f8-aa6e-7088a5c7ae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417566649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3417566649
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4192059148
Short name T897
Test name
Test status
Simulation time 68519930 ps
CPU time 0.75 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:50:55 PM PDT 24
Peak memory 205784 kb
Host smart-b82b4d04-9f3b-401a-a3c4-6ce67d68a12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192059148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4192059148
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1953165001
Short name T109
Test name
Test status
Simulation time 191706716 ps
CPU time 2.75 seconds
Started May 19 01:50:37 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 215280 kb
Host smart-ef013810-5861-4f9e-af6f-b5ab2a9213f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953165001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1953165001
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1802436284
Short name T672
Test name
Test status
Simulation time 290420333 ps
CPU time 3.33 seconds
Started May 19 01:50:38 PM PDT 24
Finished May 19 01:50:43 PM PDT 24
Peak memory 208428 kb
Host smart-777da618-85fb-4762-9ee5-c0dfbbd49812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802436284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1802436284
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1237734444
Short name T397
Test name
Test status
Simulation time 1977862475 ps
CPU time 22.2 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:20 PM PDT 24
Peak memory 209408 kb
Host smart-2ac28fbe-a090-4a40-a94b-34fd8c0da447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237734444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1237734444
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1546247148
Short name T297
Test name
Test status
Simulation time 83598045 ps
CPU time 2.9 seconds
Started May 19 01:50:41 PM PDT 24
Finished May 19 01:50:45 PM PDT 24
Peak memory 214356 kb
Host smart-366acb23-1f2a-4e99-bb27-2b0157dcca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546247148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1546247148
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.335072440
Short name T293
Test name
Test status
Simulation time 151772267 ps
CPU time 2.74 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 214272 kb
Host smart-14f46989-2ec8-4c10-aa45-6e42dd25d617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335072440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.335072440
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.166618894
Short name T654
Test name
Test status
Simulation time 190494386 ps
CPU time 3.39 seconds
Started May 19 01:50:51 PM PDT 24
Finished May 19 01:50:55 PM PDT 24
Peak memory 210360 kb
Host smart-31d33434-7bd3-4935-92e4-1c96a65f4774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166618894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.166618894
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.468794720
Short name T454
Test name
Test status
Simulation time 3099651572 ps
CPU time 18.83 seconds
Started May 19 01:50:48 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 209412 kb
Host smart-8dfb8cc1-35f8-43da-ae22-4b2b9e795f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468794720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.468794720
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3711944436
Short name T858
Test name
Test status
Simulation time 241254844 ps
CPU time 8.27 seconds
Started May 19 01:50:37 PM PDT 24
Finished May 19 01:50:47 PM PDT 24
Peak memory 208028 kb
Host smart-078a93f8-6c7d-4e0e-be0c-93d035d4b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711944436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3711944436
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2156855151
Short name T528
Test name
Test status
Simulation time 150044307 ps
CPU time 2.93 seconds
Started May 19 01:50:55 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 206884 kb
Host smart-0924ccf2-9eca-4220-8b8d-edd2192627bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156855151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2156855151
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.98045240
Short name T626
Test name
Test status
Simulation time 128200675 ps
CPU time 2.83 seconds
Started May 19 01:50:38 PM PDT 24
Finished May 19 01:50:42 PM PDT 24
Peak memory 206900 kb
Host smart-4f936a8e-b05d-430b-a4c6-91e724f3620f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98045240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.98045240
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.227925980
Short name T723
Test name
Test status
Simulation time 128182644 ps
CPU time 3.27 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 208872 kb
Host smart-a66d9873-4f85-4dd2-9d5b-d5387be96034
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227925980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.227925980
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4064095004
Short name T693
Test name
Test status
Simulation time 238725212 ps
CPU time 2.41 seconds
Started May 19 01:50:44 PM PDT 24
Finished May 19 01:50:47 PM PDT 24
Peak memory 209796 kb
Host smart-96c7f595-027f-42d5-8c55-feff2085c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064095004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4064095004
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.997982682
Short name T82
Test name
Test status
Simulation time 39105747 ps
CPU time 2.36 seconds
Started May 19 01:50:36 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 208392 kb
Host smart-cd2f212e-ccb0-406d-9e22-6b16ba8e6e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997982682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.997982682
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1736400407
Short name T770
Test name
Test status
Simulation time 16506904 ps
CPU time 0.95 seconds
Started May 19 01:50:42 PM PDT 24
Finished May 19 01:50:44 PM PDT 24
Peak memory 206412 kb
Host smart-afd7ed57-b770-4d75-aa1d-aa8a6d660fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736400407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1736400407
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2995630415
Short name T130
Test name
Test status
Simulation time 137997513 ps
CPU time 6.43 seconds
Started May 19 01:50:47 PM PDT 24
Finished May 19 01:50:54 PM PDT 24
Peak memory 222568 kb
Host smart-13ffd2c8-5f4a-482a-8271-6480ff8c12a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995630415 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2995630415
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2964964433
Short name T883
Test name
Test status
Simulation time 2706218865 ps
CPU time 9.77 seconds
Started May 19 01:50:50 PM PDT 24
Finished May 19 01:51:00 PM PDT 24
Peak memory 214492 kb
Host smart-aae84102-73bb-4eb3-a330-ff424fb56d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964964433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2964964433
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3002113896
Short name T115
Test name
Test status
Simulation time 131776553 ps
CPU time 1.4 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:50:51 PM PDT 24
Peak memory 209816 kb
Host smart-5628cb36-6a73-45e9-b3c4-d5bb403b6c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002113896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3002113896
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3940641767
Short name T449
Test name
Test status
Simulation time 188572127 ps
CPU time 0.73 seconds
Started May 19 01:51:04 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 205924 kb
Host smart-33ec6682-b82e-4711-b125-e996e02e184a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940641767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3940641767
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1769361337
Short name T266
Test name
Test status
Simulation time 45497444 ps
CPU time 3.57 seconds
Started May 19 01:50:46 PM PDT 24
Finished May 19 01:50:50 PM PDT 24
Peak memory 215704 kb
Host smart-d650a8d3-344e-4cb6-8d27-492cf1d4fcec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769361337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1769361337
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.392103135
Short name T668
Test name
Test status
Simulation time 75113114 ps
CPU time 2.61 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 208380 kb
Host smart-ea927b59-370c-45ef-a03a-244890f468c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392103135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.392103135
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1584860746
Short name T248
Test name
Test status
Simulation time 2211964989 ps
CPU time 28.81 seconds
Started May 19 01:50:56 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 218404 kb
Host smart-dd823fb6-33f0-4bc2-ad76-2a7972105fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584860746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1584860746
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.145550542
Short name T849
Test name
Test status
Simulation time 492011835 ps
CPU time 5.35 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 209360 kb
Host smart-8735b0eb-9dc8-43ce-93bf-4e73a4f9a795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145550542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.145550542
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.30913346
Short name T256
Test name
Test status
Simulation time 357766810 ps
CPU time 2.97 seconds
Started May 19 01:50:54 PM PDT 24
Finished May 19 01:50:58 PM PDT 24
Peak memory 214364 kb
Host smart-82ab2662-f8af-4ba1-8536-041279847ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30913346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.30913346
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.278709045
Short name T817
Test name
Test status
Simulation time 559515275 ps
CPU time 3.86 seconds
Started May 19 01:50:58 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 220016 kb
Host smart-5437ff54-190c-4b9b-afca-08451e433489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278709045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.278709045
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3676207605
Short name T712
Test name
Test status
Simulation time 2523886669 ps
CPU time 16.99 seconds
Started May 19 01:50:46 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 207228 kb
Host smart-6ea4eb2b-e900-4e33-a477-2ed3963c8ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676207605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3676207605
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1107869541
Short name T246
Test name
Test status
Simulation time 257044681 ps
CPU time 3.3 seconds
Started May 19 01:50:49 PM PDT 24
Finished May 19 01:50:53 PM PDT 24
Peak memory 208588 kb
Host smart-588850fc-77b2-47e3-9246-a20a3ef565bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107869541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1107869541
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.706248831
Short name T713
Test name
Test status
Simulation time 369588252 ps
CPU time 2.79 seconds
Started May 19 01:50:52 PM PDT 24
Finished May 19 01:50:56 PM PDT 24
Peak memory 208908 kb
Host smart-f2cfaa91-5557-4eca-a04a-9dd9c5a17829
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706248831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.706248831
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.628228966
Short name T800
Test name
Test status
Simulation time 547968479 ps
CPU time 4.52 seconds
Started May 19 01:50:47 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 207072 kb
Host smart-f344636f-c44f-4bf0-b33b-941a10b1cfd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628228966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.628228966
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2895399494
Short name T640
Test name
Test status
Simulation time 118143638 ps
CPU time 4.22 seconds
Started May 19 01:50:52 PM PDT 24
Finished May 19 01:50:57 PM PDT 24
Peak memory 208624 kb
Host smart-8bd59a9e-1dd3-4ed5-9f88-bcfeaf02f324
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895399494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2895399494
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.322978520
Short name T107
Test name
Test status
Simulation time 181683188 ps
CPU time 2.35 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 208936 kb
Host smart-7692a081-43bc-4dbf-a729-13d4974b7d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322978520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.322978520
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2274962576
Short name T782
Test name
Test status
Simulation time 3664553514 ps
CPU time 20.19 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 207800 kb
Host smart-d72c44ee-1240-4dfc-bdf0-decac208d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274962576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2274962576
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3414296
Short name T326
Test name
Test status
Simulation time 1197937177 ps
CPU time 11.81 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 220584 kb
Host smart-d5078062-68f9-4c23-add1-cc59d4346851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414296 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3414296
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.985228559
Short name T258
Test name
Test status
Simulation time 214880345 ps
CPU time 3.76 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 210148 kb
Host smart-f3b12de7-4872-44d9-ab71-d3c277f5f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985228559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.985228559
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2340909325
Short name T789
Test name
Test status
Simulation time 62753822 ps
CPU time 0.91 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 206108 kb
Host smart-33f8c671-b46e-4ac6-9f8e-d48ac6faeefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340909325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2340909325
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2285964951
Short name T36
Test name
Test status
Simulation time 257414179 ps
CPU time 3.68 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 221720 kb
Host smart-c5e4cfbf-b626-4f1e-98ce-c2c7f6054dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285964951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2285964951
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.475437266
Short name T491
Test name
Test status
Simulation time 421235385 ps
CPU time 3.22 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 208012 kb
Host smart-fe6e90b7-e549-4ea9-ad62-0d1096b351af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475437266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.475437266
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.808158107
Short name T351
Test name
Test status
Simulation time 181299436 ps
CPU time 1.91 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 214348 kb
Host smart-3cc84fde-18b0-4fbc-8b5f-48c3024b3c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808158107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.808158107
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1933065900
Short name T643
Test name
Test status
Simulation time 68358435 ps
CPU time 3.66 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 214304 kb
Host smart-46ef1aab-40c3-4452-a470-f5ecc72d19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933065900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1933065900
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.404653699
Short name T55
Test name
Test status
Simulation time 2377300498 ps
CPU time 14.17 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:49:56 PM PDT 24
Peak memory 222560 kb
Host smart-1eac4156-d3b9-429c-aac0-ca3eb8750126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404653699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.404653699
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1986102448
Short name T562
Test name
Test status
Simulation time 4607722039 ps
CPU time 44.99 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 209664 kb
Host smart-ec87176f-b753-4700-b0fa-7fc2e031a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986102448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1986102448
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1823099062
Short name T310
Test name
Test status
Simulation time 1916188439 ps
CPU time 20.14 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 208456 kb
Host smart-f6f93fbf-b4a3-4ff2-8bd6-d5457d0e82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823099062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1823099062
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2701151499
Short name T751
Test name
Test status
Simulation time 97359391 ps
CPU time 2.76 seconds
Started May 19 01:49:33 PM PDT 24
Finished May 19 01:49:40 PM PDT 24
Peak memory 207532 kb
Host smart-77bc6a87-ff3d-4888-a7f9-e8d02b66c4e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701151499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2701151499
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2318829077
Short name T797
Test name
Test status
Simulation time 789294931 ps
CPU time 18.64 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 208344 kb
Host smart-53fa9e2e-0078-4333-a13b-b05c89c6ed35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318829077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2318829077
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3765557613
Short name T432
Test name
Test status
Simulation time 505426184 ps
CPU time 3.46 seconds
Started May 19 01:49:55 PM PDT 24
Finished May 19 01:49:59 PM PDT 24
Peak memory 208644 kb
Host smart-921b1688-733f-4dae-b9b0-db35cd8ffe4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765557613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3765557613
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.190185416
Short name T675
Test name
Test status
Simulation time 44875551 ps
CPU time 2.19 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 208732 kb
Host smart-846c0a62-0e3d-4963-b6da-8aad1fd83c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190185416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.190185416
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4029762632
Short name T560
Test name
Test status
Simulation time 275232905 ps
CPU time 2.4 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 206900 kb
Host smart-b6c63a46-9e49-4bcb-91e8-47795af9a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029762632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4029762632
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2662018187
Short name T222
Test name
Test status
Simulation time 1669909624 ps
CPU time 43.49 seconds
Started May 19 01:49:37 PM PDT 24
Finished May 19 01:50:25 PM PDT 24
Peak memory 214300 kb
Host smart-3f89cb6d-8c7c-4eac-a874-c0f9e7129265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662018187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2662018187
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3801306936
Short name T642
Test name
Test status
Simulation time 230294864 ps
CPU time 5.17 seconds
Started May 19 01:49:35 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 209244 kb
Host smart-a69fa108-9a03-45bb-83e3-4575ca136ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801306936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3801306936
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1932801010
Short name T630
Test name
Test status
Simulation time 7959516107 ps
CPU time 16.87 seconds
Started May 19 01:49:48 PM PDT 24
Finished May 19 01:50:06 PM PDT 24
Peak memory 211260 kb
Host smart-16b1e0b5-05e8-4add-819f-0857a1b086ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932801010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1932801010
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3933062330
Short name T420
Test name
Test status
Simulation time 53037581 ps
CPU time 0.92 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:08 PM PDT 24
Peak memory 206044 kb
Host smart-c22db7f3-43f0-4fab-be37-9cdf0902c5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933062330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3933062330
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3044329739
Short name T597
Test name
Test status
Simulation time 189089235 ps
CPU time 1.89 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 207556 kb
Host smart-68f6614d-c71a-4a0f-a742-2292689ec713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044329739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3044329739
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2400839880
Short name T276
Test name
Test status
Simulation time 102738787 ps
CPU time 2.12 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 214324 kb
Host smart-03492d53-2446-4442-b543-2a6415fc1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400839880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2400839880
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.891377005
Short name T680
Test name
Test status
Simulation time 105827164 ps
CPU time 3.91 seconds
Started May 19 01:50:54 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 222484 kb
Host smart-ba2fbf5e-52d7-4009-bdcb-cfbf1aa30eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891377005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.891377005
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3468267101
Short name T218
Test name
Test status
Simulation time 97800476 ps
CPU time 4.65 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 222692 kb
Host smart-138fd8ee-a55d-41fb-b74b-2d302c9540cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468267101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3468267101
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1587459352
Short name T785
Test name
Test status
Simulation time 281175340 ps
CPU time 3.83 seconds
Started May 19 01:50:55 PM PDT 24
Finished May 19 01:51:00 PM PDT 24
Peak memory 208072 kb
Host smart-2e30d38e-030f-4b29-84a9-923bbc40a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587459352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1587459352
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3337422167
Short name T764
Test name
Test status
Simulation time 153813114 ps
CPU time 4.8 seconds
Started May 19 01:50:50 PM PDT 24
Finished May 19 01:50:56 PM PDT 24
Peak memory 208364 kb
Host smart-cf184802-a886-4f47-b284-09cd3a16adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337422167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3337422167
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3110101363
Short name T433
Test name
Test status
Simulation time 149695116 ps
CPU time 4.24 seconds
Started May 19 01:50:54 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 206976 kb
Host smart-3c3f5b90-bc7f-414d-8020-87ba79e01c47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110101363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3110101363
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.631289832
Short name T535
Test name
Test status
Simulation time 366750285 ps
CPU time 6.32 seconds
Started May 19 01:50:51 PM PDT 24
Finished May 19 01:50:58 PM PDT 24
Peak memory 207984 kb
Host smart-2e5fb21d-281a-4131-8fa0-23873fa876b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631289832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.631289832
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2947313391
Short name T742
Test name
Test status
Simulation time 38420133 ps
CPU time 2.66 seconds
Started May 19 01:50:56 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 207460 kb
Host smart-53fba944-2285-4961-b329-8be3f0ace9e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947313391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2947313391
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.362020162
Short name T794
Test name
Test status
Simulation time 95090755 ps
CPU time 3.22 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:04 PM PDT 24
Peak memory 214368 kb
Host smart-33b14227-56d3-4233-9ede-bc13458a584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362020162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.362020162
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3258652522
Short name T393
Test name
Test status
Simulation time 86240653 ps
CPU time 2.63 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:00 PM PDT 24
Peak memory 206748 kb
Host smart-ebed939f-acca-4f75-ba83-2948647f4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258652522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3258652522
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.221599976
Short name T191
Test name
Test status
Simulation time 469512712 ps
CPU time 18.11 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 215808 kb
Host smart-213bc2da-c6b5-4607-87a3-60c5a8f70d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221599976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.221599976
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1254887659
Short name T183
Test name
Test status
Simulation time 425753637 ps
CPU time 16.03 seconds
Started May 19 01:51:04 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 219992 kb
Host smart-a7c464e0-ddd6-49a4-876f-ab44c229b9dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254887659 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1254887659
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1673560530
Short name T328
Test name
Test status
Simulation time 103745382 ps
CPU time 4.41 seconds
Started May 19 01:50:56 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 209456 kb
Host smart-74de74f1-66c3-4034-8e21-cf717c319c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673560530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1673560530
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3808062525
Short name T58
Test name
Test status
Simulation time 137513970 ps
CPU time 1.63 seconds
Started May 19 01:50:53 PM PDT 24
Finished May 19 01:50:56 PM PDT 24
Peak memory 210512 kb
Host smart-c1c13a3c-9973-4638-b2d7-8fdb6aab1c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808062525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3808062525
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2714414977
Short name T644
Test name
Test status
Simulation time 54834131 ps
CPU time 0.9 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 205984 kb
Host smart-2de8aced-7477-4aac-a633-339e296238ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714414977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2714414977
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3470840791
Short name T518
Test name
Test status
Simulation time 3721756441 ps
CPU time 17.75 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 214624 kb
Host smart-d7b860a1-7b2d-4b73-a278-b3bee7f95956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470840791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3470840791
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3761359612
Short name T395
Test name
Test status
Simulation time 133009374 ps
CPU time 2.23 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:09 PM PDT 24
Peak memory 207800 kb
Host smart-0ff59789-13cf-4b3a-8954-eee12b5fc52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761359612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3761359612
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2311577157
Short name T666
Test name
Test status
Simulation time 73829304 ps
CPU time 2.89 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 214324 kb
Host smart-ea8e336a-facb-479c-b61c-f097b65432de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311577157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2311577157
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3680672677
Short name T836
Test name
Test status
Simulation time 1188166009 ps
CPU time 4.29 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 222400 kb
Host smart-6b654639-2470-4c45-a7a8-053f742bd516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680672677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3680672677
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3774670825
Short name T60
Test name
Test status
Simulation time 666349459 ps
CPU time 4.27 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 209508 kb
Host smart-66757881-d409-4619-b176-da73011e1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774670825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3774670825
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.594821364
Short name T249
Test name
Test status
Simulation time 51152573 ps
CPU time 3.71 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 214216 kb
Host smart-df7a323b-74b5-481f-8113-81c948716fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594821364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.594821364
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2294025023
Short name T251
Test name
Test status
Simulation time 107008203 ps
CPU time 2.79 seconds
Started May 19 01:50:55 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 208612 kb
Host smart-d818fccf-5831-415c-85b4-c27ddcda3965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294025023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2294025023
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1827397947
Short name T478
Test name
Test status
Simulation time 5436892162 ps
CPU time 35.38 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:49 PM PDT 24
Peak memory 208604 kb
Host smart-1157a43f-642c-4595-9268-fb97d8e3730c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827397947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1827397947
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.268382811
Short name T442
Test name
Test status
Simulation time 27120146 ps
CPU time 2.17 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 208716 kb
Host smart-ed51a19a-fc92-4a27-944e-441dd5af6c44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268382811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.268382811
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2096046581
Short name T464
Test name
Test status
Simulation time 198736786 ps
CPU time 4.92 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 207792 kb
Host smart-3fef499d-ce74-4b5c-a372-12a444727022
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096046581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2096046581
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.729621900
Short name T674
Test name
Test status
Simulation time 35124756 ps
CPU time 1.9 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 209292 kb
Host smart-2426a9a2-9024-4545-b3bb-552dbc6f2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729621900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.729621900
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2323768525
Short name T806
Test name
Test status
Simulation time 31422583 ps
CPU time 2.06 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 206816 kb
Host smart-8729676f-c999-4b66-a1e5-b71c9ec0f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323768525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2323768525
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.4172895694
Short name T190
Test name
Test status
Simulation time 11149576804 ps
CPU time 35.42 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 216092 kb
Host smart-499b0762-c6ff-4607-9e57-3150b424e371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172895694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.4172895694
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3344152980
Short name T755
Test name
Test status
Simulation time 1294871435 ps
CPU time 12.15 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 222532 kb
Host smart-9ea8b0de-c1e5-4735-9e41-6555093b66fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344152980 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3344152980
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.300423310
Short name T856
Test name
Test status
Simulation time 999696577 ps
CPU time 7.18 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 214372 kb
Host smart-4ccdd93b-2c5b-47c3-b949-45fb9ebe52f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300423310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.300423310
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1679497606
Short name T139
Test name
Test status
Simulation time 306247476 ps
CPU time 5.35 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:09 PM PDT 24
Peak memory 210484 kb
Host smart-7306c97f-ec1e-458b-9b11-52401d200b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679497606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1679497606
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.569297797
Short name T569
Test name
Test status
Simulation time 37700987 ps
CPU time 0.77 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 205924 kb
Host smart-37671a00-586c-469c-a2da-fcc338ebf9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569297797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.569297797
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.555755966
Short name T835
Test name
Test status
Simulation time 144579726 ps
CPU time 2.93 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:09 PM PDT 24
Peak memory 220636 kb
Host smart-e473a51c-a5b4-4fcd-ae66-fcbf65a6ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555755966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.555755966
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2904961360
Short name T728
Test name
Test status
Simulation time 39533548 ps
CPU time 2.05 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 208880 kb
Host smart-c2dc58a2-f9ae-4fdd-a1d4-34a5d1aa5cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904961360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2904961360
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1986671605
Short name T373
Test name
Test status
Simulation time 900454230 ps
CPU time 8.81 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 214420 kb
Host smart-d7021ddf-831e-4963-ad61-e60c8efd8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986671605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1986671605
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2570389011
Short name T859
Test name
Test status
Simulation time 66857576 ps
CPU time 3.58 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:05 PM PDT 24
Peak memory 214284 kb
Host smart-411fa83e-e882-4ffb-b30d-b2f0f257ab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570389011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2570389011
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1960543851
Short name T68
Test name
Test status
Simulation time 133324818 ps
CPU time 4.83 seconds
Started May 19 01:51:04 PM PDT 24
Finished May 19 01:51:09 PM PDT 24
Peak memory 220656 kb
Host smart-396af58d-4ccb-4bfb-94d3-98cf12950474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960543851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1960543851
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2123724932
Short name T615
Test name
Test status
Simulation time 6301579223 ps
CPU time 26.24 seconds
Started May 19 01:51:04 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 208768 kb
Host smart-39bd98d5-f623-499a-93a0-18e2ceabc3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123724932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2123724932
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2532400170
Short name T759
Test name
Test status
Simulation time 280508777 ps
CPU time 3.62 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:02 PM PDT 24
Peak memory 208848 kb
Host smart-5f40bf8e-a7cb-4b8c-8959-4b5e988309e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532400170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2532400170
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1106018846
Short name T423
Test name
Test status
Simulation time 31200177 ps
CPU time 2.29 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 206840 kb
Host smart-322ad1ac-0968-4cc1-8417-9e286278bbd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106018846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1106018846
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.221822945
Short name T599
Test name
Test status
Simulation time 5567150997 ps
CPU time 13.58 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:20 PM PDT 24
Peak memory 208576 kb
Host smart-248d0e5a-5aaa-425b-8427-dbeca072de0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221822945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.221822945
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3109292796
Short name T565
Test name
Test status
Simulation time 1988323682 ps
CPU time 47.63 seconds
Started May 19 01:50:56 PM PDT 24
Finished May 19 01:51:45 PM PDT 24
Peak memory 208676 kb
Host smart-1a45ba2e-bdf0-4d01-9c8f-b41e45ba69e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109292796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3109292796
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3223335712
Short name T904
Test name
Test status
Simulation time 363052655 ps
CPU time 4.6 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:05 PM PDT 24
Peak memory 214408 kb
Host smart-7635a80a-acfe-4e38-a14a-7fce06256ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223335712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3223335712
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1069059949
Short name T396
Test name
Test status
Simulation time 285541868 ps
CPU time 3.65 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 208836 kb
Host smart-6af5f15b-6c20-4213-ae2d-e2d121b0d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069059949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1069059949
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1074390081
Short name T303
Test name
Test status
Simulation time 3175073656 ps
CPU time 30.01 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:45 PM PDT 24
Peak memory 222556 kb
Host smart-116518af-d459-4154-9535-10ab896c4f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074390081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1074390081
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2517532948
Short name T132
Test name
Test status
Simulation time 544184120 ps
CPU time 25.06 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 222728 kb
Host smart-fb655715-7365-4173-bcff-902c02d14cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517532948 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2517532948
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1171686855
Short name T388
Test name
Test status
Simulation time 687970280 ps
CPU time 8.77 seconds
Started May 19 01:50:57 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 208136 kb
Host smart-d2ceec24-59e0-49a4-9827-3628622152d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171686855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1171686855
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2673394434
Short name T381
Test name
Test status
Simulation time 176511080 ps
CPU time 2.15 seconds
Started May 19 01:51:00 PM PDT 24
Finished May 19 01:51:03 PM PDT 24
Peak memory 210164 kb
Host smart-16437e5d-20f2-4d9e-965f-dc829c325649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673394434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2673394434
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1917237823
Short name T631
Test name
Test status
Simulation time 119274973 ps
CPU time 0.72 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 205888 kb
Host smart-dd80e378-5f7f-4c0b-9fdf-b2612a16e368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917237823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1917237823
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1899312562
Short name T399
Test name
Test status
Simulation time 238797255 ps
CPU time 12.61 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 215348 kb
Host smart-4930580a-3d27-4b75-96e8-e413a986b5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899312562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1899312562
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.320703743
Short name T556
Test name
Test status
Simulation time 139091296 ps
CPU time 1.63 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:05 PM PDT 24
Peak memory 215916 kb
Host smart-0377fc25-2b83-48fe-bfe5-86deff737cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320703743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.320703743
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2516481249
Short name T318
Test name
Test status
Simulation time 1067396223 ps
CPU time 7.15 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 210316 kb
Host smart-56484f14-7ec6-4067-a1f2-d79d545433c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516481249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2516481249
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.587099461
Short name T557
Test name
Test status
Simulation time 98734971 ps
CPU time 4.19 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 220916 kb
Host smart-f385940a-b5ca-42c3-9b2c-38d0dde46f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587099461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.587099461
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.317275684
Short name T741
Test name
Test status
Simulation time 49066976 ps
CPU time 2.3 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 214292 kb
Host smart-17692337-c387-409d-9ab5-6804329d62c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317275684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.317275684
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.665468907
Short name T56
Test name
Test status
Simulation time 592760214 ps
CPU time 4.72 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 219880 kb
Host smart-5893117d-7340-43f1-b002-96aa921f38f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665468907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.665468907
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2190105525
Short name T695
Test name
Test status
Simulation time 228597029 ps
CPU time 8.17 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 214200 kb
Host smart-a760be5d-a2e1-4b7e-aff6-881dd75f7d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190105525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2190105525
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.74210565
Short name T779
Test name
Test status
Simulation time 3204141517 ps
CPU time 56.53 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:52:05 PM PDT 24
Peak memory 207948 kb
Host smart-64b0312d-7976-43e6-9218-8a7ef882c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74210565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.74210565
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1404002563
Short name T530
Test name
Test status
Simulation time 220955435 ps
CPU time 6.57 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:10 PM PDT 24
Peak memory 208748 kb
Host smart-fbbdd17a-b82e-4037-a460-4b55357be432
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404002563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1404002563
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1985080692
Short name T200
Test name
Test status
Simulation time 1126065263 ps
CPU time 6.37 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 208680 kb
Host smart-c1bfbe81-1933-4d48-9a98-fa6af20d4e77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985080692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1985080692
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2530772616
Short name T305
Test name
Test status
Simulation time 86504254 ps
CPU time 3.52 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 206888 kb
Host smart-a8ec361a-40bc-479c-82fd-8fad9575cfd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530772616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2530772616
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2967065786
Short name T573
Test name
Test status
Simulation time 99895644 ps
CPU time 2.5 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:17 PM PDT 24
Peak memory 208044 kb
Host smart-949ea5c5-9990-47d4-92e0-a7e63c13d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967065786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2967065786
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2439669811
Short name T735
Test name
Test status
Simulation time 1798550115 ps
CPU time 33.16 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 222504 kb
Host smart-bc6ac52a-465d-43ab-81cd-e43dbe961f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439669811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2439669811
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2109101085
Short name T71
Test name
Test status
Simulation time 1141438092 ps
CPU time 8.11 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 220136 kb
Host smart-e93848de-dbdf-4370-87d3-472358f71576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109101085 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2109101085
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.370459373
Short name T623
Test name
Test status
Simulation time 36658020 ps
CPU time 2.81 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 208220 kb
Host smart-bddf8115-708b-4417-a577-ca2efc769479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370459373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.370459373
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2120703904
Short name T912
Test name
Test status
Simulation time 92818228 ps
CPU time 2.63 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 210432 kb
Host smart-89801a62-9054-4f7d-83b6-3158a4dd1795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120703904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2120703904
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2627989568
Short name T497
Test name
Test status
Simulation time 15779751 ps
CPU time 0.8 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 205916 kb
Host smart-73b81b2c-0a32-448b-866e-7d514defb9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627989568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2627989568
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3097563524
Short name T288
Test name
Test status
Simulation time 128438004 ps
CPU time 2.84 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:10 PM PDT 24
Peak memory 215008 kb
Host smart-23066d3b-49c1-4f37-9317-6657398a9d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097563524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3097563524
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.796459818
Short name T205
Test name
Test status
Simulation time 218945486 ps
CPU time 2.81 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:06 PM PDT 24
Peak memory 214648 kb
Host smart-8b6ac663-4082-4cfb-bbc4-f1c74f0ab041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796459818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.796459818
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2405882572
Short name T829
Test name
Test status
Simulation time 115108786 ps
CPU time 2.02 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:05 PM PDT 24
Peak memory 207028 kb
Host smart-39319fbd-1874-4a57-8564-133950f8f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405882572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2405882572
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3446880336
Short name T334
Test name
Test status
Simulation time 65582388 ps
CPU time 2.16 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:05 PM PDT 24
Peak memory 214348 kb
Host smart-f34a94a4-e528-4fad-90b5-f91854870755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446880336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3446880336
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4212478026
Short name T820
Test name
Test status
Simulation time 131882222 ps
CPU time 3.15 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 214276 kb
Host smart-99035f0f-807f-4f2c-b1fd-ba0c2a00822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212478026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4212478026
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3317317884
Short name T490
Test name
Test status
Simulation time 124416479 ps
CPU time 3.92 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 222480 kb
Host smart-047fd8d5-2abc-4765-b729-7072af78137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317317884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3317317884
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.240764400
Short name T667
Test name
Test status
Simulation time 59050631 ps
CPU time 3.53 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 214340 kb
Host smart-7a9ee0b4-00ef-45d0-8cd3-1a8a91b894cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240764400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.240764400
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1962909756
Short name T480
Test name
Test status
Simulation time 348747608 ps
CPU time 2.6 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 206920 kb
Host smart-44c0a804-fd1d-4ff6-978c-9da089163d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962909756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1962909756
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2488415606
Short name T653
Test name
Test status
Simulation time 514998306 ps
CPU time 6.84 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 208640 kb
Host smart-556abae9-df2b-4d11-ad2e-a3fbba2507d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488415606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2488415606
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1250200184
Short name T539
Test name
Test status
Simulation time 117034031 ps
CPU time 4.92 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:07 PM PDT 24
Peak memory 209164 kb
Host smart-b00f42f9-cad8-4bbd-a412-e1aecbf30777
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250200184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1250200184
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3784837392
Short name T291
Test name
Test status
Simulation time 163720082 ps
CPU time 2.38 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 206864 kb
Host smart-f49e815f-b717-4cda-817b-dae23c6adabf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784837392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3784837392
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2657322634
Short name T404
Test name
Test status
Simulation time 76306866 ps
CPU time 1.9 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 209688 kb
Host smart-5855c065-749b-423e-bd3c-fb32fb5d05fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657322634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2657322634
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2962334464
Short name T135
Test name
Test status
Simulation time 199886584 ps
CPU time 2.63 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 206728 kb
Host smart-3d1f5d75-2c44-45d5-8c85-76365cc93eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962334464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2962334464
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3979519627
Short name T215
Test name
Test status
Simulation time 4049470682 ps
CPU time 40.48 seconds
Started May 19 01:51:01 PM PDT 24
Finished May 19 01:51:43 PM PDT 24
Peak memory 215256 kb
Host smart-dfef1711-b08b-4220-a18e-4bc2e02b10e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979519627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3979519627
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1667140811
Short name T646
Test name
Test status
Simulation time 1052317244 ps
CPU time 35.46 seconds
Started May 19 01:51:02 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 214356 kb
Host smart-63be5512-2238-483f-9004-ab5729a4b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667140811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1667140811
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1347535692
Short name T138
Test name
Test status
Simulation time 240115340 ps
CPU time 3.03 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:20 PM PDT 24
Peak memory 210512 kb
Host smart-0ed557bd-c483-4ad6-ac10-fc030caa7880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347535692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1347535692
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2655928587
Short name T704
Test name
Test status
Simulation time 72208082 ps
CPU time 1.01 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 206184 kb
Host smart-caf2e167-eca3-4f55-bb8d-b8bb7103025d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655928587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2655928587
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3439514451
Short name T364
Test name
Test status
Simulation time 37531471 ps
CPU time 3.05 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 214396 kb
Host smart-fea54e1a-3a5b-461f-89c7-2e2456c2fc61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439514451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3439514451
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1934538896
Short name T659
Test name
Test status
Simulation time 59750318 ps
CPU time 2.11 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 214516 kb
Host smart-67edee78-05da-4e7b-992f-f6d0f2706b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934538896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1934538896
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.987349795
Short name T51
Test name
Test status
Simulation time 80921385 ps
CPU time 1.71 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 214352 kb
Host smart-720ea5d9-dd08-424d-8563-9c5122cf539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987349795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.987349795
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1206614916
Short name T710
Test name
Test status
Simulation time 146610988 ps
CPU time 2.93 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 214232 kb
Host smart-32b7c1d3-288d-4fe1-ad7b-44d011c64743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206614916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1206614916
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.149537353
Short name T329
Test name
Test status
Simulation time 150036308 ps
CPU time 2.79 seconds
Started May 19 01:51:04 PM PDT 24
Finished May 19 01:51:08 PM PDT 24
Peak memory 214360 kb
Host smart-b580ba59-8a06-49eb-a619-aec2822110f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149537353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.149537353
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2080588920
Short name T861
Test name
Test status
Simulation time 267407424 ps
CPU time 2.58 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 208868 kb
Host smart-3a23d583-806b-41f7-ad19-40b3104d7a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080588920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2080588920
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2666157989
Short name T570
Test name
Test status
Simulation time 2992698781 ps
CPU time 36.75 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:52:07 PM PDT 24
Peak memory 208556 kb
Host smart-a3487d16-cfdf-46a8-9f3f-c3781841e067
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666157989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2666157989
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3555081996
Short name T234
Test name
Test status
Simulation time 93867008 ps
CPU time 3.35 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 208448 kb
Host smart-34304be2-17f8-46f5-a4b0-2d8e69ea3529
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555081996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3555081996
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.560254466
Short name T89
Test name
Test status
Simulation time 90332627 ps
CPU time 3.23 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 207060 kb
Host smart-ad5569d2-c3e3-44cd-96ba-5505eedd24c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560254466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.560254466
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3558113327
Short name T915
Test name
Test status
Simulation time 416974983 ps
CPU time 3.57 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 208772 kb
Host smart-d17be300-f4f9-41ba-89c2-62a3c397bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558113327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3558113327
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.388999298
Short name T687
Test name
Test status
Simulation time 235271246 ps
CPU time 5.5 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 208468 kb
Host smart-94e457ba-da70-4311-afd9-99772675cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388999298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.388999298
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.666730748
Short name T847
Test name
Test status
Simulation time 1607859390 ps
CPU time 21.2 seconds
Started May 19 01:51:11 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 214988 kb
Host smart-1d82953e-59d5-46e9-aa1d-2e1a01971050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666730748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.666730748
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1483577348
Short name T689
Test name
Test status
Simulation time 429717489 ps
CPU time 5.19 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 206996 kb
Host smart-4fc7cc3f-65f1-4902-979d-4a33de522739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483577348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1483577348
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3431818927
Short name T754
Test name
Test status
Simulation time 23716206 ps
CPU time 1.7 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 209956 kb
Host smart-447a0ad5-a6fb-4f9f-aba9-e90ea4c93300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431818927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3431818927
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3288084892
Short name T685
Test name
Test status
Simulation time 16436305 ps
CPU time 1 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 206100 kb
Host smart-8ed9663d-a4ca-4528-bd71-4383d17aa53d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288084892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3288084892
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2778613514
Short name T830
Test name
Test status
Simulation time 67000005 ps
CPU time 3.84 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:20 PM PDT 24
Peak memory 223000 kb
Host smart-98a20a6c-7482-475e-ab15-63ca20a478df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778613514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2778613514
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.117043328
Short name T238
Test name
Test status
Simulation time 800633990 ps
CPU time 15.72 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 209976 kb
Host smart-0e9f9765-bd8f-4855-9d26-3fcd6c753f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117043328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.117043328
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1039099833
Short name T531
Test name
Test status
Simulation time 89533244 ps
CPU time 2.13 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 220108 kb
Host smart-1a72a3c9-54e7-42c9-941f-19f79af183af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039099833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1039099833
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3368911385
Short name T816
Test name
Test status
Simulation time 411484649 ps
CPU time 3.63 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 210256 kb
Host smart-d7e22933-3c62-444a-b740-f57a33d3fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368911385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3368911385
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3206564936
Short name T617
Test name
Test status
Simulation time 202322919 ps
CPU time 3.65 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 207800 kb
Host smart-bfc89a46-8aae-41bf-8cf9-160b26442f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206564936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3206564936
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1333604048
Short name T435
Test name
Test status
Simulation time 579767937 ps
CPU time 3.1 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 206912 kb
Host smart-7a8d5981-fe23-4a65-9f61-3107a7539948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333604048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1333604048
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.315792436
Short name T871
Test name
Test status
Simulation time 90632583 ps
CPU time 2.49 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 206724 kb
Host smart-e81e4f58-f6a8-4b53-a87b-b22f97ca7c19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315792436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.315792436
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3156985031
Short name T778
Test name
Test status
Simulation time 164590190 ps
CPU time 6.7 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 208544 kb
Host smart-ffaf027b-753d-4053-bd10-9197913203c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156985031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3156985031
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2125015550
Short name T638
Test name
Test status
Simulation time 231102319 ps
CPU time 3.03 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 208732 kb
Host smart-6e7cc92b-9459-4c15-be6d-5a395ceec0c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125015550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2125015550
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1415540686
Short name T542
Test name
Test status
Simulation time 127227584 ps
CPU time 2.79 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 216172 kb
Host smart-1f86ba90-067a-49bc-8b9e-5c4e085cefa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415540686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1415540686
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3614632530
Short name T670
Test name
Test status
Simulation time 2256426678 ps
CPU time 27.52 seconds
Started May 19 01:51:14 PM PDT 24
Finished May 19 01:51:44 PM PDT 24
Peak memory 208932 kb
Host smart-6ac7371b-64a7-4b69-b063-7bfae0fc3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614632530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3614632530
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1531513381
Short name T889
Test name
Test status
Simulation time 4329859562 ps
CPU time 27.89 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 208180 kb
Host smart-80dfb67d-836c-4797-bc03-b20deb084485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531513381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1531513381
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.845435011
Short name T665
Test name
Test status
Simulation time 494811524 ps
CPU time 19.8 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 221400 kb
Host smart-792f2c1c-4c68-41f5-8146-4345a45cda51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845435011 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.845435011
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3542533335
Short name T239
Test name
Test status
Simulation time 228907317 ps
CPU time 3.88 seconds
Started May 19 01:51:09 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 214600 kb
Host smart-dfef6ae8-348f-488e-b991-d51ff3b20413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542533335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3542533335
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2439333203
Short name T736
Test name
Test status
Simulation time 42335096 ps
CPU time 1.78 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 209792 kb
Host smart-09db2c06-2093-4f89-9299-ee5ad1f85ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439333203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2439333203
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3854261360
Short name T524
Test name
Test status
Simulation time 10253929 ps
CPU time 0.83 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 205940 kb
Host smart-7ec2d951-78ed-4276-b913-ec95032de353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854261360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3854261360
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1467537220
Short name T283
Test name
Test status
Simulation time 154518537 ps
CPU time 3.02 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 215472 kb
Host smart-f5dd0d3c-266e-4c23-8ca3-6548a3254596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467537220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1467537220
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1654904146
Short name T873
Test name
Test status
Simulation time 39145562 ps
CPU time 2.51 seconds
Started May 19 01:51:10 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 214448 kb
Host smart-f6de3334-2cd5-4d01-908c-fb1d1c671283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654904146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1654904146
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1642675381
Short name T102
Test name
Test status
Simulation time 88171418 ps
CPU time 4.53 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 214312 kb
Host smart-cba093b7-f41d-4a1f-a759-260cdbfa0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642675381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1642675381
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4230639733
Short name T494
Test name
Test status
Simulation time 327770009 ps
CPU time 2.63 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 220596 kb
Host smart-b534ada2-2ab7-4b41-8ab8-728db2f723b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230639733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4230639733
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3387651632
Short name T216
Test name
Test status
Simulation time 53457257 ps
CPU time 3.76 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 220768 kb
Host smart-35bbf5b1-3001-43eb-9c68-b7a865eeced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387651632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3387651632
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2996599067
Short name T482
Test name
Test status
Simulation time 6778711984 ps
CPU time 14.74 seconds
Started May 19 01:51:03 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 209796 kb
Host smart-de40df85-2b21-43cb-88c2-136a91a0087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996599067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2996599067
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1968252474
Short name T398
Test name
Test status
Simulation time 104368447 ps
CPU time 2.64 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 208268 kb
Host smart-b0a8393b-bcaf-43cc-9467-e66653c5b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968252474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1968252474
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2512612910
Short name T582
Test name
Test status
Simulation time 42982393 ps
CPU time 1.91 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 207420 kb
Host smart-723b61da-1418-4273-97fc-82d3a21e2c42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512612910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2512612910
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.660440539
Short name T536
Test name
Test status
Simulation time 213588686 ps
CPU time 2.49 seconds
Started May 19 01:51:11 PM PDT 24
Finished May 19 01:51:16 PM PDT 24
Peak memory 206856 kb
Host smart-f14f3fa0-e222-4022-9a4d-b1d89feaefba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660440539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.660440539
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.945220166
Short name T534
Test name
Test status
Simulation time 286841163 ps
CPU time 8.95 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 208556 kb
Host smart-5fdaed35-5bce-4616-9565-e1c41032de7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945220166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.945220166
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2327509710
Short name T559
Test name
Test status
Simulation time 184895986 ps
CPU time 6.28 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 209696 kb
Host smart-af8936e2-eb52-435a-b4b5-0bb457367e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327509710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2327509710
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2480904136
Short name T495
Test name
Test status
Simulation time 113852791 ps
CPU time 2.91 seconds
Started May 19 01:51:13 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 208480 kb
Host smart-97461718-c8a8-4e6f-8b5b-711fbf9f9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480904136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2480904136
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2406778202
Short name T323
Test name
Test status
Simulation time 1116284178 ps
CPU time 20.43 seconds
Started May 19 01:51:11 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 220660 kb
Host smart-41df5eb6-1b4f-4c35-a938-2cdd8ba3e5b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406778202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2406778202
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3344639328
Short name T349
Test name
Test status
Simulation time 78847814 ps
CPU time 3.47 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 207540 kb
Host smart-eddaf5f1-805c-4a1c-8f51-5aa2febf97c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344639328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3344639328
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3123691335
Short name T768
Test name
Test status
Simulation time 104921454 ps
CPU time 2.37 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:09 PM PDT 24
Peak memory 210304 kb
Host smart-88ca1ad8-d884-4462-97d3-d63a4d6ee0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123691335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3123691335
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2009237022
Short name T885
Test name
Test status
Simulation time 178589702 ps
CPU time 0.83 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 205972 kb
Host smart-cf4cc77b-56de-4ae8-9ab1-3fc140608d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009237022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2009237022
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2774248646
Short name T409
Test name
Test status
Simulation time 1012990251 ps
CPU time 3.95 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:15 PM PDT 24
Peak memory 215572 kb
Host smart-e1588017-763f-49d3-a43c-b502b635945b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774248646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2774248646
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2804102969
Short name T206
Test name
Test status
Simulation time 52403268 ps
CPU time 2.79 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:20 PM PDT 24
Peak memory 220568 kb
Host smart-72c5467b-db74-4a75-88ac-73411b882eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804102969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2804102969
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.931291942
Short name T809
Test name
Test status
Simulation time 624633219 ps
CPU time 4.89 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 218180 kb
Host smart-fdb8e85f-88ec-4089-8954-f4f6d65417df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931291942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.931291942
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3503926797
Short name T903
Test name
Test status
Simulation time 88358162 ps
CPU time 3.09 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 214268 kb
Host smart-e9cf2243-cc0a-476c-b94f-7b062f5643d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503926797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3503926797
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1125403494
Short name T352
Test name
Test status
Simulation time 40145185 ps
CPU time 2.85 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 217288 kb
Host smart-bc46e3d5-61b7-4ef0-8bd5-a21d49a32b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125403494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1125403494
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1898196928
Short name T526
Test name
Test status
Simulation time 405961474 ps
CPU time 1.67 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 206128 kb
Host smart-da7a8709-b0f2-4735-ab70-6688c9fd49ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898196928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1898196928
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.565108446
Short name T791
Test name
Test status
Simulation time 1083229206 ps
CPU time 7.3 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 207368 kb
Host smart-12ed797b-c456-4695-8581-a586ec37f677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565108446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.565108446
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4082470351
Short name T590
Test name
Test status
Simulation time 1093819747 ps
CPU time 3.01 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 208560 kb
Host smart-24e37586-17dd-44da-989e-306e8cd0c2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082470351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4082470351
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.572026965
Short name T285
Test name
Test status
Simulation time 26936653 ps
CPU time 2.15 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 208864 kb
Host smart-2a2fd872-737e-412f-8af4-3e24887b300e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572026965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.572026965
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.813573350
Short name T436
Test name
Test status
Simulation time 33657285 ps
CPU time 2.28 seconds
Started May 19 01:51:08 PM PDT 24
Finished May 19 01:51:13 PM PDT 24
Peak memory 208712 kb
Host smart-42ac0d3e-4f2f-4276-9a93-19e20c1bc78f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813573350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.813573350
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3956495882
Short name T706
Test name
Test status
Simulation time 5145404802 ps
CPU time 37.08 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:52:01 PM PDT 24
Peak memory 207928 kb
Host smart-09f4997d-536a-40fe-8b3f-55314b9a7873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956495882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3956495882
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1088664138
Short name T620
Test name
Test status
Simulation time 254262491 ps
CPU time 2.87 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 209496 kb
Host smart-804cc370-48ab-4685-a89c-93739cb916a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088664138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1088664138
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1203293211
Short name T577
Test name
Test status
Simulation time 251817533 ps
CPU time 4.89 seconds
Started May 19 01:51:05 PM PDT 24
Finished May 19 01:51:11 PM PDT 24
Peak memory 207948 kb
Host smart-95ab007f-7cb3-4d0a-adf7-a7ab4bde7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203293211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1203293211
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1966082919
Short name T181
Test name
Test status
Simulation time 239466259 ps
CPU time 6.82 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 222480 kb
Host smart-f43beef8-069b-483e-9b8a-98d4de0d4480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966082919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1966082919
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.674885149
Short name T264
Test name
Test status
Simulation time 108334915 ps
CPU time 4.81 seconds
Started May 19 01:51:07 PM PDT 24
Finished May 19 01:51:14 PM PDT 24
Peak memory 214356 kb
Host smart-4f7f77dd-cbd1-4921-8d72-1cf60f797f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674885149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.674885149
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2287076115
Short name T808
Test name
Test status
Simulation time 9581200 ps
CPU time 0.8 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 205944 kb
Host smart-f771b64b-0143-4e59-b222-e214b505234b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287076115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2287076115
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1359329506
Short name T401
Test name
Test status
Simulation time 175978799 ps
CPU time 9.42 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 214372 kb
Host smart-a8cf8f81-0c94-47f0-a884-06b6c3194642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359329506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1359329506
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3798668519
Short name T66
Test name
Test status
Simulation time 80911312 ps
CPU time 2.03 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 207776 kb
Host smart-a43716c4-7e7c-410f-9560-cc2fbbfb23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798668519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3798668519
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.32094453
Short name T93
Test name
Test status
Simulation time 73609732 ps
CPU time 1.48 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 214156 kb
Host smart-f705c5f0-420c-4272-b707-eee930bf3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32094453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.32094453
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.524683714
Short name T865
Test name
Test status
Simulation time 264895524 ps
CPU time 2.93 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 214604 kb
Host smart-9795969a-4be0-443e-834b-484c16f7f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524683714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.524683714
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.575131607
Short name T508
Test name
Test status
Simulation time 83016809 ps
CPU time 3.86 seconds
Started May 19 01:51:06 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 207668 kb
Host smart-032b2d4a-722b-4af8-a793-a4bf4902a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575131607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.575131607
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4139105197
Short name T519
Test name
Test status
Simulation time 343830368 ps
CPU time 4.01 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 209028 kb
Host smart-770077f8-29cb-4aa1-abea-bf90d26abce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139105197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4139105197
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1805476866
Short name T609
Test name
Test status
Simulation time 518571455 ps
CPU time 6.08 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 207068 kb
Host smart-2c93c230-d909-4d33-a9d4-86b889f16b46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805476866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1805476866
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2596825192
Short name T389
Test name
Test status
Simulation time 348359549 ps
CPU time 4.2 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 208820 kb
Host smart-02c4d3ff-1d00-4c77-a40f-25e14814257f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596825192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2596825192
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4082624927
Short name T37
Test name
Test status
Simulation time 140065688 ps
CPU time 5.61 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 208920 kb
Host smart-ce4a61e3-907f-4139-88ad-fdfbc00da491
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082624927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4082624927
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3339787517
Short name T886
Test name
Test status
Simulation time 1035315316 ps
CPU time 6.52 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 218192 kb
Host smart-efb30fe4-011b-447c-b278-cde5d2bcbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339787517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3339787517
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1496940557
Short name T607
Test name
Test status
Simulation time 735369992 ps
CPU time 2.56 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 207092 kb
Host smart-b765d879-4d6d-41a6-ac01-19703f77a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496940557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1496940557
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3461981674
Short name T866
Test name
Test status
Simulation time 3311623157 ps
CPU time 13.25 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:43 PM PDT 24
Peak memory 215464 kb
Host smart-f7226235-5d73-4dd1-89e7-92ff015de44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461981674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3461981674
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3213068363
Short name T842
Test name
Test status
Simulation time 91404263 ps
CPU time 6.09 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 218828 kb
Host smart-cd687612-ae89-4752-b333-d3d7e377961d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213068363 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3213068363
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2524890155
Short name T309
Test name
Test status
Simulation time 3979360335 ps
CPU time 19.95 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 208204 kb
Host smart-4beb7100-1f38-4b69-9ffc-b115653eda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524890155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2524890155
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1037776517
Short name T502
Test name
Test status
Simulation time 250667007 ps
CPU time 4.46 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 210948 kb
Host smart-b4cf326c-cd39-433b-87b1-b5759270472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037776517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1037776517
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2950603272
Short name T864
Test name
Test status
Simulation time 11179202 ps
CPU time 0.74 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 205872 kb
Host smart-21c39eb3-3a51-40a8-811d-d10e606cc3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950603272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2950603272
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4042034092
Short name T260
Test name
Test status
Simulation time 58506761 ps
CPU time 4.22 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 214296 kb
Host smart-d596b62e-dc0d-4839-8671-46f0b3af5a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042034092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4042034092
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2922125484
Short name T22
Test name
Test status
Simulation time 76392949 ps
CPU time 2.84 seconds
Started May 19 01:50:00 PM PDT 24
Finished May 19 01:50:04 PM PDT 24
Peak memory 220652 kb
Host smart-06c25140-ef5d-4bf4-be75-609bf3fc409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922125484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2922125484
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.962309388
Short name T361
Test name
Test status
Simulation time 39258066 ps
CPU time 2.36 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 214284 kb
Host smart-9df4e814-db64-4fb3-bd92-b3b67ad0161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962309388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.962309388
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.805581255
Short name T101
Test name
Test status
Simulation time 176743418 ps
CPU time 2.82 seconds
Started May 19 01:49:38 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 208832 kb
Host smart-5ade486e-5515-4ea1-ac57-fcb5176bebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805581255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.805581255
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1808326312
Short name T801
Test name
Test status
Simulation time 95330662 ps
CPU time 3.19 seconds
Started May 19 01:49:39 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 214268 kb
Host smart-6c008a2a-c135-44c8-a348-74da850175d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808326312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1808326312
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2411550805
Short name T7
Test name
Test status
Simulation time 474591663 ps
CPU time 4.27 seconds
Started May 19 01:49:46 PM PDT 24
Finished May 19 01:49:51 PM PDT 24
Peak memory 209308 kb
Host smart-b35f450e-0b85-4fc8-a196-c1b0d15b19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411550805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2411550805
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.601769964
Short name T344
Test name
Test status
Simulation time 1307501892 ps
CPU time 6.06 seconds
Started May 19 01:49:41 PM PDT 24
Finished May 19 01:49:50 PM PDT 24
Peak memory 218564 kb
Host smart-2d76eb1e-f321-468f-8ef3-8bbd038aea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601769964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.601769964
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1709625979
Short name T47
Test name
Test status
Simulation time 2700849528 ps
CPU time 10.07 seconds
Started May 19 01:49:56 PM PDT 24
Finished May 19 01:50:07 PM PDT 24
Peak memory 234220 kb
Host smart-11421234-4022-4bda-9420-99b32d3b6b1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709625979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1709625979
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2240093090
Short name T265
Test name
Test status
Simulation time 134716591 ps
CPU time 4.28 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:51 PM PDT 24
Peak memory 206940 kb
Host smart-96914027-56fd-4485-b919-951344460405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240093090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2240093090
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2394397691
Short name T711
Test name
Test status
Simulation time 839130451 ps
CPU time 9.28 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:50:02 PM PDT 24
Peak memory 209060 kb
Host smart-bf57908d-7b9c-4e61-9ba4-0632e09b261e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394397691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2394397691
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2540497851
Short name T758
Test name
Test status
Simulation time 160885428 ps
CPU time 4.76 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 208464 kb
Host smart-9d255a2c-b9fc-4fc2-a6b4-acbe14af0cf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540497851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2540497851
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.508562247
Short name T714
Test name
Test status
Simulation time 194787297 ps
CPU time 2.51 seconds
Started May 19 01:49:36 PM PDT 24
Finished May 19 01:49:44 PM PDT 24
Peak memory 206984 kb
Host smart-47021fd4-9758-4f8b-912e-6fb0d4315ab6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508562247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.508562247
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2815925691
Short name T484
Test name
Test status
Simulation time 1263005491 ps
CPU time 10.8 seconds
Started May 19 01:49:49 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 208612 kb
Host smart-3a95957d-3ba5-4095-8661-c68faff0cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815925691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2815925691
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1203180772
Short name T629
Test name
Test status
Simulation time 580329997 ps
CPU time 5.59 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:52 PM PDT 24
Peak memory 208060 kb
Host smart-f09c9286-84ca-40ea-82c7-ac125a4cfec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203180772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1203180772
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3249946639
Short name T302
Test name
Test status
Simulation time 584251677 ps
CPU time 6.09 seconds
Started May 19 01:49:41 PM PDT 24
Finished May 19 01:49:50 PM PDT 24
Peak memory 210148 kb
Host smart-dd41dfc1-f309-40cc-9156-97f99e219a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249946639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3249946639
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1205505306
Short name T811
Test name
Test status
Simulation time 248089023 ps
CPU time 6.26 seconds
Started May 19 01:49:56 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 210920 kb
Host smart-205fade0-e67a-4b16-a1be-c63e508126b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205505306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1205505306
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.665012001
Short name T105
Test name
Test status
Simulation time 10907878 ps
CPU time 0.92 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 205972 kb
Host smart-de939902-5f1c-4070-937b-ec02d56f3b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665012001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.665012001
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.286950430
Short name T32
Test name
Test status
Simulation time 81926150 ps
CPU time 2.71 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 210188 kb
Host smart-251e726c-d6b3-4e52-82c7-2f32bf7a18fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286950430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.286950430
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3132613792
Short name T796
Test name
Test status
Simulation time 320215848 ps
CPU time 2.5 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 207140 kb
Host smart-55b8ba9d-0252-4cf6-8ce7-c834ddeced84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132613792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3132613792
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1303366069
Short name T747
Test name
Test status
Simulation time 99069260 ps
CPU time 2.74 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 209492 kb
Host smart-2b44dd40-bf72-4293-b89c-c2f8db276a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303366069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1303366069
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.591913624
Short name T225
Test name
Test status
Simulation time 208928972 ps
CPU time 3.48 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 207580 kb
Host smart-f9dea103-d695-4af2-ac1a-e141ef9b586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591913624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.591913624
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2322472827
Short name T287
Test name
Test status
Simulation time 47505563 ps
CPU time 2.15 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 207992 kb
Host smart-477c44df-c45e-41c7-b538-6fcdbda3eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322472827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2322472827
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1537619290
Short name T424
Test name
Test status
Simulation time 144470743 ps
CPU time 3.96 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 208232 kb
Host smart-13b25eec-8b68-487d-ab29-89ba89c32ed9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537619290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1537619290
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.823874427
Short name T844
Test name
Test status
Simulation time 460257804 ps
CPU time 4.17 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 208692 kb
Host smart-46709387-aa14-4607-ba89-29cb40db9d1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823874427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.823874427
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2458557996
Short name T676
Test name
Test status
Simulation time 3219314109 ps
CPU time 44.26 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 209320 kb
Host smart-c6063d0e-2d2d-4fe2-ac47-29d8e175afa1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458557996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2458557996
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2205304088
Short name T444
Test name
Test status
Simulation time 271274054 ps
CPU time 8.62 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 215768 kb
Host smart-284efcd6-1d58-4db6-a46a-b7f6ece75c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205304088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2205304088
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.431545524
Short name T549
Test name
Test status
Simulation time 48400220 ps
CPU time 2.23 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 207124 kb
Host smart-0ecc355b-0cc7-48b2-85d8-ce9ac77e0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431545524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.431545524
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.4262359302
Short name T306
Test name
Test status
Simulation time 3624993292 ps
CPU time 37.92 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:52:07 PM PDT 24
Peak memory 215072 kb
Host smart-173cf7a2-c27f-46e3-afbc-2b8056062825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262359302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4262359302
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.431709410
Short name T819
Test name
Test status
Simulation time 192279018 ps
CPU time 11.47 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 220724 kb
Host smart-5d6cfa44-63d5-4e07-91a9-1bda8bd38357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431709410 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.431709410
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1428371818
Short name T694
Test name
Test status
Simulation time 551915401 ps
CPU time 5.54 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 209324 kb
Host smart-bc6a2120-3505-4f17-af62-be3da71154d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428371818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1428371818
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3916061157
Short name T38
Test name
Test status
Simulation time 161590236 ps
CPU time 2.24 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 210172 kb
Host smart-0a25c8b9-b13c-44c1-bdbb-ccc6274f3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916061157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3916061157
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2687132153
Short name T678
Test name
Test status
Simulation time 9841499 ps
CPU time 0.81 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 205940 kb
Host smart-59d581b6-c002-4d3f-85a0-44b376bc91f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687132153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2687132153
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1675501393
Short name T9
Test name
Test status
Simulation time 85959577 ps
CPU time 1.97 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 214736 kb
Host smart-b144464c-fcbc-480d-a3c9-e081dc4d2ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675501393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1675501393
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3708549114
Short name T684
Test name
Test status
Simulation time 49329979 ps
CPU time 1.76 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 207320 kb
Host smart-a2a3114f-82c4-4052-bf58-3e98efb91ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708549114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3708549114
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1491985509
Short name T872
Test name
Test status
Simulation time 27650066 ps
CPU time 2.11 seconds
Started May 19 01:51:14 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 208708 kb
Host smart-df317919-c21b-447f-8ad1-7394f51d0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491985509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1491985509
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1011694965
Short name T40
Test name
Test status
Simulation time 203866152 ps
CPU time 3.1 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 220080 kb
Host smart-8e8ca121-15cf-488f-bb91-2949d6db4221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011694965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1011694965
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2906031745
Short name T786
Test name
Test status
Simulation time 366333695 ps
CPU time 3.17 seconds
Started May 19 01:51:14 PM PDT 24
Finished May 19 01:51:19 PM PDT 24
Peak memory 219868 kb
Host smart-04635357-7d01-4332-89d2-8ead998cf281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906031745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2906031745
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3460921430
Short name T737
Test name
Test status
Simulation time 34238896 ps
CPU time 2.46 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 209996 kb
Host smart-e9c384b3-23d8-4bc7-88af-0c424521871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460921430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3460921430
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3769353996
Short name T585
Test name
Test status
Simulation time 374213679 ps
CPU time 6.61 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 208332 kb
Host smart-64629ae7-3253-4434-a976-c3873a93915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769353996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3769353996
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1125201422
Short name T793
Test name
Test status
Simulation time 2810800979 ps
CPU time 35.36 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 208572 kb
Host smart-85cde998-9f27-4d87-bd81-e3df99a6012f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125201422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1125201422
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4142784283
Short name T752
Test name
Test status
Simulation time 280156883 ps
CPU time 4.46 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 208960 kb
Host smart-5add42dd-fb92-4af5-a76e-f5d08e7f2925
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142784283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4142784283
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3828857793
Short name T430
Test name
Test status
Simulation time 81741338 ps
CPU time 3.07 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:23 PM PDT 24
Peak memory 206924 kb
Host smart-f16ff1d4-c920-41ae-bec0-667947b4cf21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828857793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3828857793
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3471019329
Short name T263
Test name
Test status
Simulation time 809883067 ps
CPU time 2.42 seconds
Started May 19 01:51:14 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 209428 kb
Host smart-b5b025a2-3ede-44aa-ba46-21573b7f2531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471019329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3471019329
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.418916119
Short name T881
Test name
Test status
Simulation time 663420029 ps
CPU time 10.93 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:43 PM PDT 24
Peak memory 208576 kb
Host smart-bba2bb28-bdd7-4c0e-8ba3-94ea247508e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418916119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.418916119
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3654476544
Short name T852
Test name
Test status
Simulation time 816385979 ps
CPU time 14.04 seconds
Started May 19 01:51:11 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 222576 kb
Host smart-fe141e9c-0300-4e72-b027-c93149a0632f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654476544 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3654476544
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.722031497
Short name T661
Test name
Test status
Simulation time 576385375 ps
CPU time 8.65 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:42 PM PDT 24
Peak memory 209080 kb
Host smart-8fdc408b-c028-43c5-91ed-23f47b7150ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722031497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.722031497
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4060139486
Short name T44
Test name
Test status
Simulation time 83655898 ps
CPU time 2.71 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 209900 kb
Host smart-9532a820-850f-4bcb-b859-95d3528ed748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060139486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4060139486
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3844621926
Short name T662
Test name
Test status
Simulation time 10611154 ps
CPU time 0.83 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 205940 kb
Host smart-d4b31bec-48c4-40e3-b926-927805905de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844621926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3844621926
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2524465743
Short name T916
Test name
Test status
Simulation time 34067643 ps
CPU time 2.08 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 214316 kb
Host smart-005cfc10-fcc8-4a0a-9d56-a429cabdc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524465743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2524465743
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1793812829
Short name T914
Test name
Test status
Simulation time 85636177 ps
CPU time 3.92 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 210496 kb
Host smart-e88c88ef-5995-4037-9ff0-8fc069d6a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793812829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1793812829
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2559754698
Short name T357
Test name
Test status
Simulation time 1707344359 ps
CPU time 8.01 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 209784 kb
Host smart-91f4b5da-e04b-4acb-91ee-b920f971d0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559754698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2559754698
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1580975603
Short name T230
Test name
Test status
Simulation time 514831751 ps
CPU time 4.69 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 206068 kb
Host smart-a0f59ca7-3aa4-4bbe-b343-08ee5691cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580975603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1580975603
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1066762375
Short name T851
Test name
Test status
Simulation time 52596915 ps
CPU time 2.38 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 210184 kb
Host smart-5aa9615e-1ae6-4d8c-9af1-2fbebc9c4456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066762375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1066762375
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2335091060
Short name T14
Test name
Test status
Simulation time 169416316 ps
CPU time 2.6 seconds
Started May 19 01:51:28 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 218240 kb
Host smart-5051ae5f-9af6-47a8-aa26-4433065e0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335091060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2335091060
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1598542231
Short name T479
Test name
Test status
Simulation time 72499662 ps
CPU time 2.25 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 206868 kb
Host smart-59a43d91-6a2e-48cd-afb7-18f513fc5c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598542231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1598542231
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2527919825
Short name T707
Test name
Test status
Simulation time 52361646 ps
CPU time 3.03 seconds
Started May 19 01:51:12 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 207268 kb
Host smart-974670d9-dc80-469e-9328-220d39f7719f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527919825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2527919825
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.879819255
Short name T240
Test name
Test status
Simulation time 125350075 ps
CPU time 2.48 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 208780 kb
Host smart-67b24b06-c6f4-487e-98f3-a757ff94f6b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879819255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.879819255
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3483717171
Short name T896
Test name
Test status
Simulation time 115340406 ps
CPU time 2.98 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 206976 kb
Host smart-8af403cc-4105-4872-9ba0-34b768396234
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483717171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3483717171
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1575992615
Short name T634
Test name
Test status
Simulation time 128101995 ps
CPU time 3.58 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 208732 kb
Host smart-8839db8d-dbd7-40ee-85ab-da814b1c2b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575992615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1575992615
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2929416287
Short name T818
Test name
Test status
Simulation time 280688036 ps
CPU time 3.91 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 208588 kb
Host smart-c42396aa-cf98-4f6d-94f8-bb18b3a9a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929416287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2929416287
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.562878056
Short name T724
Test name
Test status
Simulation time 1309455781 ps
CPU time 8.65 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 209308 kb
Host smart-4e229e37-43f5-4b15-9308-3d6de5d58088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562878056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.562878056
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3730300091
Short name T765
Test name
Test status
Simulation time 87367813 ps
CPU time 2.52 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 207824 kb
Host smart-8a355b34-bb68-42bc-ae00-928e35002ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730300091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3730300091
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3008299235
Short name T378
Test name
Test status
Simulation time 545332101 ps
CPU time 15.25 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:51:47 PM PDT 24
Peak memory 210900 kb
Host smart-977f1749-a3bb-49cf-8a46-60128dab287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008299235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3008299235
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.88876940
Short name T458
Test name
Test status
Simulation time 13395995 ps
CPU time 0.73 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:18 PM PDT 24
Peak memory 205988 kb
Host smart-ac7c4272-a3d0-44f2-ae13-cc8564218bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88876940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.88876940
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3905815773
Short name T908
Test name
Test status
Simulation time 555558438 ps
CPU time 10.2 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:45 PM PDT 24
Peak memory 214712 kb
Host smart-e20fd95b-de37-432d-9f54-850806658fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905815773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3905815773
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2129151672
Short name T73
Test name
Test status
Simulation time 328114089 ps
CPU time 3.17 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 209736 kb
Host smart-dcea2f83-debc-47b6-af6d-26dedd55f395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129151672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2129151672
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1551965038
Short name T686
Test name
Test status
Simulation time 24102374 ps
CPU time 1.82 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 214352 kb
Host smart-a85455e9-4af2-4ef7-b415-51517037eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551965038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1551965038
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2275369429
Short name T882
Test name
Test status
Simulation time 216293988 ps
CPU time 4.63 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 214236 kb
Host smart-9a7d24e1-730e-4309-9a2f-babd5cba4334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275369429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2275369429
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3587358946
Short name T473
Test name
Test status
Simulation time 79859368 ps
CPU time 3.9 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 214364 kb
Host smart-01373821-de1e-4928-b932-58f2e8e86cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587358946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3587358946
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2720621927
Short name T223
Test name
Test status
Simulation time 527250350 ps
CPU time 6.36 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 208812 kb
Host smart-cc6b3d25-e62c-486f-ab48-08821c92fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720621927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2720621927
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4032524757
Short name T683
Test name
Test status
Simulation time 99950042 ps
CPU time 1.91 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 207492 kb
Host smart-1003f3ab-b264-4415-bc32-821edddaded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032524757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4032524757
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1312571894
Short name T198
Test name
Test status
Simulation time 158928724 ps
CPU time 6.2 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 208936 kb
Host smart-955c2e0c-4b3f-4d9b-8fdf-b8807086442f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312571894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1312571894
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2275732012
Short name T911
Test name
Test status
Simulation time 118911037 ps
CPU time 3.29 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 206908 kb
Host smart-e5a655ef-3a73-42b0-819d-d869a8722aae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275732012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2275732012
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3613897387
Short name T554
Test name
Test status
Simulation time 78608273 ps
CPU time 3 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 206992 kb
Host smart-3aaa3adf-99e8-4068-b465-50221cfaf0cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613897387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3613897387
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.678254406
Short name T394
Test name
Test status
Simulation time 72553994 ps
CPU time 1.51 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 215876 kb
Host smart-7e530c67-22e3-48b0-8ef2-809577e9a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678254406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.678254406
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.73952650
Short name T440
Test name
Test status
Simulation time 264453596 ps
CPU time 3.34 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 207968 kb
Host smart-6b3dd7d9-27a4-4089-a976-a559b7a6510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73952650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.73952650
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.63801083
Short name T350
Test name
Test status
Simulation time 114162246 ps
CPU time 2.41 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 208844 kb
Host smart-3da1a3c8-d6d2-4b90-bccc-ed6f7b0d8bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63801083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.63801083
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3720409161
Short name T625
Test name
Test status
Simulation time 84023317 ps
CPU time 3.03 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 209924 kb
Host smart-57793fac-1c0a-4228-874e-a128850c70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720409161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3720409161
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.530610955
Short name T673
Test name
Test status
Simulation time 42545306 ps
CPU time 0.73 seconds
Started May 19 01:51:28 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 205972 kb
Host smart-2dec7d27-acdf-4eef-aee4-f21454f027d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530610955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.530610955
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3093838962
Short name T402
Test name
Test status
Simulation time 631048579 ps
CPU time 16.1 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:52 PM PDT 24
Peak memory 214472 kb
Host smart-77041182-a3e8-4906-a027-ccb98dce2786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093838962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3093838962
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.228006352
Short name T769
Test name
Test status
Simulation time 604396897 ps
CPU time 4.16 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 222744 kb
Host smart-c2b4e7d9-0347-45b3-964b-57962aba2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228006352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.228006352
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3655316384
Short name T586
Test name
Test status
Simulation time 1822404798 ps
CPU time 12.79 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:44 PM PDT 24
Peak memory 209108 kb
Host smart-747d4eff-c1eb-4768-8d96-2b8687861e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655316384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3655316384
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2905566126
Short name T335
Test name
Test status
Simulation time 29889803 ps
CPU time 2.09 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 214432 kb
Host smart-7952154a-35d0-45ae-81ab-02cf5cf1b3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905566126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2905566126
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3451124347
Short name T700
Test name
Test status
Simulation time 91926349 ps
CPU time 2.74 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 207144 kb
Host smart-2c2ff441-fb6f-4faa-be9b-3effd05f5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451124347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3451124347
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.398644946
Short name T613
Test name
Test status
Simulation time 40817542 ps
CPU time 2.88 seconds
Started May 19 01:51:24 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 214408 kb
Host smart-aff36f48-7f3b-438e-9d76-e3452d66ca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398644946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.398644946
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2611108384
Short name T15
Test name
Test status
Simulation time 77788614 ps
CPU time 3.3 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 208756 kb
Host smart-173269f1-6bbd-4f7f-b0c1-a01d41a76699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611108384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2611108384
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1962864398
Short name T290
Test name
Test status
Simulation time 187688008 ps
CPU time 6.21 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 208712 kb
Host smart-38991c1f-1e8f-4c8f-9764-5b4420b3b480
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962864398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1962864398
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2942931273
Short name T837
Test name
Test status
Simulation time 3129376543 ps
CPU time 22.29 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 208756 kb
Host smart-6315174c-1d03-4904-a77f-d7a28ffb926c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942931273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2942931273
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3202430354
Short name T137
Test name
Test status
Simulation time 275503143 ps
CPU time 3.49 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 208604 kb
Host smart-c0b1d296-0c83-44d9-8ee0-c5e02e75088c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202430354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3202430354
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1438236764
Short name T648
Test name
Test status
Simulation time 52884247 ps
CPU time 2.7 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 206964 kb
Host smart-813c4707-5f28-4c78-b349-95b48283a063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438236764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1438236764
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1414273203
Short name T193
Test name
Test status
Simulation time 2071333698 ps
CPU time 51.22 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:52:16 PM PDT 24
Peak memory 216560 kb
Host smart-986e12a7-75d5-4a4c-ae83-17df90845a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414273203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1414273203
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.408000638
Short name T632
Test name
Test status
Simulation time 1444347454 ps
CPU time 35.47 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:52:08 PM PDT 24
Peak memory 210576 kb
Host smart-7f6aa7de-bfce-4282-b9ee-d9d608e49da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408000638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.408000638
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3719827875
Short name T375
Test name
Test status
Simulation time 613236881 ps
CPU time 9.11 seconds
Started May 19 01:51:16 PM PDT 24
Finished May 19 01:51:27 PM PDT 24
Peak memory 209908 kb
Host smart-22f32d1a-026e-4170-98dc-064e77e497e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719827875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3719827875
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3596595660
Short name T799
Test name
Test status
Simulation time 12450940 ps
CPU time 0.86 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 205972 kb
Host smart-1fd52a65-462b-40b5-843b-f5fda4f739d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596595660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3596595660
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1393769659
Short name T236
Test name
Test status
Simulation time 193397976 ps
CPU time 5.75 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 215496 kb
Host smart-faa6645a-bd94-4b79-892c-c77e8c744a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393769659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1393769659
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2633494456
Short name T20
Test name
Test status
Simulation time 480637784 ps
CPU time 4.4 seconds
Started May 19 01:51:33 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 209176 kb
Host smart-143f33f5-e514-4967-89f1-d55132340185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633494456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2633494456
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2951022230
Short name T595
Test name
Test status
Simulation time 151808634 ps
CPU time 2.23 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 206788 kb
Host smart-8dd6b77f-a74d-49ae-8417-13a4d161840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951022230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2951022230
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2874832878
Short name T295
Test name
Test status
Simulation time 75181760 ps
CPU time 1.81 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 214568 kb
Host smart-6878bc03-9b46-4351-b3dc-b4c0d532d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874832878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2874832878
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.560573886
Short name T91
Test name
Test status
Simulation time 163657185 ps
CPU time 3.55 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:31 PM PDT 24
Peak memory 214288 kb
Host smart-5e6a04e0-55c2-4d48-87b4-0ff5a4e666a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560573886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.560573886
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1758715247
Short name T606
Test name
Test status
Simulation time 36242931 ps
CPU time 2.62 seconds
Started May 19 01:51:28 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 208344 kb
Host smart-2eeb92d7-27ba-4c68-8d48-72f38cfc49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758715247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1758715247
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1620086751
Short name T588
Test name
Test status
Simulation time 3176195276 ps
CPU time 34.12 seconds
Started May 19 01:51:15 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 209376 kb
Host smart-24e181da-b493-4951-8983-8260012f6cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620086751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1620086751
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3600253016
Short name T468
Test name
Test status
Simulation time 44457780 ps
CPU time 2.46 seconds
Started May 19 01:51:36 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 208100 kb
Host smart-0011f09e-83e7-46b8-bb0e-fe416d022a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600253016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3600253016
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2931972447
Short name T584
Test name
Test status
Simulation time 979647167 ps
CPU time 6.38 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 208340 kb
Host smart-787ef011-e5f3-4ff4-ab6a-b8c710ef3ac6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931972447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2931972447
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.919836095
Short name T427
Test name
Test status
Simulation time 158985960 ps
CPU time 4.06 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:26 PM PDT 24
Peak memory 208080 kb
Host smart-42931820-36b1-4520-8abd-a08b4180d499
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919836095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.919836095
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2073015437
Short name T574
Test name
Test status
Simulation time 339216123 ps
CPU time 4.6 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 206876 kb
Host smart-c6142f89-fd1e-4147-abe1-d808724abf4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073015437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2073015437
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2353110206
Short name T845
Test name
Test status
Simulation time 166944414 ps
CPU time 2.58 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 214348 kb
Host smart-fc6469a2-a283-4284-9a43-cd3a559558c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353110206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2353110206
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2909948403
Short name T913
Test name
Test status
Simulation time 223719075 ps
CPU time 2.7 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 208744 kb
Host smart-f79b8106-51c9-49a7-84ab-4cd258f3ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909948403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2909948403
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2915533614
Short name T79
Test name
Test status
Simulation time 4971775378 ps
CPU time 101.02 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:53:10 PM PDT 24
Peak memory 222564 kb
Host smart-aaafa404-9488-4d53-9854-35af812763fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915533614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2915533614
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3091250964
Short name T226
Test name
Test status
Simulation time 80619773 ps
CPU time 2.8 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:51:28 PM PDT 24
Peak memory 208360 kb
Host smart-fd404d98-ae29-43b2-9417-301eb6406658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091250964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3091250964
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2428210588
Short name T489
Test name
Test status
Simulation time 181796839 ps
CPU time 0.84 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 205936 kb
Host smart-d621225e-8d72-4b09-81da-ce5594b293e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428210588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2428210588
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2071082754
Short name T134
Test name
Test status
Simulation time 34594852 ps
CPU time 2.53 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:30 PM PDT 24
Peak memory 214372 kb
Host smart-28900f40-18f5-4c32-8212-36f1ca0ad069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071082754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2071082754
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1021219029
Short name T616
Test name
Test status
Simulation time 39625262 ps
CPU time 1.68 seconds
Started May 19 01:51:25 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 207504 kb
Host smart-d134ba65-c36c-4a38-a388-656c4e40c76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021219029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1021219029
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3122938902
Short name T336
Test name
Test status
Simulation time 34544496 ps
CPU time 2.08 seconds
Started May 19 01:51:36 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 214188 kb
Host smart-214f3396-4f6c-4663-91c2-277fc666d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122938902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3122938902
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2699856017
Short name T738
Test name
Test status
Simulation time 164834938 ps
CPU time 2.21 seconds
Started May 19 01:51:42 PM PDT 24
Finished May 19 01:51:45 PM PDT 24
Peak memory 214332 kb
Host smart-ca2f5da9-4ce2-497e-b745-5e08f1f63f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699856017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2699856017
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2590915118
Short name T114
Test name
Test status
Simulation time 335494626 ps
CPU time 6.39 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 214332 kb
Host smart-39b6dfcc-1b13-4c82-8caf-391f4989c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590915118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2590915118
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.229438010
Short name T253
Test name
Test status
Simulation time 194275612 ps
CPU time 1.88 seconds
Started May 19 01:51:34 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 207172 kb
Host smart-a7e583d4-871e-4f25-88a5-6aa0e56687e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229438010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.229438010
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1602214118
Short name T496
Test name
Test status
Simulation time 134823402 ps
CPU time 4.58 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:35 PM PDT 24
Peak memory 207040 kb
Host smart-898a031c-923f-404a-9ca7-d2666eba4966
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602214118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1602214118
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2085382493
Short name T875
Test name
Test status
Simulation time 288172217 ps
CPU time 6.17 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 207956 kb
Host smart-5dc5ecd7-f7e8-4d9b-995b-bfa42c70da00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085382493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2085382493
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1602941192
Short name T783
Test name
Test status
Simulation time 170717043 ps
CPU time 2.31 seconds
Started May 19 01:51:30 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 207044 kb
Host smart-e4a1e1a3-b2d6-4740-9901-b0ceaa503006
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602941192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1602941192
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2531510188
Short name T446
Test name
Test status
Simulation time 166809431 ps
CPU time 2.89 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 209956 kb
Host smart-1416c9c8-6c99-4c03-9ff3-809df68e6dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531510188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2531510188
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3348069899
Short name T608
Test name
Test status
Simulation time 580834608 ps
CPU time 6.01 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:29 PM PDT 24
Peak memory 208052 kb
Host smart-f7df9456-8cbf-4b96-859f-57bf701ea42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348069899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3348069899
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3463356271
Short name T899
Test name
Test status
Simulation time 172291971 ps
CPU time 4.43 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 208244 kb
Host smart-40a557df-ba9d-4bb5-b719-d1f41f5aa2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463356271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3463356271
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2887872598
Short name T157
Test name
Test status
Simulation time 303346094 ps
CPU time 2.59 seconds
Started May 19 01:51:31 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 210016 kb
Host smart-23a9ec9f-e3bc-47bc-9905-11e6ff437f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887872598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2887872598
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2664769671
Short name T516
Test name
Test status
Simulation time 28508948 ps
CPU time 0.92 seconds
Started May 19 01:51:41 PM PDT 24
Finished May 19 01:51:42 PM PDT 24
Peak memory 206096 kb
Host smart-b9f42edb-29c8-4b2a-a1a9-b8f5368a14f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664769671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2664769671
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1232622667
Short name T414
Test name
Test status
Simulation time 201929825 ps
CPU time 4.27 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 215304 kb
Host smart-6ac4f5f0-b49c-4850-9653-4658151ce3ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232622667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1232622667
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2874563637
Short name T42
Test name
Test status
Simulation time 116640054 ps
CPU time 1.91 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:50 PM PDT 24
Peak memory 208448 kb
Host smart-b796107b-345c-44ec-be74-f57c268bbf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874563637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2874563637
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3795041790
Short name T313
Test name
Test status
Simulation time 171885027 ps
CPU time 3.02 seconds
Started May 19 01:51:17 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 208396 kb
Host smart-19a03af4-d477-4897-aa39-cae4e61e13db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795041790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3795041790
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1192155031
Short name T374
Test name
Test status
Simulation time 103398575 ps
CPU time 2.29 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 217708 kb
Host smart-06e89392-2614-4e47-a54f-23a90831c724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192155031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1192155031
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.201499053
Short name T746
Test name
Test status
Simulation time 161745992 ps
CPU time 4.39 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 220540 kb
Host smart-8099bf07-c060-4817-a069-376da102e303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201499053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.201499053
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4149965318
Short name T202
Test name
Test status
Simulation time 415991294 ps
CPU time 2.56 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 209612 kb
Host smart-1fda133a-3f04-45b1-a9b9-2e3b69109340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149965318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4149965318
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.784140305
Short name T834
Test name
Test status
Simulation time 326816354 ps
CPU time 7.34 seconds
Started May 19 01:51:20 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 208496 kb
Host smart-843f0c49-7c9b-4fc7-b3c5-1f753bc39541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784140305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.784140305
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.32303425
Short name T708
Test name
Test status
Simulation time 60675985 ps
CPU time 2.87 seconds
Started May 19 01:51:25 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 207824 kb
Host smart-83067958-1b65-4388-9e0d-2724febcc845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32303425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.32303425
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1309700811
Short name T324
Test name
Test status
Simulation time 303130812 ps
CPU time 3.3 seconds
Started May 19 01:51:18 PM PDT 24
Finished May 19 01:51:25 PM PDT 24
Peak memory 208920 kb
Host smart-2b92f865-5495-4764-b72b-7fe778d4299c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309700811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1309700811
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1479989501
Short name T593
Test name
Test status
Simulation time 105161338 ps
CPU time 3.44 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 208652 kb
Host smart-ed7706f4-b40a-4de3-851d-f9f3ec052cfa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479989501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1479989501
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3297252830
Short name T722
Test name
Test status
Simulation time 1503118184 ps
CPU time 37.44 seconds
Started May 19 01:51:19 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 209024 kb
Host smart-daca3c94-71c6-467b-8ced-dda275ff014e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297252830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3297252830
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3463774983
Short name T113
Test name
Test status
Simulation time 674435188 ps
CPU time 3.3 seconds
Started May 19 01:51:26 PM PDT 24
Finished May 19 01:51:36 PM PDT 24
Peak memory 216268 kb
Host smart-a31dfb1d-3cb7-4269-b524-43fd6d49a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463774983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3463774983
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.316646147
Short name T802
Test name
Test status
Simulation time 113154232 ps
CPU time 3.23 seconds
Started May 19 01:51:29 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 208476 kb
Host smart-a7e9a87e-efe9-4b4a-89de-d57fb3df292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316646147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.316646147
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3864599716
Short name T641
Test name
Test status
Simulation time 21302252819 ps
CPU time 47.71 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:52:18 PM PDT 24
Peak memory 215924 kb
Host smart-b52af22e-e384-4fcd-a3a4-f759c821944d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864599716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3864599716
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.33597178
Short name T740
Test name
Test status
Simulation time 118478886 ps
CPU time 7.84 seconds
Started May 19 01:51:25 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 219892 kb
Host smart-84865d3d-6755-43ef-a9ee-6f7eaaf84bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597178 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.33597178
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3091209028
Short name T506
Test name
Test status
Simulation time 33566201 ps
CPU time 2.43 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 207784 kb
Host smart-abb93cc5-79b4-46d7-a8db-75f7f7753d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091209028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3091209028
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3257699481
Short name T46
Test name
Test status
Simulation time 316285769 ps
CPU time 4.62 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 211032 kb
Host smart-91bf71c9-d8cc-4450-8280-8bde3ee1246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257699481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3257699481
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1763901100
Short name T839
Test name
Test status
Simulation time 44244518 ps
CPU time 0.72 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 205972 kb
Host smart-abc90bc6-d6f9-45aa-baa5-30b5c0df5419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763901100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1763901100
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4025983083
Short name T876
Test name
Test status
Simulation time 176675939 ps
CPU time 2.58 seconds
Started May 19 01:51:44 PM PDT 24
Finished May 19 01:51:47 PM PDT 24
Peak memory 208616 kb
Host smart-c9cb9e0e-20a9-433a-9740-e54664d7bc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025983083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4025983083
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3039263104
Short name T671
Test name
Test status
Simulation time 359767125 ps
CPU time 2.71 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:32 PM PDT 24
Peak memory 210296 kb
Host smart-48140c9d-daed-4fe7-a18a-46dece02e773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039263104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3039263104
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3963250655
Short name T821
Test name
Test status
Simulation time 331476997 ps
CPU time 2.39 seconds
Started May 19 01:51:34 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 221492 kb
Host smart-7ca6288d-f3e8-4a44-aa60-aec91d65a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963250655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3963250655
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1832205297
Short name T201
Test name
Test status
Simulation time 100005163 ps
CPU time 3.84 seconds
Started May 19 01:51:22 PM PDT 24
Finished May 19 01:51:34 PM PDT 24
Peak memory 214348 kb
Host smart-bda59e2e-1194-4b05-a0a3-f42fcfdcaae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832205297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1832205297
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3286304492
Short name T510
Test name
Test status
Simulation time 4312254861 ps
CPU time 22.01 seconds
Started May 19 01:51:21 PM PDT 24
Finished May 19 01:51:51 PM PDT 24
Peak memory 214392 kb
Host smart-e043d102-d095-47c2-9353-2a0f657023db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286304492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3286304492
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3629350445
Short name T416
Test name
Test status
Simulation time 894098438 ps
CPU time 21.49 seconds
Started May 19 01:51:44 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 208208 kb
Host smart-b725f10b-297d-4f61-974b-0fbc59edef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629350445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3629350445
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2167621594
Short name T483
Test name
Test status
Simulation time 407144698 ps
CPU time 4.73 seconds
Started May 19 01:51:47 PM PDT 24
Finished May 19 01:51:52 PM PDT 24
Peak memory 206812 kb
Host smart-1243377e-29fe-4cae-8cac-077df1f3e10d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167621594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2167621594
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3093407683
Short name T619
Test name
Test status
Simulation time 67386405 ps
CPU time 3.57 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:55 PM PDT 24
Peak memory 209116 kb
Host smart-65109ca9-ab1d-44f2-a434-d12a53c8292d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093407683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3093407683
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2342043379
Short name T696
Test name
Test status
Simulation time 102059081 ps
CPU time 4.15 seconds
Started May 19 01:51:32 PM PDT 24
Finished May 19 01:51:39 PM PDT 24
Peak memory 206908 kb
Host smart-2b60309c-497c-45c0-8520-f9d970c0b006
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342043379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2342043379
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.330839766
Short name T233
Test name
Test status
Simulation time 97690084 ps
CPU time 4.12 seconds
Started May 19 01:51:48 PM PDT 24
Finished May 19 01:51:59 PM PDT 24
Peak memory 222324 kb
Host smart-b8856283-46e2-4438-a067-4965e4a590ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330839766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.330839766
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2258050757
Short name T85
Test name
Test status
Simulation time 353394231 ps
CPU time 2.85 seconds
Started May 19 01:51:23 PM PDT 24
Finished May 19 01:51:33 PM PDT 24
Peak memory 208560 kb
Host smart-1408d719-1c4a-40f2-af6a-010c9e87e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258050757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2258050757
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.512563971
Short name T111
Test name
Test status
Simulation time 101941838 ps
CPU time 4.33 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 208976 kb
Host smart-a165f83c-84de-48ba-907a-d2b98f5a5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512563971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.512563971
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.509089351
Short name T538
Test name
Test status
Simulation time 4360756981 ps
CPU time 27.69 seconds
Started May 19 01:51:38 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 211104 kb
Host smart-4983ed8e-a264-45bc-9701-e053ab1db8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509089351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.509089351
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4117350270
Short name T827
Test name
Test status
Simulation time 12083278 ps
CPU time 0.75 seconds
Started May 19 01:51:44 PM PDT 24
Finished May 19 01:51:45 PM PDT 24
Peak memory 205956 kb
Host smart-1739dd89-f914-4f2a-9578-baf842f944df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117350270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4117350270
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3045727877
Short name T370
Test name
Test status
Simulation time 98987752 ps
CPU time 5.47 seconds
Started May 19 01:51:36 PM PDT 24
Finished May 19 01:51:42 PM PDT 24
Peak memory 222492 kb
Host smart-06459af4-ecc5-4f24-9206-801f4af69528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045727877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3045727877
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2875038707
Short name T314
Test name
Test status
Simulation time 1673581217 ps
CPU time 17.67 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 208640 kb
Host smart-ffff2692-f482-4591-a24d-9fe885d4f300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875038707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2875038707
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2970655109
Short name T273
Test name
Test status
Simulation time 134458814 ps
CPU time 2.77 seconds
Started May 19 01:51:34 PM PDT 24
Finished May 19 01:51:38 PM PDT 24
Peak memory 214568 kb
Host smart-64f4af86-d757-4b23-a6dd-754c157f7e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970655109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2970655109
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1584685349
Short name T229
Test name
Test status
Simulation time 131187810 ps
CPU time 3.06 seconds
Started May 19 01:51:49 PM PDT 24
Finished May 19 01:51:54 PM PDT 24
Peak memory 214284 kb
Host smart-024c9e9e-e638-4984-ada3-6702070c2c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584685349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1584685349
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2934922866
Short name T753
Test name
Test status
Simulation time 26447880 ps
CPU time 1.21 seconds
Started May 19 01:51:38 PM PDT 24
Finished May 19 01:51:40 PM PDT 24
Peak memory 206212 kb
Host smart-90b96a24-3378-44d1-8331-f284fe710f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934922866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2934922866
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.561829866
Short name T88
Test name
Test status
Simulation time 560908845 ps
CPU time 4.85 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 209192 kb
Host smart-ac54879a-2ce2-4b49-ad36-7aa3f6518bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561829866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.561829866
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2331399973
Short name T304
Test name
Test status
Simulation time 2405743371 ps
CPU time 16.36 seconds
Started May 19 01:51:38 PM PDT 24
Finished May 19 01:51:55 PM PDT 24
Peak memory 208128 kb
Host smart-2f387bbd-75ee-4eeb-ace7-4bea085f0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331399973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2331399973
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1442218165
Short name T1
Test name
Test status
Simulation time 5762853503 ps
CPU time 58.03 seconds
Started May 19 01:51:38 PM PDT 24
Finished May 19 01:52:37 PM PDT 24
Peak memory 209064 kb
Host smart-9cc5fe34-7a56-45a5-b576-0d0369b299f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442218165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1442218165
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1349915832
Short name T422
Test name
Test status
Simulation time 166707113 ps
CPU time 5.74 seconds
Started May 19 01:51:38 PM PDT 24
Finished May 19 01:51:44 PM PDT 24
Peak memory 208088 kb
Host smart-edfdb7a9-eaa9-4eca-885d-f7e1d55f8e03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349915832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1349915832
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1005587210
Short name T826
Test name
Test status
Simulation time 76030733 ps
CPU time 2.66 seconds
Started May 19 01:51:53 PM PDT 24
Finished May 19 01:51:58 PM PDT 24
Peak memory 208676 kb
Host smart-ca6f2205-92da-4370-b988-1edfd919e018
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005587210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1005587210
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1965718750
Short name T3
Test name
Test status
Simulation time 38402396 ps
CPU time 1.87 seconds
Started May 19 01:51:50 PM PDT 24
Finished May 19 01:51:55 PM PDT 24
Peak memory 215240 kb
Host smart-5b4afe98-d358-4532-a36a-8840841af7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965718750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1965718750
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2910994887
Short name T756
Test name
Test status
Simulation time 446590445 ps
CPU time 3.21 seconds
Started May 19 01:51:51 PM PDT 24
Finished May 19 01:51:57 PM PDT 24
Peak memory 206904 kb
Host smart-5f81f689-9db6-47af-9517-82ab004cba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910994887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2910994887
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2932056805
Short name T850
Test name
Test status
Simulation time 809570141 ps
CPU time 8.81 seconds
Started May 19 01:51:27 PM PDT 24
Finished May 19 01:51:42 PM PDT 24
Peak memory 208600 kb
Host smart-28557598-91ba-4684-ba99-ac79011c2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932056805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2932056805
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3667854714
Short name T767
Test name
Test status
Simulation time 71924030 ps
CPU time 2.09 seconds
Started May 19 01:51:44 PM PDT 24
Finished May 19 01:51:47 PM PDT 24
Peak memory 209916 kb
Host smart-fdf924ac-99ad-4036-8188-1b667768ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667854714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3667854714
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2001841190
Short name T520
Test name
Test status
Simulation time 42569052 ps
CPU time 0.93 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 205976 kb
Host smart-fc24306d-dadc-439d-8f32-b60a9e1331df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001841190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2001841190
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.611728509
Short name T23
Test name
Test status
Simulation time 113117577 ps
CPU time 2.33 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 216804 kb
Host smart-21be022c-458c-4a1d-a9a1-0724b72b5494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611728509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.611728509
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3727168980
Short name T227
Test name
Test status
Simulation time 193698064 ps
CPU time 2.42 seconds
Started May 19 01:49:59 PM PDT 24
Finished May 19 01:50:02 PM PDT 24
Peak memory 207548 kb
Host smart-e7d1fd65-0f35-403d-9eeb-a61c7c206de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727168980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3727168980
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2755876851
Short name T366
Test name
Test status
Simulation time 67061524 ps
CPU time 1.47 seconds
Started May 19 01:49:40 PM PDT 24
Finished May 19 01:49:45 PM PDT 24
Peak memory 214420 kb
Host smart-86d2a762-50a6-41a8-901c-c6b3f01e5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755876851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2755876851
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.751900605
Short name T515
Test name
Test status
Simulation time 196407978 ps
CPU time 3.53 seconds
Started May 19 01:50:06 PM PDT 24
Finished May 19 01:50:10 PM PDT 24
Peak memory 214368 kb
Host smart-03f7ac63-f08b-41fb-b588-2418b5953abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751900605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.751900605
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2832914729
Short name T300
Test name
Test status
Simulation time 297926277 ps
CPU time 10.64 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:10 PM PDT 24
Peak memory 214280 kb
Host smart-51679995-4836-4863-a149-9669d96e16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832914729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2832914729
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.997980409
Short name T822
Test name
Test status
Simulation time 2173114814 ps
CPU time 14.65 seconds
Started May 19 01:50:02 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 208116 kb
Host smart-e89d2f33-09e0-4be9-bf8a-ab87daa3cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997980409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.997980409
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2232198771
Short name T880
Test name
Test status
Simulation time 538035958 ps
CPU time 3.16 seconds
Started May 19 01:49:59 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 208648 kb
Host smart-60289ad5-9820-4f90-b532-817e86a72410
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232198771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2232198771
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2183476597
Short name T869
Test name
Test status
Simulation time 25240297 ps
CPU time 1.9 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:46 PM PDT 24
Peak memory 206836 kb
Host smart-d467d2b9-89dd-435a-b41b-778ceeeee5dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183476597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2183476597
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1312327345
Short name T726
Test name
Test status
Simulation time 275497838 ps
CPU time 4.22 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 207040 kb
Host smart-ad1d5655-663e-4297-a5d8-cce3c6d1412f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312327345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1312327345
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.306037455
Short name T907
Test name
Test status
Simulation time 48056891 ps
CPU time 2.66 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 209168 kb
Host smart-9f194e5b-22fd-45dd-820d-88a206903943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306037455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.306037455
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2001697246
Short name T551
Test name
Test status
Simulation time 307703992 ps
CPU time 2.63 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 207416 kb
Host smart-c0492567-851d-485a-a46e-35e026e756a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001697246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2001697246
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1109305703
Short name T307
Test name
Test status
Simulation time 35126516 ps
CPU time 2.57 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 207708 kb
Host smart-37035f7f-746c-43be-8d9a-e06eb58cdab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109305703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1109305703
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.99535738
Short name T748
Test name
Test status
Simulation time 82987315 ps
CPU time 2.26 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 210076 kb
Host smart-ae6d0c4d-066e-49f0-b7f3-467ad7f99ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99535738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.99535738
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1540816252
Short name T450
Test name
Test status
Simulation time 16056237 ps
CPU time 1 seconds
Started May 19 01:50:02 PM PDT 24
Finished May 19 01:50:04 PM PDT 24
Peak memory 206328 kb
Host smart-6b83cbf4-82c2-416b-8e6b-079f4299d2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540816252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1540816252
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2379444472
Short name T815
Test name
Test status
Simulation time 2289010687 ps
CPU time 4.61 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:49:55 PM PDT 24
Peak memory 214376 kb
Host smart-f9c6ac96-312f-4712-ac4f-7b063bfefc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379444472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2379444472
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.77985890
Short name T455
Test name
Test status
Simulation time 42945194 ps
CPU time 2.75 seconds
Started May 19 01:49:43 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 208208 kb
Host smart-236272b1-f110-49af-a7d8-fec19b79ffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77985890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.77985890
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2429844978
Short name T870
Test name
Test status
Simulation time 366869478 ps
CPU time 3.91 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 219728 kb
Host smart-3438f151-2513-4731-85b3-92fb46da8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429844978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2429844978
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.304350969
Short name T739
Test name
Test status
Simulation time 5116402054 ps
CPU time 57.14 seconds
Started May 19 01:50:00 PM PDT 24
Finished May 19 01:50:58 PM PDT 24
Peak memory 208936 kb
Host smart-50bfc462-ca3c-4617-8bb0-0d06af9de1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304350969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.304350969
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2536798188
Short name T690
Test name
Test status
Simulation time 143336933 ps
CPU time 3.88 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:02 PM PDT 24
Peak memory 207796 kb
Host smart-e9792f45-5b9a-4942-adda-cccc1e6bfe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536798188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2536798188
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1922695293
Short name T525
Test name
Test status
Simulation time 202379363 ps
CPU time 3.24 seconds
Started May 19 01:49:41 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 206964 kb
Host smart-d6825c6c-7e59-4b10-98e4-15f59d900676
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922695293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1922695293
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2736060061
Short name T552
Test name
Test status
Simulation time 129192533 ps
CPU time 4.92 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 207188 kb
Host smart-136a112b-8085-43cc-a63a-39c01144a228
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736060061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2736060061
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.260558208
Short name T241
Test name
Test status
Simulation time 69937063 ps
CPU time 3.21 seconds
Started May 19 01:49:53 PM PDT 24
Finished May 19 01:49:57 PM PDT 24
Peak memory 208908 kb
Host smart-49fea36b-dc90-4bdd-9c46-0944084221fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260558208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.260558208
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1707343284
Short name T838
Test name
Test status
Simulation time 1654520997 ps
CPU time 3.17 seconds
Started May 19 01:49:54 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 214344 kb
Host smart-9a672bbe-078d-4e1c-bdce-a22e976b33f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707343284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1707343284
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.197434918
Short name T419
Test name
Test status
Simulation time 116208425 ps
CPU time 4.2 seconds
Started May 19 01:49:53 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 206932 kb
Host smart-b4c1da3c-ef63-451e-8f28-250842de24ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197434918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.197434918
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.847260315
Short name T203
Test name
Test status
Simulation time 12741595892 ps
CPU time 68.69 seconds
Started May 19 01:49:49 PM PDT 24
Finished May 19 01:50:59 PM PDT 24
Peak memory 216068 kb
Host smart-9954569c-9093-4cd9-b4ca-f86e42a42b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847260315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.847260315
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1227021108
Short name T186
Test name
Test status
Simulation time 1038002785 ps
CPU time 19.36 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 220584 kb
Host smart-561821bd-d913-4a1f-a671-b2b05715e57b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227021108 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1227021108
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2277025155
Short name T572
Test name
Test status
Simulation time 245579826 ps
CPU time 3.61 seconds
Started May 19 01:49:46 PM PDT 24
Finished May 19 01:49:51 PM PDT 24
Peak memory 208048 kb
Host smart-7b4f6b9c-b341-43e9-b3a5-4c75dacf9e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277025155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2277025155
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4072406784
Short name T701
Test name
Test status
Simulation time 252969328 ps
CPU time 2.31 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:49:47 PM PDT 24
Peak memory 209860 kb
Host smart-c8bbc8b0-77a7-4a94-bf02-118e5f0428ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072406784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4072406784
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3197364711
Short name T550
Test name
Test status
Simulation time 42997548 ps
CPU time 0.87 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:49:55 PM PDT 24
Peak memory 205936 kb
Host smart-cb0dacd7-18c6-4f6c-9194-13ea32a0c255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197364711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3197364711
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.258839851
Short name T331
Test name
Test status
Simulation time 52984741 ps
CPU time 3.7 seconds
Started May 19 01:49:56 PM PDT 24
Finished May 19 01:50:01 PM PDT 24
Peak memory 215284 kb
Host smart-1f4d9752-9b0f-4d5d-bb37-3a47d80769ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258839851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.258839851
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3986500642
Short name T451
Test name
Test status
Simulation time 138590628 ps
CPU time 4.05 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:10 PM PDT 24
Peak memory 210436 kb
Host smart-d6ab7062-5392-4dc7-b846-d9219129724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986500642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3986500642
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1946032305
Short name T367
Test name
Test status
Simulation time 96940658 ps
CPU time 3.16 seconds
Started May 19 01:49:46 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 221744 kb
Host smart-da441e87-8768-4b4c-8037-f3c4b547cdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946032305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1946032305
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3157547920
Short name T369
Test name
Test status
Simulation time 115091478 ps
CPU time 3.32 seconds
Started May 19 01:50:04 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 222372 kb
Host smart-a384047b-09f9-49be-986a-11ca5cce32e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157547920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3157547920
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2539167249
Short name T884
Test name
Test status
Simulation time 295148965 ps
CPU time 5.76 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:49:59 PM PDT 24
Peak memory 214372 kb
Host smart-c0d454a8-1d26-470c-933e-67b60227d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539167249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2539167249
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.167471066
Short name T780
Test name
Test status
Simulation time 117018184 ps
CPU time 3.72 seconds
Started May 19 01:50:10 PM PDT 24
Finished May 19 01:50:14 PM PDT 24
Peak memory 207368 kb
Host smart-8023deeb-d515-4319-9703-50f4f19647f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167471066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.167471066
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3830741317
Short name T546
Test name
Test status
Simulation time 194755361 ps
CPU time 2.9 seconds
Started May 19 01:50:06 PM PDT 24
Finished May 19 01:50:10 PM PDT 24
Peak memory 206804 kb
Host smart-2964e5ba-d343-48a7-a49d-f523042ac8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830741317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3830741317
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.491286670
Short name T682
Test name
Test status
Simulation time 52155883 ps
CPU time 2.59 seconds
Started May 19 01:50:04 PM PDT 24
Finished May 19 01:50:07 PM PDT 24
Peak memory 206984 kb
Host smart-5860e2b7-76d9-4827-b18f-3f989475e723
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491286670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.491286670
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.642476422
Short name T750
Test name
Test status
Simulation time 304497458 ps
CPU time 2.41 seconds
Started May 19 01:49:44 PM PDT 24
Finished May 19 01:49:48 PM PDT 24
Peak memory 206860 kb
Host smart-19a3f3b9-7bad-4798-ab83-1bd516ce3fa9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642476422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.642476422
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2108937859
Short name T545
Test name
Test status
Simulation time 307037130 ps
CPU time 5.01 seconds
Started May 19 01:49:54 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 209004 kb
Host smart-9b33ff74-40f7-43d9-a243-c94ae0cf3588
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108937859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2108937859
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1435038566
Short name T612
Test name
Test status
Simulation time 1275302423 ps
CPU time 21.03 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 208848 kb
Host smart-6bc5e248-20f0-41ee-8dec-739f46e2f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435038566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1435038566
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1567352321
Short name T892
Test name
Test status
Simulation time 5714692308 ps
CPU time 45.77 seconds
Started May 19 01:49:42 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 208712 kb
Host smart-74ec40b8-4510-43ef-9d6b-d2fcc393c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567352321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1567352321
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3302813680
Short name T185
Test name
Test status
Simulation time 873366239 ps
CPU time 17.82 seconds
Started May 19 01:49:53 PM PDT 24
Finished May 19 01:50:12 PM PDT 24
Peak memory 222740 kb
Host smart-f860239c-b137-4201-ae7f-04cac3b03c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302813680 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3302813680
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3274184235
Short name T390
Test name
Test status
Simulation time 267191125 ps
CPU time 3.94 seconds
Started May 19 01:50:04 PM PDT 24
Finished May 19 01:50:08 PM PDT 24
Peak memory 208136 kb
Host smart-c63c788e-d63a-45dc-a7f9-c844a56d1d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274184235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3274184235
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1959161011
Short name T649
Test name
Test status
Simulation time 45046187 ps
CPU time 1.33 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 209424 kb
Host smart-e0992ac2-f526-4c17-be8e-10206f53eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959161011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1959161011
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.626876767
Short name T421
Test name
Test status
Simulation time 92817083 ps
CPU time 0.75 seconds
Started May 19 01:49:54 PM PDT 24
Finished May 19 01:49:56 PM PDT 24
Peak memory 205980 kb
Host smart-6e1e4fca-4ba3-484d-951e-6967030329ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626876767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.626876767
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.603843762
Short name T325
Test name
Test status
Simulation time 220036288 ps
CPU time 4.03 seconds
Started May 19 01:49:49 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 214348 kb
Host smart-bf766b91-4b1b-4493-a06c-62840b35e6ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603843762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.603843762
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.504140825
Short name T568
Test name
Test status
Simulation time 85313185 ps
CPU time 2.2 seconds
Started May 19 01:50:06 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 214332 kb
Host smart-295a1743-6ce7-4906-b97e-08a12b218a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504140825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.504140825
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3280253114
Short name T893
Test name
Test status
Simulation time 167948703 ps
CPU time 3.71 seconds
Started May 19 01:49:50 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 214344 kb
Host smart-550e4137-7ca1-40fd-a84a-4ee86cec291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280253114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3280253114
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.723972434
Short name T651
Test name
Test status
Simulation time 41657555 ps
CPU time 2.67 seconds
Started May 19 01:50:09 PM PDT 24
Finished May 19 01:50:12 PM PDT 24
Peak memory 211216 kb
Host smart-74db5b03-3a85-4d02-8a7d-2b8381d52621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723972434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.723972434
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3928367070
Short name T217
Test name
Test status
Simulation time 116019823 ps
CPU time 3.28 seconds
Started May 19 01:49:55 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 214268 kb
Host smart-12996b0b-101a-4916-988c-ed87f75be3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928367070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3928367070
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2645910580
Short name T854
Test name
Test status
Simulation time 5623830093 ps
CPU time 40.17 seconds
Started May 19 01:49:48 PM PDT 24
Finished May 19 01:50:29 PM PDT 24
Peak memory 209964 kb
Host smart-c81c3863-8129-4199-b9e3-900ac91e4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645910580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2645910580
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3032625468
Short name T598
Test name
Test status
Simulation time 22366249 ps
CPU time 1.96 seconds
Started May 19 01:49:46 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 207012 kb
Host smart-45fe8a5d-4de3-43d5-beae-81edb463959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032625468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3032625468
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4181606950
Short name T772
Test name
Test status
Simulation time 205051543 ps
CPU time 7.07 seconds
Started May 19 01:49:52 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 208704 kb
Host smart-200ca06f-d622-4e91-8ad5-04b87e921b76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181606950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4181606950
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4008120108
Short name T447
Test name
Test status
Simulation time 34806363 ps
CPU time 2.45 seconds
Started May 19 01:49:54 PM PDT 24
Finished May 19 01:49:57 PM PDT 24
Peak memory 206796 kb
Host smart-899cadc7-5658-4d6b-a302-2c88fd078b8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008120108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4008120108
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2209269633
Short name T745
Test name
Test status
Simulation time 146954036 ps
CPU time 4.57 seconds
Started May 19 01:49:47 PM PDT 24
Finished May 19 01:49:52 PM PDT 24
Peak memory 208616 kb
Host smart-51db7c22-726f-42a1-bb51-0a20c96d8def
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209269633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2209269633
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1339568352
Short name T898
Test name
Test status
Simulation time 130453724 ps
CPU time 3.11 seconds
Started May 19 01:49:54 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 214316 kb
Host smart-b3428102-3243-4b9e-9d22-b23267a1aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339568352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1339568352
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1428299830
Short name T463
Test name
Test status
Simulation time 152648987 ps
CPU time 3.34 seconds
Started May 19 01:49:45 PM PDT 24
Finished May 19 01:49:50 PM PDT 24
Peak memory 208804 kb
Host smart-6f20d4c8-e643-482e-ac0d-20ef9b78962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428299830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1428299830
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.551634002
Short name T529
Test name
Test status
Simulation time 65492882 ps
CPU time 3.92 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 210260 kb
Host smart-9f449592-745e-4c2e-a00a-fea8e4921e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551634002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.551634002
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.599586251
Short name T359
Test name
Test status
Simulation time 474386864 ps
CPU time 6.01 seconds
Started May 19 01:49:58 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 209344 kb
Host smart-da9bfd05-0ecc-48f3-823f-5f50950d75bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599586251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.599586251
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1816736354
Short name T461
Test name
Test status
Simulation time 564228692 ps
CPU time 5.46 seconds
Started May 19 01:50:06 PM PDT 24
Finished May 19 01:50:12 PM PDT 24
Peak memory 210640 kb
Host smart-6c82b050-1980-4be2-914c-f056f025812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816736354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1816736354
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2064085596
Short name T459
Test name
Test status
Simulation time 20710153 ps
CPU time 0.95 seconds
Started May 19 01:50:01 PM PDT 24
Finished May 19 01:50:03 PM PDT 24
Peak memory 206136 kb
Host smart-618dce2c-090d-4ebd-a4ff-89c8da4955c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064085596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2064085596
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1900130075
Short name T244
Test name
Test status
Simulation time 450870774 ps
CPU time 4.72 seconds
Started May 19 01:50:07 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 215928 kb
Host smart-53986f69-edf9-4b03-8fd6-798d78159c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900130075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1900130075
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1179905361
Short name T825
Test name
Test status
Simulation time 68242328 ps
CPU time 1.87 seconds
Started May 19 01:50:02 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 207800 kb
Host smart-e1e52f11-faaa-4a64-943a-347ff25d91b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179905361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1179905361
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2263765634
Short name T658
Test name
Test status
Simulation time 104008856 ps
CPU time 1.79 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:08 PM PDT 24
Peak memory 207940 kb
Host smart-785d03e1-ed08-4ab0-82bc-1d5a610d9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263765634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2263765634
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1191475152
Short name T103
Test name
Test status
Simulation time 807868537 ps
CPU time 5.77 seconds
Started May 19 01:50:07 PM PDT 24
Finished May 19 01:50:13 PM PDT 24
Peak memory 214344 kb
Host smart-c8d48a85-122c-4a00-8f03-e9c15c3de7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191475152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1191475152
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.938829210
Short name T773
Test name
Test status
Simulation time 439186648 ps
CPU time 7.39 seconds
Started May 19 01:49:50 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 222648 kb
Host smart-4288286d-bca7-4728-8213-96f75f2e45ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938829210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.938829210
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3892057528
Short name T53
Test name
Test status
Simulation time 302766561 ps
CPU time 3.58 seconds
Started May 19 01:50:15 PM PDT 24
Finished May 19 01:50:22 PM PDT 24
Peak memory 220384 kb
Host smart-74c4a24a-04b2-4b25-b452-0253665a81e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892057528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3892057528
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.201070254
Short name T503
Test name
Test status
Simulation time 4400454020 ps
CPU time 29.12 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 214464 kb
Host smart-464be568-fa5b-46c9-a05a-b6a85be68e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201070254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.201070254
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3402736072
Short name T471
Test name
Test status
Simulation time 463973634 ps
CPU time 3.25 seconds
Started May 19 01:50:02 PM PDT 24
Finished May 19 01:50:05 PM PDT 24
Peak memory 208568 kb
Host smart-652c2779-83af-41cc-8b44-9823c7c3a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402736072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3402736072
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1115253584
Short name T345
Test name
Test status
Simulation time 5960380630 ps
CPU time 42.62 seconds
Started May 19 01:50:07 PM PDT 24
Finished May 19 01:50:50 PM PDT 24
Peak memory 209180 kb
Host smart-516eeadf-b0f1-41c7-b1bd-14f6fdcf8593
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115253584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1115253584
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2831288998
Short name T474
Test name
Test status
Simulation time 211402175 ps
CPU time 7.32 seconds
Started May 19 01:50:05 PM PDT 24
Finished May 19 01:50:14 PM PDT 24
Peak memory 208428 kb
Host smart-1898590d-3763-43ad-be70-81d886ac064e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831288998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2831288998
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1387286842
Short name T635
Test name
Test status
Simulation time 55846236 ps
CPU time 1.77 seconds
Started May 19 01:50:24 PM PDT 24
Finished May 19 01:50:27 PM PDT 24
Peak memory 207084 kb
Host smart-ef9146f4-889e-4736-90b1-8e2899564a86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387286842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1387286842
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3776872884
Short name T734
Test name
Test status
Simulation time 84471788 ps
CPU time 2.41 seconds
Started May 19 01:49:57 PM PDT 24
Finished May 19 01:50:00 PM PDT 24
Peak memory 207816 kb
Host smart-320c4a33-13e1-4b42-b4c5-3c6f315e47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776872884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3776872884
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2181128170
Short name T434
Test name
Test status
Simulation time 195997238 ps
CPU time 4.41 seconds
Started May 19 01:50:07 PM PDT 24
Finished May 19 01:50:12 PM PDT 24
Peak memory 206900 kb
Host smart-3c52d980-58c5-4268-b188-b699fe57219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181128170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2181128170
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3097536568
Short name T614
Test name
Test status
Simulation time 60021024 ps
CPU time 0.93 seconds
Started May 19 01:49:55 PM PDT 24
Finished May 19 01:49:57 PM PDT 24
Peak memory 206132 kb
Host smart-fcfd9c1f-6228-4744-89f1-421a65a60360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097536568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3097536568
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4250146576
Short name T537
Test name
Test status
Simulation time 376595679 ps
CPU time 8.45 seconds
Started May 19 01:49:59 PM PDT 24
Finished May 19 01:50:09 PM PDT 24
Peak memory 207952 kb
Host smart-ee9e2e7f-bad6-470e-b966-72a5bfd5ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250146576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4250146576
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1435148038
Short name T377
Test name
Test status
Simulation time 65467914 ps
CPU time 2.17 seconds
Started May 19 01:50:11 PM PDT 24
Finished May 19 01:50:14 PM PDT 24
Peak memory 210184 kb
Host smart-510e365e-8717-4b00-a59d-81098e284b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435148038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1435148038
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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