Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
53569 |
1 |
|
|
T1 |
57 |
|
T2 |
21 |
|
T3 |
63 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31452 |
1 |
|
|
T1 |
57 |
|
T3 |
8 |
|
T12 |
57 |
auto[1] |
22117 |
1 |
|
|
T2 |
21 |
|
T3 |
55 |
|
T13 |
49 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26263 |
1 |
|
|
T1 |
29 |
|
T2 |
11 |
|
T3 |
32 |
auto[1] |
27306 |
1 |
|
|
T1 |
28 |
|
T2 |
10 |
|
T3 |
31 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
15459 |
1 |
|
|
T1 |
29 |
|
T3 |
4 |
|
T12 |
29 |
all_values[0] |
auto[0] |
auto[1] |
15993 |
1 |
|
|
T1 |
28 |
|
T3 |
4 |
|
T12 |
28 |
all_values[0] |
auto[1] |
auto[0] |
10804 |
1 |
|
|
T2 |
11 |
|
T3 |
28 |
|
T13 |
25 |
all_values[0] |
auto[1] |
auto[1] |
11313 |
1 |
|
|
T2 |
10 |
|
T3 |
27 |
|
T13 |
24 |