Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.79	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	77	253	76.67

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	58	222	79.29	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4539

1

T2

1

T3

2

T12

4

auto[1]

513

1

T1

3

T109

1

T86

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4539

1

T2

1

T3

2

T12

4

auto[1]

513

1

T1

3

T109

1

T86

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4543

1

T1

1

T2

1

T3

2

auto[1]

509

1

T1

2

T12

1

T15

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4543

1

T1

1

T2

1

T3

2

auto[1]

509

1

T1

2

T12

1

T15

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T46	1		T123	5		T47	4
auto[OpGenId]	1066	1			T2	1		T12	2		T13	1
auto[OpGenSwOut]	1015	1			T1	2		T3	1		T18	1
auto[OpGenHwOut]	2484	1			T1	1		T3	1		T12	2
auto[OpDisable]	84	1			T47	2		T50	1		T55	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T46	1		T123	5		T47	4
auto[OpGenId]	1066	1			T2	1		T12	2		T13	1
auto[OpGenSwOut]	1015	1			T1	2		T3	1		T18	1
auto[OpGenHwOut]	2484	1			T1	1		T3	1		T12	2
auto[OpDisable]	84	1			T47	2		T50	1		T55	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4494

1

T1

1

T2

1

T3

2

auto[1]

558

1

T1

2

T12

2

T84

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4494

1

T1

1

T2

1

T3

2

auto[1]

558

1

T1

2

T12

2

T84

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4755

1

T1

3

T2

1

T3

2

auto[1]

297

1

T123

6

T80

6

T124

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1750	1			T1	1		T2	1		T3	1
auto[1]	663	1			T12	1		T84	1		T85	1
auto[2]	665	1			T1	1		T3	1		T12	2
auto[3]	638	1			T1	1		T15	1		T85	2
auto[4]	332	1			T47	2		T79	1		T50	1
auto[5]	348	1			T15	2		T85	1		T86	2
auto[6]	332	1			T85	1		T86	2		T49	1
auto[7]	324	1			T47	4		T79	2		T83	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1336	1			T15	2		T85	2		T86	4
clear_one[1]	663	1			T12	1		T84	1		T85	1
clear_one[2]	665	1			T1	1		T3	1		T12	2
clear_one[3]	638	1			T1	1		T15	1		T85	2
clear_none	1750	1			T1	1		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	924	1			T3	2		T13	2		T17	1
auto[StInit]	595	1			T2	1		T12	1		T15	1
auto[StCreatorRootKey]	551	1			T12	1		T15	1		T84	1
auto[StOwnerIntKey]	506	1			T15	1		T18	1		T109	1
auto[StOwnerKey]	450	1			T1	1		T15	1		T85	1
auto[StDisabled]	1761	1			T1	2		T12	2		T15	4
auto[StInvalid]	265	1			T35	6		T36	4		T34	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	924	1			T3	2		T13	2		T17	1
auto[StInit]	595	1			T2	1		T12	1		T15	1
auto[StCreatorRootKey]	551	1			T12	1		T15	1		T84	1
auto[StOwnerIntKey]	506	1			T15	1		T18	1		T109	1
auto[StOwnerKey]	450	1			T1	1		T15	1		T85	1
auto[StDisabled]	1761	1			T1	2		T12	2		T15	4
auto[StInvalid]	265	1			T35	6		T36	4		T34	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	58	222	79.29	58

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T240	1		T241	1		T242	1
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T13	1		T17	1		T18	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	136	1			T3	1		T47	2		T23	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	242	1			T13	1		T86	1		T47	1
auto[0]	auto[StInit]	auto[OpAdvance]	45	1			T123	1		T47	1		T23	1
auto[0]	auto[StInit]	auto[OpGenId]	81	1			T2	1		T47	1		T207	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	80	1			T65	1		T57	1		T140	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	169	1			T12	1		T15	1		T85	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T46	1		T123	3		T243	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	45	1			T47	1		T24	1		T71	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T84	1		T47	1		T65	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	79	1			T15	1		T79	1		T80	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T217	1		T25	1		T244	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	36	1			T47	1		T50	1		T245	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	34	1			T123	1		T47	1		T24	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T109	1		T65	1		T57	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T123	1		T47	1		T65	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T69	1		T246	1		T76	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T1	1		T115	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T82	1		T55	1		T66	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	35	1			T48	1		T145	5		T243	1
auto[0]	auto[StDisabled]	auto[OpGenId]	68	1			T47	1		T207	1		T118	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T123	2		T65	1		T137	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T85	1		T123	1		T50	1
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T47	1		T57	1		T48	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T36	1		T248	1		T249	1
auto[0]	auto[StInvalid]	auto[OpGenId]	19	1			T35	1		T91	1		T250	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	22	1			T51	1		T105	2		T93	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	27	1			T34	1		T105	1		T110	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T57	1		T63	1		T251	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T252	1		T199	1		T20	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T63	2		T194	1		T253	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T211	1		T254	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T55	1		T101	2		T255	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T57	1		T256	1		T257	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T47	1		T50	1		T83	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T258	2		T213	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T65	1		T213	1		T260	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T261	1		T53	1		T255	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T47	1		T55	1		T262	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T263	1		T132	1		T264	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T265	1		T266	1		T267	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T132	1		T211	1		T213	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T55	1		T124	2		T261	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T47	1		T80	1		T260	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	7	1			T69	1		T53	2		T241	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T144	1		T71	2		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T79	1		T262	1		T269	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	21	1			T55	1		T256	1		T69	1
auto[1]	auto[StDisabled]	auto[OpGenId]	62	1			T84	1		T55	1		T57	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T47	1		T207	1		T57	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T12	1		T85	1		T79	3
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T70	1		T69	1		T257	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T92	1		T270	1		T271	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T35	2		T51	1		T113	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T110	1		T91	1		T272	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T92	1		T273	1		T274	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T63	1		T257	1		T102	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T55	1		T63	2		T69	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	42	1			T3	1		T86	1		T79	2
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T275	1		T276	1		T277	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T47	1		T252	1		T278	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T111	1		T275	1		T279	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	19	1			T280	1		T281	1		T94	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T76	1		T282	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T12	1		T140	1		T145	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T57	1		T63	1		T64	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T49	1		T283	1		T145	3
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T47	1		T124	1		T211	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T80	2		T65	1		T100	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T18	1		T80	1		T145	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T15	1		T85	1		T47	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T124	1		T261	1		T69	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T24	1		T65	2		T200	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T209	1		T284	1		T264	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T86	1		T124	1		T57	2
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T124	1		T143	1		T285	1
auto[2]	auto[StDisabled]	auto[OpGenId]	52	1			T12	1		T80	1		T55	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T80	2		T55	1		T135	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T1	1		T15	2		T82	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T57	1		T284	1		T260	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T35	1		T286	1		T287	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T35	1		T92	1		T288	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T289	1		T290	1		T274	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T113	2		T291	1		T292	1
auto[3]	auto[StReset]	auto[OpGenId]	25	1			T50	1		T55	1		T57	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	12	1			T48	1		T293	1		T194	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	44	1			T79	1		T83	1		T55	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T20	1		T294	1		T94	1
auto[3]	auto[StInit]	auto[OpGenId]	7	1			T57	1		T53	1		T295	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T69	1		T102	1		T296	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T63	1		T297	1		T64	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T143	1		T71	1		T25	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T81	1		T69	1		T71	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T55	1		T63	1		T103	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T85	1		T82	1		T83	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T63	1		T243	1		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T293	1		T63	1		T69	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T47	1		T64	1		T299	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T86	1		T48	1		T135	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T55	1		T245	1		T300	3
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T143	3		T32	1		T301	2
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T23	1		T65	1		T251	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T83	1		T302	1		T303	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	26	1			T65	1		T209	1		T132	1
auto[3]	auto[StDisabled]	auto[OpGenId]	43	1			T60	1		T138	1		T252	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T1	1		T63	2		T69	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	142	1			T15	1		T85	1		T86	2
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T47	1		T66	1		T136	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T93	1		T273	1		T304	1
auto[3]	auto[StInvalid]	auto[OpGenId]	8	1			T36	1		T305	1		T306	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T105	2		T307	1		T308	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T36	1		T90	1		T309	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T293	1		T63	1		T291	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T53	1		T264	1		T310	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	12	1			T50	1		T297	1		T311	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T312	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T313	1		T314	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T251	1		T222	1		T315	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	18	1			T112	1		T316	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T278	1		T318	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T55	1		T48	1		T71	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T320	1		T132	1		T95	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T321	1		T112	1		T322	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T258	1		T255	1		T323	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T72	1		T198	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T209	1		T200	1		T213	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T60	1		T285	1		T199	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T71	1		T325	1		T197	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	14	1			T138	1		T199	1		T201	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T64	1		T39	1		T258	2
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T47	1		T326	1		T327	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T63	1		T64	2		T328	1
auto[4]	auto[StDisabled]	auto[OpGenId]	18	1			T55	1		T243	1		T104	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T57	1		T137	1		T210	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T47	1		T79	1		T326	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T329	1		T264	1		T330	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T331	1		T332	1		T333	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T110	1		T290	1		T288	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T35	1		T36	1		T304	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T334	1		T335	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T47	1		T93	1		T115	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T65	1		T63	1		T92	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	14	1			T139	1		T297	1		T253	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T336	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T243	1		T32	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	11	1			T285	1		T94	1		T337	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T86	1		T114	1		T115	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T338	2		T339	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T57	1		T70	1		T69	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T213	1		T340	1		T222	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T207	1		T131	2		T69	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T68	1		T132	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T57	1		T131	1		T247	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T260	1		T341	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T83	1		T139	1		T342	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T343	1		T195	1		T344	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	3	1			T135	1		T345	1		T99	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T131	1		T346	2		T347	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T15	1		T85	1		T283	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	6	1			T142	1		T241	1		T348	1
auto[5]	auto[StDisabled]	auto[OpGenId]	38	1			T57	1		T209	1		T69	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T48	1		T256	1		T131	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T15	1		T86	1		T82	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T50	1		T55	1		T183	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T93	1		T92	1		T304	1
auto[5]	auto[StInvalid]	auto[OpGenId]	9	1			T110	1		T289	1		T335	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T349	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T105	1		T91	1		T272	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T57	1		T350	1		T351	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T132	1		T30	1		T53	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T49	1		T55	1		T92	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T64	1		T352	1		T300	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T55	1		T131	1		T264	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	6	1			T328	1		T353	1		T354	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T256	1		T355	1		T356	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T53	1		T357	1		T358	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T55	1		T75	1		T359	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T86	1		T139	1		T342	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T360	2		T361	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T211	1		T362	1		T363	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T23	1		T364	1		T365	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T269	1		T366	1		T253	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T193	1		T53	1		T211	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T68	1		T71	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T63	1		T368	1		T369	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T342	1		T370	1		T63	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T57	1		T213	1		T371	1
auto[6]	auto[StDisabled]	auto[OpGenId]	19	1			T55	1		T71	1		T194	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T55	1		T63	1		T115	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T85	1		T86	1		T82	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T115	1		T73	1		T76	1
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T273	1		T250	1		T334	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T93	1		T349	1		T372	2
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T90	1		T113	1		T373	1
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T23	1		T134	1		T94	2
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T47	1		T115	1		T364	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T55	1		T352	1		T278	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T374	1		T116	2		T101	1
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T367	1		T87	1		T375	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T134	1		T115	1		T376	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T79	1		T143	3		T212	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T57	1		T134	1		T143	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T118	1		T63	1		T377	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T194	1		T378	1		T230	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T370	1		T200	1		T115	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T47	1		T64	1		T115	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T264	1		T379	1		T380	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T79	1		T370	1		T381	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T142	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T71	1		T382	1		T338	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T383	1		T228	1		T384	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T47	1		T297	1		T381	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T69	1		T213	1		T260	1
auto[7]	auto[StDisabled]	auto[OpGenId]	21	1			T385	1		T261	1		T64	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T47	1		T69	1		T383	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T83	1		T134	1		T139	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T63	1		T182	1		T77	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T270	1		T308	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T289	1		T307	2		T304	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T34	1		T105	1		T250	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T272	1		T291	1		T335	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1336

1

T15

2

T85

2

T86

4

clear_one[1]

auto[0]

auto[0]

auto[0]

393

1

T47

4

T80

3

T50

1

clear_one[1]

auto[0]

auto[0]

auto[1]

126

1

T79

4

T55

2

T57

1

clear_one[1]

auto[0]

auto[1]

auto[0]

115

1

T85

1

T55

1

T124

1

clear_one[1]

auto[0]

auto[1]

auto[1]

29

1

T12

1

T84

1

T57

1

clear_one[2]

auto[0]

auto[0]

auto[0]

406

1

T3

1

T12

1

T15

3

clear_one[2]

auto[0]

auto[0]

auto[1]

128

1

T12

1

T80

1

T82

2

clear_one[2]

auto[1]

auto[0]

auto[0]

96

1

T86

1

T47

1

T49

1

clear_one[2]

auto[1]

auto[0]

auto[1]

35

1

T1

1

T65

1

T57

1

clear_one[3]

auto[0]

auto[0]

auto[0]

365

1

T47

1

T79

1

T50

1

clear_one[3]

auto[0]

auto[1]

auto[0]

118

1

T15

1

T85

2

T65

1

clear_one[3]

auto[1]

auto[0]

auto[0]

126

1

T86

3

T83

2

T65

1

clear_one[3]

auto[1]

auto[1]

auto[0]

29

1

T1

1

T47

1

T66

1

clear_none

auto[0]

auto[0]

auto[0]

1227

1

T2

1

T3

1

T12

1

clear_none

auto[0]

auto[0]

auto[1]

138

1

T79

1

T82

2

T65

1

clear_none

auto[0]

auto[1]

auto[0]

130

1

T15

1

T85

1

T123

5

clear_none

auto[0]

auto[1]

auto[1]

28

1

T55

1

T140

1

T118

1

clear_none

auto[1]

auto[0]

auto[0]

125

1

T47

1

T50

2

T83

1

clear_none

auto[1]

auto[0]

auto[1]

42

1

T109

1

T47

1

T65

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T66

1

T24

1

T137

1

clear_none

auto[1]

auto[1]

auto[1]

32

1

T1

1

T47

1

T145

7

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1251	1			T15	2		T85	2		T86	4
clear_all	auto[1]	85	1			T143	3		T258	2		T116	2
clear_one[1]	auto[0]	631	1			T12	1		T84	1		T85	1
clear_one[1]	auto[1]	32	1			T80	2		T124	1		T143	1
clear_one[2]	auto[0]	621	1			T1	1		T3	1		T12	2
clear_one[2]	auto[1]	44	1			T80	4		T124	2		T143	1
clear_one[3]	auto[0]	597	1			T1	1		T15	1		T85	2
clear_one[3]	auto[1]	41	1			T143	3		T294	1		T346	2
clear_none	auto[0]	1655	1			T1	1		T2	1		T3	1
clear_none	auto[1]	95	1			T123	6		T144	3		T145	5