Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10409

1

T1

10

T2

5

T3

14

auto[Attestation]

7252

1

T1

10

T2

3

T3

9

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2685	1			T1	2		T2	1		T3	3
auto[Aes]	3105	1			T1	6		T2	1		T3	6
auto[Kmac]	3230	1			T1	5		T2	2		T3	2
auto[Otbn]	3210	1			T1	5		T3	2		T12	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7208	1			T1	8		T2	2		T3	8
auto[OpGenId]	5431	1			T1	2		T2	4		T3	10
auto[OpGenSwOut]	5626	1			T1	6		T3	6		T12	8
auto[OpGenHwOut]	6604	1			T1	12		T2	4		T3	7
auto[OpDisable]	151	1			T47	2		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10241

1

T1

10

T2

8

T3

14

auto[OpDoneFail]

14779

1

T1

18

T2

2

T3

17

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5916	1			T1	1		T2	1		T3	5
auto[StInit]	3561	1			T1	5		T2	3		T3	2
auto[StCreatorRootKey]	3074	1			T1	2		T2	6		T3	4
auto[StOwnerIntKey]	2721	1			T1	2		T3	6		T12	4
auto[StOwnerKey]	2354	1			T1	4		T3	4		T12	2
auto[StDisabled]	7394	1			T1	14		T3	10		T12	15

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	293	1			T13	1		T16	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T109	1		T47	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T13	1		T47	3		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T84	1		T109	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T3	1		T12	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	225	1			T16	1		T47	6		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	288	1			T3	1		T13	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T47	1		T49	1		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T109	1		T50	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T18	1		T47	2		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	50	1			T14	1		T47	2		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	189	1			T1	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	359	1			T13	2		T14	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	94	1			T16	1		T46	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T18	1		T123	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T12	1		T123	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	207	1			T1	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	309	1			T14	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	88	1			T46	1		T47	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T84	1		T123	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T3	1		T13	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	51	1			T1	1		T18	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	222	1			T18	2		T47	2		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	69	1			T47	3		T57	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T46	1		T47	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T12	1		T18	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T16	1		T207	1		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T80	1		T65	2		T136	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	207	1			T12	1		T18	1		T47	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T55	2		T48	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T1	1		T33	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T47	2		T37	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	62	1			T80	1		T55	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T123	1		T47	2		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	222	1			T3	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T47	1		T55	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	101	1			T14	1		T84	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T18	1		T123	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T14	1		T109	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	49	1			T47	1		T57	1		T134	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	211	1			T3	1		T14	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T47	2		T55	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T47	1		T208	1		T57	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T60	1		T65	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T12	1		T123	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	70	1			T13	1		T123	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	191	1			T1	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	266	1			T13	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T12	1		T47	2		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T47	1		T140	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T47	2		T24	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T81	1		T65	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	179	1			T1	2		T3	1		T123	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	365	1			T3	1		T86	5		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T49	1		T23	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T2	1		T3	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T109	2		T86	1		T47	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T13	1		T86	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	244	1			T18	1		T86	3		T47	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	422	1			T13	1		T47	2		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	97	1			T1	1		T85	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T15	1		T47	2		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	100	1			T13	2		T15	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	261	1			T1	1		T12	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	422	1			T18	1		T47	1		T79	14
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T55	1		T143	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T82	1		T55	2		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T3	1		T12	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T81	1		T82	1		T55	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	240	1			T18	1		T84	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	43	1			T47	1		T55	3		T63	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	93	1			T3	1		T46	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T2	1		T123	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T47	2		T24	1		T124	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T24	1		T124	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T18	1		T84	1		T123	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T47	1		T55	2		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	108	1			T1	1		T86	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T3	1		T86	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T1	1		T109	2		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T80	1		T24	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	274	1			T1	2		T3	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T47	3		T55	3		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T15	1		T109	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T2	1		T47	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T13	1		T109	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	77	1			T13	4		T47	3		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	255	1			T15	2		T85	4		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T55	1		T57	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	120	1			T17	1		T47	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T79	1		T48	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	109	1			T109	1		T33	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T1	1		T47	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	272	1			T1	2		T47	1		T79	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	194	1			T3	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	641	1			T13	1		T16	3		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	191	1			T14	1		T18	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	593	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T1	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	674	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T1	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	635	1			T14	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	192	1			T16	1		T18	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	402	1			T12	2		T18	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	197	1			T123	1		T47	4		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	392	1			T1	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	180	1			T14	1		T18	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	385	1			T3	1		T14	2		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	211	1			T12	1		T13	1		T123	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	363	1			T1	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	192	1			T47	2		T81	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	562	1			T1	2		T3	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	284	1			T2	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	729	1			T3	1		T18	1		T86	8
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T1	1		T2	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	799	1			T1	2		T12	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T12	1		T109	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	779	1			T3	1		T18	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T2	1		T123	1		T47	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	328	1			T3	1		T18	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T1	1		T3	1		T109	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	446	1			T1	3		T3	1		T86	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T2	1		T13	5		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	452	1			T15	3		T109	1		T85	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	308	1			T1	1		T109	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	469	1			T1	2		T17	1		T47	2