Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30847

1

T1

31

T2

11

T3

37

auto[1]

285

1

T123

8

T80

3

T124

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30858	1			T1	31		T2	11		T3	37
auto[134217728:268435455]	11	1			T144	1		T258	1		T240	1
auto[268435456:402653183]	8	1			T123	1		T258	1		T301	1
auto[402653184:536870911]	7	1			T258	1		T259	2		T244	1
auto[536870912:671088639]	12	1			T80	1		T145	3		T410	1
auto[671088640:805306367]	8	1			T123	1		T400	1		T244	1
auto[805306368:939524095]	7	1			T123	1		T244	1		T411	2
auto[939524096:1073741823]	10	1			T80	1		T145	2		T301	1
auto[1073741824:1207959551]	18	1			T123	1		T371	1		T301	1
auto[1207959552:1342177279]	9	1			T383	1		T116	1		T371	1
auto[1342177280:1476395007]	3	1			T412	1		T413	1		T414	1
auto[1476395008:1610612735]	12	1			T145	2		T346	1		T415	2
auto[1610612736:1744830463]	14	1			T144	1		T383	1		T258	1
auto[1744830464:1879048191]	10	1			T145	1		T294	1		T325	2
auto[1879048192:2013265919]	10	1			T123	1		T144	1		T346	1
auto[2013265920:2147483647]	5	1			T123	1		T346	1		T399	1
auto[2147483648:2281701375]	9	1			T371	1		T242	1		T338	1
auto[2281701376:2415919103]	14	1			T143	3		T258	1		T294	1
auto[2415919104:2550136831]	4	1			T123	1		T383	1		T275	1
auto[2550136832:2684354559]	9	1			T144	1		T383	1		T371	1
auto[2684354560:2818572287]	6	1			T144	1		T294	1		T240	1
auto[2818572288:2952790015]	6	1			T143	1		T415	1		T338	1
auto[2952790016:3087007743]	7	1			T360	1		T411	2		T339	1
auto[3087007744:3221225471]	11	1			T294	1		T371	1		T278	1
auto[3221225472:3355443199]	7	1			T383	1		T259	1		T325	1
auto[3355443200:3489660927]	10	1			T123	1		T124	1		T383	1
auto[3489660928:3623878655]	6	1			T144	1		T294	1		T399	1
auto[3623878656:3758096383]	8	1			T145	2		T294	1		T278	1
auto[3758096384:3892314111]	8	1			T294	1		T259	1		T241	1
auto[3892314112:4026531839]	10	1			T80	1		T144	1		T145	1
auto[4026531840:4160749567]	9	1			T124	1		T143	1		T300	1
auto[4160749568:4294967295]	6	1			T124	1		T371	1		T346	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30847	1			T1	31		T2	11		T3	37
auto[0:134217727]	auto[1]	11	1			T383	1		T371	1		T346	1
auto[134217728:268435455]	auto[1]	11	1			T144	1		T258	1		T240	1
auto[268435456:402653183]	auto[1]	8	1			T123	1		T258	1		T301	1
auto[402653184:536870911]	auto[1]	7	1			T258	1		T259	2		T244	1
auto[536870912:671088639]	auto[1]	12	1			T80	1		T145	3		T410	1
auto[671088640:805306367]	auto[1]	8	1			T123	1		T400	1		T244	1
auto[805306368:939524095]	auto[1]	7	1			T123	1		T244	1		T411	2
auto[939524096:1073741823]	auto[1]	10	1			T80	1		T145	2		T301	1
auto[1073741824:1207959551]	auto[1]	18	1			T123	1		T371	1		T301	1
auto[1207959552:1342177279]	auto[1]	9	1			T383	1		T116	1		T371	1
auto[1342177280:1476395007]	auto[1]	3	1			T412	1		T413	1		T414	1
auto[1476395008:1610612735]	auto[1]	12	1			T145	2		T346	1		T415	2
auto[1610612736:1744830463]	auto[1]	14	1			T144	1		T383	1		T258	1
auto[1744830464:1879048191]	auto[1]	10	1			T145	1		T294	1		T325	2
auto[1879048192:2013265919]	auto[1]	10	1			T123	1		T144	1		T346	1
auto[2013265920:2147483647]	auto[1]	5	1			T123	1		T346	1		T399	1
auto[2147483648:2281701375]	auto[1]	9	1			T371	1		T242	1		T338	1
auto[2281701376:2415919103]	auto[1]	14	1			T143	3		T258	1		T294	1
auto[2415919104:2550136831]	auto[1]	4	1			T123	1		T383	1		T275	1
auto[2550136832:2684354559]	auto[1]	9	1			T144	1		T383	1		T371	1
auto[2684354560:2818572287]	auto[1]	6	1			T144	1		T294	1		T240	1
auto[2818572288:2952790015]	auto[1]	6	1			T143	1		T415	1		T338	1
auto[2952790016:3087007743]	auto[1]	7	1			T360	1		T411	2		T339	1
auto[3087007744:3221225471]	auto[1]	11	1			T294	1		T371	1		T278	1
auto[3221225472:3355443199]	auto[1]	7	1			T383	1		T259	1		T325	1
auto[3355443200:3489660927]	auto[1]	10	1			T123	1		T124	1		T383	1
auto[3489660928:3623878655]	auto[1]	6	1			T144	1		T294	1		T399	1
auto[3623878656:3758096383]	auto[1]	8	1			T145	2		T294	1		T278	1
auto[3758096384:3892314111]	auto[1]	8	1			T294	1		T259	1		T241	1
auto[3892314112:4026531839]	auto[1]	10	1			T80	1		T144	1		T145	1
auto[4026531840:4160749567]	auto[1]	9	1			T124	1		T143	1		T300	1
auto[4160749568:4294967295]	auto[1]	6	1			T124	1		T371	1		T346	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T1

3

T3

2

T12

1

auto[1]

1655

1

T1

1

T2

2

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T13	1		T80	1		T50	1
auto[134217728:268435455]	107	1			T3	1		T47	1		T55	1
auto[268435456:402653183]	106	1			T47	1		T35	1		T124	2
auto[402653184:536870911]	101	1			T12	1		T46	1		T47	3
auto[536870912:671088639]	104	1			T18	1		T47	3		T55	1
auto[671088640:805306367]	104	1			T1	1		T12	1		T81	1
auto[805306368:939524095]	107	1			T17	1		T47	2		T55	1
auto[939524096:1073741823]	96	1			T47	2		T66	1		T65	1
auto[1073741824:1207959551]	110	1			T18	2		T46	1		T50	1
auto[1207959552:1342177279]	101	1			T123	1		T47	1		T50	1
auto[1342177280:1476395007]	103	1			T47	2		T66	1		T34	1
auto[1476395008:1610612735]	95	1			T13	1		T123	1		T66	1
auto[1610612736:1744830463]	107	1			T47	1		T55	2		T36	1
auto[1744830464:1879048191]	95	1			T47	1		T55	1		T65	1
auto[1879048192:2013265919]	105	1			T1	1		T2	1		T17	1
auto[2013265920:2147483647]	98	1			T13	1		T17	1		T47	1
auto[2147483648:2281701375]	86	1			T1	1		T3	1		T49	1
auto[2281701376:2415919103]	109	1			T17	1		T55	2		T66	1
auto[2415919104:2550136831]	97	1			T47	2		T55	1		T23	1
auto[2550136832:2684354559]	103	1			T47	1		T81	1		T63	3
auto[2684354560:2818572287]	94	1			T35	1		T55	1		T65	1
auto[2818572288:2952790015]	102	1			T109	1		T123	1		T59	1
auto[2952790016:3087007743]	86	1			T47	2		T36	1		T65	1
auto[3087007744:3221225471]	102	1			T12	1		T47	3		T55	3
auto[3221225472:3355443199]	107	1			T47	1		T55	1		T23	1
auto[3355443200:3489660927]	101	1			T47	1		T81	1		T55	1
auto[3489660928:3623878655]	98	1			T1	1		T2	1		T17	1
auto[3623878656:3758096383]	100	1			T47	2		T55	2		T36	2
auto[3758096384:3892314111]	92	1			T17	1		T81	1		T55	1
auto[3892314112:4026531839]	107	1			T3	2		T109	1		T47	4
auto[4026531840:4160749567]	89	1			T3	2		T123	1		T47	2
auto[4160749568:4294967295]	107	1			T13	1		T123	1		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	63	1			T13	1		T50	1		T55	3
auto[0:134217727]	auto[1]	54	1			T80	1		T55	1		T65	2
auto[134217728:268435455]	auto[0]	52	1			T3	1		T47	1		T105	1
auto[134217728:268435455]	auto[1]	55	1			T55	1		T24	1		T4	1
auto[268435456:402653183]	auto[0]	52	1			T63	1		T93	1		T92	1
auto[268435456:402653183]	auto[1]	54	1			T47	1		T35	1		T124	2
auto[402653184:536870911]	auto[0]	53	1			T46	1		T47	1		T23	2
auto[402653184:536870911]	auto[1]	48	1			T12	1		T47	2		T210	1
auto[536870912:671088639]	auto[0]	49	1			T47	1		T63	1		T91	1
auto[536870912:671088639]	auto[1]	55	1			T18	1		T47	2		T55	1
auto[671088640:805306367]	auto[0]	52	1			T1	1		T12	1		T81	1
auto[671088640:805306367]	auto[1]	52	1			T55	1		T118	1		T70	1
auto[805306368:939524095]	auto[0]	51	1			T47	2		T55	1		T23	1
auto[805306368:939524095]	auto[1]	56	1			T17	1		T124	1		T57	1
auto[939524096:1073741823]	auto[0]	42	1			T47	2		T8	1		T70	1
auto[939524096:1073741823]	auto[1]	54	1			T66	1		T65	1		T57	1
auto[1073741824:1207959551]	auto[0]	43	1			T18	1		T210	1		T245	1
auto[1073741824:1207959551]	auto[1]	67	1			T18	1		T46	1		T50	1
auto[1207959552:1342177279]	auto[0]	47	1			T123	1		T50	1		T55	1
auto[1207959552:1342177279]	auto[1]	54	1			T47	1		T55	1		T24	1
auto[1342177280:1476395007]	auto[0]	52	1			T47	2		T70	1		T383	1
auto[1342177280:1476395007]	auto[1]	51	1			T66	1		T34	1		T60	1
auto[1476395008:1610612735]	auto[0]	56	1			T66	1		T23	1		T4	1
auto[1476395008:1610612735]	auto[1]	39	1			T13	1		T123	1		T57	1
auto[1610612736:1744830463]	auto[0]	51	1			T36	1		T4	1		T60	1
auto[1610612736:1744830463]	auto[1]	56	1			T47	1		T55	2		T65	1
auto[1744830464:1879048191]	auto[0]	46	1			T63	1		T256	1		T131	1
auto[1744830464:1879048191]	auto[1]	49	1			T47	1		T55	1		T65	1
auto[1879048192:2013265919]	auto[0]	50	1			T17	1		T109	1		T47	1
auto[1879048192:2013265919]	auto[1]	55	1			T1	1		T2	1		T55	1
auto[2013265920:2147483647]	auto[0]	50	1			T13	1		T17	1		T47	1
auto[2013265920:2147483647]	auto[1]	48	1			T35	1		T65	1		T57	2
auto[2147483648:2281701375]	auto[0]	46	1			T1	1		T63	1		T243	1
auto[2147483648:2281701375]	auto[1]	40	1			T3	1		T49	1		T140	1
auto[2281701376:2415919103]	auto[0]	46	1			T17	1		T55	1		T48	1
auto[2281701376:2415919103]	auto[1]	63	1			T55	1		T66	1		T124	1
auto[2415919104:2550136831]	auto[0]	66	1			T47	2		T23	1		T63	1
auto[2415919104:2550136831]	auto[1]	31	1			T55	1		T140	1		T69	1
auto[2550136832:2684354559]	auto[0]	48	1			T47	1		T63	1		T69	1
auto[2550136832:2684354559]	auto[1]	55	1			T81	1		T63	2		T243	1
auto[2684354560:2818572287]	auto[0]	36	1			T35	1		T55	1		T110	1
auto[2684354560:2818572287]	auto[1]	58	1			T65	1		T261	1		T144	1
auto[2818572288:2952790015]	auto[0]	49	1			T109	1		T63	3		T93	1
auto[2818572288:2952790015]	auto[1]	53	1			T123	1		T59	1		T261	1
auto[2952790016:3087007743]	auto[0]	32	1			T47	1		T118	1		T209	1
auto[2952790016:3087007743]	auto[1]	54	1			T47	1		T36	1		T65	1
auto[3087007744:3221225471]	auto[0]	51	1			T47	1		T55	1		T34	1
auto[3087007744:3221225471]	auto[1]	51	1			T12	1		T47	2		T55	2
auto[3221225472:3355443199]	auto[0]	53	1			T23	1		T110	1		T91	1
auto[3221225472:3355443199]	auto[1]	54	1			T47	1		T55	1		T134	1
auto[3355443200:3489660927]	auto[0]	44	1			T47	1		T55	1		T24	1
auto[3355443200:3489660927]	auto[1]	57	1			T81	1		T48	1		T245	1
auto[3489660928:3623878655]	auto[0]	50	1			T1	1		T50	1		T105	1
auto[3489660928:3623878655]	auto[1]	48	1			T2	1		T17	1		T47	1
auto[3623878656:3758096383]	auto[0]	58	1			T55	1		T36	1		T57	1
auto[3623878656:3758096383]	auto[1]	42	1			T47	2		T55	1		T36	1
auto[3758096384:3892314111]	auto[0]	43	1			T55	1		T34	1		T4	1
auto[3758096384:3892314111]	auto[1]	49	1			T17	1		T81	1		T24	1
auto[3892314112:4026531839]	auto[0]	50	1			T47	2		T145	1		T252	1
auto[3892314112:4026531839]	auto[1]	57	1			T3	2		T109	1		T47	2
auto[4026531840:4160749567]	auto[0]	44	1			T3	1		T123	1		T47	1
auto[4026531840:4160749567]	auto[1]	45	1			T3	1		T47	1		T134	1
auto[4160749568:4294967295]	auto[0]	56	1			T13	1		T55	1		T105	1
auto[4160749568:4294967295]	auto[1]	51	1			T123	1		T47	1		T35	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1594

1

T1

2

T12

2

T13

3

auto[1]

1642

1

T1

2

T2

2

T3

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T12	1		T35	1		T34	1
auto[134217728:268435455]	97	1			T47	1		T55	1		T124	1
auto[268435456:402653183]	113	1			T47	2		T65	1		T48	2
auto[402653184:536870911]	88	1			T17	1		T47	3		T66	1
auto[536870912:671088639]	95	1			T55	1		T24	1		T124	1
auto[671088640:805306367]	96	1			T109	1		T55	1		T23	1
auto[805306368:939524095]	91	1			T46	1		T47	1		T55	1
auto[939524096:1073741823]	103	1			T2	1		T46	1		T47	2
auto[1073741824:1207959551]	96	1			T17	1		T47	1		T50	1
auto[1207959552:1342177279]	84	1			T47	1		T55	1		T4	1
auto[1342177280:1476395007]	114	1			T18	1		T123	1		T47	2
auto[1476395008:1610612735]	94	1			T3	1		T17	1		T47	1
auto[1610612736:1744830463]	104	1			T3	1		T18	1		T49	1
auto[1744830464:1879048191]	90	1			T13	1		T35	1		T55	1
auto[1879048192:2013265919]	111	1			T109	1		T47	3		T81	1
auto[2013265920:2147483647]	130	1			T1	1		T17	1		T47	2
auto[2147483648:2281701375]	100	1			T3	1		T123	1		T36	1
auto[2281701376:2415919103]	107	1			T47	1		T55	1		T23	1
auto[2415919104:2550136831]	89	1			T47	2		T55	3		T57	1
auto[2550136832:2684354559]	88	1			T3	1		T13	1		T55	1
auto[2684354560:2818572287]	124	1			T1	1		T12	1		T47	4
auto[2818572288:2952790015]	108	1			T1	1		T109	1		T123	1
auto[2952790016:3087007743]	119	1			T1	1		T47	3		T55	1
auto[3087007744:3221225471]	97	1			T12	1		T123	1		T47	1
auto[3221225472:3355443199]	89	1			T17	1		T47	1		T55	1
auto[3355443200:3489660927]	125	1			T13	1		T18	1		T47	2
auto[3489660928:3623878655]	110	1			T2	1		T17	1		T47	3
auto[3623878656:3758096383]	100	1			T3	1		T13	1		T81	1
auto[3758096384:3892314111]	102	1			T124	1		T57	1		T63	1
auto[3892314112:4026531839]	106	1			T123	1		T47	1		T55	3
auto[4026531840:4160749567]	104	1			T3	1		T47	1		T81	1
auto[4160749568:4294967295]	76	1			T47	1		T50	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T12	1		T35	1		T34	1
auto[0:134217727]	auto[1]	40	1			T145	1		T69	1		T64	1
auto[134217728:268435455]	auto[0]	39	1			T47	1		T105	1		T63	2
auto[134217728:268435455]	auto[1]	58	1			T55	1		T124	1		T65	1
auto[268435456:402653183]	auto[0]	57	1			T47	1		T48	1		T63	1
auto[268435456:402653183]	auto[1]	56	1			T47	1		T65	1		T48	1
auto[402653184:536870911]	auto[0]	52	1			T47	1		T23	1		T63	1
auto[402653184:536870911]	auto[1]	36	1			T17	1		T47	2		T66	1
auto[536870912:671088639]	auto[0]	48	1			T24	1		T134	1		T93	1
auto[536870912:671088639]	auto[1]	47	1			T55	1		T124	1		T4	1
auto[671088640:805306367]	auto[0]	44	1			T23	1		T34	1		T51	1
auto[671088640:805306367]	auto[1]	52	1			T109	1		T55	1		T57	1
auto[805306368:939524095]	auto[0]	45	1			T47	1		T36	2		T34	1
auto[805306368:939524095]	auto[1]	46	1			T46	1		T55	1		T24	1
auto[939524096:1073741823]	auto[0]	42	1			T47	2		T55	1		T145	1
auto[939524096:1073741823]	auto[1]	61	1			T2	1		T46	1		T63	1
auto[1073741824:1207959551]	auto[0]	50	1			T17	1		T50	1		T34	1
auto[1073741824:1207959551]	auto[1]	46	1			T47	1		T134	1		T48	1
auto[1207959552:1342177279]	auto[0]	41	1			T47	1		T4	1		T131	1
auto[1207959552:1342177279]	auto[1]	43	1			T55	1		T69	1		T289	1
auto[1342177280:1476395007]	auto[0]	51	1			T47	1		T55	2		T36	1
auto[1342177280:1476395007]	auto[1]	63	1			T18	1		T123	1		T47	1
auto[1476395008:1610612735]	auto[0]	47	1			T17	1		T47	1		T63	1
auto[1476395008:1610612735]	auto[1]	47	1			T3	1		T81	1		T65	2
auto[1610612736:1744830463]	auto[0]	47	1			T105	1		T110	1		T245	1
auto[1610612736:1744830463]	auto[1]	57	1			T3	1		T18	1		T49	1
auto[1744830464:1879048191]	auto[0]	55	1			T13	1		T55	1		T65	1
auto[1744830464:1879048191]	auto[1]	35	1			T35	1		T64	1		T251	1
auto[1879048192:2013265919]	auto[0]	47	1			T29	1		T51	1		T63	2
auto[1879048192:2013265919]	auto[1]	64	1			T109	1		T47	3		T81	1
auto[2013265920:2147483647]	auto[0]	64	1			T47	1		T55	1		T105	1
auto[2013265920:2147483647]	auto[1]	66	1			T1	1		T17	1		T47	1
auto[2147483648:2281701375]	auto[0]	44	1			T123	1		T65	1		T68	1
auto[2147483648:2281701375]	auto[1]	56	1			T3	1		T36	1		T60	1
auto[2281701376:2415919103]	auto[0]	58	1			T23	1		T34	1		T48	1
auto[2281701376:2415919103]	auto[1]	49	1			T47	1		T55	1		T57	1
auto[2415919104:2550136831]	auto[0]	43	1			T47	2		T55	2		T63	1
auto[2415919104:2550136831]	auto[1]	46	1			T55	1		T57	1		T137	1
auto[2550136832:2684354559]	auto[0]	44	1			T13	1		T55	1		T105	1
auto[2550136832:2684354559]	auto[1]	44	1			T3	1		T136	1		T137	1
auto[2684354560:2818572287]	auto[0]	55	1			T47	3		T36	1		T34	1
auto[2684354560:2818572287]	auto[1]	69	1			T1	1		T12	1		T47	1
auto[2818572288:2952790015]	auto[0]	63	1			T1	1		T109	1		T63	3
auto[2818572288:2952790015]	auto[1]	45	1			T123	1		T81	1		T35	1
auto[2952790016:3087007743]	auto[0]	57	1			T1	1		T47	1		T23	1
auto[2952790016:3087007743]	auto[1]	62	1			T47	2		T55	1		T65	1
auto[3087007744:3221225471]	auto[0]	47	1			T12	1		T47	1		T66	1
auto[3087007744:3221225471]	auto[1]	50	1			T123	1		T80	1		T66	1
auto[3221225472:3355443199]	auto[0]	40	1			T63	1		T91	1		T69	1
auto[3221225472:3355443199]	auto[1]	49	1			T17	1		T47	1		T55	1
auto[3355443200:3489660927]	auto[0]	70	1			T47	2		T23	1		T4	1
auto[3355443200:3489660927]	auto[1]	55	1			T13	1		T18	1		T35	1
auto[3489660928:3623878655]	auto[0]	46	1			T17	1		T256	1		T110	1
auto[3489660928:3623878655]	auto[1]	64	1			T2	1		T47	3		T55	1
auto[3623878656:3758096383]	auto[0]	56	1			T13	1		T81	1		T55	1
auto[3623878656:3758096383]	auto[1]	44	1			T3	1		T55	1		T261	1
auto[3758096384:3892314111]	auto[0]	56	1			T63	1		T67	1		T210	1
auto[3758096384:3892314111]	auto[1]	46	1			T124	1		T57	1		T144	1
auto[3892314112:4026531839]	auto[0]	56	1			T123	1		T55	2		T63	1
auto[3892314112:4026531839]	auto[1]	50	1			T47	1		T55	1		T36	1
auto[4026531840:4160749567]	auto[0]	46	1			T81	1		T118	1		T63	1
auto[4026531840:4160749567]	auto[1]	58	1			T3	1		T47	1		T55	1
auto[4160749568:4294967295]	auto[0]	38	1			T50	1		T4	1		T63	1
auto[4160749568:4294967295]	auto[1]	38	1			T47	1		T55	1		T124	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1596

1

T1

3

T3

1

T12

2

auto[1]

1640

1

T1

1

T2

2

T3

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T1	1		T3	1		T47	2
auto[134217728:268435455]	99	1			T47	3		T55	2		T65	1
auto[268435456:402653183]	102	1			T17	1		T55	2		T34	1
auto[402653184:536870911]	99	1			T46	1		T124	1		T4	1
auto[536870912:671088639]	99	1			T109	1		T47	1		T51	1
auto[671088640:805306367]	115	1			T13	1		T47	1		T55	1
auto[805306368:939524095]	108	1			T17	1		T47	5		T23	1
auto[939524096:1073741823]	81	1			T48	1		T136	1		T137	1
auto[1073741824:1207959551]	101	1			T47	2		T124	1		T36	1
auto[1207959552:1342177279]	98	1			T1	1		T47	1		T55	1
auto[1342177280:1476395007]	119	1			T3	1		T123	2		T47	1
auto[1476395008:1610612735]	116	1			T3	1		T47	2		T36	1
auto[1610612736:1744830463]	102	1			T17	1		T81	1		T35	1
auto[1744830464:1879048191]	93	1			T13	2		T123	1		T47	4
auto[1879048192:2013265919]	91	1			T109	1		T123	1		T47	1
auto[2013265920:2147483647]	80	1			T66	1		T134	1		T48	1
auto[2147483648:2281701375]	84	1			T12	1		T47	1		T50	1
auto[2281701376:2415919103]	93	1			T12	1		T47	2		T65	1
auto[2415919104:2550136831]	101	1			T13	1		T47	2		T35	1
auto[2550136832:2684354559]	102	1			T18	1		T47	1		T81	1
auto[2684354560:2818572287]	92	1			T55	1		T24	1		T65	4
auto[2818572288:2952790015]	123	1			T3	1		T47	1		T55	1
auto[2952790016:3087007743]	93	1			T17	1		T55	1		T105	1
auto[3087007744:3221225471]	94	1			T2	1		T109	1		T50	1
auto[3221225472:3355443199]	112	1			T47	1		T124	1		T34	1
auto[3355443200:3489660927]	105	1			T47	1		T50	1		T55	1
auto[3489660928:3623878655]	109	1			T46	1		T47	1		T50	1
auto[3623878656:3758096383]	100	1			T1	1		T2	1		T17	1
auto[3758096384:3892314111]	102	1			T18	1		T123	1		T47	2
auto[3892314112:4026531839]	113	1			T18	1		T47	1		T105	1
auto[4026531840:4160749567]	104	1			T3	2		T12	1		T47	1
auto[4160749568:4294967295]	108	1			T1	1		T17	1		T81	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T1	1		T47	1		T23	1
auto[0:134217727]	auto[1]	53	1			T3	1		T47	1		T55	2
auto[134217728:268435455]	auto[0]	51	1			T47	1		T55	2		T65	1
auto[134217728:268435455]	auto[1]	48	1			T47	2		T63	2		T366	1
auto[268435456:402653183]	auto[0]	55	1			T55	1		T34	1		T143	1
auto[268435456:402653183]	auto[1]	47	1			T17	1		T55	1		T65	1
auto[402653184:536870911]	auto[0]	52	1			T4	1		T256	1		T8	1
auto[402653184:536870911]	auto[1]	47	1			T46	1		T124	1		T57	1
auto[536870912:671088639]	auto[0]	52	1			T47	1		T51	1		T63	1
auto[536870912:671088639]	auto[1]	47	1			T109	1		T63	1		T131	1
auto[671088640:805306367]	auto[0]	51	1			T13	1		T23	1		T34	1
auto[671088640:805306367]	auto[1]	64	1			T47	1		T55	1		T4	1
auto[805306368:939524095]	auto[0]	60	1			T17	1		T47	3		T23	1
auto[805306368:939524095]	auto[1]	48	1			T47	2		T137	1		T261	1
auto[939524096:1073741823]	auto[0]	38	1			T143	1		T63	1		T56	1
auto[939524096:1073741823]	auto[1]	43	1			T48	1		T136	1		T137	1
auto[1073741824:1207959551]	auto[0]	48	1			T36	1		T118	1		T63	1
auto[1073741824:1207959551]	auto[1]	53	1			T47	2		T124	1		T48	1
auto[1207959552:1342177279]	auto[0]	48	1			T48	1		T256	1		T245	1
auto[1207959552:1342177279]	auto[1]	50	1			T1	1		T47	1		T55	1
auto[1342177280:1476395007]	auto[0]	52	1			T3	1		T47	1		T23	1
auto[1342177280:1476395007]	auto[1]	67	1			T123	2		T81	1		T55	3
auto[1476395008:1610612735]	auto[0]	61	1			T36	1		T118	1		T63	1
auto[1476395008:1610612735]	auto[1]	55	1			T3	1		T47	2		T137	2
auto[1610612736:1744830463]	auto[0]	53	1			T55	1		T63	1		T145	1
auto[1610612736:1744830463]	auto[1]	49	1			T17	1		T81	1		T35	1
auto[1744830464:1879048191]	auto[0]	47	1			T13	1		T123	1		T47	3
auto[1744830464:1879048191]	auto[1]	46	1			T13	1		T47	1		T55	2
auto[1879048192:2013265919]	auto[0]	45	1			T109	1		T123	1		T36	1
auto[1879048192:2013265919]	auto[1]	46	1			T47	1		T49	1		T36	1
auto[2013265920:2147483647]	auto[0]	32	1			T48	1		T145	1		T320	1
auto[2013265920:2147483647]	auto[1]	48	1			T66	1		T134	1		T261	1
auto[2147483648:2281701375]	auto[0]	37	1			T47	1		T50	1		T81	1
auto[2147483648:2281701375]	auto[1]	47	1			T12	1		T35	2		T55	1
auto[2281701376:2415919103]	auto[0]	48	1			T12	1		T47	1		T65	1
auto[2281701376:2415919103]	auto[1]	45	1			T47	1		T57	1		T59	1
auto[2415919104:2550136831]	auto[0]	55	1			T13	1		T47	2		T35	1
auto[2415919104:2550136831]	auto[1]	46	1			T134	1		T48	1		T63	1
auto[2550136832:2684354559]	auto[0]	46	1			T55	1		T58	1		T245	1
auto[2550136832:2684354559]	auto[1]	56	1			T18	1		T47	1		T81	1
auto[2684354560:2818572287]	auto[0]	40	1			T65	2		T57	1		T63	2
auto[2684354560:2818572287]	auto[1]	52	1			T55	1		T24	1		T65	2
auto[2818572288:2952790015]	auto[0]	52	1			T24	1		T36	1		T105	1
auto[2818572288:2952790015]	auto[1]	71	1			T3	1		T47	1		T55	1
auto[2952790016:3087007743]	auto[0]	42	1			T17	1		T55	1		T105	1
auto[2952790016:3087007743]	auto[1]	51	1			T65	1		T57	1		T69	2
auto[3087007744:3221225471]	auto[0]	51	1			T50	1		T55	1		T23	1
auto[3087007744:3221225471]	auto[1]	43	1			T2	1		T109	1		T24	1
auto[3221225472:3355443199]	auto[0]	55	1			T47	1		T34	1		T143	2
auto[3221225472:3355443199]	auto[1]	57	1			T124	1		T93	1		T202	1
auto[3355443200:3489660927]	auto[0]	55	1			T66	1		T140	1		T252	1
auto[3355443200:3489660927]	auto[1]	50	1			T47	1		T50	1		T55	1
auto[3489660928:3623878655]	auto[0]	52	1			T50	1		T23	1		T105	2
auto[3489660928:3623878655]	auto[1]	57	1			T46	1		T47	1		T124	1
auto[3623878656:3758096383]	auto[0]	50	1			T1	1		T17	1		T47	2
auto[3623878656:3758096383]	auto[1]	50	1			T2	1		T80	1		T65	1
auto[3758096384:3892314111]	auto[0]	48	1			T47	1		T51	1		T144	1
auto[3758096384:3892314111]	auto[1]	54	1			T18	1		T123	1		T47	1
auto[3892314112:4026531839]	auto[0]	55	1			T18	1		T47	1		T105	1
auto[3892314112:4026531839]	auto[1]	58	1			T143	1		T209	1		T210	1
auto[4026531840:4160749567]	auto[0]	57	1			T12	1		T34	1		T136	1
auto[4026531840:4160749567]	auto[1]	47	1			T3	2		T47	1		T55	2
auto[4160749568:4294967295]	auto[0]	63	1			T1	1		T55	1		T63	3
auto[4160749568:4294967295]	auto[1]	45	1			T17	1		T81	1		T60	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1601

1

T1

4

T3

1

T12

2

auto[1]

1636

1

T2

2

T3

5

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T1	1		T24	1		T36	1
auto[134217728:268435455]	104	1			T18	1		T47	2		T55	2
auto[268435456:402653183]	93	1			T18	1		T47	2		T66	1
auto[402653184:536870911]	100	1			T47	1		T34	1		T65	1
auto[536870912:671088639]	107	1			T55	2		T23	1		T36	1
auto[671088640:805306367]	86	1			T12	1		T123	1		T47	1
auto[805306368:939524095]	112	1			T13	1		T47	1		T55	1
auto[939524096:1073741823]	92	1			T12	1		T47	1		T80	1
auto[1073741824:1207959551]	111	1			T1	1		T3	1		T123	1
auto[1207959552:1342177279]	96	1			T2	1		T47	2		T81	1
auto[1342177280:1476395007]	104	1			T3	1		T17	1		T65	1
auto[1476395008:1610612735]	87	1			T3	1		T24	1		T36	1
auto[1610612736:1744830463]	135	1			T17	1		T123	1		T47	2
auto[1744830464:1879048191]	107	1			T3	1		T47	3		T81	1
auto[1879048192:2013265919]	93	1			T1	1		T18	1		T46	1
auto[2013265920:2147483647]	103	1			T47	1		T55	1		T23	1
auto[2147483648:2281701375]	89	1			T109	1		T47	1		T23	1
auto[2281701376:2415919103]	90	1			T46	1		T47	3		T55	1
auto[2415919104:2550136831]	112	1			T17	1		T29	1		T63	4
auto[2550136832:2684354559]	96	1			T3	1		T17	1		T50	1
auto[2684354560:2818572287]	77	1			T1	1		T13	1		T17	1
auto[2818572288:2952790015]	108	1			T13	1		T47	2		T55	1
auto[2952790016:3087007743]	119	1			T2	1		T109	1		T123	1
auto[3087007744:3221225471]	89	1			T47	2		T49	1		T105	2
auto[3221225472:3355443199]	104	1			T17	1		T50	1		T51	1
auto[3355443200:3489660927]	97	1			T13	1		T47	3		T55	3
auto[3489660928:3623878655]	94	1			T12	1		T123	1		T47	1
auto[3623878656:3758096383]	101	1			T47	1		T23	2		T118	1
auto[3758096384:3892314111]	105	1			T3	1		T109	1		T47	1
auto[3892314112:4026531839]	112	1			T47	1		T35	1		T55	1
auto[4026531840:4160749567]	103	1			T80	1		T50	1		T55	4
auto[4160749568:4294967295]	97	1			T47	4		T55	1		T65	2