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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4314 1 T1 6 T3 6 T12 6
auto[1] 2158 1 T1 2 T2 4 T3 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 216 1 T47 2 T55 2 T23 2
auto[134217728:268435455] 204 1 T12 2 T109 2 T57 4
auto[268435456:402653183] 196 1 T18 2 T50 2 T36 2
auto[402653184:536870911] 200 1 T47 2 T65 2 T57 2
auto[536870912:671088639] 218 1 T1 2 T109 2 T46 2
auto[671088640:805306367] 206 1 T3 2 T47 2 T24 2
auto[805306368:939524095] 194 1 T47 2 T80 2 T81 2
auto[939524096:1073741823] 250 1 T3 2 T12 2 T47 2
auto[1073741824:1207959551] 184 1 T81 2 T65 2 T134 2
auto[1207959552:1342177279] 208 1 T109 2 T47 8 T105 2
auto[1342177280:1476395007] 178 1 T13 2 T17 2 T123 2
auto[1476395008:1610612735] 210 1 T1 2 T47 2 T34 2
auto[1610612736:1744830463] 200 1 T17 2 T47 2 T35 2
auto[1744830464:1879048191] 192 1 T46 2 T47 10 T35 2
auto[1879048192:2013265919] 178 1 T13 2 T47 2 T66 2
auto[2013265920:2147483647] 240 1 T47 2 T80 2 T50 2
auto[2147483648:2281701375] 150 1 T47 2 T50 2 T55 2
auto[2281701376:2415919103] 206 1 T17 2 T47 2 T49 2
auto[2415919104:2550136831] 208 1 T1 2 T3 2 T47 6
auto[2550136832:2684354559] 216 1 T2 2 T17 2 T123 2
auto[2684354560:2818572287] 218 1 T3 2 T123 2 T47 4
auto[2818572288:2952790015] 180 1 T12 2 T17 2 T47 2
auto[2952790016:3087007743] 212 1 T13 2 T47 2 T50 2
auto[3087007744:3221225471] 158 1 T1 2 T18 2 T123 2
auto[3221225472:3355443199] 244 1 T17 2 T123 2 T23 2
auto[3355443200:3489660927] 190 1 T47 2 T51 2 T57 4
auto[3489660928:3623878655] 206 1 T13 2 T47 4 T35 2
auto[3623878656:3758096383] 190 1 T55 6 T66 2 T134 2
auto[3758096384:3892314111] 182 1 T3 2 T18 2 T55 2
auto[3892314112:4026531839] 212 1 T23 2 T34 2 T105 2
auto[4026531840:4160749567] 218 1 T2 2 T3 2 T47 2
auto[4160749568:4294967295] 208 1 T47 4 T55 4 T24 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 156 1 T55 2 T24 2 T124 2
auto[0:134217727] auto[1] 60 1 T47 2 T23 2 T65 4
auto[134217728:268435455] auto[0] 130 1 T12 2 T143 2 T256 2
auto[134217728:268435455] auto[1] 74 1 T109 2 T57 4 T48 2
auto[268435456:402653183] auto[0] 122 1 T18 2 T50 2 T36 2
auto[268435456:402653183] auto[1] 74 1 T70 2 T92 2 T328 2
auto[402653184:536870911] auto[0] 132 1 T47 2 T65 2 T57 2
auto[402653184:536870911] auto[1] 68 1 T63 4 T64 2 T199 2
auto[536870912:671088639] auto[0] 138 1 T1 2 T46 2 T47 2
auto[536870912:671088639] auto[1] 80 1 T109 2 T47 4 T81 2
auto[671088640:805306367] auto[0] 138 1 T3 2 T47 2 T65 2
auto[671088640:805306367] auto[1] 68 1 T24 2 T320 2 T93 2
auto[805306368:939524095] auto[0] 130 1 T80 2 T29 2 T55 4
auto[805306368:939524095] auto[1] 64 1 T47 2 T81 2 T48 2
auto[939524096:1073741823] auto[0] 192 1 T12 2 T55 2 T36 2
auto[939524096:1073741823] auto[1] 58 1 T3 2 T47 2 T55 2
auto[1073741824:1207959551] auto[0] 114 1 T65 2 T134 2 T137 2
auto[1073741824:1207959551] auto[1] 70 1 T81 2 T63 2 T8 2
auto[1207959552:1342177279] auto[0] 148 1 T47 4 T105 2 T65 2
auto[1207959552:1342177279] auto[1] 60 1 T109 2 T47 4 T52 2
auto[1342177280:1476395007] auto[0] 118 1 T47 4 T145 2 T8 2
auto[1342177280:1476395007] auto[1] 60 1 T13 2 T17 2 T123 2
auto[1476395008:1610612735] auto[0] 144 1 T1 2 T47 2 T65 2
auto[1476395008:1610612735] auto[1] 66 1 T34 2 T51 2 T60 2
auto[1610612736:1744830463] auto[0] 158 1 T17 2 T47 2 T35 2
auto[1610612736:1744830463] auto[1] 42 1 T63 2 T132 2 T316 2
auto[1744830464:1879048191] auto[0] 120 1 T47 2 T35 2 T36 2
auto[1744830464:1879048191] auto[1] 72 1 T46 2 T47 8 T55 2
auto[1879048192:2013265919] auto[0] 122 1 T13 2 T47 2 T66 2
auto[1879048192:2013265919] auto[1] 56 1 T48 2 T63 4 T68 2
auto[2013265920:2147483647] auto[0] 162 1 T47 2 T23 4 T65 2
auto[2013265920:2147483647] auto[1] 78 1 T80 2 T50 2 T57 2
auto[2147483648:2281701375] auto[0] 88 1 T47 2 T55 2 T124 2
auto[2147483648:2281701375] auto[1] 62 1 T50 2 T69 2 T200 2
auto[2281701376:2415919103] auto[0] 130 1 T17 2 T49 2 T55 2
auto[2281701376:2415919103] auto[1] 76 1 T47 2 T66 2 T36 2
auto[2415919104:2550136831] auto[0] 118 1 T47 2 T105 4 T57 2
auto[2415919104:2550136831] auto[1] 90 1 T1 2 T3 2 T47 4
auto[2550136832:2684354559] auto[0] 132 1 T17 2 T55 4 T66 2
auto[2550136832:2684354559] auto[1] 84 1 T2 2 T123 2 T47 2
auto[2684354560:2818572287] auto[0] 142 1 T47 4 T35 2 T24 2
auto[2684354560:2818572287] auto[1] 76 1 T3 2 T123 2 T65 2
auto[2818572288:2952790015] auto[0] 128 1 T12 2 T17 2 T23 2
auto[2818572288:2952790015] auto[1] 52 1 T47 2 T34 2 T57 2
auto[2952790016:3087007743] auto[0] 146 1 T50 2 T124 2 T245 2
auto[2952790016:3087007743] auto[1] 66 1 T13 2 T47 2 T55 4
auto[3087007744:3221225471] auto[0] 92 1 T1 2 T66 2 T4 2
auto[3087007744:3221225471] auto[1] 66 1 T18 2 T123 2 T55 2
auto[3221225472:3355443199] auto[0] 160 1 T17 2 T123 2 T23 2
auto[3221225472:3355443199] auto[1] 84 1 T51 2 T59 2 T63 4
auto[3355443200:3489660927] auto[0] 130 1 T47 2 T57 2 T63 4
auto[3355443200:3489660927] auto[1] 60 1 T51 2 T57 2 T102 2
auto[3489660928:3623878655] auto[0] 144 1 T13 2 T47 4 T35 2
auto[3489660928:3623878655] auto[1] 62 1 T124 2 T34 2 T63 4
auto[3623878656:3758096383] auto[0] 126 1 T55 2 T66 2 T252 2
auto[3623878656:3758096383] auto[1] 64 1 T55 4 T134 2 T69 2
auto[3758096384:3892314111] auto[0] 126 1 T3 2 T18 2 T55 2
auto[3758096384:3892314111] auto[1] 56 1 T69 2 T92 2 T71 2
auto[3892314112:4026531839] auto[0] 140 1 T23 2 T105 2 T63 4
auto[3892314112:4026531839] auto[1] 72 1 T34 2 T64 2 T366 2
auto[4026531840:4160749567] auto[0] 156 1 T3 2 T81 4 T55 2
auto[4026531840:4160749567] auto[1] 62 1 T2 2 T47 2 T136 2
auto[4160749568:4294967295] auto[0] 132 1 T47 4 T55 2 T24 2
auto[4160749568:4294967295] auto[1] 76 1 T55 2 T69 2 T257 4

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