Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2927

1

T1

4

T2

2

T3

6

auto[1]

276

1

T123

12

T80

10

T124

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	1		T123	1		T47	3
auto[134217728:268435455]	86	1			T3	1		T123	2		T29	1
auto[268435456:402653183]	111	1			T80	1		T55	2		T65	2
auto[402653184:536870911]	102	1			T3	1		T109	1		T123	1
auto[536870912:671088639]	97	1			T18	1		T47	2		T66	1
auto[671088640:805306367]	103	1			T123	1		T47	3		T80	1
auto[805306368:939524095]	115	1			T3	1		T123	1		T47	1
auto[939524096:1073741823]	92	1			T13	1		T24	1		T105	1
auto[1073741824:1207959551]	113	1			T1	1		T3	1		T123	1
auto[1207959552:1342177279]	86	1			T12	1		T47	1		T66	1
auto[1342177280:1476395007]	114	1			T13	1		T47	2		T35	1
auto[1476395008:1610612735]	108	1			T47	1		T80	1		T81	1
auto[1610612736:1744830463]	102	1			T123	3		T47	2		T81	1
auto[1744830464:1879048191]	100	1			T1	1		T123	1		T47	2
auto[1879048192:2013265919]	97	1			T13	1		T46	1		T50	1
auto[2013265920:2147483647]	83	1			T47	2		T55	3		T143	1
auto[2147483648:2281701375]	103	1			T109	1		T47	2		T55	1
auto[2281701376:2415919103]	93	1			T47	1		T81	1		T124	1
auto[2415919104:2550136831]	115	1			T123	1		T47	1		T81	1
auto[2550136832:2684354559]	91	1			T12	1		T47	1		T80	1
auto[2684354560:2818572287]	96	1			T80	1		T124	2		T34	1
auto[2818572288:2952790015]	86	1			T50	2		T4	1		T48	1
auto[2952790016:3087007743]	96	1			T18	1		T23	1		T105	1
auto[3087007744:3221225471]	91	1			T47	1		T80	2		T124	1
auto[3221225472:3355443199]	94	1			T3	1		T109	1		T47	4
auto[3355443200:3489660927]	92	1			T123	1		T47	1		T49	1
auto[3489660928:3623878655]	129	1			T3	1		T13	1		T80	2
auto[3623878656:3758096383]	101	1			T2	1		T18	1		T47	2
auto[3758096384:3892314111]	87	1			T123	1		T65	1		T57	1
auto[3892314112:4026531839]	97	1			T12	1		T17	1		T123	1
auto[4026531840:4160749567]	100	1			T1	1		T17	1		T123	1
auto[4160749568:4294967295]	114	1			T1	1		T123	1		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T2	1		T47	3		T81	1
auto[0:134217727]	auto[1]	11	1			T123	1		T383	2		T116	1
auto[134217728:268435455]	auto[0]	73	1			T3	1		T29	1		T51	2
auto[134217728:268435455]	auto[1]	13	1			T123	2		T145	1		T399	1
auto[268435456:402653183]	auto[0]	98	1			T55	2		T65	2		T137	1
auto[268435456:402653183]	auto[1]	13	1			T80	1		T145	1		T259	1
auto[402653184:536870911]	auto[0]	91	1			T3	1		T109	1		T47	1
auto[402653184:536870911]	auto[1]	11	1			T123	1		T294	1		T346	1
auto[536870912:671088639]	auto[0]	92	1			T18	1		T47	2		T66	1
auto[536870912:671088639]	auto[1]	5	1			T144	1		T116	1		T371	1
auto[671088640:805306367]	auto[0]	93	1			T47	3		T143	1		T63	2
auto[671088640:805306367]	auto[1]	10	1			T123	1		T80	1		T346	1
auto[805306368:939524095]	auto[0]	103	1			T3	1		T123	1		T47	1
auto[805306368:939524095]	auto[1]	12	1			T145	1		T371	1		T346	1
auto[939524096:1073741823]	auto[0]	85	1			T13	1		T24	1		T105	1
auto[939524096:1073741823]	auto[1]	7	1			T383	1		T301	1		T418	1
auto[1073741824:1207959551]	auto[0]	104	1			T1	1		T3	1		T123	1
auto[1073741824:1207959551]	auto[1]	9	1			T80	1		T116	1		T338	2
auto[1207959552:1342177279]	auto[0]	71	1			T12	1		T47	1		T66	1
auto[1207959552:1342177279]	auto[1]	15	1			T145	1		T346	3		T240	1
auto[1342177280:1476395007]	auto[0]	107	1			T13	1		T47	2		T35	1
auto[1342177280:1476395007]	auto[1]	7	1			T145	1		T371	1		T301	1
auto[1476395008:1610612735]	auto[0]	99	1			T47	1		T81	1		T55	1
auto[1476395008:1610612735]	auto[1]	9	1			T80	1		T383	1		T294	2
auto[1610612736:1744830463]	auto[0]	91	1			T47	2		T81	1		T55	1
auto[1610612736:1744830463]	auto[1]	11	1			T123	3		T301	1		T325	1
auto[1744830464:1879048191]	auto[0]	93	1			T1	1		T47	2		T55	3
auto[1744830464:1879048191]	auto[1]	7	1			T123	1		T371	2		T241	2
auto[1879048192:2013265919]	auto[0]	93	1			T13	1		T46	1		T50	1
auto[1879048192:2013265919]	auto[1]	4	1			T383	1		T371	1		T399	1
auto[2013265920:2147483647]	auto[0]	76	1			T47	2		T55	3		T143	1
auto[2013265920:2147483647]	auto[1]	7	1			T145	1		T371	1		T301	1
auto[2147483648:2281701375]	auto[0]	91	1			T109	1		T47	2		T55	1
auto[2147483648:2281701375]	auto[1]	12	1			T143	1		T383	1		T258	1
auto[2281701376:2415919103]	auto[0]	85	1			T47	1		T81	1		T34	1
auto[2281701376:2415919103]	auto[1]	8	1			T124	1		T300	1		T242	1
auto[2415919104:2550136831]	auto[0]	107	1			T123	1		T47	1		T81	1
auto[2415919104:2550136831]	auto[1]	8	1			T258	1		T278	1		T240	1
auto[2550136832:2684354559]	auto[0]	81	1			T12	1		T47	1		T80	1
auto[2550136832:2684354559]	auto[1]	10	1			T301	1		T399	1		T242	1
auto[2684354560:2818572287]	auto[0]	89	1			T80	1		T124	1		T34	1
auto[2684354560:2818572287]	auto[1]	7	1			T124	1		T346	1		T415	1
auto[2818572288:2952790015]	auto[0]	78	1			T50	2		T4	1		T48	1
auto[2818572288:2952790015]	auto[1]	8	1			T143	1		T244	1		T360	1
auto[2952790016:3087007743]	auto[0]	87	1			T18	1		T23	1		T105	1
auto[2952790016:3087007743]	auto[1]	9	1			T143	2		T145	1		T346	1
auto[3087007744:3221225471]	auto[0]	85	1			T47	1		T124	1		T36	1
auto[3087007744:3221225471]	auto[1]	6	1			T80	2		T143	1		T415	1
auto[3221225472:3355443199]	auto[0]	88	1			T3	1		T109	1		T47	4
auto[3221225472:3355443199]	auto[1]	6	1			T143	1		T145	1		T294	1
auto[3355443200:3489660927]	auto[0]	86	1			T123	1		T47	1		T49	1
auto[3355443200:3489660927]	auto[1]	6	1			T145	1		T346	1		T325	1
auto[3489660928:3623878655]	auto[0]	120	1			T3	1		T13	1		T55	1
auto[3489660928:3623878655]	auto[1]	9	1			T80	2		T258	1		T412	1
auto[3623878656:3758096383]	auto[0]	98	1			T2	1		T18	1		T47	2
auto[3623878656:3758096383]	auto[1]	3	1			T80	1		T410	1		T360	1
auto[3758096384:3892314111]	auto[0]	80	1			T65	1		T57	1		T134	1
auto[3758096384:3892314111]	auto[1]	7	1			T123	1		T294	1		T301	1
auto[3892314112:4026531839]	auto[0]	91	1			T12	1		T17	1		T123	1
auto[3892314112:4026531839]	auto[1]	6	1			T371	1		T275	1		T241	1
auto[4026531840:4160749567]	auto[0]	88	1			T1	1		T17	1		T47	2
auto[4026531840:4160749567]	auto[1]	12	1			T123	1		T143	1		T145	1
auto[4160749568:4294967295]	auto[0]	106	1			T1	1		T47	1		T55	1
auto[4160749568:4294967295]	auto[1]	8	1			T123	1		T80	1		T383	2