Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.11 98.46 100.00 99.02 98.41 91.17


Total test records in report: 1081
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T1006 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3550221108 May 21 02:26:17 PM PDT 24 May 21 02:26:22 PM PDT 24 344884077 ps
T1007 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.55891515 May 21 02:26:12 PM PDT 24 May 21 02:26:17 PM PDT 24 274096065 ps
T1008 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.832415390 May 21 02:26:30 PM PDT 24 May 21 02:26:32 PM PDT 24 38414554 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1449762885 May 21 02:25:23 PM PDT 24 May 21 02:25:26 PM PDT 24 110746356 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.922808888 May 21 02:25:57 PM PDT 24 May 21 02:26:02 PM PDT 24 183152050 ps
T1011 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2435254725 May 21 02:25:54 PM PDT 24 May 21 02:26:03 PM PDT 24 255364007 ps
T1012 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2341956728 May 21 02:25:55 PM PDT 24 May 21 02:25:58 PM PDT 24 665401383 ps
T1013 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.548975170 May 21 02:25:48 PM PDT 24 May 21 02:25:53 PM PDT 24 218427277 ps
T1014 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2469118002 May 21 02:25:47 PM PDT 24 May 21 02:25:49 PM PDT 24 9266033 ps
T1015 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1465835985 May 21 02:25:54 PM PDT 24 May 21 02:25:58 PM PDT 24 777950824 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3043725596 May 21 02:25:40 PM PDT 24 May 21 02:25:43 PM PDT 24 45024916 ps
T166 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.57340621 May 21 02:25:52 PM PDT 24 May 21 02:25:58 PM PDT 24 984529042 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1596760645 May 21 02:25:34 PM PDT 24 May 21 02:25:37 PM PDT 24 115360841 ps
T1018 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.833519031 May 21 02:26:11 PM PDT 24 May 21 02:26:13 PM PDT 24 15963843 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3214480955 May 21 02:25:37 PM PDT 24 May 21 02:25:41 PM PDT 24 93004345 ps
T1020 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2466860890 May 21 02:25:47 PM PDT 24 May 21 02:25:49 PM PDT 24 12174880 ps
T1021 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1175355838 May 21 02:26:23 PM PDT 24 May 21 02:26:24 PM PDT 24 34584186 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.118877137 May 21 02:25:23 PM PDT 24 May 21 02:25:32 PM PDT 24 450190362 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.577819125 May 21 02:25:31 PM PDT 24 May 21 02:25:39 PM PDT 24 490386767 ps
T1024 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4126459511 May 21 02:25:22 PM PDT 24 May 21 02:25:28 PM PDT 24 278123638 ps
T1025 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1991782053 May 21 02:25:17 PM PDT 24 May 21 02:25:25 PM PDT 24 256085885 ps
T1026 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1264257977 May 21 02:26:30 PM PDT 24 May 21 02:26:32 PM PDT 24 28996631 ps
T1027 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3190797816 May 21 02:26:12 PM PDT 24 May 21 02:26:14 PM PDT 24 13069665 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3360229238 May 21 02:25:48 PM PDT 24 May 21 02:25:52 PM PDT 24 122857036 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3191237536 May 21 02:25:59 PM PDT 24 May 21 02:26:01 PM PDT 24 89707336 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2587994750 May 21 02:25:53 PM PDT 24 May 21 02:25:55 PM PDT 24 13082355 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3369732591 May 21 02:25:23 PM PDT 24 May 21 02:25:29 PM PDT 24 118070982 ps
T1032 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4123818608 May 21 02:26:26 PM PDT 24 May 21 02:26:27 PM PDT 24 21524904 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3443609408 May 21 02:25:55 PM PDT 24 May 21 02:25:57 PM PDT 24 12235436 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.791861739 May 21 02:25:29 PM PDT 24 May 21 02:25:32 PM PDT 24 27317879 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2672187181 May 21 02:25:30 PM PDT 24 May 21 02:25:35 PM PDT 24 266601251 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3333675163 May 21 02:25:54 PM PDT 24 May 21 02:25:56 PM PDT 24 73617574 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.603199290 May 21 02:25:27 PM PDT 24 May 21 02:25:30 PM PDT 24 171888552 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3846565210 May 21 02:25:53 PM PDT 24 May 21 02:25:55 PM PDT 24 11951697 ps
T1039 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4079221918 May 21 02:26:30 PM PDT 24 May 21 02:26:33 PM PDT 24 11088762 ps
T1040 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2477694142 May 21 02:25:31 PM PDT 24 May 21 02:25:33 PM PDT 24 67941758 ps
T1041 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2597957598 May 21 02:26:18 PM PDT 24 May 21 02:26:20 PM PDT 24 71874095 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3652716131 May 21 02:25:17 PM PDT 24 May 21 02:25:20 PM PDT 24 15167347 ps
T1043 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.993579645 May 21 02:25:57 PM PDT 24 May 21 02:25:59 PM PDT 24 8304146 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3861049019 May 21 02:25:18 PM PDT 24 May 21 02:25:21 PM PDT 24 276449866 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1422500972 May 21 02:25:54 PM PDT 24 May 21 02:25:56 PM PDT 24 35714336 ps
T173 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4092486389 May 21 02:26:16 PM PDT 24 May 21 02:26:28 PM PDT 24 297960964 ps
T1046 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4106197017 May 21 02:25:26 PM PDT 24 May 21 02:25:30 PM PDT 24 91927695 ps
T1047 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2370288536 May 21 02:26:01 PM PDT 24 May 21 02:26:04 PM PDT 24 47876863 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.306803339 May 21 02:25:36 PM PDT 24 May 21 02:25:38 PM PDT 24 60245403 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4032692195 May 21 02:25:18 PM PDT 24 May 21 02:25:23 PM PDT 24 252248719 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.696687765 May 21 02:25:33 PM PDT 24 May 21 02:25:34 PM PDT 24 15229154 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4208370088 May 21 02:25:34 PM PDT 24 May 21 02:25:39 PM PDT 24 252616126 ps
T1052 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1953128051 May 21 02:26:14 PM PDT 24 May 21 02:26:18 PM PDT 24 82146348 ps
T1053 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1802143116 May 21 02:25:57 PM PDT 24 May 21 02:26:03 PM PDT 24 897150574 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3663499936 May 21 02:25:30 PM PDT 24 May 21 02:25:34 PM PDT 24 338877353 ps
T1055 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.465755285 May 21 02:26:26 PM PDT 24 May 21 02:26:27 PM PDT 24 160154445 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3151124547 May 21 02:25:53 PM PDT 24 May 21 02:25:56 PM PDT 24 51322694 ps
T1057 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.983684724 May 21 02:26:14 PM PDT 24 May 21 02:26:19 PM PDT 24 475861227 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3885895238 May 21 02:25:17 PM PDT 24 May 21 02:25:21 PM PDT 24 53806291 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3480381987 May 21 02:26:10 PM PDT 24 May 21 02:26:17 PM PDT 24 441924200 ps
T1060 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3057236172 May 21 02:26:28 PM PDT 24 May 21 02:26:30 PM PDT 24 63889331 ps
T1061 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1988717062 May 21 02:26:19 PM PDT 24 May 21 02:26:21 PM PDT 24 17278490 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3835541014 May 21 02:25:22 PM PDT 24 May 21 02:25:32 PM PDT 24 252027203 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3121851895 May 21 02:26:19 PM PDT 24 May 21 02:26:22 PM PDT 24 30231671 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.362309609 May 21 02:25:18 PM PDT 24 May 21 02:25:21 PM PDT 24 171878645 ps
T1065 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2938385465 May 21 02:25:54 PM PDT 24 May 21 02:25:58 PM PDT 24 91888268 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3823033784 May 21 02:26:14 PM PDT 24 May 21 02:26:18 PM PDT 24 172076635 ps
T1067 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.108956492 May 21 02:26:28 PM PDT 24 May 21 02:26:30 PM PDT 24 41228399 ps
T1068 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3872274948 May 21 02:26:09 PM PDT 24 May 21 02:26:11 PM PDT 24 28580457 ps
T1069 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1207790358 May 21 02:25:48 PM PDT 24 May 21 02:25:52 PM PDT 24 29174622 ps
T1070 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2804079362 May 21 02:26:24 PM PDT 24 May 21 02:26:26 PM PDT 24 118279241 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1492958964 May 21 02:25:35 PM PDT 24 May 21 02:26:02 PM PDT 24 3589029916 ps
T1072 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.245627583 May 21 02:26:14 PM PDT 24 May 21 02:26:20 PM PDT 24 115142189 ps
T1073 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4294556987 May 21 02:25:55 PM PDT 24 May 21 02:26:04 PM PDT 24 164336232 ps
T1074 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.354716108 May 21 02:25:25 PM PDT 24 May 21 02:25:27 PM PDT 24 22354670 ps
T1075 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.609807566 May 21 02:26:28 PM PDT 24 May 21 02:26:30 PM PDT 24 28317748 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3144252105 May 21 02:25:18 PM PDT 24 May 21 02:25:35 PM PDT 24 1965835347 ps
T157 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2788769649 May 21 02:26:13 PM PDT 24 May 21 02:26:20 PM PDT 24 426980971 ps
T1077 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2229967468 May 21 02:26:13 PM PDT 24 May 21 02:26:16 PM PDT 24 18142302 ps
T165 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1556125177 May 21 02:25:35 PM PDT 24 May 21 02:25:43 PM PDT 24 337595357 ps
T1078 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3890152205 May 21 02:25:52 PM PDT 24 May 21 02:25:55 PM PDT 24 297899166 ps
T162 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3708136936 May 21 02:26:12 PM PDT 24 May 21 02:26:20 PM PDT 24 241937454 ps
T1079 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2941342201 May 21 02:26:26 PM PDT 24 May 21 02:26:27 PM PDT 24 47225103 ps
T1080 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2376119545 May 21 02:25:55 PM PDT 24 May 21 02:25:57 PM PDT 24 80734653 ps
T1081 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3667777269 May 21 02:26:18 PM PDT 24 May 21 02:26:21 PM PDT 24 34342524 ps

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1054378497
Short name T3
Test name
Test status
Simulation time 1036236626 ps
CPU time 8.29 seconds
Started May 21 02:55:38 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 214404 kb
Host smart-173454c0-76a5-414c-b291-602ee9be6903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054378497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1054378497
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.258744423
Short name T47
Test name
Test status
Simulation time 2739161868 ps
CPU time 30.5 seconds
Started May 21 02:57:15 PM PDT 24
Finished May 21 02:57:50 PM PDT 24
Peak memory 222524 kb
Host smart-23029222-22b3-4325-acbe-c2f81d8df8ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258744423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.258744423
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.770935747
Short name T48
Test name
Test status
Simulation time 530645464 ps
CPU time 8.6 seconds
Started May 21 02:56:40 PM PDT 24
Finished May 21 02:56:58 PM PDT 24
Peak memory 222712 kb
Host smart-7a9ed2ba-6970-470d-a4e0-e4b723eb103e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770935747 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.770935747
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3380307690
Short name T63
Test name
Test status
Simulation time 2194559091 ps
CPU time 40.17 seconds
Started May 21 02:55:12 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 216580 kb
Host smart-894c41e1-dea5-4c90-a1f2-969f14371bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380307690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3380307690
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1249117903
Short name T9
Test name
Test status
Simulation time 1605277191 ps
CPU time 13.67 seconds
Started May 21 02:54:22 PM PDT 24
Finished May 21 02:54:38 PM PDT 24
Peak memory 237984 kb
Host smart-dc808a54-f5ee-4269-b79d-68d026396865
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249117903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1249117903
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1749204538
Short name T52
Test name
Test status
Simulation time 419229971 ps
CPU time 14.08 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 222704 kb
Host smart-f61f3534-c071-4ba7-9e90-4320de1f4763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749204538 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1749204538
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1364249986
Short name T53
Test name
Test status
Simulation time 653783231 ps
CPU time 33.54 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 222612 kb
Host smart-28e8b426-a167-4a1b-82e1-7b01da439f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364249986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1364249986
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1366707833
Short name T4
Test name
Test status
Simulation time 172250323 ps
CPU time 2.62 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 222864 kb
Host smart-256dfc2f-2c64-4b82-9770-6487191d43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366707833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1366707833
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1250080691
Short name T123
Test name
Test status
Simulation time 752967046 ps
CPU time 36.89 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 222508 kb
Host smart-21cd7b81-b72a-41dc-8da4-c5488278feea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250080691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1250080691
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1419369940
Short name T121
Test name
Test status
Simulation time 1277098781 ps
CPU time 12.96 seconds
Started May 21 02:25:36 PM PDT 24
Finished May 21 02:25:49 PM PDT 24
Peak memory 214404 kb
Host smart-1d1311ce-65cd-41f4-a384-f28ae7ea9610
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419369940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1419369940
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1387056932
Short name T64
Test name
Test status
Simulation time 1176961607 ps
CPU time 25.15 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 220876 kb
Host smart-5f0b7c1b-f71a-40dc-8189-2c69830120b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387056932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1387056932
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1864735214
Short name T7
Test name
Test status
Simulation time 624037054 ps
CPU time 7.48 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 214712 kb
Host smart-1072f917-c705-49db-9b6c-68cb5a3f3c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864735214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1864735214
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3731967582
Short name T313
Test name
Test status
Simulation time 177346155 ps
CPU time 8.61 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 215476 kb
Host smart-a6416211-fa3c-4a89-b565-f2199a29b262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731967582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3731967582
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_random.352987856
Short name T1
Test name
Test status
Simulation time 50978606 ps
CPU time 3.14 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 208344 kb
Host smart-de4279a6-135b-4c6c-9547-061ac8310190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352987856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.352987856
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3439366953
Short name T301
Test name
Test status
Simulation time 2170970669 ps
CPU time 31.25 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 214792 kb
Host smart-043382d1-b8cb-4fed-84ac-5f3a0c96f4d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439366953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3439366953
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.189062717
Short name T24
Test name
Test status
Simulation time 1957022666 ps
CPU time 30.07 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 214312 kb
Host smart-6a033ffa-e181-4dc1-a8d0-2e8db0fec2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189062717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.189062717
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1042667926
Short name T33
Test name
Test status
Simulation time 222542749 ps
CPU time 4.56 seconds
Started May 21 02:54:58 PM PDT 24
Finished May 21 02:55:07 PM PDT 24
Peak memory 211032 kb
Host smart-700ecf9f-53aa-4503-8a1f-3f85b80d686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042667926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1042667926
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3954544873
Short name T71
Test name
Test status
Simulation time 1648823377 ps
CPU time 56.83 seconds
Started May 21 02:55:56 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 217628 kb
Host smart-1d810973-5c30-4c76-8838-ebf351a77087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954544873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3954544873
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1035403872
Short name T360
Test name
Test status
Simulation time 1586056114 ps
CPU time 25.98 seconds
Started May 21 02:56:15 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 215396 kb
Host smart-942ea49f-d119-4120-8db8-14ad44675b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035403872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1035403872
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3269323392
Short name T57
Test name
Test status
Simulation time 2882805867 ps
CPU time 24.04 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:56:15 PM PDT 24
Peak memory 222744 kb
Host smart-d41a04da-36b6-4f37-890d-3fd02b474370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269323392 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3269323392
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3591565105
Short name T156
Test name
Test status
Simulation time 255905992 ps
CPU time 3.54 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:26:02 PM PDT 24
Peak memory 213908 kb
Host smart-e4fc8351-9b52-499b-ba3e-3ec00d5c5f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591565105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3591565105
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3274690259
Short name T780
Test name
Test status
Simulation time 126824559 ps
CPU time 6.41 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 214348 kb
Host smart-856d5baf-6d1a-454b-abe2-38c69e0fc296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274690259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3274690259
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4184306044
Short name T35
Test name
Test status
Simulation time 285321633 ps
CPU time 3.89 seconds
Started May 21 02:54:57 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 214388 kb
Host smart-0ad3eb03-cf43-47d5-b776-8b8bd9a314b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184306044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4184306044
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.225851599
Short name T88
Test name
Test status
Simulation time 128774121 ps
CPU time 5.22 seconds
Started May 21 02:55:12 PM PDT 24
Finished May 21 02:55:25 PM PDT 24
Peak memory 209604 kb
Host smart-6a7547a8-4528-4afa-898a-073b1b3844ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225851599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.225851599
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.513514752
Short name T20
Test name
Test status
Simulation time 96717232 ps
CPU time 3.3 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:30 PM PDT 24
Peak memory 210488 kb
Host smart-9d5126dd-d53c-4217-b2c3-5f7924bd06b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513514752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.513514752
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1266521045
Short name T145
Test name
Test status
Simulation time 5398607429 ps
CPU time 135.04 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:59:04 PM PDT 24
Peak memory 214612 kb
Host smart-8ae5dc71-3e7f-4c71-baf2-aacb71d2bbf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266521045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1266521045
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3807784426
Short name T55
Test name
Test status
Simulation time 472857832 ps
CPU time 19.73 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:54 PM PDT 24
Peak memory 222452 kb
Host smart-7dcc7b93-1751-44a6-958a-0b544e2e4800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807784426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3807784426
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2805462574
Short name T460
Test name
Test status
Simulation time 324506693 ps
CPU time 3.43 seconds
Started May 21 02:56:56 PM PDT 24
Finished May 21 02:57:05 PM PDT 24
Peak memory 210092 kb
Host smart-42c3dd27-27ae-4296-bf2e-29a1bfa70165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805462574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2805462574
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.138645570
Short name T176
Test name
Test status
Simulation time 114958386 ps
CPU time 3.97 seconds
Started May 21 02:55:40 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 222752 kb
Host smart-997a3377-67be-4357-a044-8c3f7a8ceeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138645570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.138645570
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2268752897
Short name T383
Test name
Test status
Simulation time 636311403 ps
CPU time 30.18 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:56:19 PM PDT 24
Peak memory 215396 kb
Host smart-3fad5c3b-87be-4ef0-9ad2-be1607f94e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268752897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2268752897
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.589935506
Short name T225
Test name
Test status
Simulation time 55511636 ps
CPU time 2.15 seconds
Started May 21 02:54:49 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 214552 kb
Host smart-db4ad697-2671-41ee-a9f7-54d7e13038fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589935506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.589935506
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3234913015
Short name T132
Test name
Test status
Simulation time 2267697485 ps
CPU time 23.7 seconds
Started May 21 02:56:46 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 222756 kb
Host smart-89f29fb4-c78a-4730-860f-16a3d2f65a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234913015 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3234913015
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2067986883
Short name T128
Test name
Test status
Simulation time 79280131 ps
CPU time 1.85 seconds
Started May 21 02:25:22 PM PDT 24
Finished May 21 02:25:25 PM PDT 24
Peak memory 214412 kb
Host smart-8e2a7edb-ce05-42ee-9dbd-8d6f83934ca3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067986883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2067986883
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3758137819
Short name T338
Test name
Test status
Simulation time 192083786 ps
CPU time 10.76 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 214872 kb
Host smart-09cc5a64-731c-4c11-a3d8-b170b2bf846e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758137819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3758137819
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3263553012
Short name T222
Test name
Test status
Simulation time 7630272644 ps
CPU time 219.83 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 03:00:28 PM PDT 24
Peak memory 215792 kb
Host smart-3612177e-b3e7-43ef-82d4-1189a49a0d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263553012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3263553012
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.378609566
Short name T425
Test name
Test status
Simulation time 51157582 ps
CPU time 0.77 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 205980 kb
Host smart-101abfb8-8806-4a38-b15f-34e95908247f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378609566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.378609566
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3995890990
Short name T143
Test name
Test status
Simulation time 1571879013 ps
CPU time 84.24 seconds
Started May 21 02:55:31 PM PDT 24
Finished May 21 02:57:04 PM PDT 24
Peak memory 222552 kb
Host smart-48945279-525b-4c74-8f41-a0867dda2c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995890990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3995890990
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2418120895
Short name T211
Test name
Test status
Simulation time 2468640705 ps
CPU time 27.25 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:57:06 PM PDT 24
Peak memory 221160 kb
Host smart-9182862d-dd65-42d9-a66f-b157d0078c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418120895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2418120895
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.289191177
Short name T105
Test name
Test status
Simulation time 50475042 ps
CPU time 1.92 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 216872 kb
Host smart-fabe8875-dbb1-4aa1-b142-6002c060eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289191177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.289191177
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.608829969
Short name T244
Test name
Test status
Simulation time 621474359 ps
CPU time 33.44 seconds
Started May 21 02:56:40 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 214368 kb
Host smart-463be97f-fcbb-45e0-9c35-880c32ed4814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608829969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.608829969
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.655160503
Short name T239
Test name
Test status
Simulation time 1054540968 ps
CPU time 22.48 seconds
Started May 21 02:56:29 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 222656 kb
Host smart-9c899cc8-eb56-4bef-aca1-06f6dc0d2d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655160503 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.655160503
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.335438086
Short name T15
Test name
Test status
Simulation time 77897862 ps
CPU time 3.42 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 208268 kb
Host smart-54c2847a-0041-459d-9a5f-a1700a327b6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335438086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.335438086
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3644869605
Short name T25
Test name
Test status
Simulation time 1520756571 ps
CPU time 5.47 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 208864 kb
Host smart-aab3c85e-3bb2-4525-84fb-e99e66738e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644869605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3644869605
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1500040069
Short name T92
Test name
Test status
Simulation time 148779609 ps
CPU time 2.86 seconds
Started May 21 02:57:24 PM PDT 24
Finished May 21 02:57:33 PM PDT 24
Peak memory 222468 kb
Host smart-996e6fdb-8acd-4eac-bad7-69c1218238d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500040069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1500040069
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4094401488
Short name T159
Test name
Test status
Simulation time 285840878 ps
CPU time 5.74 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:06 PM PDT 24
Peak memory 205816 kb
Host smart-ab9f34eb-87b4-44e4-9be4-a8eb2dea8294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094401488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4094401488
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.734561504
Short name T324
Test name
Test status
Simulation time 3592062956 ps
CPU time 34.51 seconds
Started May 21 02:55:11 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 215420 kb
Host smart-15625285-c218-4f6d-9497-79499fbf47f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734561504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.734561504
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1556125177
Short name T165
Test name
Test status
Simulation time 337595357 ps
CPU time 7.06 seconds
Started May 21 02:25:35 PM PDT 24
Finished May 21 02:25:43 PM PDT 24
Peak memory 213964 kb
Host smart-3063ccbe-1cf8-4574-948d-7f5718680a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556125177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1556125177
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3815714413
Short name T160
Test name
Test status
Simulation time 792923284 ps
CPU time 7.14 seconds
Started May 21 02:25:49 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 205804 kb
Host smart-2403ae41-b1b1-4c5a-af8f-e3c85e952368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815714413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3815714413
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3144252105
Short name T1076
Test name
Test status
Simulation time 1965835347 ps
CPU time 16.28 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:35 PM PDT 24
Peak memory 214368 kb
Host smart-0a986723-a879-419f-b31d-6807b730751b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144252105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3144252105
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1698632528
Short name T175
Test name
Test status
Simulation time 85087144 ps
CPU time 3.74 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 218212 kb
Host smart-a55f5a98-ec56-468f-94e6-9e01d31de882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698632528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1698632528
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2641898752
Short name T177
Test name
Test status
Simulation time 463908622 ps
CPU time 4.3 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:48 PM PDT 24
Peak memory 222644 kb
Host smart-3d66fe4e-227d-4b16-8ca3-9e7510e6e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641898752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2641898752
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3807878632
Short name T288
Test name
Test status
Simulation time 442862274 ps
CPU time 5.45 seconds
Started May 21 02:55:34 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 214336 kb
Host smart-e87e0e59-b3cf-4776-b6dd-158911c16d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807878632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3807878632
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3434734405
Short name T241
Test name
Test status
Simulation time 191341039 ps
CPU time 3.55 seconds
Started May 21 02:57:11 PM PDT 24
Finished May 21 02:57:19 PM PDT 24
Peak memory 214388 kb
Host smart-2d7435aa-03ea-4f4c-a7ef-db304ef8abb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434734405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3434734405
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1206211957
Short name T305
Test name
Test status
Simulation time 83741069 ps
CPU time 4.19 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:03 PM PDT 24
Peak memory 214320 kb
Host smart-e8cdcc2a-12c8-48ae-82f6-af2935a1a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206211957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1206211957
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2202857875
Short name T32
Test name
Test status
Simulation time 200273751 ps
CPU time 3.74 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 214700 kb
Host smart-17063e53-60e1-4838-be81-cee60404879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202857875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2202857875
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3730508220
Short name T180
Test name
Test status
Simulation time 679581450 ps
CPU time 4.31 seconds
Started May 21 02:56:06 PM PDT 24
Finished May 21 02:56:18 PM PDT 24
Peak memory 217764 kb
Host smart-3272e88c-498a-49ab-a57b-375556a2ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730508220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3730508220
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3301943117
Short name T955
Test name
Test status
Simulation time 115241286 ps
CPU time 3.14 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:26:01 PM PDT 24
Peak memory 214256 kb
Host smart-92468e60-a0b6-4fa9-bf98-f92a33d61014
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301943117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3301943117
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1281718548
Short name T414
Test name
Test status
Simulation time 213839911 ps
CPU time 6.33 seconds
Started May 21 02:55:08 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 215140 kb
Host smart-78da0ada-528f-420d-b81c-04218e40c1c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281718548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1281718548
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.217204304
Short name T260
Test name
Test status
Simulation time 13409219708 ps
CPU time 64.09 seconds
Started May 21 02:55:12 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 222572 kb
Host smart-245213de-4d5a-4bde-af1c-938674d7ed95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217204304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.217204304
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3191020712
Short name T139
Test name
Test status
Simulation time 441368246 ps
CPU time 6.15 seconds
Started May 21 02:55:22 PM PDT 24
Finished May 21 02:55:37 PM PDT 24
Peak memory 208688 kb
Host smart-e87b5f88-f0e4-443b-a80d-76a84c4ba409
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191020712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3191020712
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.4105570141
Short name T395
Test name
Test status
Simulation time 214120802 ps
CPU time 3.95 seconds
Started May 21 02:56:00 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 210108 kb
Host smart-bedf1a70-076a-41d5-aeaa-2aa97fac58f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105570141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.4105570141
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.744190666
Short name T101
Test name
Test status
Simulation time 135746421 ps
CPU time 3.02 seconds
Started May 21 02:56:18 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 214376 kb
Host smart-84a7e1d5-ee7d-4239-b885-48ae3e01ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744190666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.744190666
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.387288479
Short name T308
Test name
Test status
Simulation time 56782543 ps
CPU time 3.37 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 214436 kb
Host smart-554d6b76-4016-4b5e-829e-058a6e7b0a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387288479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.387288479
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3837751825
Short name T319
Test name
Test status
Simulation time 112585983 ps
CPU time 2.22 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 222464 kb
Host smart-d0c8256a-0412-41c6-83d2-59fb50111e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837751825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3837751825
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3654575047
Short name T349
Test name
Test status
Simulation time 1909446930 ps
CPU time 10.78 seconds
Started May 21 02:56:45 PM PDT 24
Finished May 21 02:57:05 PM PDT 24
Peak memory 222512 kb
Host smart-ebdda45f-167f-4b3a-a931-6a6e50dcf775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654575047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3654575047
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2769125912
Short name T264
Test name
Test status
Simulation time 1748713590 ps
CPU time 19.09 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:36 PM PDT 24
Peak memory 215848 kb
Host smart-027d543b-f030-4454-a052-cb59c1d39e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769125912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2769125912
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3132156676
Short name T275
Test name
Test status
Simulation time 875580167 ps
CPU time 46.15 seconds
Started May 21 02:55:03 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 215612 kb
Host smart-caf4c2ba-379a-46eb-8682-598e23170b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132156676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3132156676
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.514232465
Short name T178
Test name
Test status
Simulation time 416750709 ps
CPU time 6.53 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 222744 kb
Host smart-80c47d0c-3ff8-41f5-b27b-465dab1d5b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514232465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.514232465
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.191824127
Short name T179
Test name
Test status
Simulation time 170847564 ps
CPU time 3.55 seconds
Started May 21 02:56:06 PM PDT 24
Finished May 21 02:56:17 PM PDT 24
Peak memory 222776 kb
Host smart-5dfcae42-f4a3-4f88-b233-fc2b7013b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191824127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.191824127
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2326628331
Short name T195
Test name
Test status
Simulation time 9071655426 ps
CPU time 57.51 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 216100 kb
Host smart-e2b2ed5d-d2f5-49da-964b-41632c22e3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326628331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2326628331
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2417519287
Short name T249
Test name
Test status
Simulation time 98717773 ps
CPU time 2.03 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 214252 kb
Host smart-26ae702e-cf70-4ff9-9d0c-e5df8ba1c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417519287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2417519287
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3797355256
Short name T115
Test name
Test status
Simulation time 896530344 ps
CPU time 24.19 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 222616 kb
Host smart-7d3d3b68-7d28-43b3-a775-b0e185dca8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797355256 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3797355256
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1763236178
Short name T230
Test name
Test status
Simulation time 1112356243 ps
CPU time 22.37 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 222556 kb
Host smart-30276c10-0044-4d1b-aa9e-4d0e039f3905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763236178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1763236178
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1694235383
Short name T337
Test name
Test status
Simulation time 105286093 ps
CPU time 4.23 seconds
Started May 21 02:56:15 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 209752 kb
Host smart-f3012e99-4bd8-440f-838d-f4fce43706b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694235383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1694235383
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2192132416
Short name T234
Test name
Test status
Simulation time 72752096 ps
CPU time 3.49 seconds
Started May 21 02:56:28 PM PDT 24
Finished May 21 02:56:43 PM PDT 24
Peak memory 208112 kb
Host smart-5bd28b13-dd8c-4d21-9ea6-cc97c8d93bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192132416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2192132416
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1402656477
Short name T346
Test name
Test status
Simulation time 155296549 ps
CPU time 9.11 seconds
Started May 21 02:57:21 PM PDT 24
Finished May 21 02:57:36 PM PDT 24
Peak memory 214316 kb
Host smart-a51eac35-7997-4232-9ad3-ddb4387c4ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402656477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1402656477
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2044019235
Short name T171
Test name
Test status
Simulation time 145386790 ps
CPU time 5.27 seconds
Started May 21 02:26:01 PM PDT 24
Finished May 21 02:26:07 PM PDT 24
Peak memory 213900 kb
Host smart-3c589b39-9c86-4f2d-a5c2-9bce993e2191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044019235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2044019235
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1102116332
Short name T161
Test name
Test status
Simulation time 289237845 ps
CPU time 7.04 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:22 PM PDT 24
Peak memory 214200 kb
Host smart-e90cbc42-f984-481f-8f11-7000b9ff1137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102116332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1102116332
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3477113655
Short name T154
Test name
Test status
Simulation time 197069604 ps
CPU time 3.14 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:23 PM PDT 24
Peak memory 213984 kb
Host smart-2bb2a9ab-bbf3-4b92-8eff-f7668f3cdc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477113655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3477113655
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3279173483
Short name T167
Test name
Test status
Simulation time 182399982 ps
CPU time 4.41 seconds
Started May 21 02:25:33 PM PDT 24
Finished May 21 02:25:38 PM PDT 24
Peak memory 213936 kb
Host smart-62f794ec-6063-4696-9d6d-285f45afc2df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279173483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3279173483
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2523051012
Short name T163
Test name
Test status
Simulation time 184559807 ps
CPU time 4.32 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:26:02 PM PDT 24
Peak memory 213964 kb
Host smart-9756d48c-5e00-46bc-a3c3-7a6ee859873b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523051012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2523051012
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3563144987
Short name T158
Test name
Test status
Simulation time 486443272 ps
CPU time 2.78 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:13 PM PDT 24
Peak memory 210388 kb
Host smart-520df40a-b037-4d34-bc08-39982791aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563144987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3563144987
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.58774240
Short name T21
Test name
Test status
Simulation time 37216582 ps
CPU time 2.48 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 220020 kb
Host smart-529e8c34-8d49-4961-bcdf-9dd182b0dbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58774240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.58774240
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.757158798
Short name T155
Test name
Test status
Simulation time 156096916 ps
CPU time 2 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 210344 kb
Host smart-c327d942-717e-489e-aab5-97e3ccee61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757158798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.757158798
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1099475397
Short name T62
Test name
Test status
Simulation time 98009513 ps
CPU time 2.47 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 210056 kb
Host smart-c5a4c9e8-8d3e-423b-86b1-022ff8c90db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099475397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1099475397
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2304931355
Short name T889
Test name
Test status
Simulation time 201555595 ps
CPU time 3.33 seconds
Started May 21 02:54:16 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 215148 kb
Host smart-5e76c9e0-c350-4b46-b9ed-3c11df525204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304931355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2304931355
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.460814227
Short name T881
Test name
Test status
Simulation time 90943909 ps
CPU time 3.14 seconds
Started May 21 02:54:17 PM PDT 24
Finished May 21 02:54:24 PM PDT 24
Peak memory 214576 kb
Host smart-4c1daf34-1f6c-4037-a92a-20d907cede14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460814227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.460814227
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.129400149
Short name T46
Test name
Test status
Simulation time 60353278 ps
CPU time 2.74 seconds
Started May 21 02:54:15 PM PDT 24
Finished May 21 02:54:20 PM PDT 24
Peak memory 209336 kb
Host smart-ff9beea3-7cf6-4b8f-b754-6054d8234c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129400149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.129400149
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2143494042
Short name T235
Test name
Test status
Simulation time 4604138265 ps
CPU time 10 seconds
Started May 21 02:54:19 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 222700 kb
Host smart-a7146bb6-1fe1-4951-a5e7-949a1b513584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143494042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2143494042
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_random.2769935410
Short name T498
Test name
Test status
Simulation time 1150204399 ps
CPU time 7.89 seconds
Started May 21 02:55:08 PM PDT 24
Finished May 21 02:55:21 PM PDT 24
Peak memory 218512 kb
Host smart-7f2886b7-e17c-4707-ad6f-29066724cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769935410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2769935410
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3853584052
Short name T392
Test name
Test status
Simulation time 332935326 ps
CPU time 1.78 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 210236 kb
Host smart-9c02633f-fc6e-41d1-b505-295ea1278cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853584052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3853584052
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.814347189
Short name T312
Test name
Test status
Simulation time 44752047 ps
CPU time 3.55 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 215208 kb
Host smart-584ca942-b365-4000-82ea-1439c8b773d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814347189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.814347189
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4104859318
Short name T219
Test name
Test status
Simulation time 230897208 ps
CPU time 4.36 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 207268 kb
Host smart-82cf5fdc-bec3-42e4-888a-a9f1ea225322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104859318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4104859318
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2765561489
Short name T332
Test name
Test status
Simulation time 93906681 ps
CPU time 1.9 seconds
Started May 21 02:55:32 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 214284 kb
Host smart-a4b808ba-9999-4b30-9817-d010b268f8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765561489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2765561489
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1259130093
Short name T227
Test name
Test status
Simulation time 77261403 ps
CPU time 3.85 seconds
Started May 21 02:55:27 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 209484 kb
Host smart-a1a847bd-49e5-44f9-b869-23a59ab35d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259130093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1259130093
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1576881671
Short name T409
Test name
Test status
Simulation time 144090789 ps
CPU time 2.13 seconds
Started May 21 02:55:32 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 207592 kb
Host smart-1e42b33f-9a6c-4f78-ae4b-c79595ae4ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576881671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1576881671
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3958359824
Short name T197
Test name
Test status
Simulation time 4555220244 ps
CPU time 43.48 seconds
Started May 21 02:55:32 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 215996 kb
Host smart-6e9bbd2c-7f28-4bc3-b9fc-410ac5dc6852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958359824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3958359824
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2070781864
Short name T220
Test name
Test status
Simulation time 114093954 ps
CPU time 5 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 214692 kb
Host smart-169522f0-198b-4865-962d-ade163219b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070781864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2070781864
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1272908813
Short name T375
Test name
Test status
Simulation time 642362149 ps
CPU time 5.24 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 210144 kb
Host smart-504ef807-860c-42b1-a3f9-8483b5b6da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272908813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1272908813
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3580463342
Short name T282
Test name
Test status
Simulation time 458091958 ps
CPU time 9.3 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 214356 kb
Host smart-eccfd464-424f-4ab9-8972-7378eafd4349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580463342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3580463342
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3553475137
Short name T142
Test name
Test status
Simulation time 1211637904 ps
CPU time 17.13 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:42 PM PDT 24
Peak memory 221116 kb
Host smart-9ea8aae9-2666-4395-856f-e3b2d1d2222b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553475137 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3553475137
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_random.114926440
Short name T345
Test name
Test status
Simulation time 100009415 ps
CPU time 4.2 seconds
Started May 21 02:54:37 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 214408 kb
Host smart-8086cf79-567d-450c-855f-b1df92f71329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114926440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.114926440
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1375043483
Short name T335
Test name
Test status
Simulation time 218630585 ps
CPU time 3.59 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 214292 kb
Host smart-e3347110-929f-4237-95ac-0c3bb4d62669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375043483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1375043483
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1008385893
Short name T325
Test name
Test status
Simulation time 2129821784 ps
CPU time 27.97 seconds
Started May 21 02:54:42 PM PDT 24
Finished May 21 02:55:13 PM PDT 24
Peak memory 214708 kb
Host smart-2646920f-3beb-44bb-8c87-44ea5dfc5f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008385893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1008385893
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.433876428
Short name T336
Test name
Test status
Simulation time 4347922270 ps
CPU time 46.98 seconds
Started May 21 02:56:52 PM PDT 24
Finished May 21 02:57:46 PM PDT 24
Peak memory 210272 kb
Host smart-7aa50a20-af39-4f10-b833-489d4bf1fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433876428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.433876428
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4072074366
Short name T421
Test name
Test status
Simulation time 71364929 ps
CPU time 4.27 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 215208 kb
Host smart-0722b76b-bcb5-4968-881b-a1da09c043c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072074366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4072074366
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2876869616
Short name T387
Test name
Test status
Simulation time 372880460 ps
CPU time 7.27 seconds
Started May 21 02:57:08 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 220700 kb
Host smart-713f3e2b-49fc-4f92-aebe-8673d2e9842d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876869616 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2876869616
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2937682137
Short name T8
Test name
Test status
Simulation time 440199956 ps
CPU time 2.23 seconds
Started May 21 02:54:53 PM PDT 24
Finished May 21 02:54:57 PM PDT 24
Peak memory 210032 kb
Host smart-4ee91a87-3324-450e-afa2-19bd8de0b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937682137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2937682137
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.350941584
Short name T181
Test name
Test status
Simulation time 114148701 ps
CPU time 4.23 seconds
Started May 21 02:55:31 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 218256 kb
Host smart-e556472b-a696-4dff-9788-13a43e6e9a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350941584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.350941584
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.607185616
Short name T67
Test name
Test status
Simulation time 164477069 ps
CPU time 8.5 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 222760 kb
Host smart-0193c8ed-6342-4e6b-8932-389ff48a5c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607185616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.607185616
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1455917635
Short name T973
Test name
Test status
Simulation time 546979539 ps
CPU time 8 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:25 PM PDT 24
Peak memory 205784 kb
Host smart-9aa16b1d-e8fb-489e-92bb-f104bf338b4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455917635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
455917635
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1991782053
Short name T1025
Test name
Test status
Simulation time 256085885 ps
CPU time 6.24 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:25 PM PDT 24
Peak memory 205792 kb
Host smart-6025aae8-5d67-4a63-832e-f8069a009802
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991782053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
991782053
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3767363071
Short name T927
Test name
Test status
Simulation time 39790196 ps
CPU time 1.1 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 205764 kb
Host smart-3d682d27-71e1-4db3-9cda-3f4bd84f3d9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767363071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
767363071
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3894642471
Short name T949
Test name
Test status
Simulation time 41914104 ps
CPU time 1.9 seconds
Started May 21 02:25:16 PM PDT 24
Finished May 21 02:25:19 PM PDT 24
Peak memory 222168 kb
Host smart-f0dae5b5-ddc0-45f7-b706-429c1662bfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894642471 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3894642471
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2258145164
Short name T147
Test name
Test status
Simulation time 18147857 ps
CPU time 1.02 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 205656 kb
Host smart-b6ecf58b-45fc-4562-ae04-ea5f430b5924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258145164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2258145164
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3652716131
Short name T1042
Test name
Test status
Simulation time 15167347 ps
CPU time 0.89 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 205600 kb
Host smart-f318aa8d-1161-4f85-af2a-6d75703c1e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652716131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3652716131
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2300866092
Short name T986
Test name
Test status
Simulation time 38794284 ps
CPU time 2.57 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 205780 kb
Host smart-3ebe8d5c-2e94-4397-a33b-8f2fde24efa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300866092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2300866092
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3861049019
Short name T1044
Test name
Test status
Simulation time 276449866 ps
CPU time 2.23 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:21 PM PDT 24
Peak memory 214424 kb
Host smart-d12c91b2-8034-4f00-a1a1-87797891955d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861049019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3861049019
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.362309609
Short name T1064
Test name
Test status
Simulation time 171878645 ps
CPU time 2.26 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:21 PM PDT 24
Peak memory 214024 kb
Host smart-560daf96-6ddd-498c-b946-07980fdde6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362309609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.362309609
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3885895238
Short name T1058
Test name
Test status
Simulation time 53806291 ps
CPU time 3.02 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:21 PM PDT 24
Peak memory 214012 kb
Host smart-0d92584a-ef27-4c47-b713-c2579d15fb61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885895238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3885895238
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3835541014
Short name T1062
Test name
Test status
Simulation time 252027203 ps
CPU time 8.73 seconds
Started May 21 02:25:22 PM PDT 24
Finished May 21 02:25:32 PM PDT 24
Peak memory 205856 kb
Host smart-95131603-3734-4da3-9d23-d2d1d38fd0f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835541014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
835541014
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.118877137
Short name T1022
Test name
Test status
Simulation time 450190362 ps
CPU time 7.96 seconds
Started May 21 02:25:23 PM PDT 24
Finished May 21 02:25:32 PM PDT 24
Peak memory 205840 kb
Host smart-df01f2bf-31f0-49ea-ac73-abd20584a8c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118877137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.118877137
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2225672430
Short name T1000
Test name
Test status
Simulation time 82911545 ps
CPU time 0.94 seconds
Started May 21 02:25:23 PM PDT 24
Finished May 21 02:25:25 PM PDT 24
Peak memory 205660 kb
Host smart-b7c7e443-d8b1-4af8-aeee-126412c886ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225672430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
225672430
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.354716108
Short name T1074
Test name
Test status
Simulation time 22354670 ps
CPU time 1.5 seconds
Started May 21 02:25:25 PM PDT 24
Finished May 21 02:25:27 PM PDT 24
Peak memory 214052 kb
Host smart-35a9976e-4a25-4622-bf20-95f0dc5b10e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354716108 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.354716108
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1449762885
Short name T1009
Test name
Test status
Simulation time 110746356 ps
CPU time 1.2 seconds
Started May 21 02:25:23 PM PDT 24
Finished May 21 02:25:26 PM PDT 24
Peak memory 205848 kb
Host smart-77d7fb62-2276-4507-8fc1-c3562534a862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449762885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1449762885
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3803104269
Short name T923
Test name
Test status
Simulation time 19340465 ps
CPU time 0.76 seconds
Started May 21 02:25:26 PM PDT 24
Finished May 21 02:25:27 PM PDT 24
Peak memory 205440 kb
Host smart-ddf54e6e-b0d3-4e3e-a15d-9676dbd08a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803104269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3803104269
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4106197017
Short name T1046
Test name
Test status
Simulation time 91927695 ps
CPU time 2.98 seconds
Started May 21 02:25:26 PM PDT 24
Finished May 21 02:25:30 PM PDT 24
Peak memory 214012 kb
Host smart-7206f9c5-cfde-4373-9a7b-45be4cfe1ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106197017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4106197017
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4032692195
Short name T1049
Test name
Test status
Simulation time 252248719 ps
CPU time 3.66 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:23 PM PDT 24
Peak memory 214340 kb
Host smart-415905f1-4a0a-4804-a3a9-4bc7dee8b833
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032692195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4032692195
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3777382659
Short name T129
Test name
Test status
Simulation time 197878879 ps
CPU time 7.71 seconds
Started May 21 02:25:16 PM PDT 24
Finished May 21 02:25:24 PM PDT 24
Peak memory 214432 kb
Host smart-e5931c4b-09d1-4566-9494-f7f061cd9271
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777382659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3777382659
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3738423255
Short name T976
Test name
Test status
Simulation time 187691708 ps
CPU time 1.77 seconds
Started May 21 02:25:24 PM PDT 24
Finished May 21 02:25:27 PM PDT 24
Peak memory 213964 kb
Host smart-7f163371-29ad-429d-9874-1c292f6396b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738423255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3738423255
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3369732591
Short name T1031
Test name
Test status
Simulation time 118070982 ps
CPU time 5.15 seconds
Started May 21 02:25:23 PM PDT 24
Finished May 21 02:25:29 PM PDT 24
Peak memory 213980 kb
Host smart-f3034da9-2b4e-4378-86f8-7167b7fb0fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369732591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3369732591
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3151124547
Short name T1056
Test name
Test status
Simulation time 51322694 ps
CPU time 1.53 seconds
Started May 21 02:25:53 PM PDT 24
Finished May 21 02:25:56 PM PDT 24
Peak memory 213996 kb
Host smart-7e45e7ac-261b-426a-bea7-8357e1c2289b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151124547 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3151124547
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1221262542
Short name T991
Test name
Test status
Simulation time 32690463 ps
CPU time 0.88 seconds
Started May 21 02:25:55 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 205600 kb
Host smart-866b3d5e-c741-4f8a-9558-3a86c4d544eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221262542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1221262542
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1422500972
Short name T1045
Test name
Test status
Simulation time 35714336 ps
CPU time 0.75 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:56 PM PDT 24
Peak memory 205544 kb
Host smart-d48bf0c9-6852-48c9-ae57-804a27994fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422500972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1422500972
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.79283029
Short name T965
Test name
Test status
Simulation time 116984652 ps
CPU time 2.47 seconds
Started May 21 02:25:53 PM PDT 24
Finished May 21 02:25:56 PM PDT 24
Peak memory 205800 kb
Host smart-2812f467-c875-49a4-bf15-63cc2e92f0f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79283029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sam
e_csr_outstanding.79283029
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.922808888
Short name T1010
Test name
Test status
Simulation time 183152050 ps
CPU time 3.54 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:26:02 PM PDT 24
Peak memory 214348 kb
Host smart-ebf00736-65ae-40e1-bb67-266e0f33ab86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922808888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.922808888
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2435254725
Short name T1011
Test name
Test status
Simulation time 255364007 ps
CPU time 7.42 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:26:03 PM PDT 24
Peak memory 220384 kb
Host smart-08c1a32a-ad9a-4a8a-ae77-461b7ced04b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435254725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2435254725
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1007236265
Short name T920
Test name
Test status
Simulation time 47771772 ps
CPU time 2.06 seconds
Started May 21 02:25:56 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 213900 kb
Host smart-8405fccd-57c2-4dc6-b4b6-f49c3223eeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007236265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1007236265
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.57340621
Short name T166
Test name
Test status
Simulation time 984529042 ps
CPU time 4.78 seconds
Started May 21 02:25:52 PM PDT 24
Finished May 21 02:25:58 PM PDT 24
Peak memory 213832 kb
Host smart-b0798aca-7888-49b3-8639-47ad633832b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57340621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.57340621
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.683552190
Short name T944
Test name
Test status
Simulation time 87734064 ps
CPU time 1.94 seconds
Started May 21 02:25:56 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 214008 kb
Host smart-c58ec6d6-22ed-4bf5-aa07-ab22a2d23898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683552190 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.683552190
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3333675163
Short name T1036
Test name
Test status
Simulation time 73617574 ps
CPU time 1.09 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:56 PM PDT 24
Peak memory 205628 kb
Host smart-cc3a7b4a-2ca9-4341-b364-fe3daba65c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333675163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3333675163
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3846565210
Short name T1038
Test name
Test status
Simulation time 11951697 ps
CPU time 0.86 seconds
Started May 21 02:25:53 PM PDT 24
Finished May 21 02:25:55 PM PDT 24
Peak memory 205468 kb
Host smart-b7567671-b51d-4bdc-a4d7-782f4fdb01dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846565210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3846565210
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2376119545
Short name T1080
Test name
Test status
Simulation time 80734653 ps
CPU time 1.44 seconds
Started May 21 02:25:55 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 205788 kb
Host smart-3364eab6-3f65-4de7-9dff-1a51b880970a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376119545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2376119545
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3890152205
Short name T1078
Test name
Test status
Simulation time 297899166 ps
CPU time 2.31 seconds
Started May 21 02:25:52 PM PDT 24
Finished May 21 02:25:55 PM PDT 24
Peak memory 214288 kb
Host smart-bcb2321f-9837-430d-8cc7-a1dc9ff0f901
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890152205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3890152205
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1802143116
Short name T1053
Test name
Test status
Simulation time 897150574 ps
CPU time 5.12 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:26:03 PM PDT 24
Peak memory 214352 kb
Host smart-a829ae82-69fa-4967-808e-aa05e841aa9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802143116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1802143116
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2938385465
Short name T1065
Test name
Test status
Simulation time 91888268 ps
CPU time 2.3 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:58 PM PDT 24
Peak memory 213976 kb
Host smart-b5393439-1d71-416a-8bd8-628f8ce3667d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938385465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2938385465
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2948344064
Short name T952
Test name
Test status
Simulation time 21227840 ps
CPU time 1.64 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:03 PM PDT 24
Peak memory 214020 kb
Host smart-084f431a-3b20-4eb3-a330-048b6b5e9ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948344064 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2948344064
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.105072771
Short name T971
Test name
Test status
Simulation time 28449852 ps
CPU time 1.72 seconds
Started May 21 02:26:01 PM PDT 24
Finished May 21 02:26:04 PM PDT 24
Peak memory 205624 kb
Host smart-a142296b-de1c-4716-beee-5fdcf9608359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105072771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.105072771
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2611311444
Short name T1003
Test name
Test status
Simulation time 20457620 ps
CPU time 0.71 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:01 PM PDT 24
Peak memory 205508 kb
Host smart-263a47ad-6187-42c3-9e6d-1b446fe0ab5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611311444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2611311444
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2370288536
Short name T1047
Test name
Test status
Simulation time 47876863 ps
CPU time 1.81 seconds
Started May 21 02:26:01 PM PDT 24
Finished May 21 02:26:04 PM PDT 24
Peak memory 205792 kb
Host smart-23ee91f1-070e-4db3-aaf8-ad1aa85340ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370288536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2370288536
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1888863881
Short name T981
Test name
Test status
Simulation time 893879956 ps
CPU time 12.58 seconds
Started May 21 02:25:59 PM PDT 24
Finished May 21 02:26:12 PM PDT 24
Peak memory 214364 kb
Host smart-a6c2c06d-794f-45ba-b06c-cc25144b8dbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888863881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1888863881
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1953883264
Short name T995
Test name
Test status
Simulation time 427719903 ps
CPU time 3.86 seconds
Started May 21 02:26:01 PM PDT 24
Finished May 21 02:26:06 PM PDT 24
Peak memory 213980 kb
Host smart-238eb761-db9b-4a94-ad93-2d79734bb66e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953883264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1953883264
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1592748219
Short name T964
Test name
Test status
Simulation time 50597058 ps
CPU time 2.33 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:03 PM PDT 24
Peak memory 214032 kb
Host smart-4f3f618c-7e8d-451f-b780-8dc1d308b7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592748219 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1592748219
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1629725680
Short name T975
Test name
Test status
Simulation time 61489193 ps
CPU time 0.93 seconds
Started May 21 02:25:59 PM PDT 24
Finished May 21 02:26:01 PM PDT 24
Peak memory 205648 kb
Host smart-4c1b5392-64ac-4c79-a65a-b8ad9b553cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629725680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1629725680
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3191237536
Short name T1029
Test name
Test status
Simulation time 89707336 ps
CPU time 0.68 seconds
Started May 21 02:25:59 PM PDT 24
Finished May 21 02:26:01 PM PDT 24
Peak memory 205504 kb
Host smart-7d42bff7-2311-466f-b8d9-eece943112db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191237536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3191237536
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1067066098
Short name T205
Test name
Test status
Simulation time 218853102 ps
CPU time 2.9 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:03 PM PDT 24
Peak memory 205824 kb
Host smart-fd1f7bb1-8d63-472d-8842-9c68f5c06db2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067066098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1067066098
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1165513247
Short name T126
Test name
Test status
Simulation time 268475084 ps
CPU time 2.55 seconds
Started May 21 02:25:59 PM PDT 24
Finished May 21 02:26:02 PM PDT 24
Peak memory 214292 kb
Host smart-5ae4255f-4436-43cb-bff4-952be2c2551e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165513247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1165513247
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2407328436
Short name T943
Test name
Test status
Simulation time 1661267541 ps
CPU time 14.67 seconds
Started May 21 02:26:00 PM PDT 24
Finished May 21 02:26:15 PM PDT 24
Peak memory 214344 kb
Host smart-65fe90d4-b879-4962-ae54-7931b0e43608
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407328436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2407328436
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.7752383
Short name T997
Test name
Test status
Simulation time 26892563 ps
CPU time 1.89 seconds
Started May 21 02:26:02 PM PDT 24
Finished May 21 02:26:04 PM PDT 24
Peak memory 205792 kb
Host smart-fa030ece-a47e-452d-a584-d4a42cf1bdd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7752383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.7752383
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2770947663
Short name T968
Test name
Test status
Simulation time 16052363 ps
CPU time 1.07 seconds
Started May 21 02:26:10 PM PDT 24
Finished May 21 02:26:12 PM PDT 24
Peak memory 205712 kb
Host smart-8a6021e2-1a3f-442a-9e42-fb3bba60d941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770947663 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2770947663
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1302927964
Short name T1005
Test name
Test status
Simulation time 21089225 ps
CPU time 1.2 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:16 PM PDT 24
Peak memory 205928 kb
Host smart-e0709489-b0f9-445b-9ea4-4cde58f53e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302927964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1302927964
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3190797816
Short name T1027
Test name
Test status
Simulation time 13069665 ps
CPU time 0.73 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:14 PM PDT 24
Peak memory 205456 kb
Host smart-b06fbe1a-0904-41e9-a531-c7949386505e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190797816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3190797816
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3361913885
Short name T152
Test name
Test status
Simulation time 90540778 ps
CPU time 1.81 seconds
Started May 21 02:26:10 PM PDT 24
Finished May 21 02:26:13 PM PDT 24
Peak memory 205800 kb
Host smart-1960d390-75e9-41be-9667-1aacc17905a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361913885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3361913885
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2727339399
Short name T122
Test name
Test status
Simulation time 353043093 ps
CPU time 1.97 seconds
Started May 21 02:26:09 PM PDT 24
Finished May 21 02:26:11 PM PDT 24
Peak memory 214352 kb
Host smart-70c3a913-ba79-4aa2-a541-d73f69bf1d92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727339399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2727339399
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3480381987
Short name T1059
Test name
Test status
Simulation time 441924200 ps
CPU time 5.11 seconds
Started May 21 02:26:10 PM PDT 24
Finished May 21 02:26:17 PM PDT 24
Peak memory 214464 kb
Host smart-dbfef9af-f0dd-4063-9c79-765d2067f57c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480381987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3480381987
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.55891515
Short name T1007
Test name
Test status
Simulation time 274096065 ps
CPU time 3.59 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:17 PM PDT 24
Peak memory 213964 kb
Host smart-5ee26c87-51f6-49ba-aa59-d6453d74eacf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55891515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.55891515
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3708136936
Short name T162
Test name
Test status
Simulation time 241937454 ps
CPU time 6.79 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 213912 kb
Host smart-e7e5d902-6d76-4944-8ead-e36e9c074bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708136936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3708136936
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3872274948
Short name T1068
Test name
Test status
Simulation time 28580457 ps
CPU time 1.06 seconds
Started May 21 02:26:09 PM PDT 24
Finished May 21 02:26:11 PM PDT 24
Peak memory 214056 kb
Host smart-7eb6bc02-22ee-4029-b475-b407425ced19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872274948 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3872274948
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3430011728
Short name T978
Test name
Test status
Simulation time 96227291 ps
CPU time 1.25 seconds
Started May 21 02:26:08 PM PDT 24
Finished May 21 02:26:10 PM PDT 24
Peak memory 205744 kb
Host smart-d16dfd72-4c51-4419-97c4-ee3a495beb01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430011728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3430011728
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.833519031
Short name T1018
Test name
Test status
Simulation time 15963843 ps
CPU time 0.83 seconds
Started May 21 02:26:11 PM PDT 24
Finished May 21 02:26:13 PM PDT 24
Peak memory 205540 kb
Host smart-fa217d24-0284-4dea-841f-8549f4a6a3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833519031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.833519031
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.405845338
Short name T946
Test name
Test status
Simulation time 1457662868 ps
CPU time 2.78 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:16 PM PDT 24
Peak memory 205788 kb
Host smart-5020594d-f202-4af9-b9bb-46f0236ec210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405845338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.405845338
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2770004845
Short name T125
Test name
Test status
Simulation time 146717546 ps
CPU time 2.02 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:17 PM PDT 24
Peak memory 214404 kb
Host smart-dba71405-4261-4b30-a293-e84426da7362
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770004845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2770004845
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1623057362
Short name T966
Test name
Test status
Simulation time 746018859 ps
CPU time 9.22 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:23 PM PDT 24
Peak memory 214408 kb
Host smart-142ef6a1-6be4-431a-a036-e5be3e7f9af9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623057362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1623057362
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4069762023
Short name T954
Test name
Test status
Simulation time 22499264 ps
CPU time 1.62 seconds
Started May 21 02:26:11 PM PDT 24
Finished May 21 02:26:14 PM PDT 24
Peak memory 213928 kb
Host smart-a51fc6bd-b6ca-4e98-b6cc-aa1acdde5ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069762023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4069762023
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2002087003
Short name T921
Test name
Test status
Simulation time 44407005 ps
CPU time 1.15 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:16 PM PDT 24
Peak memory 205792 kb
Host smart-ed7304a7-976c-4153-a3e9-fdecb0662def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002087003 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2002087003
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2221492313
Short name T146
Test name
Test status
Simulation time 99127450 ps
CPU time 0.92 seconds
Started May 21 02:26:12 PM PDT 24
Finished May 21 02:26:15 PM PDT 24
Peak memory 205536 kb
Host smart-371d9c16-b849-46a1-a4c0-05e79fda2ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221492313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2221492313
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2229967468
Short name T1077
Test name
Test status
Simulation time 18142302 ps
CPU time 0.75 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:16 PM PDT 24
Peak memory 205540 kb
Host smart-530449f7-8ff2-4004-9a7a-058ed9a4ed66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229967468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2229967468
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1351431054
Short name T936
Test name
Test status
Simulation time 351243407 ps
CPU time 2.43 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:18 PM PDT 24
Peak memory 205844 kb
Host smart-76c3017e-e06f-437e-aec8-f646a3c1bb6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351431054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1351431054
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.453644534
Short name T130
Test name
Test status
Simulation time 65840253 ps
CPU time 2.48 seconds
Started May 21 02:26:10 PM PDT 24
Finished May 21 02:26:13 PM PDT 24
Peak memory 214388 kb
Host smart-6ff5c650-c440-42b3-8c1f-a67d6f66e9a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453644534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.453644534
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3466966760
Short name T939
Test name
Test status
Simulation time 655071973 ps
CPU time 7.01 seconds
Started May 21 02:26:10 PM PDT 24
Finished May 21 02:26:18 PM PDT 24
Peak memory 214396 kb
Host smart-a723c69f-7f70-4620-a37f-c31deca7d91a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466966760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3466966760
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.983684724
Short name T1057
Test name
Test status
Simulation time 475861227 ps
CPU time 2.99 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:19 PM PDT 24
Peak memory 213948 kb
Host smart-d827c38b-9318-4a7e-9a70-26a4a846dece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983684724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.983684724
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.940972725
Short name T169
Test name
Test status
Simulation time 579121651 ps
CPU time 7.03 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:22 PM PDT 24
Peak memory 205796 kb
Host smart-7fc0ff37-ad17-4a28-a880-1310373a6fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940972725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.940972725
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3003247882
Short name T924
Test name
Test status
Simulation time 16714934 ps
CPU time 1.02 seconds
Started May 21 02:26:11 PM PDT 24
Finished May 21 02:26:13 PM PDT 24
Peak memory 205656 kb
Host smart-dda3b857-eaf9-4d33-abbd-d00be6ba1bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003247882 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3003247882
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3294660188
Short name T982
Test name
Test status
Simulation time 31325764 ps
CPU time 1.21 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:17 PM PDT 24
Peak memory 205808 kb
Host smart-b10c56dd-e265-457a-9a42-620872b855af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294660188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3294660188
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3839935426
Short name T967
Test name
Test status
Simulation time 12422701 ps
CPU time 0.8 seconds
Started May 21 02:26:15 PM PDT 24
Finished May 21 02:26:18 PM PDT 24
Peak memory 205440 kb
Host smart-34e15a44-5d13-4bd9-9472-9ab1575d7365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839935426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3839935426
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3823033784
Short name T1066
Test name
Test status
Simulation time 172076635 ps
CPU time 1.6 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:18 PM PDT 24
Peak memory 205808 kb
Host smart-14d01f13-b12a-4fcb-9106-e932ea25d53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823033784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3823033784
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2397871125
Short name T120
Test name
Test status
Simulation time 205595667 ps
CPU time 1.79 seconds
Started May 21 02:26:15 PM PDT 24
Finished May 21 02:26:19 PM PDT 24
Peak memory 214356 kb
Host smart-168a65ab-7587-406d-af91-c47920aa6f41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397871125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2397871125
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.245627583
Short name T1072
Test name
Test status
Simulation time 115142189 ps
CPU time 4.12 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 220316 kb
Host smart-a9ea4fb0-437c-48c0-b42b-f23085f3a8b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245627583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.245627583
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2618392539
Short name T953
Test name
Test status
Simulation time 443749397 ps
CPU time 4.11 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 213916 kb
Host smart-d8528b61-18b8-4abb-bdf4-cc04c7c58e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618392539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2618392539
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2788769649
Short name T157
Test name
Test status
Simulation time 426980971 ps
CPU time 4.91 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 214044 kb
Host smart-a08f2213-7cb6-4886-9bd0-c50ac5219c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788769649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2788769649
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.802659730
Short name T929
Test name
Test status
Simulation time 177298615 ps
CPU time 1.06 seconds
Started May 21 02:26:17 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 205648 kb
Host smart-14b5c813-2ccd-4016-9ec8-0b00f13ee5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802659730 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.802659730
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1081314259
Short name T148
Test name
Test status
Simulation time 14140286 ps
CPU time 0.93 seconds
Started May 21 02:26:17 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 205652 kb
Host smart-e28b3b39-b634-4a95-8f72-0771e5e4258e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081314259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1081314259
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3181428987
Short name T918
Test name
Test status
Simulation time 8967514 ps
CPU time 0.71 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:16 PM PDT 24
Peak memory 205448 kb
Host smart-ce5fe557-eff5-4585-9b7e-123f09e6125a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181428987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3181428987
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4275254069
Short name T977
Test name
Test status
Simulation time 59009110 ps
CPU time 1.65 seconds
Started May 21 02:26:17 PM PDT 24
Finished May 21 02:26:21 PM PDT 24
Peak memory 205780 kb
Host smart-622f73d6-a6e2-48a6-93c2-c086cfb0ea44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275254069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4275254069
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.840494234
Short name T999
Test name
Test status
Simulation time 119617070 ps
CPU time 2.52 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:19 PM PDT 24
Peak memory 214336 kb
Host smart-4fb5f0fc-a531-44bf-8f88-2870c31c675a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840494234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.840494234
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3318044489
Short name T974
Test name
Test status
Simulation time 864655798 ps
CPU time 8.23 seconds
Started May 21 02:26:13 PM PDT 24
Finished May 21 02:26:24 PM PDT 24
Peak memory 222520 kb
Host smart-cbcd6975-1597-4f17-86dc-0779fa6689f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318044489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3318044489
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1953128051
Short name T1052
Test name
Test status
Simulation time 82146348 ps
CPU time 1.79 seconds
Started May 21 02:26:14 PM PDT 24
Finished May 21 02:26:18 PM PDT 24
Peak memory 214036 kb
Host smart-bf5aeb0e-41f9-4749-a9fe-45e31ff871eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953128051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1953128051
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4092486389
Short name T173
Test name
Test status
Simulation time 297960964 ps
CPU time 10.55 seconds
Started May 21 02:26:16 PM PDT 24
Finished May 21 02:26:28 PM PDT 24
Peak memory 213972 kb
Host smart-68b1dae3-127f-47fa-885c-6ab2b46bbf38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092486389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4092486389
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3667777269
Short name T1081
Test name
Test status
Simulation time 34342524 ps
CPU time 1.3 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:21 PM PDT 24
Peak memory 213972 kb
Host smart-0bf7de2f-0389-4e59-811a-a74378dd982c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667777269 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3667777269
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3305836469
Short name T969
Test name
Test status
Simulation time 247961577 ps
CPU time 1.06 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 205668 kb
Host smart-0806ae95-3045-4bab-9719-62534dcae6fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305836469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3305836469
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4027084954
Short name T951
Test name
Test status
Simulation time 46090004 ps
CPU time 0.72 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:21 PM PDT 24
Peak memory 205428 kb
Host smart-c8a21889-53a7-4799-ac35-70216bedcb40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027084954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4027084954
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2626936134
Short name T940
Test name
Test status
Simulation time 155508165 ps
CPU time 2.46 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:22 PM PDT 24
Peak memory 205708 kb
Host smart-1c493cb5-d80e-48a2-8d24-f308c5ed2940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626936134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2626936134
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3550221108
Short name T1006
Test name
Test status
Simulation time 344884077 ps
CPU time 3.62 seconds
Started May 21 02:26:17 PM PDT 24
Finished May 21 02:26:22 PM PDT 24
Peak memory 214320 kb
Host smart-56912374-f321-4231-9abe-ddeb000b4a7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550221108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3550221108
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2536299911
Short name T127
Test name
Test status
Simulation time 523977522 ps
CPU time 4.14 seconds
Started May 21 02:26:17 PM PDT 24
Finished May 21 02:26:23 PM PDT 24
Peak memory 214252 kb
Host smart-f7c22c7b-2f36-44f1-8965-36062da5f4ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536299911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2536299911
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3121851895
Short name T1063
Test name
Test status
Simulation time 30231671 ps
CPU time 1.98 seconds
Started May 21 02:26:19 PM PDT 24
Finished May 21 02:26:22 PM PDT 24
Peak memory 213996 kb
Host smart-d90b6ff5-603d-4e1b-9514-e72191771a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121851895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3121851895
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.577819125
Short name T1023
Test name
Test status
Simulation time 490386767 ps
CPU time 7.47 seconds
Started May 21 02:25:31 PM PDT 24
Finished May 21 02:25:39 PM PDT 24
Peak memory 205788 kb
Host smart-951c5240-7a85-45a6-a0d0-181dbe417765
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577819125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.577819125
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.652094326
Short name T960
Test name
Test status
Simulation time 25501700782 ps
CPU time 19.13 seconds
Started May 21 02:25:25 PM PDT 24
Finished May 21 02:25:45 PM PDT 24
Peak memory 205868 kb
Host smart-25ef8eb8-2c91-43dd-bd73-abe9c9a5a0e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652094326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.652094326
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3064633144
Short name T922
Test name
Test status
Simulation time 49696637 ps
CPU time 1.31 seconds
Started May 21 02:25:23 PM PDT 24
Finished May 21 02:25:25 PM PDT 24
Peak memory 205784 kb
Host smart-5bf71363-bdd5-4216-a5d2-6a3b8e9fb953
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064633144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
064633144
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.603199290
Short name T1037
Test name
Test status
Simulation time 171888552 ps
CPU time 1.65 seconds
Started May 21 02:25:27 PM PDT 24
Finished May 21 02:25:30 PM PDT 24
Peak memory 213980 kb
Host smart-901759c4-4ba3-4bcb-87df-d55b8bcbc40e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603199290 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.603199290
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2076236666
Short name T970
Test name
Test status
Simulation time 33730291 ps
CPU time 1.61 seconds
Started May 21 02:25:25 PM PDT 24
Finished May 21 02:25:28 PM PDT 24
Peak memory 205736 kb
Host smart-34bb528c-d943-42fc-b4dd-73ff660836f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076236666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2076236666
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3711117609
Short name T983
Test name
Test status
Simulation time 56640492 ps
CPU time 0.7 seconds
Started May 21 02:25:25 PM PDT 24
Finished May 21 02:25:27 PM PDT 24
Peak memory 205456 kb
Host smart-c4152656-bf57-4d4d-9d4d-68cafbdbc5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711117609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3711117609
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3663499936
Short name T1054
Test name
Test status
Simulation time 338877353 ps
CPU time 2.52 seconds
Started May 21 02:25:30 PM PDT 24
Finished May 21 02:25:34 PM PDT 24
Peak memory 205756 kb
Host smart-c33dc4ae-5540-4429-84e7-9ac93cde939b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663499936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3663499936
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.418314439
Short name T119
Test name
Test status
Simulation time 342544125 ps
CPU time 6.5 seconds
Started May 21 02:25:25 PM PDT 24
Finished May 21 02:25:32 PM PDT 24
Peak memory 220272 kb
Host smart-8be1a515-d8e9-40ab-b627-43f0d421947c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418314439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.418314439
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4126459511
Short name T1024
Test name
Test status
Simulation time 278123638 ps
CPU time 4.48 seconds
Started May 21 02:25:22 PM PDT 24
Finished May 21 02:25:28 PM PDT 24
Peak memory 213980 kb
Host smart-ed554724-77db-41de-8ebe-ed7e741fae86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126459511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4126459511
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2627993926
Short name T164
Test name
Test status
Simulation time 176262836 ps
CPU time 5.06 seconds
Started May 21 02:25:21 PM PDT 24
Finished May 21 02:25:27 PM PDT 24
Peak memory 213876 kb
Host smart-4acc57ef-4f05-4448-9742-79e4feb442e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627993926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2627993926
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2597957598
Short name T1041
Test name
Test status
Simulation time 71874095 ps
CPU time 0.78 seconds
Started May 21 02:26:18 PM PDT 24
Finished May 21 02:26:20 PM PDT 24
Peak memory 205532 kb
Host smart-101f5e6d-3980-4bb7-8fc0-3de8e983aac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597957598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2597957598
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1988717062
Short name T1061
Test name
Test status
Simulation time 17278490 ps
CPU time 0.72 seconds
Started May 21 02:26:19 PM PDT 24
Finished May 21 02:26:21 PM PDT 24
Peak memory 205512 kb
Host smart-5ae85a69-2370-4265-a44b-e6b4d0ef5dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988717062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1988717062
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1175355838
Short name T1021
Test name
Test status
Simulation time 34584186 ps
CPU time 0.87 seconds
Started May 21 02:26:23 PM PDT 24
Finished May 21 02:26:24 PM PDT 24
Peak memory 205528 kb
Host smart-80623d6a-7ea0-49c2-8dec-501480e2a7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175355838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1175355838
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2941342201
Short name T1079
Test name
Test status
Simulation time 47225103 ps
CPU time 0.76 seconds
Started May 21 02:26:26 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205532 kb
Host smart-c79644d0-5fd7-434b-b9ab-f0abf586c496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941342201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2941342201
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2804079362
Short name T1070
Test name
Test status
Simulation time 118279241 ps
CPU time 0.77 seconds
Started May 21 02:26:24 PM PDT 24
Finished May 21 02:26:26 PM PDT 24
Peak memory 205548 kb
Host smart-4e439004-7bdb-45c2-b581-bf995aa0345d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804079362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2804079362
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.465755285
Short name T1055
Test name
Test status
Simulation time 160154445 ps
CPU time 0.76 seconds
Started May 21 02:26:26 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205456 kb
Host smart-abd54888-ebb9-4983-beed-797dd99478c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465755285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.465755285
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4123818608
Short name T1032
Test name
Test status
Simulation time 21524904 ps
CPU time 0.73 seconds
Started May 21 02:26:26 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205528 kb
Host smart-b9ce6bd1-782d-440a-83c5-319f2d7e6ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123818608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4123818608
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4042315391
Short name T979
Test name
Test status
Simulation time 68207572 ps
CPU time 0.71 seconds
Started May 21 02:26:26 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205532 kb
Host smart-06d67cb1-5f0e-4e9c-8330-b333c954aa49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042315391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4042315391
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2299165177
Short name T914
Test name
Test status
Simulation time 27540274 ps
CPU time 0.69 seconds
Started May 21 02:26:24 PM PDT 24
Finished May 21 02:26:26 PM PDT 24
Peak memory 205528 kb
Host smart-72e882b3-58bf-4fb5-b4b4-41991a3e9d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299165177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2299165177
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1357112840
Short name T961
Test name
Test status
Simulation time 13697885 ps
CPU time 0.72 seconds
Started May 21 02:26:24 PM PDT 24
Finished May 21 02:26:26 PM PDT 24
Peak memory 205528 kb
Host smart-5055a3f1-db4f-4242-bb85-4f1e4b178507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357112840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1357112840
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2672187181
Short name T1035
Test name
Test status
Simulation time 266601251 ps
CPU time 3.78 seconds
Started May 21 02:25:30 PM PDT 24
Finished May 21 02:25:35 PM PDT 24
Peak memory 205728 kb
Host smart-afead39e-b72e-4174-80f7-4cef0606e4ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672187181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
672187181
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3379771830
Short name T1004
Test name
Test status
Simulation time 3903653486 ps
CPU time 16.02 seconds
Started May 21 02:25:30 PM PDT 24
Finished May 21 02:25:47 PM PDT 24
Peak memory 205824 kb
Host smart-9ec0359e-f898-41ec-a62f-14b24c5bcdd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379771830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
379771830
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3796179601
Short name T937
Test name
Test status
Simulation time 247117102 ps
CPU time 1.11 seconds
Started May 21 02:25:31 PM PDT 24
Finished May 21 02:25:33 PM PDT 24
Peak memory 205796 kb
Host smart-1bc3ea6b-e9c8-4a23-837f-33594552d1aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796179601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
796179601
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2477694142
Short name T1040
Test name
Test status
Simulation time 67941758 ps
CPU time 1.26 seconds
Started May 21 02:25:31 PM PDT 24
Finished May 21 02:25:33 PM PDT 24
Peak memory 214104 kb
Host smart-96e21a42-9da4-4d12-8bdb-112ffc70a392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477694142 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2477694142
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.696687765
Short name T1050
Test name
Test status
Simulation time 15229154 ps
CPU time 1.14 seconds
Started May 21 02:25:33 PM PDT 24
Finished May 21 02:25:34 PM PDT 24
Peak memory 205712 kb
Host smart-6a3979dd-1183-4527-9c6b-b65c17a9c383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696687765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.696687765
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2598106898
Short name T985
Test name
Test status
Simulation time 31753209 ps
CPU time 0.71 seconds
Started May 21 02:25:29 PM PDT 24
Finished May 21 02:25:31 PM PDT 24
Peak memory 205552 kb
Host smart-06b6a2c0-8e0a-46dd-8fad-c5f222dc8725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598106898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2598106898
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.913926983
Short name T150
Test name
Test status
Simulation time 488580082 ps
CPU time 4.56 seconds
Started May 21 02:25:29 PM PDT 24
Finished May 21 02:25:35 PM PDT 24
Peak memory 205776 kb
Host smart-bdfee6de-1a5c-44fc-ae3e-0af51a4cfbef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913926983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.913926983
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.338720897
Short name T980
Test name
Test status
Simulation time 416805735 ps
CPU time 3.49 seconds
Started May 21 02:25:29 PM PDT 24
Finished May 21 02:25:34 PM PDT 24
Peak memory 214384 kb
Host smart-8e3e2ce9-cc3d-4aff-b2b7-2dfd63e5eed4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338720897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.338720897
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2433893564
Short name T933
Test name
Test status
Simulation time 672066890 ps
CPU time 4.37 seconds
Started May 21 02:25:31 PM PDT 24
Finished May 21 02:25:36 PM PDT 24
Peak memory 214440 kb
Host smart-bb4250d3-8db9-4bc6-9810-b8e57b838aa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433893564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2433893564
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.791861739
Short name T1034
Test name
Test status
Simulation time 27317879 ps
CPU time 2.21 seconds
Started May 21 02:25:29 PM PDT 24
Finished May 21 02:25:32 PM PDT 24
Peak memory 217348 kb
Host smart-e7770af4-49b3-477b-81c1-7667b28a8e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791861739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.791861739
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1051361890
Short name T941
Test name
Test status
Simulation time 12217520 ps
CPU time 0.89 seconds
Started May 21 02:26:25 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205436 kb
Host smart-a6872d81-25b5-4a2b-9f81-5f3cf922fc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051361890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1051361890
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.141801645
Short name T942
Test name
Test status
Simulation time 17319263 ps
CPU time 0.79 seconds
Started May 21 02:26:26 PM PDT 24
Finished May 21 02:26:27 PM PDT 24
Peak memory 205540 kb
Host smart-213e34da-bdbc-4ae5-b56f-b46188c9c8c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141801645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.141801645
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.108956492
Short name T1067
Test name
Test status
Simulation time 41228399 ps
CPU time 0.72 seconds
Started May 21 02:26:28 PM PDT 24
Finished May 21 02:26:30 PM PDT 24
Peak memory 205444 kb
Host smart-3a1d2ed6-410b-4364-836f-f6d52aa7a6e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108956492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.108956492
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3115459751
Short name T987
Test name
Test status
Simulation time 42369556 ps
CPU time 0.87 seconds
Started May 21 02:26:31 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 205452 kb
Host smart-5112f42c-3972-44a3-8c4f-fde1e143aab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115459751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3115459751
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1264257977
Short name T1026
Test name
Test status
Simulation time 28996631 ps
CPU time 0.68 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205456 kb
Host smart-f7a3230e-4452-4a5c-8a72-4148c3badcf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264257977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1264257977
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.978268573
Short name T992
Test name
Test status
Simulation time 48128085 ps
CPU time 0.83 seconds
Started May 21 02:26:31 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 205504 kb
Host smart-71d22678-d69b-4de3-8a75-42caa27afd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978268573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.978268573
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4079221918
Short name T1039
Test name
Test status
Simulation time 11088762 ps
CPU time 0.74 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 205556 kb
Host smart-3265befc-c891-4fd1-b268-8a6823f33b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079221918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4079221918
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2343182370
Short name T950
Test name
Test status
Simulation time 10152822 ps
CPU time 0.81 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:31 PM PDT 24
Peak memory 205552 kb
Host smart-4881c3a8-7e55-4932-9d25-0d1ba8e8afa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343182370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2343182370
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1192895503
Short name T915
Test name
Test status
Simulation time 11368844 ps
CPU time 0.72 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205532 kb
Host smart-2504352a-ef49-45b8-83d6-02a41148a6bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192895503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1192895503
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2783847458
Short name T916
Test name
Test status
Simulation time 12021471 ps
CPU time 0.82 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205544 kb
Host smart-0fc763f4-d099-4712-94e4-71d9a6bba1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783847458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2783847458
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4208370088
Short name T1051
Test name
Test status
Simulation time 252616126 ps
CPU time 4.7 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:39 PM PDT 24
Peak memory 205824 kb
Host smart-9f2f0f72-ac68-471b-a503-903359c18d5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208370088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
208370088
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1492958964
Short name T1071
Test name
Test status
Simulation time 3589029916 ps
CPU time 26.13 seconds
Started May 21 02:25:35 PM PDT 24
Finished May 21 02:26:02 PM PDT 24
Peak memory 205868 kb
Host smart-960e9faa-6473-4003-b5ff-f5407aa8a8e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492958964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
492958964
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.306803339
Short name T1048
Test name
Test status
Simulation time 60245403 ps
CPU time 1.5 seconds
Started May 21 02:25:36 PM PDT 24
Finished May 21 02:25:38 PM PDT 24
Peak memory 205724 kb
Host smart-f1f94fa6-4d94-4002-bded-03f663bbf579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306803339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.306803339
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.658247261
Short name T932
Test name
Test status
Simulation time 86134722 ps
CPU time 1.63 seconds
Started May 21 02:25:35 PM PDT 24
Finished May 21 02:25:37 PM PDT 24
Peak memory 214112 kb
Host smart-40eba4b8-db2c-490e-8d54-a350ec0135d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658247261 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.658247261
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2138695342
Short name T153
Test name
Test status
Simulation time 41332301 ps
CPU time 1.61 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:36 PM PDT 24
Peak memory 205672 kb
Host smart-9ef01873-f09c-46ef-a1c7-7e903e1581e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138695342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2138695342
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2992232683
Short name T956
Test name
Test status
Simulation time 147599172 ps
CPU time 0.7 seconds
Started May 21 02:25:37 PM PDT 24
Finished May 21 02:25:38 PM PDT 24
Peak memory 205520 kb
Host smart-fbc280e3-6860-4242-b4e9-3aefc1b2ca3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992232683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2992232683
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1091547477
Short name T186
Test name
Test status
Simulation time 112809618 ps
CPU time 2.18 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:37 PM PDT 24
Peak memory 205856 kb
Host smart-2c7ecf17-ac84-4ee0-93fe-b802a504fef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091547477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1091547477
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3834897523
Short name T962
Test name
Test status
Simulation time 109200362 ps
CPU time 2.16 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:37 PM PDT 24
Peak memory 214268 kb
Host smart-1d7ea3a4-60d9-402f-b075-ad55f347dce6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834897523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3834897523
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2066674913
Short name T935
Test name
Test status
Simulation time 92132650 ps
CPU time 4.88 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:40 PM PDT 24
Peak memory 214336 kb
Host smart-229c2af0-745c-4d0c-99a2-366911f98d46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066674913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2066674913
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1596760645
Short name T1017
Test name
Test status
Simulation time 115360841 ps
CPU time 2.39 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:37 PM PDT 24
Peak memory 216268 kb
Host smart-c199ffea-5daf-4691-a7bd-e49c4094f1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596760645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1596760645
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.718098162
Short name T172
Test name
Test status
Simulation time 414843745 ps
CPU time 4.59 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:40 PM PDT 24
Peak memory 213968 kb
Host smart-fe3f62d1-fec5-478d-bbd8-de1adb1b1782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718098162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
718098162
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.174579125
Short name T998
Test name
Test status
Simulation time 16625293 ps
CPU time 0.94 seconds
Started May 21 02:26:29 PM PDT 24
Finished May 21 02:26:31 PM PDT 24
Peak memory 205624 kb
Host smart-bb092126-906d-4888-a77e-ec5b786aae3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174579125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.174579125
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3057236172
Short name T1060
Test name
Test status
Simulation time 63889331 ps
CPU time 0.71 seconds
Started May 21 02:26:28 PM PDT 24
Finished May 21 02:26:30 PM PDT 24
Peak memory 205516 kb
Host smart-b13340c0-ea3b-4309-8ab6-d256231c17bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057236172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3057236172
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2557499502
Short name T1001
Test name
Test status
Simulation time 9429931 ps
CPU time 0.73 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205512 kb
Host smart-8261cfd6-1b89-42bc-92d7-9d508c3d1833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557499502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2557499502
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1835500216
Short name T947
Test name
Test status
Simulation time 58220410 ps
CPU time 0.76 seconds
Started May 21 02:26:34 PM PDT 24
Finished May 21 02:26:35 PM PDT 24
Peak memory 205364 kb
Host smart-66ecdcc6-9c24-4178-a3d3-30eae38a3adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835500216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1835500216
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.65241959
Short name T988
Test name
Test status
Simulation time 12594108 ps
CPU time 0.84 seconds
Started May 21 02:26:31 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 205440 kb
Host smart-5ba364e8-56b2-432c-af4c-35dd7686d87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65241959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.65241959
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.832415390
Short name T1008
Test name
Test status
Simulation time 38414554 ps
CPU time 0.82 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205536 kb
Host smart-43f4fc2e-2e3e-4ebc-888e-f5e026779f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832415390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.832415390
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2837532448
Short name T957
Test name
Test status
Simulation time 31499327 ps
CPU time 0.82 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:31 PM PDT 24
Peak memory 205444 kb
Host smart-f9a1605f-ecd9-46ea-bdf6-c02211a362e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837532448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2837532448
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2707629051
Short name T938
Test name
Test status
Simulation time 15900903 ps
CPU time 0.92 seconds
Started May 21 02:26:31 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 205668 kb
Host smart-cb8d562c-27f8-4351-aced-4d1c983fefe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707629051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2707629051
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.397951295
Short name T945
Test name
Test status
Simulation time 8697592 ps
CPU time 0.83 seconds
Started May 21 02:26:30 PM PDT 24
Finished May 21 02:26:32 PM PDT 24
Peak memory 205560 kb
Host smart-1d196a5f-5415-4582-b89a-c10eadf802ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397951295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.397951295
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.609807566
Short name T1075
Test name
Test status
Simulation time 28317748 ps
CPU time 0.69 seconds
Started May 21 02:26:28 PM PDT 24
Finished May 21 02:26:30 PM PDT 24
Peak memory 205520 kb
Host smart-78377b82-a988-4abc-a4a6-15a4da4cb44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609807566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.609807566
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3043725596
Short name T1016
Test name
Test status
Simulation time 45024916 ps
CPU time 2.05 seconds
Started May 21 02:25:40 PM PDT 24
Finished May 21 02:25:43 PM PDT 24
Peak memory 214020 kb
Host smart-6f134e59-6a39-4b9a-969a-144c254498a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043725596 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3043725596
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2126615885
Short name T958
Test name
Test status
Simulation time 23748299 ps
CPU time 1.1 seconds
Started May 21 02:25:39 PM PDT 24
Finished May 21 02:25:41 PM PDT 24
Peak memory 205776 kb
Host smart-73bf8857-3360-49e1-9ed0-be64cbbf23b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126615885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2126615885
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.272949817
Short name T930
Test name
Test status
Simulation time 28731347 ps
CPU time 0.76 seconds
Started May 21 02:25:40 PM PDT 24
Finished May 21 02:25:41 PM PDT 24
Peak memory 205456 kb
Host smart-51b2640f-825d-42ab-ae5b-9ef2871f21bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272949817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.272949817
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4230733894
Short name T919
Test name
Test status
Simulation time 84398975 ps
CPU time 2.01 seconds
Started May 21 02:25:40 PM PDT 24
Finished May 21 02:25:42 PM PDT 24
Peak memory 205784 kb
Host smart-0f352793-eb43-42ea-a549-f6f3a2ffbd85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230733894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4230733894
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2690324832
Short name T996
Test name
Test status
Simulation time 82805357 ps
CPU time 3.16 seconds
Started May 21 02:25:34 PM PDT 24
Finished May 21 02:25:38 PM PDT 24
Peak memory 214320 kb
Host smart-12569dcc-1839-4f31-866e-2fe15294d3ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690324832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2690324832
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3214480955
Short name T1019
Test name
Test status
Simulation time 93004345 ps
CPU time 3.45 seconds
Started May 21 02:25:37 PM PDT 24
Finished May 21 02:25:41 PM PDT 24
Peak memory 216276 kb
Host smart-f6935ec8-c39d-43ca-b834-e352b5b3cbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214480955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3214480955
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3944124499
Short name T398
Test name
Test status
Simulation time 55495913 ps
CPU time 1.55 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:49 PM PDT 24
Peak memory 213904 kb
Host smart-5694f531-4de6-4e71-b5ba-fd81446f1b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944124499 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3944124499
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3247900696
Short name T990
Test name
Test status
Simulation time 73293520 ps
CPU time 1.12 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:50 PM PDT 24
Peak memory 205600 kb
Host smart-fffff8d9-d7d4-408c-a30e-d2cf9647d591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247900696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3247900696
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2469118002
Short name T1014
Test name
Test status
Simulation time 9266033 ps
CPU time 0.7 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:49 PM PDT 24
Peak memory 205456 kb
Host smart-7d854c25-065d-487a-ac6f-300bb1317b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469118002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2469118002
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2613305081
Short name T151
Test name
Test status
Simulation time 357264589 ps
CPU time 2.6 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:51 PM PDT 24
Peak memory 205836 kb
Host smart-81057bc0-8729-4e1f-bad9-5a86fbd178d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613305081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2613305081
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1794312884
Short name T1002
Test name
Test status
Simulation time 228261968 ps
CPU time 3.84 seconds
Started May 21 02:25:46 PM PDT 24
Finished May 21 02:25:51 PM PDT 24
Peak memory 214356 kb
Host smart-9f4c3e1e-72b9-413e-a689-558b553d8a4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794312884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1794312884
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.539948525
Short name T931
Test name
Test status
Simulation time 643477580 ps
CPU time 5.48 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:54 PM PDT 24
Peak memory 214400 kb
Host smart-fbca59f8-a8f9-40d1-b952-327ea0353b3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539948525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.539948525
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1555450842
Short name T948
Test name
Test status
Simulation time 127833634 ps
CPU time 4.24 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:54 PM PDT 24
Peak memory 217140 kb
Host smart-4d03832c-12e7-4c7a-aea9-08869281f5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555450842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1555450842
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1125891062
Short name T963
Test name
Test status
Simulation time 67091218 ps
CPU time 2.71 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:52 PM PDT 24
Peak memory 213908 kb
Host smart-2296f927-813d-40d7-af58-8f1fe384404e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125891062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1125891062
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1207790358
Short name T1069
Test name
Test status
Simulation time 29174622 ps
CPU time 2.11 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:52 PM PDT 24
Peak memory 219600 kb
Host smart-deaf6d43-b36a-466f-a4b5-601344fae7d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207790358 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1207790358
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.832428139
Short name T972
Test name
Test status
Simulation time 33194440 ps
CPU time 1.12 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:50 PM PDT 24
Peak memory 205796 kb
Host smart-7f1b042f-080a-4f7b-960b-363f6b8c6085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832428139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.832428139
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2466860890
Short name T1020
Test name
Test status
Simulation time 12174880 ps
CPU time 0.71 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:49 PM PDT 24
Peak memory 205532 kb
Host smart-95d57e7a-d7ca-4e68-b70f-aeefade13e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466860890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2466860890
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2123975646
Short name T149
Test name
Test status
Simulation time 75839792 ps
CPU time 1.47 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:51 PM PDT 24
Peak memory 205720 kb
Host smart-581bfdb2-dade-45d5-87db-2e1d424b8b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123975646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2123975646
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.890912756
Short name T928
Test name
Test status
Simulation time 632036897 ps
CPU time 2.54 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:52 PM PDT 24
Peak memory 214396 kb
Host smart-44f2dafa-9fa8-4a8a-8484-4baf523c6b1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890912756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.890912756
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3425530394
Short name T993
Test name
Test status
Simulation time 666386885 ps
CPU time 4.94 seconds
Started May 21 02:25:47 PM PDT 24
Finished May 21 02:25:54 PM PDT 24
Peak memory 214316 kb
Host smart-b18a4d45-92a4-4119-b02f-f09cd343552a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425530394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3425530394
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3360229238
Short name T1028
Test name
Test status
Simulation time 122857036 ps
CPU time 2.19 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:52 PM PDT 24
Peak memory 216256 kb
Host smart-0f8bac04-f07b-45e5-9ed8-115300199300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360229238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3360229238
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2506583387
Short name T934
Test name
Test status
Simulation time 43932873 ps
CPU time 1.25 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 214092 kb
Host smart-89cf68a1-bc60-4612-b80c-b2387f88c4c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506583387 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2506583387
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3996448645
Short name T984
Test name
Test status
Simulation time 36173267 ps
CPU time 1.51 seconds
Started May 21 02:25:56 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 205784 kb
Host smart-1e854058-da42-45ba-8ebc-73aca146f78a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996448645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3996448645
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.993579645
Short name T1043
Test name
Test status
Simulation time 8304146 ps
CPU time 0.69 seconds
Started May 21 02:25:57 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 205492 kb
Host smart-1da56763-a3dd-4880-97e5-f8bb118fb43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993579645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.993579645
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1842470139
Short name T989
Test name
Test status
Simulation time 60941775 ps
CPU time 2.47 seconds
Started May 21 02:25:52 PM PDT 24
Finished May 21 02:25:55 PM PDT 24
Peak memory 205776 kb
Host smart-c2063bad-0df9-4403-9853-1ed18469d040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842470139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1842470139
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.548975170
Short name T1013
Test name
Test status
Simulation time 218427277 ps
CPU time 3.48 seconds
Started May 21 02:25:48 PM PDT 24
Finished May 21 02:25:53 PM PDT 24
Peak memory 214412 kb
Host smart-142760f7-69f1-4efa-a53d-c8050070492e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548975170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.548975170
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.440149916
Short name T926
Test name
Test status
Simulation time 1444750809 ps
CPU time 13.07 seconds
Started May 21 02:25:53 PM PDT 24
Finished May 21 02:26:07 PM PDT 24
Peak memory 214464 kb
Host smart-a501188c-a236-41cf-8f41-b21c9a4c1ae5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440149916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.440149916
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1923418468
Short name T994
Test name
Test status
Simulation time 199645915 ps
CPU time 3.53 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 216612 kb
Host smart-d1e3e5b2-055b-4e01-8a0b-fb9afd91d661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923418468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1923418468
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3165870513
Short name T917
Test name
Test status
Simulation time 191054451 ps
CPU time 2.74 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:58 PM PDT 24
Peak memory 205792 kb
Host smart-4c4ae6f3-8162-4e70-ad57-ab8199aa06b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165870513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3165870513
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2613809374
Short name T959
Test name
Test status
Simulation time 122158436 ps
CPU time 1.66 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 216396 kb
Host smart-858cd4e8-0ac9-4708-9231-788275b17e24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613809374 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2613809374
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3443609408
Short name T1033
Test name
Test status
Simulation time 12235436 ps
CPU time 1.06 seconds
Started May 21 02:25:55 PM PDT 24
Finished May 21 02:25:57 PM PDT 24
Peak memory 205708 kb
Host smart-b21bcad4-8d56-4b74-b5bb-ae19a9ab8c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443609408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3443609408
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2587994750
Short name T1030
Test name
Test status
Simulation time 13082355 ps
CPU time 0.71 seconds
Started May 21 02:25:53 PM PDT 24
Finished May 21 02:25:55 PM PDT 24
Peak memory 205428 kb
Host smart-06aadc5a-f09a-430c-b5f3-ba04137737b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587994750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2587994750
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2341956728
Short name T1012
Test name
Test status
Simulation time 665401383 ps
CPU time 1.99 seconds
Started May 21 02:25:55 PM PDT 24
Finished May 21 02:25:58 PM PDT 24
Peak memory 205856 kb
Host smart-79dbb5c4-a5ca-4501-b54f-5e4d3a17fc30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341956728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2341956728
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1465835985
Short name T1015
Test name
Test status
Simulation time 777950824 ps
CPU time 2.89 seconds
Started May 21 02:25:54 PM PDT 24
Finished May 21 02:25:58 PM PDT 24
Peak memory 214312 kb
Host smart-2933feeb-f2b9-4ade-bf68-2c4fcddb883a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465835985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1465835985
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4294556987
Short name T1073
Test name
Test status
Simulation time 164336232 ps
CPU time 6.98 seconds
Started May 21 02:25:55 PM PDT 24
Finished May 21 02:26:04 PM PDT 24
Peak memory 214496 kb
Host smart-6b22a710-61a9-45fe-9335-dce4c25462c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294556987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4294556987
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2743491278
Short name T925
Test name
Test status
Simulation time 60491319 ps
CPU time 2.3 seconds
Started May 21 02:25:56 PM PDT 24
Finished May 21 02:25:59 PM PDT 24
Peak memory 215200 kb
Host smart-06d7dc07-681d-4c0a-aff4-bdfd0845b9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743491278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2743491278
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2500963209
Short name T742
Test name
Test status
Simulation time 58537514 ps
CPU time 0.82 seconds
Started May 21 02:54:16 PM PDT 24
Finished May 21 02:54:19 PM PDT 24
Peak memory 205980 kb
Host smart-0e461090-9a73-4a69-98c1-7dc50fec283a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500963209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2500963209
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1589718302
Short name T905
Test name
Test status
Simulation time 257315400 ps
CPU time 4.12 seconds
Started May 21 02:54:22 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 210584 kb
Host smart-3cec5530-7a43-4110-aa39-97be1c96a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589718302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1589718302
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3959588753
Short name T534
Test name
Test status
Simulation time 683676882 ps
CPU time 3.34 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 209124 kb
Host smart-8e76eda4-b512-491c-b843-01ee2beb8e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959588753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3959588753
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.4108862281
Short name T511
Test name
Test status
Simulation time 53809544 ps
CPU time 2.32 seconds
Started May 21 02:54:24 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 214280 kb
Host smart-583632a5-e8ad-484f-b197-713d62b3b45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108862281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.4108862281
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.1249706128
Short name T827
Test name
Test status
Simulation time 291850085 ps
CPU time 7.4 seconds
Started May 21 02:54:17 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 214404 kb
Host smart-fa88e025-8f94-4d70-95ac-e7f12e3fc0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249706128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1249706128
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1882413112
Short name T44
Test name
Test status
Simulation time 287831196 ps
CPU time 9.31 seconds
Started May 21 02:54:16 PM PDT 24
Finished May 21 02:54:27 PM PDT 24
Peak memory 229836 kb
Host smart-4d5a1f69-c819-4b0e-88e2-dea8a1c4d093
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882413112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1882413112
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1128991413
Short name T293
Test name
Test status
Simulation time 992798826 ps
CPU time 21.76 seconds
Started May 21 02:54:22 PM PDT 24
Finished May 21 02:54:46 PM PDT 24
Peak memory 208860 kb
Host smart-e0623912-8b49-42ee-a8f7-ef5a2ec3d027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128991413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1128991413
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4007134421
Short name T342
Test name
Test status
Simulation time 323126271 ps
CPU time 3.21 seconds
Started May 21 02:54:19 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 206992 kb
Host smart-e5debed2-5fb1-4ad0-b95e-cb6316c33aa3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007134421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4007134421
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3244971419
Short name T353
Test name
Test status
Simulation time 107712485 ps
CPU time 3.69 seconds
Started May 21 02:54:18 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 209100 kb
Host smart-40020ed9-5962-43e4-884d-0c7f17dbe88d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244971419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3244971419
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2725917320
Short name T789
Test name
Test status
Simulation time 80076081 ps
CPU time 3.12 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 206964 kb
Host smart-f7ede2e8-fbd5-478e-83c4-a129cded7d34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725917320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2725917320
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2307492855
Short name T611
Test name
Test status
Simulation time 2174369107 ps
CPU time 3.38 seconds
Started May 21 02:54:16 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 214392 kb
Host smart-a5d68db1-7f70-4ab0-b754-db88fe0e6f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307492855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2307492855
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2341468462
Short name T863
Test name
Test status
Simulation time 155594247 ps
CPU time 2.39 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 206948 kb
Host smart-e5790687-c145-4b70-95ed-60f02538d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341468462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2341468462
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2124597525
Short name T729
Test name
Test status
Simulation time 222706069 ps
CPU time 7.33 seconds
Started May 21 02:54:17 PM PDT 24
Finished May 21 02:54:27 PM PDT 24
Peak memory 208724 kb
Host smart-beb8bcef-9500-4630-8b2c-ef03992228f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124597525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2124597525
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3582126648
Short name T724
Test name
Test status
Simulation time 460308948 ps
CPU time 7.78 seconds
Started May 21 02:54:19 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 211124 kb
Host smart-ec8b31b2-4fe3-420a-b307-cc512ed0946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582126648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3582126648
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2641120778
Short name T537
Test name
Test status
Simulation time 20080612 ps
CPU time 0.83 seconds
Started May 21 02:54:26 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 205936 kb
Host smart-69a00a4b-cdfb-4c08-a925-a8ee75b0fe63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641120778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2641120778
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1913151404
Short name T838
Test name
Test status
Simulation time 36765239 ps
CPU time 2.99 seconds
Started May 21 02:54:25 PM PDT 24
Finished May 21 02:54:31 PM PDT 24
Peak memory 215380 kb
Host smart-f78987da-cbe3-4657-9c89-019f9912ec2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913151404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1913151404
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3677512612
Short name T29
Test name
Test status
Simulation time 59216505 ps
CPU time 2.74 seconds
Started May 21 02:54:27 PM PDT 24
Finished May 21 02:54:33 PM PDT 24
Peak memory 208916 kb
Host smart-0f5f28d2-578b-4ffd-b5a4-33ee65466ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677512612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3677512612
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1816242334
Short name T546
Test name
Test status
Simulation time 83345676 ps
CPU time 4.06 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:30 PM PDT 24
Peak memory 210132 kb
Host smart-169c435f-3ae9-4d8a-99fd-463840b7c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816242334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1816242334
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1246682066
Short name T390
Test name
Test status
Simulation time 85716220 ps
CPU time 4.28 seconds
Started May 21 02:54:24 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 214420 kb
Host smart-3055570d-b93f-4d9a-924c-15387671e87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246682066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1246682066
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1172326743
Short name T666
Test name
Test status
Simulation time 499803838 ps
CPU time 1.99 seconds
Started May 21 02:54:21 PM PDT 24
Finished May 21 02:54:26 PM PDT 24
Peak memory 214304 kb
Host smart-6ed0848a-8194-4e6f-99f4-d7a04e301c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172326743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1172326743
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.412576806
Short name T790
Test name
Test status
Simulation time 69368403 ps
CPU time 2.97 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 215904 kb
Host smart-f36c346f-edeb-4f90-82b2-99ffa2d2108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412576806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.412576806
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4250225567
Short name T601
Test name
Test status
Simulation time 3621607956 ps
CPU time 15.2 seconds
Started May 21 02:54:22 PM PDT 24
Finished May 21 02:54:40 PM PDT 24
Peak memory 209304 kb
Host smart-eaec8e00-6089-4f26-bf6e-49b4db4c3a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250225567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4250225567
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2029629799
Short name T451
Test name
Test status
Simulation time 656511212 ps
CPU time 4.55 seconds
Started May 21 02:54:25 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 206924 kb
Host smart-f9e7ea28-f587-44ab-a203-cf43b81641b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029629799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2029629799
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3697103938
Short name T187
Test name
Test status
Simulation time 124008957 ps
CPU time 2.44 seconds
Started May 21 02:54:24 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 207048 kb
Host smart-ed62390e-7e77-4d46-a1c0-60f225102de4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697103938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3697103938
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1499303029
Short name T864
Test name
Test status
Simulation time 1315785319 ps
CPU time 15.09 seconds
Started May 21 02:54:25 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 208588 kb
Host smart-058cf908-abaa-409e-bb12-742003172dcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499303029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1499303029
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4142801809
Short name T584
Test name
Test status
Simulation time 288577029 ps
CPU time 6.5 seconds
Started May 21 02:54:24 PM PDT 24
Finished May 21 02:54:34 PM PDT 24
Peak memory 208624 kb
Host smart-7a41c5c2-a6f4-4af1-9beb-9a9ebfab4a1e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142801809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4142801809
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2560794388
Short name T416
Test name
Test status
Simulation time 496684242 ps
CPU time 2.3 seconds
Started May 21 02:54:23 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 208876 kb
Host smart-a36f6466-0f4f-4ab6-82d4-d22d16b36303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560794388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2560794388
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2152446479
Short name T208
Test name
Test status
Simulation time 533291383 ps
CPU time 3.67 seconds
Started May 21 02:54:18 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 207904 kb
Host smart-62aa6b46-e41c-405d-9d55-bf0ebb9cfa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152446479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2152446479
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4002020789
Short name T453
Test name
Test status
Simulation time 196219815 ps
CPU time 3.94 seconds
Started May 21 02:54:21 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 207996 kb
Host smart-c6174273-98fe-43c5-91de-1f91cf82ea13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002020789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4002020789
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1237506675
Short name T449
Test name
Test status
Simulation time 45097439 ps
CPU time 1.86 seconds
Started May 21 02:54:25 PM PDT 24
Finished May 21 02:54:30 PM PDT 24
Peak memory 207860 kb
Host smart-417a2b35-77b0-4f3c-82ae-9e80eea1bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237506675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1237506675
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2236867710
Short name T813
Test name
Test status
Simulation time 6022377086 ps
CPU time 21.79 seconds
Started May 21 02:54:22 PM PDT 24
Finished May 21 02:54:46 PM PDT 24
Peak memory 211200 kb
Host smart-180131f6-a1d9-42d4-af4a-53be1d2c09e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236867710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2236867710
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.302004279
Short name T28
Test name
Test status
Simulation time 277566986 ps
CPU time 3.59 seconds
Started May 21 02:55:10 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 221540 kb
Host smart-84574993-5a25-4860-822e-bb07292b42e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302004279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.302004279
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1446671592
Short name T49
Test name
Test status
Simulation time 285925110 ps
CPU time 2.45 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 218508 kb
Host smart-b82b6bf3-0a40-4cdb-b910-d50ad1f73a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446671592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1446671592
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4252574673
Short name T102
Test name
Test status
Simulation time 40562608 ps
CPU time 2.69 seconds
Started May 21 02:55:10 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 222228 kb
Host smart-af3d7f5c-e637-4b56-bdf5-231afb197774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252574673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4252574673
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.253473079
Short name T250
Test name
Test status
Simulation time 237851889 ps
CPU time 2.55 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:15 PM PDT 24
Peak memory 214384 kb
Host smart-719c9a29-bfe2-4dab-a856-94a859787fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253473079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.253473079
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3556431738
Short name T900
Test name
Test status
Simulation time 235006111 ps
CPU time 5.75 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:17 PM PDT 24
Peak memory 214320 kb
Host smart-f7919e6f-7b7b-4ff0-92be-ed653ba5d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556431738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3556431738
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1678547924
Short name T659
Test name
Test status
Simulation time 41717218 ps
CPU time 1.86 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 206924 kb
Host smart-8713c044-a7ab-42ec-9919-a6366adf428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678547924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1678547924
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2685772278
Short name T86
Test name
Test status
Simulation time 390147576 ps
CPU time 3.04 seconds
Started May 21 02:55:09 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 208876 kb
Host smart-f6b02b80-f4ae-4bc7-9ded-4e5cd25ad674
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685772278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2685772278
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1345395601
Short name T297
Test name
Test status
Simulation time 206395974 ps
CPU time 7.24 seconds
Started May 21 02:55:10 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 209112 kb
Host smart-22b83a42-6f36-4b40-8020-0ecacb9d3469
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345395601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1345395601
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3851099430
Short name T512
Test name
Test status
Simulation time 366808718 ps
CPU time 2.82 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:15 PM PDT 24
Peak memory 207024 kb
Host smart-f4d1d33e-94bc-4834-908b-2c5c014937e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851099430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3851099430
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.987939149
Short name T2
Test name
Test status
Simulation time 166913267 ps
CPU time 2.26 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 209168 kb
Host smart-95a0076d-cffa-4b49-bbe0-b5bb9967e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987939149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.987939149
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2439132502
Short name T434
Test name
Test status
Simulation time 37447929 ps
CPU time 2.24 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:13 PM PDT 24
Peak memory 208300 kb
Host smart-c24b1aef-6304-4320-b2a5-62a232e57810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439132502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2439132502
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2979744519
Short name T310
Test name
Test status
Simulation time 119532604 ps
CPU time 5.7 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 214360 kb
Host smart-20cec18a-fdbc-47a3-80e7-6b3d5f45fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979744519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2979744519
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.885259526
Short name T912
Test name
Test status
Simulation time 48907665 ps
CPU time 0.72 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:55:21 PM PDT 24
Peak memory 205948 kb
Host smart-bbe39028-699a-407f-95df-65e9abdbfe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885259526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.885259526
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1135484113
Short name T556
Test name
Test status
Simulation time 254106133 ps
CPU time 2.23 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 209008 kb
Host smart-f9989132-b137-45d6-a643-e94ca9d3bd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135484113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1135484113
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.672739817
Short name T372
Test name
Test status
Simulation time 482975333 ps
CPU time 3.75 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 214328 kb
Host smart-5459c862-a7b1-4c8e-9ca5-9cdcc172bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672739817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.672739817
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1534345125
Short name T202
Test name
Test status
Simulation time 142133420 ps
CPU time 2.82 seconds
Started May 21 02:55:07 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 214700 kb
Host smart-ff178c47-7a8e-443a-801a-5fe7034d3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534345125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1534345125
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2162816602
Short name T820
Test name
Test status
Simulation time 315250910 ps
CPU time 5.69 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:17 PM PDT 24
Peak memory 207952 kb
Host smart-edcdf462-1830-45fd-8660-d7fcc1ecd8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162816602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2162816602
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.932361521
Short name T385
Test name
Test status
Simulation time 221113108 ps
CPU time 1.75 seconds
Started May 21 02:55:08 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 207140 kb
Host smart-a4e93d68-5943-4c54-9fef-f4a10c1a5701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932361521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.932361521
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2670063843
Short name T849
Test name
Test status
Simulation time 627695594 ps
CPU time 5.06 seconds
Started May 21 02:55:09 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 209068 kb
Host smart-c1256f2a-5f7b-45db-9f0b-38479f854379
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670063843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2670063843
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3173953296
Short name T818
Test name
Test status
Simulation time 33155756 ps
CPU time 2.27 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 206948 kb
Host smart-ab03e327-fa3a-4787-9305-bfc98ff6f3db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173953296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3173953296
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2510341824
Short name T850
Test name
Test status
Simulation time 248338908 ps
CPU time 3.4 seconds
Started May 21 02:55:10 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 208800 kb
Host smart-71921b31-19aa-414a-8831-350c5e5b0c7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510341824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2510341824
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3448728530
Short name T846
Test name
Test status
Simulation time 43019278 ps
CPU time 1.66 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 208156 kb
Host smart-a59a2573-413d-4dbd-add3-b89ea628a790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448728530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3448728530
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2280016417
Short name T406
Test name
Test status
Simulation time 1238691078 ps
CPU time 12.06 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 206828 kb
Host smart-57df7193-ab90-42c5-adb0-618aeac3d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280016417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2280016417
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1416426569
Short name T72
Test name
Test status
Simulation time 1101742781 ps
CPU time 12 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 219476 kb
Host smart-814e262a-dea3-4c3a-ac4b-dde53b79fc38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416426569 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1416426569
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.678753257
Short name T298
Test name
Test status
Simulation time 664696735 ps
CPU time 4.72 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 209648 kb
Host smart-5ef6757e-cb90-465c-b34d-40093199c559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678753257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.678753257
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1061724322
Short name T634
Test name
Test status
Simulation time 38203743 ps
CPU time 0.84 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:23 PM PDT 24
Peak memory 205980 kb
Host smart-27730522-8704-42de-9ce2-738b5d22592b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061724322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1061724322
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2118685528
Short name T578
Test name
Test status
Simulation time 241111522 ps
CPU time 2.62 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:25 PM PDT 24
Peak memory 214352 kb
Host smart-a3397603-39a5-4aa2-9216-d03994a569d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118685528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2118685528
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3140120223
Short name T373
Test name
Test status
Simulation time 81899693 ps
CPU time 2.84 seconds
Started May 21 02:55:16 PM PDT 24
Finished May 21 02:55:27 PM PDT 24
Peak memory 214372 kb
Host smart-ff4b4fce-f564-482f-b5f9-020eadf3ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140120223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3140120223
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.838900788
Short name T608
Test name
Test status
Simulation time 217508984 ps
CPU time 3.49 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:55:24 PM PDT 24
Peak memory 214340 kb
Host smart-1589b413-e829-4da0-b8bb-270d4329d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838900788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.838900788
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3043507593
Short name T805
Test name
Test status
Simulation time 831545228 ps
CPU time 3.26 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:27 PM PDT 24
Peak memory 214376 kb
Host smart-4af0cc87-a7b5-4ab8-ba0a-e5ca6aad7ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043507593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3043507593
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.656980144
Short name T252
Test name
Test status
Simulation time 252606779 ps
CPU time 9.34 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 218408 kb
Host smart-3f3dc025-5127-418a-b870-1b1f319ee8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656980144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.656980144
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.65981891
Short name T490
Test name
Test status
Simulation time 950434034 ps
CPU time 11.18 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:41 PM PDT 24
Peak memory 208412 kb
Host smart-12afd04e-4237-4abf-9924-6afb4f4dbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65981891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.65981891
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.558744229
Short name T408
Test name
Test status
Simulation time 19623047251 ps
CPU time 43.94 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:56:08 PM PDT 24
Peak memory 208704 kb
Host smart-23a8ca52-7be2-4500-a5eb-ff111697643a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558744229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.558744229
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3531522652
Short name T496
Test name
Test status
Simulation time 283103244 ps
CPU time 3.53 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 208956 kb
Host smart-f8b0cd77-68b5-46c3-85f5-16114683972a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531522652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3531522652
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1215551966
Short name T486
Test name
Test status
Simulation time 357227709 ps
CPU time 3.51 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:25 PM PDT 24
Peak memory 208812 kb
Host smart-cfa28019-a9d8-4154-91c9-ba12ecea9ac5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215551966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1215551966
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.660827496
Short name T651
Test name
Test status
Simulation time 168167337 ps
CPU time 2.47 seconds
Started May 21 02:55:11 PM PDT 24
Finished May 21 02:55:21 PM PDT 24
Peak memory 218464 kb
Host smart-03e9aa21-cd6f-4fde-853a-2932f22fb699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660827496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.660827496
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.53046360
Short name T476
Test name
Test status
Simulation time 48022492 ps
CPU time 2.47 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:26 PM PDT 24
Peak memory 206936 kb
Host smart-971110cc-be40-4e02-8d68-0345836b4fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53046360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.53046360
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1145864078
Short name T664
Test name
Test status
Simulation time 2373703350 ps
CPU time 18.91 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 221400 kb
Host smart-706c1a56-bea3-4e73-b85f-fbe30b9bc564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145864078 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1145864078
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1491666201
Short name T662
Test name
Test status
Simulation time 1068092611 ps
CPU time 11.06 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 208540 kb
Host smart-877804ef-7973-49b3-90f5-c65b7caf53ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491666201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1491666201
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3803607910
Short name T580
Test name
Test status
Simulation time 86260606 ps
CPU time 1.52 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 209748 kb
Host smart-32ca2e9b-23b8-408d-bdac-2c1864be4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803607910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3803607910
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1289101697
Short name T189
Test name
Test status
Simulation time 20442267 ps
CPU time 0.85 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 206004 kb
Host smart-d2dd1305-4756-4d3c-8cf5-e555c589db6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289101697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1289101697
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2532984728
Short name T422
Test name
Test status
Simulation time 953720258 ps
CPU time 12.13 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 213760 kb
Host smart-6920dc39-3b26-4f76-a121-8bd9b975f854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532984728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2532984728
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.855006974
Short name T587
Test name
Test status
Simulation time 64023174 ps
CPU time 1.53 seconds
Started May 21 02:55:22 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 209448 kb
Host smart-0893a8b6-289e-47a9-9a58-542f4a1accac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855006974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.855006974
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2642364602
Short name T491
Test name
Test status
Simulation time 25255961 ps
CPU time 1.46 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 206400 kb
Host smart-ff151c71-3191-4af7-af56-c51f08e0a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642364602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2642364602
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1898612081
Short name T104
Test name
Test status
Simulation time 500589662 ps
CPU time 10.67 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:36 PM PDT 24
Peak memory 214352 kb
Host smart-189fe1b6-1d43-4758-a02d-083b4727f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898612081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1898612081
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2871217503
Short name T585
Test name
Test status
Simulation time 45620757 ps
CPU time 2.92 seconds
Started May 21 02:55:18 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 214336 kb
Host smart-ec709f7a-266a-4086-abf3-39a0721a5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871217503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2871217503
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.639306474
Short name T238
Test name
Test status
Simulation time 31670969 ps
CPU time 2.53 seconds
Started May 21 02:55:18 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 208472 kb
Host smart-21da4b7a-e34e-48ff-89ac-c9b361ae2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639306474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.639306474
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.235398209
Short name T571
Test name
Test status
Simulation time 30828029865 ps
CPU time 77.12 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 208612 kb
Host smart-8233e415-23a9-465a-bd5b-82d6bb97d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235398209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.235398209
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1639804467
Short name T548
Test name
Test status
Simulation time 140158562 ps
CPU time 3.4 seconds
Started May 21 02:55:16 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 207688 kb
Host smart-653ab11f-8f99-4f08-ac14-5e415d5b658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639804467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1639804467
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.47415904
Short name T609
Test name
Test status
Simulation time 3412824435 ps
CPU time 58.04 seconds
Started May 21 02:55:13 PM PDT 24
Finished May 21 02:56:19 PM PDT 24
Peak memory 208072 kb
Host smart-2c3d6980-df64-4721-ac0e-6ea8692ba0a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47415904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.47415904
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1082847148
Short name T303
Test name
Test status
Simulation time 169638171 ps
CPU time 2.53 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:26 PM PDT 24
Peak memory 207112 kb
Host smart-a2b6269e-1bd7-4412-b76c-59bfcbe53e83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082847148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1082847148
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2896544805
Short name T719
Test name
Test status
Simulation time 192595085 ps
CPU time 2.46 seconds
Started May 21 02:55:15 PM PDT 24
Finished May 21 02:55:26 PM PDT 24
Peak memory 208468 kb
Host smart-a58030b3-d7fd-479b-9e3a-98fb4447670f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896544805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2896544805
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3874956459
Short name T456
Test name
Test status
Simulation time 216573531 ps
CPU time 2.6 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 215800 kb
Host smart-8c06f9b4-3104-4de8-a1f9-044f1a9006a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874956459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3874956459
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.299317502
Short name T405
Test name
Test status
Simulation time 100975058 ps
CPU time 3.03 seconds
Started May 21 02:55:14 PM PDT 24
Finished May 21 02:55:25 PM PDT 24
Peak memory 207392 kb
Host smart-6f2fdac5-26ce-4bae-b342-03716b3dae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299317502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.299317502
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.992900643
Short name T6
Test name
Test status
Simulation time 72688584 ps
CPU time 4.56 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 222548 kb
Host smart-f794a7e5-149a-43fa-a5b1-15ed1ebee562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992900643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.992900643
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1121953765
Short name T493
Test name
Test status
Simulation time 1926985966 ps
CPU time 12.87 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 208520 kb
Host smart-38a7bc12-c611-4cbf-ac16-7c9e219ac0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121953765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1121953765
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3418157894
Short name T544
Test name
Test status
Simulation time 488505926 ps
CPU time 10.52 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 219400 kb
Host smart-6c0402b9-b3bd-4f56-a87f-6a90cb7c271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418157894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3418157894
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.282399308
Short name T427
Test name
Test status
Simulation time 18006976 ps
CPU time 0.76 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 205968 kb
Host smart-476d336a-c090-428f-8ccd-d6185bc6f4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282399308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.282399308
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4126374893
Short name T896
Test name
Test status
Simulation time 257867159 ps
CPU time 13.44 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 214560 kb
Host smart-bc1781f0-04a1-46ed-a9ea-d957359e21be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126374893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4126374893
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3844418944
Short name T26
Test name
Test status
Simulation time 448086200 ps
CPU time 3.62 seconds
Started May 21 02:55:16 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 221776 kb
Host smart-cc86ca7b-7851-4608-833b-3a42e8597c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844418944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3844418944
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.158383822
Short name T329
Test name
Test status
Simulation time 71494477 ps
CPU time 3.14 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 209136 kb
Host smart-fd0f5a4c-bd95-4f56-aee6-bad9218104a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158383822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.158383822
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3133159802
Short name T605
Test name
Test status
Simulation time 113392321 ps
CPU time 5.17 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 214380 kb
Host smart-8b7c379f-2077-46d0-81e5-3675bf18618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133159802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3133159802
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.444976193
Short name T272
Test name
Test status
Simulation time 659168921 ps
CPU time 5.33 seconds
Started May 21 02:55:18 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 222428 kb
Host smart-e81df02f-d493-414e-9b58-e585b7fc0aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444976193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.444976193
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.503048887
Short name T610
Test name
Test status
Simulation time 251284595 ps
CPU time 3.56 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 208940 kb
Host smart-cc7b8bb1-0677-4e89-b555-ab489da64ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503048887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.503048887
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3560310883
Short name T695
Test name
Test status
Simulation time 44160193 ps
CPU time 2.92 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 207132 kb
Host smart-d9b4ef44-cb96-4eba-ba2a-0ac7f436434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560310883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3560310883
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2327121551
Short name T736
Test name
Test status
Simulation time 6525668860 ps
CPU time 31.1 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 208580 kb
Host smart-1854a980-f3bf-4aca-8c8b-85b457a2652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327121551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2327121551
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3429095760
Short name T856
Test name
Test status
Simulation time 27174165 ps
CPU time 2.02 seconds
Started May 21 02:55:21 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 208696 kb
Host smart-78bc91aa-379f-407e-b3fd-5796a70b995b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429095760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3429095760
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3886325667
Short name T269
Test name
Test status
Simulation time 359174757 ps
CPU time 5.44 seconds
Started May 21 02:55:18 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 207000 kb
Host smart-6d7aac7f-8d27-4375-a630-791096248522
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886325667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3886325667
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3426388105
Short name T478
Test name
Test status
Simulation time 276954595 ps
CPU time 2.89 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:34 PM PDT 24
Peak memory 208404 kb
Host smart-7852f93f-e1b2-42e9-9bea-82f92f13af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426388105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3426388105
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3432214091
Short name T697
Test name
Test status
Simulation time 247017032 ps
CPU time 2.93 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 206736 kb
Host smart-92cdb5c3-0715-4099-977c-93ccc946cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432214091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3432214091
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.637853316
Short name T897
Test name
Test status
Simulation time 1734916096 ps
CPU time 18.56 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 221056 kb
Host smart-cfa0c33b-4814-43de-8d14-8f64503be3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637853316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.637853316
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1525326709
Short name T590
Test name
Test status
Simulation time 339670926 ps
CPU time 7.78 seconds
Started May 21 02:55:18 PM PDT 24
Finished May 21 02:55:34 PM PDT 24
Peak memory 214376 kb
Host smart-e71fbb08-3abe-43ca-8167-c0e63f55afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525326709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1525326709
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3586165208
Short name T481
Test name
Test status
Simulation time 300692447 ps
CPU time 2.88 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 210544 kb
Host smart-407168bb-b2bc-4b38-b262-2de04013eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586165208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3586165208
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.69008774
Short name T680
Test name
Test status
Simulation time 14593192 ps
CPU time 0.87 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 206168 kb
Host smart-4492efee-1169-498c-ab71-427c2fe3dd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69008774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.69008774
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.218137268
Short name T418
Test name
Test status
Simulation time 913174995 ps
CPU time 13.53 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 214356 kb
Host smart-ed045d09-fa4f-4b12-ad62-7145294e9c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218137268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.218137268
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2623749588
Short name T470
Test name
Test status
Simulation time 77132903 ps
CPU time 2.2 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 208864 kb
Host smart-c91e990e-d176-4d32-b8fc-f064cde6a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623749588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2623749588
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1902053567
Short name T761
Test name
Test status
Simulation time 147163063 ps
CPU time 3.36 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 214304 kb
Host smart-39a1ac1c-a5cc-4514-b491-d4bb652d6451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902053567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1902053567
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3138735930
Short name T377
Test name
Test status
Simulation time 2390102619 ps
CPU time 8.91 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 222580 kb
Host smart-ec295653-bfc6-4bcf-adfe-9501818154d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138735930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3138735930
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2173993053
Short name T553
Test name
Test status
Simulation time 4851698762 ps
CPU time 81.61 seconds
Started May 21 02:55:22 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 208240 kb
Host smart-3aec4dbd-62ad-4627-9b24-1153b796c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173993053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2173993053
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1596734347
Short name T857
Test name
Test status
Simulation time 291439849 ps
CPU time 2.86 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 206852 kb
Host smart-480fdd26-464a-4fa0-a0cd-6c3d050c2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596734347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1596734347
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3887997063
Short name T622
Test name
Test status
Simulation time 308150979 ps
CPU time 4.96 seconds
Started May 21 02:55:17 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 208012 kb
Host smart-0e840d5b-09e4-4769-83db-450b52e8e54d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887997063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3887997063
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3425372037
Short name T442
Test name
Test status
Simulation time 540727308 ps
CPU time 4.96 seconds
Started May 21 02:55:20 PM PDT 24
Finished May 21 02:55:34 PM PDT 24
Peak memory 208688 kb
Host smart-a8bde68b-a67b-4a48-988d-75ddc154de57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425372037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3425372037
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2140071556
Short name T381
Test name
Test status
Simulation time 64819510 ps
CPU time 3.18 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:31 PM PDT 24
Peak memory 206944 kb
Host smart-e75e0a4a-4cae-4541-9c4f-d162f6a47fe6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140071556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2140071556
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2457138916
Short name T628
Test name
Test status
Simulation time 128694001 ps
CPU time 1.75 seconds
Started May 21 02:55:26 PM PDT 24
Finished May 21 02:55:36 PM PDT 24
Peak memory 209120 kb
Host smart-a7182192-997d-4ce9-81c5-7ff92505266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457138916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2457138916
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.270760501
Short name T752
Test name
Test status
Simulation time 32364335 ps
CPU time 2.11 seconds
Started May 21 02:55:19 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 207272 kb
Host smart-d7dada56-95d5-46d3-bb8f-8c3cd03944a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270760501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.270760501
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.39887503
Short name T243
Test name
Test status
Simulation time 629502659 ps
CPU time 11.16 seconds
Started May 21 02:55:24 PM PDT 24
Finished May 21 02:55:44 PM PDT 24
Peak memory 209108 kb
Host smart-8dbb911c-c464-418b-815f-8d78d7141381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39887503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.39887503
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1250079875
Short name T183
Test name
Test status
Simulation time 776235174 ps
CPU time 16.72 seconds
Started May 21 02:55:26 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 222692 kb
Host smart-d0d5ed68-4ded-4d2a-9a8d-4bf85e04a15a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250079875 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1250079875
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1107715318
Short name T263
Test name
Test status
Simulation time 307917003 ps
CPU time 8.35 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 218344 kb
Host smart-a4af298a-2aaa-41c5-9aa0-6e2a83d9ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107715318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1107715318
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.258565504
Short name T592
Test name
Test status
Simulation time 124412438 ps
CPU time 2.66 seconds
Started May 21 02:55:24 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 209924 kb
Host smart-bc6ef86f-a36c-4ece-be3c-67beae449872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258565504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.258565504
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.361561263
Short name T436
Test name
Test status
Simulation time 55628109 ps
CPU time 1.01 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 206160 kb
Host smart-418d8fab-ac5f-4d86-ae33-f34da23961f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361561263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.361561263
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1404796014
Short name T413
Test name
Test status
Simulation time 53663541 ps
CPU time 4.08 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 214360 kb
Host smart-64339765-6bc1-4300-9039-408b261bacdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404796014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1404796014
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.628695439
Short name T248
Test name
Test status
Simulation time 88795176 ps
CPU time 3.67 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:37 PM PDT 24
Peak memory 214420 kb
Host smart-a3df5345-649e-4294-8436-d5738427d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628695439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.628695439
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3829863411
Short name T520
Test name
Test status
Simulation time 43756679 ps
CPU time 2.36 seconds
Started May 21 02:55:27 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 214356 kb
Host smart-0525be54-6aa7-4872-9dbc-370ac23804d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829863411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3829863411
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_random.3832178365
Short name T210
Test name
Test status
Simulation time 716678314 ps
CPU time 5.51 seconds
Started May 21 02:55:25 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 214332 kb
Host smart-02091b89-1b62-4b16-ae70-b670a791cc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832178365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3832178365
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.852044713
Short name T665
Test name
Test status
Simulation time 258919078 ps
CPU time 2.92 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 207228 kb
Host smart-03f30296-6ed1-4652-8882-f9c1ea4a1f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852044713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.852044713
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3277176342
Short name T283
Test name
Test status
Simulation time 63511018 ps
CPU time 3.19 seconds
Started May 21 02:55:26 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 206892 kb
Host smart-1475988e-d31e-4c53-98f9-5cf9ea0f3306
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277176342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3277176342
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4167517316
Short name T737
Test name
Test status
Simulation time 4075136049 ps
CPU time 26.51 seconds
Started May 21 02:55:26 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 208492 kb
Host smart-9d750a14-324e-448c-8bca-c938ef4e2412
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167517316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4167517316
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3844107571
Short name T704
Test name
Test status
Simulation time 314633863 ps
CPU time 3.54 seconds
Started May 21 02:55:26 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 208924 kb
Host smart-22626177-f1a2-4afa-aa36-86fdde256115
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844107571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3844107571
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3041617622
Short name T673
Test name
Test status
Simulation time 253120325 ps
CPU time 2.44 seconds
Started May 21 02:55:27 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 207244 kb
Host smart-6d723c24-26ab-412e-8d72-cdf0ba656c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041617622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3041617622
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3056128381
Short name T206
Test name
Test status
Simulation time 629055369 ps
CPU time 3.48 seconds
Started May 21 02:55:32 PM PDT 24
Finished May 21 02:55:44 PM PDT 24
Peak memory 208512 kb
Host smart-db0f959c-49c1-4ce1-a7cc-6414f7e023e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056128381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3056128381
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3651398905
Short name T543
Test name
Test status
Simulation time 6442583500 ps
CPU time 103.6 seconds
Started May 21 02:55:32 PM PDT 24
Finished May 21 02:57:24 PM PDT 24
Peak memory 219732 kb
Host smart-6c68f41e-3e39-4f16-9ed4-34ec05fe9603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651398905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3651398905
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3767509631
Short name T236
Test name
Test status
Simulation time 975492619 ps
CPU time 8.47 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 222668 kb
Host smart-3f01a1f5-634b-43a9-beb9-5fed11ab6aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767509631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3767509631
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1585673721
Short name T350
Test name
Test status
Simulation time 107067674 ps
CPU time 4.96 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:37 PM PDT 24
Peak memory 214464 kb
Host smart-35a905ac-ee06-4eb9-995f-d31e0baa21a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585673721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1585673721
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.114861022
Short name T806
Test name
Test status
Simulation time 123113069 ps
CPU time 3.26 seconds
Started May 21 02:55:27 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 210524 kb
Host smart-0d9704e4-756e-417e-a72b-0dd4f55330a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114861022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.114861022
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.980429097
Short name T901
Test name
Test status
Simulation time 10757375 ps
CPU time 0.85 seconds
Started May 21 02:55:29 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 205940 kb
Host smart-ca98a487-7cf8-4bff-9599-3d1fd0eb85e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980429097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.980429097
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3009550028
Short name T767
Test name
Test status
Simulation time 154876003 ps
CPU time 3.42 seconds
Started May 21 02:55:33 PM PDT 24
Finished May 21 02:55:45 PM PDT 24
Peak memory 209664 kb
Host smart-2ae7500d-ebf2-4485-8756-c7df3d8318af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009550028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3009550028
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3519171709
Short name T270
Test name
Test status
Simulation time 75968927 ps
CPU time 2.6 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 214360 kb
Host smart-ec782051-2ea9-4f98-bc75-107399930675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519171709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3519171709
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2478190234
Short name T90
Test name
Test status
Simulation time 187417298 ps
CPU time 3.25 seconds
Started May 21 02:55:28 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 221828 kb
Host smart-569141c5-4c87-4ef2-a7fd-40b3840a08cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478190234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2478190234
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3860610829
Short name T911
Test name
Test status
Simulation time 176069263 ps
CPU time 3.73 seconds
Started May 21 02:55:31 PM PDT 24
Finished May 21 02:55:44 PM PDT 24
Peak memory 220644 kb
Host smart-8f4cc24c-2588-45a9-8f8a-3765d3cd7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860610829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3860610829
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2856535885
Short name T771
Test name
Test status
Simulation time 71280712 ps
CPU time 2.52 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 214396 kb
Host smart-d89d2f32-c9c3-451c-a9de-29c07cd6a479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856535885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2856535885
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1011637375
Short name T207
Test name
Test status
Simulation time 4922687115 ps
CPU time 18.77 seconds
Started May 21 02:55:33 PM PDT 24
Finished May 21 02:56:00 PM PDT 24
Peak memory 208596 kb
Host smart-f1de1136-81c2-44b2-bf92-07a810330d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011637375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1011637375
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.500393412
Short name T677
Test name
Test status
Simulation time 289391229 ps
CPU time 3.14 seconds
Started May 21 02:55:30 PM PDT 24
Finished May 21 02:55:41 PM PDT 24
Peak memory 207132 kb
Host smart-333639fb-e6d5-4971-bee4-00adcd5bd183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500393412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.500393412
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.837207578
Short name T902
Test name
Test status
Simulation time 60492307 ps
CPU time 3.02 seconds
Started May 21 02:55:30 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 208856 kb
Host smart-7045d72d-f4c6-4535-afae-885782affd14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837207578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.837207578
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1435740261
Short name T466
Test name
Test status
Simulation time 204177283 ps
CPU time 4.79 seconds
Started May 21 02:55:34 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 208936 kb
Host smart-09a3d997-73bb-4ebe-8cfa-e0df402f987b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435740261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1435740261
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.881554164
Short name T852
Test name
Test status
Simulation time 130854824 ps
CPU time 2.5 seconds
Started May 21 02:55:30 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 208048 kb
Host smart-eb0c1d5d-2e85-44cf-ae4a-889fb73f182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881554164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.881554164
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1732362209
Short name T832
Test name
Test status
Simulation time 317946575 ps
CPU time 3.28 seconds
Started May 21 02:55:23 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 208592 kb
Host smart-4c72bd91-3c72-47f4-b678-4ab260a474dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732362209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1732362209
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3787876637
Short name T228
Test name
Test status
Simulation time 2317320375 ps
CPU time 29.85 seconds
Started May 21 02:55:31 PM PDT 24
Finished May 21 02:56:09 PM PDT 24
Peak memory 222748 kb
Host smart-b6fdaeab-bdb1-42a5-9ef7-1345c8ba4f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787876637 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3787876637
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.876495281
Short name T542
Test name
Test status
Simulation time 165612210 ps
CPU time 4.07 seconds
Started May 21 02:55:33 PM PDT 24
Finished May 21 02:55:46 PM PDT 24
Peak memory 214400 kb
Host smart-43e3f9c7-1038-457a-a978-97d3962014e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876495281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.876495281
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.702060437
Short name T397
Test name
Test status
Simulation time 49722532 ps
CPU time 2.31 seconds
Started May 21 02:55:30 PM PDT 24
Finished May 21 02:55:40 PM PDT 24
Peak memory 209936 kb
Host smart-3f7a2962-c055-42f2-ac17-4506dfd43949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702060437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.702060437
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2745649676
Short name T661
Test name
Test status
Simulation time 21844440 ps
CPU time 0.77 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:55:45 PM PDT 24
Peak memory 205964 kb
Host smart-218ba319-a8ed-48e0-8261-3f5fdeeda2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745649676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2745649676
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.411783933
Short name T731
Test name
Test status
Simulation time 94519397 ps
CPU time 5.57 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:54 PM PDT 24
Peak memory 214824 kb
Host smart-5c5e366f-1bb1-48ab-8a8a-0c2275dab4c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411783933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.411783933
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2745154386
Short name T854
Test name
Test status
Simulation time 96784153 ps
CPU time 2.03 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 207536 kb
Host smart-b130b9b5-da3e-48bd-bef9-d81d91083862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745154386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2745154386
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1012940363
Short name T304
Test name
Test status
Simulation time 78100926 ps
CPU time 2.6 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 214424 kb
Host smart-cd718099-fea9-43f1-a045-83e8a736bf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012940363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1012940363
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.903811690
Short name T232
Test name
Test status
Simulation time 41542188 ps
CPU time 2.94 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 220436 kb
Host smart-36a9ff99-d6c0-4942-9617-a015dfc96387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903811690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.903811690
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3749659451
Short name T140
Test name
Test status
Simulation time 770125727 ps
CPU time 5.93 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 214344 kb
Host smart-694abc6a-b804-45bc-afd7-32c7bce443c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749659451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3749659451
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3416680305
Short name T828
Test name
Test status
Simulation time 452848675 ps
CPU time 2.49 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 206796 kb
Host smart-bd7cce9c-e9d1-492c-9348-2b8b24057985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416680305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3416680305
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1597745872
Short name T452
Test name
Test status
Simulation time 34307353 ps
CPU time 2.33 seconds
Started May 21 02:55:39 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 207016 kb
Host smart-46a3f67b-bb91-412c-98a9-4e0bc97f3d4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597745872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1597745872
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1247658440
Short name T281
Test name
Test status
Simulation time 73464908 ps
CPU time 2.7 seconds
Started May 21 02:55:31 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 208448 kb
Host smart-f1af227e-0700-4917-9ebb-8a1f194d6472
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247658440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1247658440
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2625616784
Short name T759
Test name
Test status
Simulation time 1348389079 ps
CPU time 15.77 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 208060 kb
Host smart-f6f3bcc0-263b-41ce-a73f-0972a9333598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625616784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2625616784
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2567632174
Short name T629
Test name
Test status
Simulation time 643223366 ps
CPU time 2.92 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 207556 kb
Host smart-460bfb50-a91b-40fc-b869-88b3daf45a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567632174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2567632174
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3045258241
Short name T699
Test name
Test status
Simulation time 32568832 ps
CPU time 2.08 seconds
Started May 21 02:55:29 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 206760 kb
Host smart-baae5475-34f9-415e-b843-04bf0ec8ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045258241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3045258241
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3759069226
Short name T884
Test name
Test status
Simulation time 2271109888 ps
CPU time 67.48 seconds
Started May 21 02:55:36 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 215412 kb
Host smart-9bdd6b81-0f10-41ef-aeee-6bec8095b689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759069226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3759069226
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.750324156
Short name T184
Test name
Test status
Simulation time 673339025 ps
CPU time 9.32 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 222660 kb
Host smart-531cc6bc-1b81-4322-8b52-934a551ff5d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750324156 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.750324156
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1676385879
Short name T394
Test name
Test status
Simulation time 22996954 ps
CPU time 1.39 seconds
Started May 21 02:55:35 PM PDT 24
Finished May 21 02:55:44 PM PDT 24
Peak memory 208708 kb
Host smart-a87aeb4d-7d32-4dfb-a437-f94135997279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676385879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1676385879
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1421094806
Short name T751
Test name
Test status
Simulation time 28118575 ps
CPU time 0.81 seconds
Started May 21 02:55:43 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 206000 kb
Host smart-5d78c226-9d36-4768-b0e7-bb6a35896721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421094806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1421094806
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.881150632
Short name T410
Test name
Test status
Simulation time 156010366 ps
CPU time 4.81 seconds
Started May 21 02:55:38 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 214356 kb
Host smart-6cd44f49-4eb8-49e5-923c-de29be0b973e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881150632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.881150632
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1774871304
Short name T860
Test name
Test status
Simulation time 74706835 ps
CPU time 3.11 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 210276 kb
Host smart-9435203b-746e-49c7-afdc-11503a80f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774871304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1774871304
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3218301212
Short name T96
Test name
Test status
Simulation time 800341903 ps
CPU time 5.62 seconds
Started May 21 02:55:47 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 214396 kb
Host smart-3b688672-7f48-4add-adc4-0936abdda376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218301212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3218301212
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.336974165
Short name T727
Test name
Test status
Simulation time 117831092 ps
CPU time 2.47 seconds
Started May 21 02:55:45 PM PDT 24
Finished May 21 02:55:54 PM PDT 24
Peak memory 214344 kb
Host smart-f9caf481-3c30-4107-99fd-347cd7968817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336974165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.336974165
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2348026630
Short name T226
Test name
Test status
Simulation time 254575424 ps
CPU time 3.19 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 219940 kb
Host smart-cb58b025-de1b-42bb-9c53-5cbe2d5f95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348026630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2348026630
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.997462233
Short name T652
Test name
Test status
Simulation time 258781305 ps
CPU time 3.88 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 207788 kb
Host smart-2f710ba3-cc99-4c4e-a5d4-99a1129f276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997462233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.997462233
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3236014366
Short name T772
Test name
Test status
Simulation time 81517316 ps
CPU time 1.8 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 206832 kb
Host smart-793247f8-b18d-4425-b82b-a89158a6232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236014366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3236014366
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2398237395
Short name T280
Test name
Test status
Simulation time 737112274 ps
CPU time 5.61 seconds
Started May 21 02:55:35 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 208920 kb
Host smart-6224c0a0-3b73-4fe3-941f-fd9df286e229
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398237395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2398237395
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.532226809
Short name T529
Test name
Test status
Simulation time 72124706 ps
CPU time 1.79 seconds
Started May 21 02:55:37 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 206792 kb
Host smart-280c7f17-22fc-47c7-a0b8-b2ae76836a93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532226809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.532226809
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2664413423
Short name T794
Test name
Test status
Simulation time 660129227 ps
CPU time 7.12 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 208076 kb
Host smart-66b624eb-986e-4dc9-9521-12b86ba82c38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664413423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2664413423
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4193231803
Short name T603
Test name
Test status
Simulation time 50848556 ps
CPU time 2.66 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 209008 kb
Host smart-ef8985bf-2a66-47a3-98d0-b20652ab5962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193231803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4193231803
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2676597533
Short name T446
Test name
Test status
Simulation time 192927686 ps
CPU time 2.6 seconds
Started May 21 02:55:39 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 206988 kb
Host smart-24b98b62-9e3d-4492-9d2d-86b609fc1c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676597533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2676597533
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2581692974
Short name T618
Test name
Test status
Simulation time 211622848 ps
CPU time 9.03 seconds
Started May 21 02:55:43 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 220204 kb
Host smart-f8e9d7e8-2d51-48f1-96af-6a03703ae5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581692974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2581692974
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1549954262
Short name T384
Test name
Test status
Simulation time 1344430030 ps
CPU time 20.47 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 221408 kb
Host smart-8a6ab921-883d-41b4-95e0-34bd93e1dcaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549954262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1549954262
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4030204443
Short name T256
Test name
Test status
Simulation time 166483478 ps
CPU time 6.77 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 214396 kb
Host smart-9a9170fa-2a89-48c7-8c71-ca0e4bdaae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030204443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4030204443
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2155807210
Short name T519
Test name
Test status
Simulation time 82391550 ps
CPU time 2.11 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 210116 kb
Host smart-322e6729-6fcc-4701-93e6-0ca21fc98628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155807210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2155807210
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3400500988
Short name T565
Test name
Test status
Simulation time 173234581 ps
CPU time 0.89 seconds
Started May 21 02:54:32 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 205960 kb
Host smart-b2d234d3-3f08-45f8-b28f-ea9b938f4aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400500988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3400500988
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4102865696
Short name T116
Test name
Test status
Simulation time 47520701 ps
CPU time 3.47 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 222544 kb
Host smart-98966579-dd6b-4a6f-9fbf-ff866504d795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102865696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4102865696
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2243855679
Short name T619
Test name
Test status
Simulation time 235241831 ps
CPU time 2.93 seconds
Started May 21 02:54:39 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 209212 kb
Host smart-dc3fe896-4064-4afd-b1bd-e0004ae1595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243855679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2243855679
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3395498718
Short name T657
Test name
Test status
Simulation time 56261271 ps
CPU time 1.75 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 209148 kb
Host smart-d5b3c8ad-cf27-435f-acc8-cb15a8f50793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395498718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3395498718
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1983839127
Short name T887
Test name
Test status
Simulation time 217644505 ps
CPU time 3.92 seconds
Started May 21 02:54:31 PM PDT 24
Finished May 21 02:54:39 PM PDT 24
Peak memory 214320 kb
Host smart-5809258e-044c-47fe-8eb8-afa2390fcf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983839127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1983839127
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3809286142
Short name T826
Test name
Test status
Simulation time 190662695 ps
CPU time 3.02 seconds
Started May 21 02:54:39 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 215136 kb
Host smart-455968ed-e250-429d-a689-e74a7c9665d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809286142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3809286142
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3217988625
Short name T237
Test name
Test status
Simulation time 46277997 ps
CPU time 3.34 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 220332 kb
Host smart-29d3d0d3-109b-482e-939c-e1db7397d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217988625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3217988625
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1504250155
Short name T823
Test name
Test status
Simulation time 2567859869 ps
CPU time 63.57 seconds
Started May 21 02:54:28 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 209300 kb
Host smart-f3701303-5c1a-4f9a-96e9-f70a62ca72e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504250155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1504250155
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.455485323
Short name T10
Test name
Test status
Simulation time 430262729 ps
CPU time 5.48 seconds
Started May 21 02:54:29 PM PDT 24
Finished May 21 02:54:38 PM PDT 24
Peak memory 233704 kb
Host smart-5ba6d4d4-7354-488e-a927-158d9a25c75b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455485323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.455485323
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2905110230
Short name T907
Test name
Test status
Simulation time 165443788 ps
CPU time 2.77 seconds
Started May 21 02:54:24 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 206824 kb
Host smart-db15da4c-69c4-4079-923f-9fd9283a66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905110230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2905110230
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1444596884
Short name T562
Test name
Test status
Simulation time 266908580 ps
CPU time 3.66 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:38 PM PDT 24
Peak memory 208588 kb
Host smart-8386e562-14b1-4415-8e34-14eb4210d44b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444596884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1444596884
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2279637954
Short name T458
Test name
Test status
Simulation time 323254547 ps
CPU time 4.94 seconds
Started May 21 02:54:28 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 206840 kb
Host smart-343f0e87-24ac-42fe-8848-a0b667292e9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279637954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2279637954
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3412578672
Short name T593
Test name
Test status
Simulation time 35524051 ps
CPU time 2.29 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 207116 kb
Host smart-0d5cb9eb-6d25-4ba2-bb9c-2bbf0dccf8af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412578672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3412578672
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4033190367
Short name T615
Test name
Test status
Simulation time 79408597 ps
CPU time 2.1 seconds
Started May 21 02:54:31 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 208328 kb
Host smart-ee664972-0d58-461c-adf4-959c6409cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033190367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4033190367
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3935260739
Short name T670
Test name
Test status
Simulation time 37186620 ps
CPU time 2.37 seconds
Started May 21 02:54:25 PM PDT 24
Finished May 21 02:54:30 PM PDT 24
Peak memory 208304 kb
Host smart-7772f2e5-e629-49a0-8ed7-c4c1d8a2c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935260739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3935260739
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3752850026
Short name T707
Test name
Test status
Simulation time 54880939 ps
CPU time 3.74 seconds
Started May 21 02:54:33 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 207884 kb
Host smart-f11801bf-0c75-4cc4-857f-845686f582f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752850026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3752850026
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2415903277
Short name T909
Test name
Test status
Simulation time 77269847 ps
CPU time 1.82 seconds
Started May 21 02:54:31 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 214396 kb
Host smart-b2ad8178-ffe9-4a9e-9a03-c8a33826573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415903277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2415903277
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1370743319
Short name T804
Test name
Test status
Simulation time 89613321 ps
CPU time 0.82 seconds
Started May 21 02:55:43 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 206012 kb
Host smart-6102238f-9ec4-4484-a400-a0bb7dceca29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370743319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1370743319
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.187834596
Short name T769
Test name
Test status
Simulation time 38618375 ps
CPU time 2.15 seconds
Started May 21 02:55:43 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 207472 kb
Host smart-ecd830b5-fc04-4188-a35e-c549df665538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187834596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.187834596
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2568856755
Short name T103
Test name
Test status
Simulation time 37352266 ps
CPU time 2.71 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 217340 kb
Host smart-dc9d8b0c-ea66-456b-8b66-622cb8cb37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568856755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2568856755
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.618670833
Short name T333
Test name
Test status
Simulation time 98489086 ps
CPU time 3.09 seconds
Started May 21 02:55:45 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 206568 kb
Host smart-b43d50f2-0add-4907-a975-3f9992da20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618670833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.618670833
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.1230777692
Short name T277
Test name
Test status
Simulation time 167787977 ps
CPU time 5.06 seconds
Started May 21 02:55:40 PM PDT 24
Finished May 21 02:55:53 PM PDT 24
Peak memory 210320 kb
Host smart-030b34ed-5e0b-4404-9073-af89299e450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230777692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1230777692
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1974144963
Short name T882
Test name
Test status
Simulation time 138547951 ps
CPU time 2.26 seconds
Started May 21 02:55:47 PM PDT 24
Finished May 21 02:55:56 PM PDT 24
Peak memory 206896 kb
Host smart-fe12b9e7-33f4-4e37-b6b1-a47a575d0460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974144963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1974144963
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3504452142
Short name T549
Test name
Test status
Simulation time 135765520 ps
CPU time 4.23 seconds
Started May 21 02:55:45 PM PDT 24
Finished May 21 02:55:56 PM PDT 24
Peak memory 208656 kb
Host smart-80f0ff7f-d6e3-49ba-a3c4-378bc4d06f0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504452142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3504452142
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3401618619
Short name T807
Test name
Test status
Simulation time 495367402 ps
CPU time 4.21 seconds
Started May 21 02:55:41 PM PDT 24
Finished May 21 02:55:53 PM PDT 24
Peak memory 208528 kb
Host smart-dd0e13f0-f690-464d-a66a-f3c918494a5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401618619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3401618619
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.103748780
Short name T464
Test name
Test status
Simulation time 4311390563 ps
CPU time 41.05 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 208324 kb
Host smart-2c2e24d5-7c2d-4d49-b7e6-5d4b520d0efe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103748780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.103748780
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1171784754
Short name T870
Test name
Test status
Simulation time 191018887 ps
CPU time 2.18 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:55:53 PM PDT 24
Peak memory 207820 kb
Host smart-722cc813-a5ab-4e55-b81e-ab0d68ba6039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171784754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1171784754
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2489296147
Short name T624
Test name
Test status
Simulation time 2149275021 ps
CPU time 12.33 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 208004 kb
Host smart-10f954f5-70a2-4a4e-894e-47092bf1fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489296147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2489296147
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.542107595
Short name T315
Test name
Test status
Simulation time 144813432 ps
CPU time 3.27 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 218340 kb
Host smart-6b14c7a0-a9ab-4b49-8647-90bf6f449ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542107595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.542107595
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.4107909288
Short name T391
Test name
Test status
Simulation time 42421261 ps
CPU time 2.57 seconds
Started May 21 02:55:45 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 209932 kb
Host smart-99de14ec-86e3-46c3-9efc-4a23cd1a78e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107909288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4107909288
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.497027255
Short name T837
Test name
Test status
Simulation time 47654139 ps
CPU time 0.87 seconds
Started May 21 02:55:52 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 206020 kb
Host smart-53bcb164-161d-4350-9ea2-1e09e986ccf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497027255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.497027255
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2772244533
Short name T504
Test name
Test status
Simulation time 22322581 ps
CPU time 1.56 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 215560 kb
Host smart-874f4b8b-39d2-4b60-8cde-ee6395ac6f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772244533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2772244533
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2822919631
Short name T266
Test name
Test status
Simulation time 119500519 ps
CPU time 2.57 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:06 PM PDT 24
Peak memory 210036 kb
Host smart-b2d5fae8-5f47-4fe2-bdc0-98d238cce589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822919631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2822919631
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1985116417
Short name T91
Test name
Test status
Simulation time 47446341 ps
CPU time 1.97 seconds
Started May 21 02:55:51 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 214376 kb
Host smart-988998df-0036-418a-91db-3c346ebd928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985116417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1985116417
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1737362320
Short name T816
Test name
Test status
Simulation time 861323070 ps
CPU time 3.32 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:56:00 PM PDT 24
Peak memory 214252 kb
Host smart-3e443ceb-446d-4a25-a0b6-aa7cff8424c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737362320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1737362320
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3943436839
Short name T56
Test name
Test status
Simulation time 149632748 ps
CPU time 6.3 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 206728 kb
Host smart-ee4a5b1d-2397-4a6a-b33b-c1788f7d4207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943436839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3943436839
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.905253205
Short name T588
Test name
Test status
Simulation time 795469978 ps
CPU time 4.45 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:56:00 PM PDT 24
Peak memory 208848 kb
Host smart-dbeb2fcc-70b9-49bf-bf9a-6096ca1a9dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905253205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.905253205
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1526002295
Short name T880
Test name
Test status
Simulation time 967806227 ps
CPU time 13.11 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 208672 kb
Host smart-6904124b-6937-4c18-9267-d30f00bfad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526002295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1526002295
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4117473476
Short name T700
Test name
Test status
Simulation time 153102776 ps
CPU time 4.46 seconds
Started May 21 02:55:42 PM PDT 24
Finished May 21 02:55:54 PM PDT 24
Peak memory 208492 kb
Host smart-41142cd8-5966-4363-980b-b3e18647d667
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117473476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4117473476
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2320851858
Short name T515
Test name
Test status
Simulation time 267234284 ps
CPU time 7.72 seconds
Started May 21 02:55:43 PM PDT 24
Finished May 21 02:55:58 PM PDT 24
Peak memory 208692 kb
Host smart-a9aa1ec6-2ae8-431b-b74e-997d7ef9ce67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320851858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2320851858
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1932053582
Short name T403
Test name
Test status
Simulation time 2652574429 ps
CPU time 16.92 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 208096 kb
Host smart-e48b6ac0-0846-4563-bba4-e433a485ce30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932053582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1932053582
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.260352341
Short name T541
Test name
Test status
Simulation time 288970642 ps
CPU time 2.97 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 208280 kb
Host smart-45c4554e-c680-4a46-964a-213b6fe97b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260352341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.260352341
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1949024697
Short name T633
Test name
Test status
Simulation time 64245390 ps
CPU time 2.1 seconds
Started May 21 02:55:44 PM PDT 24
Finished May 21 02:55:53 PM PDT 24
Peak memory 206800 kb
Host smart-136ad6e9-7f9c-4480-8b5a-09eccb7fc34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949024697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1949024697
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2630326735
Short name T547
Test name
Test status
Simulation time 715040095 ps
CPU time 10.17 seconds
Started May 21 02:55:53 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 216676 kb
Host smart-1caf34aa-ed17-4347-9509-1ee115caadf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630326735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2630326735
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.685673489
Short name T472
Test name
Test status
Simulation time 147522860 ps
CPU time 3.47 seconds
Started May 21 02:55:52 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 208056 kb
Host smart-5b186fda-6d98-41e4-989b-6e27b6c044d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685673489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.685673489
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1440533435
Short name T726
Test name
Test status
Simulation time 59355262 ps
CPU time 2.62 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 210160 kb
Host smart-87ea70f6-1229-4d29-aac5-d38634d3bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440533435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1440533435
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.163162235
Short name T894
Test name
Test status
Simulation time 26266686 ps
CPU time 0.96 seconds
Started May 21 02:55:48 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 206172 kb
Host smart-99809399-2567-4d0b-bbc0-9f9852ef1ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163162235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.163162235
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.867943186
Short name T361
Test name
Test status
Simulation time 3326266260 ps
CPU time 10.8 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:07 PM PDT 24
Peak memory 215848 kb
Host smart-881c7b6d-6adf-416b-9dae-30b767266e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867943186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.867943186
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3235370723
Short name T630
Test name
Test status
Simulation time 294228850 ps
CPU time 3.87 seconds
Started May 21 02:55:48 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 215652 kb
Host smart-18189b0b-3d6a-47bb-8ac6-e319bfa2a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235370723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3235370723
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3370718709
Short name T685
Test name
Test status
Simulation time 108669432 ps
CPU time 2.82 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 214224 kb
Host smart-d4b0622d-e057-4ec2-a209-02dfceb75300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370718709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3370718709
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1285160003
Short name T273
Test name
Test status
Simulation time 83249931 ps
CPU time 2.02 seconds
Started May 21 02:55:51 PM PDT 24
Finished May 21 02:56:00 PM PDT 24
Peak memory 220872 kb
Host smart-5d6fe08f-bab5-4ee9-8b97-6f71ff364829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285160003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1285160003
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1043225553
Short name T204
Test name
Test status
Simulation time 38936287 ps
CPU time 2.62 seconds
Started May 21 02:55:48 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 209532 kb
Host smart-f4212ed4-f7ba-4f09-9b96-745bae9a11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043225553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1043225553
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.889708277
Short name T355
Test name
Test status
Simulation time 196673206 ps
CPU time 5.11 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:56:02 PM PDT 24
Peak memory 214360 kb
Host smart-6431d4a2-e856-4025-83aa-29ee74338e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889708277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.889708277
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3705980251
Short name T530
Test name
Test status
Simulation time 55807014 ps
CPU time 2.57 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:06 PM PDT 24
Peak memory 206616 kb
Host smart-2a19bc0f-84b6-4163-8e16-246340c7a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705980251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3705980251
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.551514432
Short name T326
Test name
Test status
Simulation time 91009692 ps
CPU time 2.7 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 207092 kb
Host smart-7c0bcab8-e469-4ec9-9959-99f36a739547
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551514432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.551514432
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1966136564
Short name T867
Test name
Test status
Simulation time 1925336818 ps
CPU time 6.09 seconds
Started May 21 02:55:48 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 207028 kb
Host smart-0b4e7303-ac35-4ca2-9c28-50ee7434c16f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966136564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1966136564
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1949593399
Short name T573
Test name
Test status
Simulation time 199691222 ps
CPU time 2.78 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 208908 kb
Host smart-99abf188-337a-4fba-8329-7ca93f77e85f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949593399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1949593399
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2262661647
Short name T810
Test name
Test status
Simulation time 109660610 ps
CPU time 2.37 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 209044 kb
Host smart-b814da39-d950-4666-a266-0304e508fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262661647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2262661647
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3107142927
Short name T770
Test name
Test status
Simulation time 1546126625 ps
CPU time 7.5 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:09 PM PDT 24
Peak memory 206560 kb
Host smart-d007717a-ba9e-4cc1-b52c-ff8943ba117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107142927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3107142927
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.124122259
Short name T895
Test name
Test status
Simulation time 5696174477 ps
CPU time 35.76 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 218652 kb
Host smart-720896d8-81e9-49f2-b8c1-3655d3de6cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124122259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.124122259
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2429786546
Short name T185
Test name
Test status
Simulation time 376405475 ps
CPU time 7.53 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 222580 kb
Host smart-087ed945-f288-482d-a349-dace9b6fba57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429786546 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2429786546
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1030840188
Short name T650
Test name
Test status
Simulation time 235511166 ps
CPU time 5.25 seconds
Started May 21 02:55:50 PM PDT 24
Finished May 21 02:56:02 PM PDT 24
Peak memory 209080 kb
Host smart-266e43fb-6b08-4e97-8f42-f947c15aa1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030840188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1030840188
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1994424542
Short name T871
Test name
Test status
Simulation time 14192520 ps
CPU time 0.78 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:02 PM PDT 24
Peak memory 206008 kb
Host smart-501e7502-ad21-4414-a5e6-f92fbf7e51e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994424542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1994424542
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2558285209
Short name T908
Test name
Test status
Simulation time 973721893 ps
CPU time 25.52 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 214736 kb
Host smart-072338ff-9ffc-4a15-9da1-4a16bf69e89c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558285209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2558285209
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.545047040
Short name T38
Test name
Test status
Simulation time 509569584 ps
CPU time 4.75 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:08 PM PDT 24
Peak memory 221736 kb
Host smart-a10319f1-96e8-4415-b1e6-6884e6db01c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545047040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.545047040
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1910844567
Short name T569
Test name
Test status
Simulation time 142394393 ps
CPU time 3.79 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 214468 kb
Host smart-491a75fa-36b7-42ad-bb5a-94948ea7b9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910844567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1910844567
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3990873532
Short name T812
Test name
Test status
Simulation time 169384975 ps
CPU time 3.74 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 214688 kb
Host smart-88587c24-b2bc-4020-9d5d-22d1ae811cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990873532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3990873532
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2345827226
Short name T595
Test name
Test status
Simulation time 92959426 ps
CPU time 2.82 seconds
Started May 21 02:56:00 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 216652 kb
Host smart-8b29f0fc-91ad-4160-ae56-7ad95c2f7397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345827226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2345827226
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3383509688
Short name T68
Test name
Test status
Simulation time 317098397 ps
CPU time 5.74 seconds
Started May 21 02:55:57 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 214448 kb
Host smart-e19e6fce-ede1-443c-bf9a-40afdd66e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383509688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3383509688
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4126307232
Short name T209
Test name
Test status
Simulation time 4016539156 ps
CPU time 73.57 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 208488 kb
Host smart-1df0fe8d-b754-4758-8a31-fa9fdc96a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126307232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4126307232
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2144976851
Short name T625
Test name
Test status
Simulation time 298928194 ps
CPU time 3 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 206888 kb
Host smart-2dc8d44f-9169-484d-a71c-f62b5f88faef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144976851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2144976851
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3567109341
Short name T557
Test name
Test status
Simulation time 62473993 ps
CPU time 2.45 seconds
Started May 21 02:55:58 PM PDT 24
Finished May 21 02:56:08 PM PDT 24
Peak memory 207392 kb
Host smart-c9c64795-d2f1-443e-a82c-aad5b6142d83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567109341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3567109341
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4256902940
Short name T253
Test name
Test status
Simulation time 880607393 ps
CPU time 6.38 seconds
Started May 21 02:55:48 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 208944 kb
Host smart-a64b9c14-2554-4fb5-95a2-e2ed0c225d8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256902940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4256902940
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2625931961
Short name T528
Test name
Test status
Simulation time 1238725402 ps
CPU time 18.47 seconds
Started May 21 02:55:57 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 208748 kb
Host smart-4f814346-5e49-42ca-9e78-414cb99c209a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625931961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2625931961
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1975253774
Short name T251
Test name
Test status
Simulation time 530659812 ps
CPU time 6.15 seconds
Started May 21 02:55:56 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 218216 kb
Host smart-2a1abb1c-14d6-4f0f-8709-bb06fa42e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975253774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1975253774
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.111331064
Short name T435
Test name
Test status
Simulation time 33956898 ps
CPU time 2.31 seconds
Started May 21 02:55:49 PM PDT 24
Finished May 21 02:55:58 PM PDT 24
Peak memory 208460 kb
Host smart-4c2f8c98-24b1-4a9b-ab15-0f364d744e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111331064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.111331064
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.980594631
Short name T224
Test name
Test status
Simulation time 480096515 ps
CPU time 10.78 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 222656 kb
Host smart-209f652d-3cc3-482e-9b94-4c53fd912c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980594631 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.980594631
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.966202451
Short name T716
Test name
Test status
Simulation time 137377236 ps
CPU time 1.7 seconds
Started May 21 02:56:00 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 210052 kb
Host smart-20d50918-df9b-470c-b09f-89a966ccb8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966202451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.966202451
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2595709720
Short name T474
Test name
Test status
Simulation time 52421769 ps
CPU time 0.94 seconds
Started May 21 02:56:03 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 206124 kb
Host smart-4117d065-7e10-446f-9d1c-cc3d476957fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595709720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2595709720
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2589982635
Short name T80
Test name
Test status
Simulation time 101432458 ps
CPU time 4.05 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:06 PM PDT 24
Peak memory 214396 kb
Host smart-ec40752d-353f-4761-9d2b-8b4061c0699a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589982635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2589982635
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.628819460
Short name T78
Test name
Test status
Simulation time 584375250 ps
CPU time 13.55 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 208852 kb
Host smart-cf4dea1b-e1b0-4487-a356-0a8a43bea6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628819460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.628819460
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1353404629
Short name T87
Test name
Test status
Simulation time 1757233471 ps
CPU time 50.12 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 219884 kb
Host smart-c85f1f7c-69c9-481d-933b-6f070f45e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353404629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1353404629
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2420608486
Short name T517
Test name
Test status
Simulation time 212976895 ps
CPU time 4.57 seconds
Started May 21 02:55:56 PM PDT 24
Finished May 21 02:56:08 PM PDT 24
Peak memory 220256 kb
Host smart-298a2e09-d2b4-43c1-8bae-f80f7ef32799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420608486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2420608486
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1307904613
Short name T613
Test name
Test status
Simulation time 100862974 ps
CPU time 4.04 seconds
Started May 21 02:55:57 PM PDT 24
Finished May 21 02:56:09 PM PDT 24
Peak memory 214408 kb
Host smart-e1c77dc0-e929-43bf-b126-c8b477f60d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307904613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1307904613
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2154096266
Short name T758
Test name
Test status
Simulation time 3597962878 ps
CPU time 21.97 seconds
Started May 21 02:56:00 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 208604 kb
Host smart-4834da51-9d69-4c56-8487-ee6570c9269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154096266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2154096266
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3186905460
Short name T317
Test name
Test status
Simulation time 165571501 ps
CPU time 2.46 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:04 PM PDT 24
Peak memory 207604 kb
Host smart-a17df094-5130-4a09-8a4a-64e63cf252fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186905460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3186905460
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3057920041
Short name T262
Test name
Test status
Simulation time 97629377 ps
CPU time 3.03 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:05 PM PDT 24
Peak memory 207048 kb
Host smart-2f8c9a59-65ce-4e47-88b8-f3081af6ba1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057920041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3057920041
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3015797472
Short name T570
Test name
Test status
Simulation time 451408404 ps
CPU time 4.38 seconds
Started May 21 02:55:55 PM PDT 24
Finished May 21 02:56:07 PM PDT 24
Peak memory 209000 kb
Host smart-46ffbd77-dc6a-481e-a642-22d9490de682
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015797472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3015797472
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1433080371
Short name T583
Test name
Test status
Simulation time 359567293 ps
CPU time 4.24 seconds
Started May 21 02:56:02 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 208232 kb
Host smart-2c62adba-6946-47ac-a1d7-b11abd07160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433080371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1433080371
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4096654356
Short name T510
Test name
Test status
Simulation time 672511498 ps
CPU time 8.23 seconds
Started May 21 02:55:54 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 206896 kb
Host smart-75e8305c-a208-490d-968d-5aeb5fd78540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096654356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4096654356
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2295038401
Short name T223
Test name
Test status
Simulation time 545798014 ps
CPU time 20.39 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 222524 kb
Host smart-15486e4a-d593-40bc-ace1-f42b856d4013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295038401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2295038401
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.360090225
Short name T473
Test name
Test status
Simulation time 517911248 ps
CPU time 9.31 seconds
Started May 21 02:55:57 PM PDT 24
Finished May 21 02:56:15 PM PDT 24
Peak memory 218240 kb
Host smart-8c294a2d-3d11-4cb8-9579-952fb0d7e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360090225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.360090225
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1666819903
Short name T840
Test name
Test status
Simulation time 23414065 ps
CPU time 0.74 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:18 PM PDT 24
Peak memory 205960 kb
Host smart-a80b7d4e-474b-45ff-a729-e51fafc5ae3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666819903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1666819903
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1930270330
Short name T348
Test name
Test status
Simulation time 41057582 ps
CPU time 3.03 seconds
Started May 21 02:56:04 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 215412 kb
Host smart-08ab8e37-7515-4da7-8e76-8073a5eb425f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930270330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1930270330
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1406018108
Short name T589
Test name
Test status
Simulation time 90886714 ps
CPU time 1.81 seconds
Started May 21 02:56:03 PM PDT 24
Finished May 21 02:56:12 PM PDT 24
Peak memory 208960 kb
Host smart-e776deaa-f19d-47f5-8dfe-1cd96ed2426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406018108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1406018108
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3875913530
Short name T136
Test name
Test status
Simulation time 174188703 ps
CPU time 2.64 seconds
Started May 21 02:56:04 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 207496 kb
Host smart-ab1aeb49-c23b-45ac-a00a-ab95744c12db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875913530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3875913530
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1529034429
Short name T51
Test name
Test status
Simulation time 47017667 ps
CPU time 2.49 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 214320 kb
Host smart-b6d0bbc6-8e87-4063-87ad-c9bb583fc01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529034429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1529034429
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.448480087
Short name T306
Test name
Test status
Simulation time 90548017 ps
CPU time 4.25 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:19 PM PDT 24
Peak memory 222424 kb
Host smart-4cf8b0c9-0712-4684-8da9-9db757fba47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448480087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.448480087
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.399579214
Short name T58
Test name
Test status
Simulation time 319174975 ps
CPU time 3 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:12 PM PDT 24
Peak memory 219256 kb
Host smart-d190fc30-b05a-4bf7-94f4-8a5b2b41b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399579214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.399579214
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.274663585
Short name T693
Test name
Test status
Simulation time 53391907 ps
CPU time 3.35 seconds
Started May 21 02:56:04 PM PDT 24
Finished May 21 02:56:15 PM PDT 24
Peak memory 214376 kb
Host smart-4bf05cda-9e85-4bd6-9715-b9eb5a85f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274663585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.274663585
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2390443969
Short name T774
Test name
Test status
Simulation time 70956849 ps
CPU time 2.65 seconds
Started May 21 02:56:04 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 208404 kb
Host smart-0ab82339-372f-4b2d-bb24-8e395791cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390443969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2390443969
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3671294377
Short name T516
Test name
Test status
Simulation time 8912510195 ps
CPU time 15.42 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 208692 kb
Host smart-ff761b7f-b58f-4a97-83a7-f1bc79bf5af8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671294377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3671294377
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3042322570
Short name T535
Test name
Test status
Simulation time 118227133 ps
CPU time 2.42 seconds
Started May 21 02:56:02 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 207724 kb
Host smart-57b36559-a294-4052-8b4e-12fd046c7f55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042322570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3042322570
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.416086080
Short name T800
Test name
Test status
Simulation time 2032698316 ps
CPU time 26.84 seconds
Started May 21 02:56:02 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 208064 kb
Host smart-fe9e8c1b-23f6-47bc-ab83-9617a4775aee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416086080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.416086080
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2119509221
Short name T407
Test name
Test status
Simulation time 42743992 ps
CPU time 2.2 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:10 PM PDT 24
Peak memory 208284 kb
Host smart-732215f0-6423-4c6a-b792-3325d38ba4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119509221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2119509221
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3475599011
Short name T748
Test name
Test status
Simulation time 490160076 ps
CPU time 5.6 seconds
Started May 21 02:56:02 PM PDT 24
Finished May 21 02:56:15 PM PDT 24
Peak memory 208772 kb
Host smart-c3e23eb1-46b6-4498-a6f6-fe476aeab1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475599011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3475599011
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3704495821
Short name T638
Test name
Test status
Simulation time 324587573 ps
CPU time 16.46 seconds
Started May 21 02:56:03 PM PDT 24
Finished May 21 02:56:26 PM PDT 24
Peak memory 215820 kb
Host smart-331df0a3-a66b-47a4-a896-bba8e78455e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704495821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3704495821
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2516037545
Short name T457
Test name
Test status
Simulation time 460440002 ps
CPU time 7.31 seconds
Started May 21 02:56:02 PM PDT 24
Finished May 21 02:56:17 PM PDT 24
Peak memory 208660 kb
Host smart-2680ae94-cf75-4226-ac27-d41e9dfd4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516037545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2516037545
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1089916060
Short name T170
Test name
Test status
Simulation time 80061148 ps
CPU time 2.34 seconds
Started May 21 02:56:01 PM PDT 24
Finished May 21 02:56:11 PM PDT 24
Peak memory 210260 kb
Host smart-e30d42e7-f232-40cc-a9f2-9b823a532929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089916060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1089916060
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.494059062
Short name T192
Test name
Test status
Simulation time 104348813 ps
CPU time 0.8 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:17 PM PDT 24
Peak memory 205996 kb
Host smart-249e2006-f0f1-4918-b7bd-d09a8dc0dfb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494059062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.494059062
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3712831984
Short name T50
Test name
Test status
Simulation time 200359359 ps
CPU time 3.61 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 218396 kb
Host smart-93509817-9b23-46ad-8d3a-6a799289e1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712831984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3712831984
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1227357341
Short name T95
Test name
Test status
Simulation time 543254487 ps
CPU time 5.35 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 214380 kb
Host smart-81727910-b0d6-4cdb-bcc0-16990bfd97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227357341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1227357341
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3032688912
Short name T643
Test name
Test status
Simulation time 638851725 ps
CPU time 2.98 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:18 PM PDT 24
Peak memory 214292 kb
Host smart-abc55ce3-30b8-4ff3-94ee-ee93ccf48391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032688912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3032688912
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1496151139
Short name T744
Test name
Test status
Simulation time 143411463 ps
CPU time 2.73 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:25 PM PDT 24
Peak memory 220208 kb
Host smart-7e33751e-a471-4bce-9e80-4b725a5119f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496151139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1496151139
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1122010961
Short name T318
Test name
Test status
Simulation time 50221418 ps
CPU time 3.07 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 207912 kb
Host smart-e7ba8523-daf9-444b-9913-14a3f99096a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122010961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1122010961
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1121393296
Short name T201
Test name
Test status
Simulation time 7199022292 ps
CPU time 43.43 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 208336 kb
Host smart-6da63786-ef33-414b-941b-060f8edfcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121393296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1121393296
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3549604452
Short name T734
Test name
Test status
Simulation time 3454324444 ps
CPU time 24.48 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 208668 kb
Host smart-d89dbadc-6af2-47e4-a9d0-bab9aaa87f71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549604452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3549604452
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1382753585
Short name T401
Test name
Test status
Simulation time 22820678 ps
CPU time 1.85 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 206908 kb
Host smart-7d064fb9-4be2-4422-b352-2f08cc40442e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382753585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1382753585
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1765695624
Short name T728
Test name
Test status
Simulation time 220312045 ps
CPU time 2.53 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 207048 kb
Host smart-ce52b633-fb32-4c95-b3ef-dd40855b8b06
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765695624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1765695624
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3300978155
Short name T203
Test name
Test status
Simulation time 1621199947 ps
CPU time 25.29 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 221580 kb
Host smart-f347399b-fc4e-4ced-bc11-0cbb16fa689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300978155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3300978155
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3411527971
Short name T14
Test name
Test status
Simulation time 116256521 ps
CPU time 3.22 seconds
Started May 21 02:56:10 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 208648 kb
Host smart-9d0ba6e9-b387-4df1-8011-711fb2679640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411527971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3411527971
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3718838017
Short name T212
Test name
Test status
Simulation time 1018869091 ps
CPU time 10.45 seconds
Started May 21 02:56:06 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 222468 kb
Host smart-1571d1c7-c5a2-4cb1-8047-9faa3836465a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718838017 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3718838017
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4026471318
Short name T12
Test name
Test status
Simulation time 165952213 ps
CPU time 4.41 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 208260 kb
Host smart-2f76b11c-518e-42a5-b233-aa8229560513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026471318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4026471318
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2834089154
Short name T43
Test name
Test status
Simulation time 118164227 ps
CPU time 3.48 seconds
Started May 21 02:56:06 PM PDT 24
Finished May 21 02:56:17 PM PDT 24
Peak memory 210508 kb
Host smart-8c7f536d-91bb-480e-9ab6-4167a22965da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834089154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2834089154
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.845796272
Short name T627
Test name
Test status
Simulation time 159212384 ps
CPU time 1.35 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 206156 kb
Host smart-16d66fab-f31b-428e-b093-e8f4ed419db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845796272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.845796272
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.971225846
Short name T415
Test name
Test status
Simulation time 3559983980 ps
CPU time 12.99 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:30 PM PDT 24
Peak memory 215448 kb
Host smart-c48de3fc-b20e-4ad1-b5c2-6f50eef523b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971225846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.971225846
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4099299434
Short name T646
Test name
Test status
Simulation time 109931311 ps
CPU time 3.35 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 221844 kb
Host smart-11242042-cd4d-4140-a6b8-c30e97425680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099299434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4099299434
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3848028643
Short name T75
Test name
Test status
Simulation time 543439118 ps
CPU time 14.6 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 222436 kb
Host smart-3abc6b5c-ffcc-403e-a507-19ce2f3e8e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848028643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3848028643
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.189941245
Short name T741
Test name
Test status
Simulation time 141596954 ps
CPU time 3.36 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 222544 kb
Host smart-55c33490-3da9-4e77-b7c0-6109402f9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189941245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.189941245
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2373499320
Short name T579
Test name
Test status
Simulation time 79615702 ps
CPU time 3.08 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 214316 kb
Host smart-cb912b07-1870-4338-92e4-11747e6c2836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373499320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2373499320
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1227732787
Short name T765
Test name
Test status
Simulation time 335862196 ps
CPU time 5 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 215176 kb
Host smart-165c0a8e-f765-45f4-bbd8-1e4a50dd5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227732787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1227732787
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.42497087
Short name T424
Test name
Test status
Simulation time 516924665 ps
CPU time 6.01 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 218428 kb
Host smart-34f55141-799e-482b-8ba1-4c0c1577cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42497087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.42497087
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.981210839
Short name T341
Test name
Test status
Simulation time 297886084 ps
CPU time 3.8 seconds
Started May 21 02:56:10 PM PDT 24
Finished May 21 02:56:25 PM PDT 24
Peak memory 208676 kb
Host smart-c78ee3c4-6066-4f82-9e21-ee9d4312ffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981210839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.981210839
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2918497409
Short name T822
Test name
Test status
Simulation time 89977910 ps
CPU time 1.83 seconds
Started May 21 02:56:10 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 207144 kb
Host smart-348040e3-972a-41ef-8432-d55a3e666fd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918497409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2918497409
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2061882993
Short name T623
Test name
Test status
Simulation time 937536976 ps
CPU time 2.98 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:19 PM PDT 24
Peak memory 206988 kb
Host smart-893ce839-a4f7-4d9d-bf81-ce44eb69c600
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061882993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2061882993
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.779446845
Short name T524
Test name
Test status
Simulation time 404989402 ps
CPU time 2.93 seconds
Started May 21 02:56:10 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 206544 kb
Host smart-86724ff3-22f7-4d4e-b10e-e30a9f6ad03c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779446845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.779446845
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3222012760
Short name T109
Test name
Test status
Simulation time 347775997 ps
CPU time 3.79 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 209084 kb
Host smart-ef1687f1-420e-4ca2-81ea-1d1b1bc61cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222012760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3222012760
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2394405798
Short name T890
Test name
Test status
Simulation time 147571788 ps
CPU time 3.47 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 208056 kb
Host smart-c99ab547-04ef-4645-84f7-f0db4c251c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394405798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2394405798
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2480530804
Short name T198
Test name
Test status
Simulation time 796256582 ps
CPU time 19.16 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 215244 kb
Host smart-e9861be6-3906-4679-8beb-e1f1e70bc5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480530804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2480530804
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1246197471
Short name T506
Test name
Test status
Simulation time 195025423 ps
CPU time 5.05 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 210216 kb
Host smart-1cc11136-b0bc-4c86-918c-0fcad401910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246197471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1246197471
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.666343151
Short name T861
Test name
Test status
Simulation time 96134124 ps
CPU time 2.3 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 210040 kb
Host smart-6ea8b918-4609-425c-a67d-2d793c2a200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666343151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.666343151
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2962535509
Short name T107
Test name
Test status
Simulation time 15859383 ps
CPU time 0.76 seconds
Started May 21 02:56:10 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 205988 kb
Host smart-6d191ce8-0026-4a19-bb53-0e2f319a8c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962535509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2962535509
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1362691195
Short name T278
Test name
Test status
Simulation time 367597648 ps
CPU time 2.87 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 215184 kb
Host smart-661401b6-07b8-4657-84f5-e2fc63d75ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362691195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1362691195
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3588259037
Short name T22
Test name
Test status
Simulation time 428926097 ps
CPU time 4.91 seconds
Started May 21 02:56:17 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 222592 kb
Host smart-7e65d128-59a5-431a-8fb8-eb987aabc94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588259037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3588259037
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3617411312
Short name T597
Test name
Test status
Simulation time 30801044 ps
CPU time 2.01 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 208264 kb
Host smart-0e58b2cd-d0cf-4374-a99c-0b6e13297bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617411312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3617411312
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1158381934
Short name T97
Test name
Test status
Simulation time 374101795 ps
CPU time 5.28 seconds
Started May 21 02:56:17 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 214300 kb
Host smart-e8f81a31-a75c-4c26-9531-6507ad71887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158381934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1158381934
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.262038828
Short name T779
Test name
Test status
Simulation time 594252943 ps
CPU time 10.58 seconds
Started May 21 02:56:16 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 212104 kb
Host smart-9daf1116-f331-4608-879c-0a27683fd0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262038828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.262038828
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2695818659
Short name T17
Test name
Test status
Simulation time 137202387 ps
CPU time 3.42 seconds
Started May 21 02:56:17 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 210128 kb
Host smart-26eaa421-256d-42b9-941d-d2146ad9ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695818659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2695818659
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2838157388
Short name T367
Test name
Test status
Simulation time 130670169 ps
CPU time 5.82 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:21 PM PDT 24
Peak memory 214460 kb
Host smart-901a9832-74d1-4dcb-8eae-314fead6a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838157388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2838157388
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3405026407
Short name T364
Test name
Test status
Simulation time 172549148 ps
CPU time 5 seconds
Started May 21 02:56:08 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 208696 kb
Host smart-00c7e1c2-6678-4579-ab24-f33085650f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405026407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3405026407
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3839550726
Short name T763
Test name
Test status
Simulation time 112456938 ps
CPU time 3.92 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 207060 kb
Host smart-14990421-1235-4ab1-90c0-b6dcd1843f13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839550726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3839550726
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.216008958
Short name T552
Test name
Test status
Simulation time 91479653 ps
CPU time 3.15 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:25 PM PDT 24
Peak memory 208600 kb
Host smart-311907a0-2d5e-4e6b-9ae3-62fe66d9ec74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216008958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.216008958
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3326051912
Short name T402
Test name
Test status
Simulation time 250307976 ps
CPU time 6.38 seconds
Started May 21 02:56:07 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 209040 kb
Host smart-09b248ff-377e-4107-a490-0aed5a33d35b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326051912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3326051912
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_smoke.576048482
Short name T844
Test name
Test status
Simulation time 86837557 ps
CPU time 3.18 seconds
Started May 21 02:56:09 PM PDT 24
Finished May 21 02:56:22 PM PDT 24
Peak memory 206900 kb
Host smart-116a121a-33a2-494e-b91d-05b3af4f09c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576048482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.576048482
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2315699071
Short name T660
Test name
Test status
Simulation time 885423042 ps
CPU time 26.46 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 208604 kb
Host smart-c3e2f660-e076-4775-b93f-0cc6eb31d06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315699071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2315699071
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.834419911
Short name T131
Test name
Test status
Simulation time 1008972326 ps
CPU time 22.25 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 222612 kb
Host smart-2e290165-0507-4ada-bb73-aa639af5e8db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834419911 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.834419911
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3649529710
Short name T255
Test name
Test status
Simulation time 64637785 ps
CPU time 4.42 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 219784 kb
Host smart-8209eab0-1474-402d-8fdf-b37db5339311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649529710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3649529710
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.628088653
Short name T910
Test name
Test status
Simulation time 54463443 ps
CPU time 2.03 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:23 PM PDT 24
Peak memory 209920 kb
Host smart-5dd59d05-94d1-45e9-93d7-d46584b4aa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628088653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.628088653
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3541812271
Short name T461
Test name
Test status
Simulation time 35652725 ps
CPU time 0.8 seconds
Started May 21 02:56:17 PM PDT 24
Finished May 21 02:56:30 PM PDT 24
Peak memory 206012 kb
Host smart-c5a81985-4069-424b-8fa3-23eec2a5982b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541812271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3541812271
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.254337705
Short name T419
Test name
Test status
Simulation time 192908207 ps
CPU time 3.86 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:30 PM PDT 24
Peak memory 214376 kb
Host smart-80d31efb-56f6-40ad-b971-c7b13762e163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254337705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.254337705
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1707650060
Short name T31
Test name
Test status
Simulation time 57548376 ps
CPU time 2.22 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:27 PM PDT 24
Peak memory 214324 kb
Host smart-437f8786-0732-4127-a104-a6d75b397a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707650060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1707650060
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3639227318
Short name T885
Test name
Test status
Simulation time 56009956 ps
CPU time 2.06 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:24 PM PDT 24
Peak memory 209244 kb
Host smart-32ffd025-6d33-481a-8f4c-7975202f29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639227318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3639227318
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2152756463
Short name T94
Test name
Test status
Simulation time 106684196 ps
CPU time 4.85 seconds
Started May 21 02:56:16 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 214352 kb
Host smart-0c37ee3e-dc89-49c5-ad98-4162e47c9168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152756463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2152756463
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3364555372
Short name T891
Test name
Test status
Simulation time 175572818 ps
CPU time 2.74 seconds
Started May 21 02:56:16 PM PDT 24
Finished May 21 02:56:31 PM PDT 24
Peak memory 214308 kb
Host smart-e3a7ba9d-6667-43ce-bd60-ebecd1d59358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364555372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3364555372
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1607933600
Short name T221
Test name
Test status
Simulation time 61408285 ps
CPU time 2.95 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 219268 kb
Host smart-0d8018bc-ce8d-4424-aa50-b49831fa1923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607933600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1607933600
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.562267216
Short name T635
Test name
Test status
Simulation time 277080510 ps
CPU time 10.27 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 219404 kb
Host smart-74bccd39-2512-48f4-8626-34fc26957636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562267216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.562267216
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3502883914
Short name T649
Test name
Test status
Simulation time 20578327 ps
CPU time 1.81 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:27 PM PDT 24
Peak memory 206880 kb
Host smart-89a3a59b-496b-427d-992c-5eb2694125a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502883914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3502883914
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2244042546
Short name T720
Test name
Test status
Simulation time 59528953 ps
CPU time 2.91 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 208028 kb
Host smart-4e33c8f5-10d7-42e5-9499-ad98fae7af7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244042546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2244042546
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3850378556
Short name T913
Test name
Test status
Simulation time 150561161 ps
CPU time 2.9 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 208848 kb
Host smart-7a0843d3-7fad-46f2-9f9b-ae4fba60744b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850378556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3850378556
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3647781525
Short name T824
Test name
Test status
Simulation time 465355605 ps
CPU time 10.35 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 208096 kb
Host smart-bf9460ae-253c-4b5d-8a40-7929a4a3693e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647781525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3647781525
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1478915938
Short name T687
Test name
Test status
Simulation time 134538879 ps
CPU time 2.32 seconds
Started May 21 02:56:15 PM PDT 24
Finished May 21 02:56:30 PM PDT 24
Peak memory 208680 kb
Host smart-ef44ec4b-423d-43be-b622-e065bc0022c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478915938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1478915938
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.638744042
Short name T433
Test name
Test status
Simulation time 679471077 ps
CPU time 6.59 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 208876 kb
Host smart-b1d3441d-9359-490f-9ac8-6c8f166edf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638744042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.638744042
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1886701006
Short name T738
Test name
Test status
Simulation time 2353451961 ps
CPU time 11.8 seconds
Started May 21 02:56:12 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 207356 kb
Host smart-6ba975f0-1563-4fc3-b189-ac87b74d31dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886701006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1886701006
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4254641317
Short name T393
Test name
Test status
Simulation time 182120474 ps
CPU time 2.11 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 210072 kb
Host smart-0aa92496-f12a-452e-83ca-d250ee2121fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254641317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.4254641317
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2557727940
Short name T431
Test name
Test status
Simulation time 12243725 ps
CPU time 0.88 seconds
Started May 21 02:54:37 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 205980 kb
Host smart-e39b85df-fd22-47d3-a864-70353705786e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557727940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2557727940
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2263471763
Short name T412
Test name
Test status
Simulation time 447288999 ps
CPU time 3.89 seconds
Started May 21 02:54:33 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 215460 kb
Host smart-b4d31586-e4d5-43d5-a3de-ea9684ef9884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263471763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2263471763
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1360570565
Short name T717
Test name
Test status
Simulation time 193191329 ps
CPU time 7.2 seconds
Started May 21 02:54:44 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 221276 kb
Host smart-d05dbf83-2e83-4110-980d-7e6082efd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360570565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1360570565
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.852573850
Short name T257
Test name
Test status
Simulation time 48608912 ps
CPU time 2.36 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 218392 kb
Host smart-a6eda285-bdf3-476a-bad9-76da7d720ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852573850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.852573850
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3764392356
Short name T287
Test name
Test status
Simulation time 87157001 ps
CPU time 1.7 seconds
Started May 21 02:54:36 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 214464 kb
Host smart-62182ffe-c216-4e02-9c91-0fccf59d2c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764392356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3764392356
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2860986006
Short name T307
Test name
Test status
Simulation time 56781314 ps
CPU time 3.16 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 214416 kb
Host smart-ab6ef61b-a659-4d7d-83b7-743138b7cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860986006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2860986006
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3046521743
Short name T229
Test name
Test status
Simulation time 34272615 ps
CPU time 2.15 seconds
Started May 21 02:54:34 PM PDT 24
Finished May 21 02:54:40 PM PDT 24
Peak memory 220924 kb
Host smart-8b7b3834-3601-49c2-b2b0-b344e3116061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046521743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3046521743
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.517860147
Short name T11
Test name
Test status
Simulation time 2647422745 ps
CPU time 10.48 seconds
Started May 21 02:54:37 PM PDT 24
Finished May 21 02:54:51 PM PDT 24
Peak memory 229216 kb
Host smart-5b2d09bf-ee5e-4ff5-b9cf-facf43485426
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517860147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.517860147
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.28057759
Short name T745
Test name
Test status
Simulation time 784045821 ps
CPU time 5.9 seconds
Started May 21 02:54:29 PM PDT 24
Finished May 21 02:54:38 PM PDT 24
Peak memory 207968 kb
Host smart-e037b100-71d9-4d07-9cf2-28b6f37a3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28057759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.28057759
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3051354123
Short name T893
Test name
Test status
Simulation time 176288821 ps
CPU time 2.58 seconds
Started May 21 02:54:39 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 206584 kb
Host smart-ac041c40-5d89-4719-857f-8d2e02b2996e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051354123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3051354123
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3341269086
Short name T484
Test name
Test status
Simulation time 125298599 ps
CPU time 4.72 seconds
Started May 21 02:54:29 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 208124 kb
Host smart-560b17f4-b841-4058-ba32-de30d3a76e91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341269086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3341269086
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1026705
Short name T501
Test name
Test status
Simulation time 121097006 ps
CPU time 2.3 seconds
Started May 21 02:54:27 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 206912 kb
Host smart-ad9797be-fec7-45fd-83fc-b8aacbfd9b5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1026705
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2647074307
Short name T352
Test name
Test status
Simulation time 44557941 ps
CPU time 2.14 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 214320 kb
Host smart-9662898d-7146-405c-a564-fb8d267a49bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647074307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2647074307
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3194667477
Short name T16
Test name
Test status
Simulation time 28044523 ps
CPU time 2.04 seconds
Started May 21 02:54:30 PM PDT 24
Finished May 21 02:54:35 PM PDT 24
Peak memory 208648 kb
Host smart-546a47fa-d1ee-421f-9898-8bb62a42653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194667477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3194667477
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3604996780
Short name T676
Test name
Test status
Simulation time 2039530146 ps
CPU time 60.58 seconds
Started May 21 02:54:36 PM PDT 24
Finished May 21 02:55:41 PM PDT 24
Peak memory 222628 kb
Host smart-0893d213-f52e-4efa-95f7-dd168ce61ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604996780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3604996780
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.336455086
Short name T809
Test name
Test status
Simulation time 137610486 ps
CPU time 3.61 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 218164 kb
Host smart-004894da-75c9-43e3-acef-810512dca792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336455086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.336455086
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2779101624
Short name T133
Test name
Test status
Simulation time 998936610 ps
CPU time 13.3 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 211232 kb
Host smart-3c30daf8-dbf7-4890-a02f-13228be37265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779101624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2779101624
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.723455554
Short name T432
Test name
Test status
Simulation time 14293244 ps
CPU time 0.77 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 205932 kb
Host smart-3b84852a-6320-4107-8016-f44dca6f983e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723455554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.723455554
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2521394355
Short name T19
Test name
Test status
Simulation time 291072383 ps
CPU time 3.52 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 221372 kb
Host smart-1fcf836e-91da-40a4-a85e-a3d73cbbba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521394355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2521394355
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1757540592
Short name T835
Test name
Test status
Simulation time 59077302 ps
CPU time 1.66 seconds
Started May 21 02:56:15 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 209388 kb
Host smart-d57bd040-4e4a-4bc5-800b-8e71c28493f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757540592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1757540592
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1696229329
Short name T217
Test name
Test status
Simulation time 328862506 ps
CPU time 3.49 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 218100 kb
Host smart-92d2e013-dd82-43ea-935f-167af16f42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696229329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1696229329
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.603672574
Short name T682
Test name
Test status
Simulation time 72345876 ps
CPU time 3.41 seconds
Started May 21 02:56:16 PM PDT 24
Finished May 21 02:56:31 PM PDT 24
Peak memory 214348 kb
Host smart-d4676819-423b-4340-bfeb-b9e171681f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603672574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.603672574
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.255191558
Short name T138
Test name
Test status
Simulation time 59359044 ps
CPU time 2.79 seconds
Started May 21 02:56:11 PM PDT 24
Finished May 21 02:56:25 PM PDT 24
Peak memory 207948 kb
Host smart-ba3e5442-4653-42aa-abd6-b7b456ca79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255191558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.255191558
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3272931730
Short name T594
Test name
Test status
Simulation time 131582763 ps
CPU time 2.51 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 206868 kb
Host smart-f431a570-9eff-4c25-84b5-f87dea05dc60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272931730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3272931730
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3125806200
Short name T550
Test name
Test status
Simulation time 553564683 ps
CPU time 3.54 seconds
Started May 21 02:56:13 PM PDT 24
Finished May 21 02:56:28 PM PDT 24
Peak memory 208764 kb
Host smart-bb16d34e-3daa-4f9b-b8df-b70b657240f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125806200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3125806200
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3053627080
Short name T600
Test name
Test status
Simulation time 250178275 ps
CPU time 6.53 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 208708 kb
Host smart-755a1f30-657e-447c-8cfa-e39d0aafbee0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053627080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3053627080
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4284570640
Short name T756
Test name
Test status
Simulation time 40942937 ps
CPU time 1.91 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 208168 kb
Host smart-0504101c-98fb-48ec-bd61-75fa57d1cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284570640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4284570640
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3280396926
Short name T586
Test name
Test status
Simulation time 129029080 ps
CPU time 2.96 seconds
Started May 21 02:56:14 PM PDT 24
Finished May 21 02:56:29 PM PDT 24
Peak memory 208920 kb
Host smart-4d2f0558-121c-45da-b0e8-2019b1e639a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280396926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3280396926
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4161375244
Short name T344
Test name
Test status
Simulation time 1838018884 ps
CPU time 32.7 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:57:05 PM PDT 24
Peak memory 215268 kb
Host smart-e507ca9f-721b-44de-b831-b84bf064e488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161375244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4161375244
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.252612332
Short name T357
Test name
Test status
Simulation time 156058419 ps
CPU time 6.52 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 222588 kb
Host smart-01d14ed0-a787-47ce-a3a8-f156d8a331bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252612332 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.252612332
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2538540344
Short name T492
Test name
Test status
Simulation time 269194154 ps
CPU time 6.23 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 208304 kb
Host smart-c1d67fc6-1eb4-4f63-b224-a86d7ce873b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538540344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2538540344
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3003455390
Short name T648
Test name
Test status
Simulation time 526082646 ps
CPU time 3.01 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 210520 kb
Host smart-2ee9ae5f-ca19-4903-8fb8-ecf133faf8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003455390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3003455390
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1856524485
Short name T444
Test name
Test status
Simulation time 7788114 ps
CPU time 0.71 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 206016 kb
Host smart-4993cd7a-e02f-4a8e-9368-97f90edf9a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856524485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1856524485
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3620618133
Short name T240
Test name
Test status
Simulation time 62644714 ps
CPU time 4.45 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 214380 kb
Host smart-9bbcea33-ba28-4ed0-a3cb-6f6549ab0bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620618133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3620618133
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2925896241
Short name T561
Test name
Test status
Simulation time 410700215 ps
CPU time 4.48 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 222792 kb
Host smart-51d9987e-771b-4249-a770-4f9781c0590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925896241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2925896241
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3077261135
Short name T296
Test name
Test status
Simulation time 59769854 ps
CPU time 2.85 seconds
Started May 21 02:56:18 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 214468 kb
Host smart-804903ff-6cf2-414b-8e51-7b2ac9b8ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077261135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3077261135
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.513885466
Short name T23
Test name
Test status
Simulation time 1014407920 ps
CPU time 5.29 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:38 PM PDT 24
Peak memory 222208 kb
Host smart-5b665f3b-6ce5-4d24-8a3f-0ddf34d79463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513885466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.513885466
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1892135746
Short name T347
Test name
Test status
Simulation time 151726104 ps
CPU time 4.26 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 210224 kb
Host smart-96047971-8632-42f4-af0d-c9b8fade3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892135746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1892135746
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1824151512
Short name T653
Test name
Test status
Simulation time 1156916247 ps
CPU time 3.27 seconds
Started May 21 02:56:26 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 214464 kb
Host smart-cfd83572-8bd3-4369-92f2-d7477f7adfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824151512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1824151512
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4265361066
Short name T382
Test name
Test status
Simulation time 144623705 ps
CPU time 2.82 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 207444 kb
Host smart-a1279083-f72b-442c-a3f2-cb719f8eaee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265361066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4265361066
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1799220216
Short name T437
Test name
Test status
Simulation time 501803011 ps
CPU time 4.51 seconds
Started May 21 02:56:23 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 206924 kb
Host smart-c197dfe5-8c3c-43ee-9aa5-159e06cf5931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799220216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1799220216
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2448052344
Short name T886
Test name
Test status
Simulation time 3402827171 ps
CPU time 35.1 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 208804 kb
Host smart-d62d2384-2548-4cfe-8324-1ecb61088392
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448052344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2448052344
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1036593114
Short name T526
Test name
Test status
Simulation time 287730880 ps
CPU time 6.05 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 208656 kb
Host smart-d4061479-4b63-42b1-b5af-9e04265199e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036593114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1036593114
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1267678286
Short name T576
Test name
Test status
Simulation time 191726091 ps
CPU time 2.9 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 210128 kb
Host smart-10903f72-c7d8-49f8-bde7-a171128df10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267678286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1267678286
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4045981774
Short name T750
Test name
Test status
Simulation time 150334065 ps
CPU time 3.96 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 206936 kb
Host smart-f3f6470d-8b6d-4ece-befc-1930f57a34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045981774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4045981774
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1126044638
Short name T247
Test name
Test status
Simulation time 293585136 ps
CPU time 4.26 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 207048 kb
Host smart-3590602f-6267-46d1-a67e-beca4813b50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126044638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1126044638
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2386697822
Short name T715
Test name
Test status
Simulation time 121434743 ps
CPU time 5.39 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 208928 kb
Host smart-6c2fe633-3504-4ecf-ac78-e681c8b099c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386697822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2386697822
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.458697424
Short name T739
Test name
Test status
Simulation time 27895813 ps
CPU time 1.63 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 209868 kb
Host smart-681eea40-e8a8-4166-a527-9311e1b2e17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458697424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.458697424
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.637055681
Short name T768
Test name
Test status
Simulation time 53520214 ps
CPU time 1 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:38 PM PDT 24
Peak memory 206188 kb
Host smart-39439b98-931f-4270-88ee-fc92e13f7540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637055681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.637055681
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.521000439
Short name T124
Test name
Test status
Simulation time 176710400 ps
CPU time 3.97 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 214316 kb
Host smart-5c90580e-cdad-4dbe-9069-087ea1598d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521000439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.521000439
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3084552254
Short name T487
Test name
Test status
Simulation time 142322096 ps
CPU time 2.33 seconds
Started May 21 02:56:29 PM PDT 24
Finished May 21 02:56:43 PM PDT 24
Peak memory 221872 kb
Host smart-6ab6217b-2c79-4571-85a0-76eff398c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084552254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3084552254
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2281547912
Short name T775
Test name
Test status
Simulation time 36037333 ps
CPU time 1.6 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 208152 kb
Host smart-46e07dd8-ce46-4716-85e2-eb2c33342a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281547912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2281547912
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1338320941
Short name T113
Test name
Test status
Simulation time 147535507 ps
CPU time 6.46 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:56:43 PM PDT 24
Peak memory 222492 kb
Host smart-d193a9cd-3f6b-47e4-aea3-4ca2945e7dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338320941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1338320941
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.3275475543
Short name T817
Test name
Test status
Simulation time 347175604 ps
CPU time 6.42 seconds
Started May 21 02:56:30 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 207968 kb
Host smart-6a77182f-d789-4b02-b6a8-c695b0542592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275475543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3275475543
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.251317142
Short name T368
Test name
Test status
Simulation time 2675554989 ps
CPU time 8.51 seconds
Started May 21 02:56:20 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 208316 kb
Host smart-e0e6eebe-2fc9-4b84-8002-3605e20dcc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251317142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.251317142
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3240897127
Short name T370
Test name
Test status
Simulation time 4644586648 ps
CPU time 39.52 seconds
Started May 21 02:56:23 PM PDT 24
Finished May 21 02:57:14 PM PDT 24
Peak memory 208388 kb
Host smart-b59877fd-b783-4bb7-b942-d11bc6b45bd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240897127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3240897127
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.124434617
Short name T711
Test name
Test status
Simulation time 131610738 ps
CPU time 3.49 seconds
Started May 21 02:56:21 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 207112 kb
Host smart-e737ceae-bf08-4735-b7ec-ae3b1b76d085
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124434617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.124434617
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.170270178
Short name T644
Test name
Test status
Simulation time 42225869 ps
CPU time 2.54 seconds
Started May 21 02:56:19 PM PDT 24
Finished May 21 02:56:34 PM PDT 24
Peak memory 207252 kb
Host smart-34e4a051-349b-4488-a749-d783f94d6d75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170270178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.170270178
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.359385552
Short name T698
Test name
Test status
Simulation time 118073052 ps
CPU time 1.77 seconds
Started May 21 02:56:28 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 209108 kb
Host smart-e4102219-796e-4761-9080-36d96501312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359385552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.359385552
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2950705302
Short name T475
Test name
Test status
Simulation time 49610887 ps
CPU time 2.6 seconds
Started May 21 02:56:22 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 206980 kb
Host smart-bf858331-ce03-4b15-8bd0-690ea2d8fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950705302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2950705302
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1406374955
Short name T462
Test name
Test status
Simulation time 516667606 ps
CPU time 5.42 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:43 PM PDT 24
Peak memory 207600 kb
Host smart-966f15a8-c098-4bde-80d2-b975c2db688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406374955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1406374955
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.200923495
Short name T694
Test name
Test status
Simulation time 32792912 ps
CPU time 1.53 seconds
Started May 21 02:56:26 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 209868 kb
Host smart-58993fe9-fc63-4fbb-a7c4-abe74e1becd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200923495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.200923495
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.93337495
Short name T755
Test name
Test status
Simulation time 64592985 ps
CPU time 0.81 seconds
Started May 21 02:56:23 PM PDT 24
Finished May 21 02:56:36 PM PDT 24
Peak memory 206016 kb
Host smart-9e769a22-ce9b-4a7a-a8b8-f502fde181ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93337495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.93337495
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.848451384
Short name T30
Test name
Test status
Simulation time 132762041 ps
CPU time 4.97 seconds
Started May 21 02:56:28 PM PDT 24
Finished May 21 02:56:45 PM PDT 24
Peak memory 219984 kb
Host smart-469aa052-b6dc-43a5-9354-f48be8a7c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848451384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.848451384
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.442889994
Short name T200
Test name
Test status
Simulation time 1415654608 ps
CPU time 11.04 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 208860 kb
Host smart-ed351614-d543-4518-8eab-72e6ee44bac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442889994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.442889994
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.209231284
Short name T567
Test name
Test status
Simulation time 107055600 ps
CPU time 3.34 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 221464 kb
Host smart-119a9b03-7134-47fa-a90f-3695dd933bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209231284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.209231284
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2336331889
Short name T722
Test name
Test status
Simulation time 1063555221 ps
CPU time 17.21 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 221116 kb
Host smart-f3b9ea21-8ddf-4c40-9e4c-c18112919b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336331889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2336331889
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3463963914
Short name T787
Test name
Test status
Simulation time 462170313 ps
CPU time 2.41 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:56:39 PM PDT 24
Peak memory 216580 kb
Host smart-e22d6771-a2b8-45fb-8fc1-2945ec28c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463963914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3463963914
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.515904425
Short name T568
Test name
Test status
Simulation time 980681128 ps
CPU time 7.5 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:44 PM PDT 24
Peak memory 210144 kb
Host smart-164ec8b9-2007-4182-aac8-0b409db0bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515904425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.515904425
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4046734089
Short name T689
Test name
Test status
Simulation time 148873667 ps
CPU time 3.56 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:56:40 PM PDT 24
Peak memory 208692 kb
Host smart-30fe7ca0-8778-49e9-810d-ce074916b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046734089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4046734089
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3205151906
Short name T632
Test name
Test status
Simulation time 128864216 ps
CPU time 3.42 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:56:42 PM PDT 24
Peak memory 206928 kb
Host smart-d04e8410-3c84-4afc-b307-c9cbb62a57c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205151906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3205151906
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.143802444
Short name T797
Test name
Test status
Simulation time 3520256805 ps
CPU time 24.41 seconds
Started May 21 02:56:24 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 208788 kb
Host smart-7229221d-c7a0-426d-b728-361df79ba195
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143802444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.143802444
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.660547194
Short name T598
Test name
Test status
Simulation time 514115917 ps
CPU time 4.25 seconds
Started May 21 02:56:25 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 208680 kb
Host smart-ff2c9455-fe89-41d5-b50e-7db76d2af81e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660547194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.660547194
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3587884881
Short name T647
Test name
Test status
Simulation time 81344462 ps
CPU time 3.3 seconds
Started May 21 02:56:28 PM PDT 24
Finished May 21 02:56:43 PM PDT 24
Peak memory 218328 kb
Host smart-8d9a5a64-601d-44e9-9b9a-1c737619b159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587884881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3587884881
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3661281484
Short name T730
Test name
Test status
Simulation time 35182602 ps
CPU time 1.66 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 206196 kb
Host smart-1410271e-9850-40ec-b213-78451f145204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661281484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3661281484
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1675360517
Short name T213
Test name
Test status
Simulation time 572715629 ps
CPU time 26.27 seconds
Started May 21 02:56:23 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 221480 kb
Host smart-7073e49d-987c-498b-b37b-0968a0576daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675360517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1675360517
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3085822401
Short name T265
Test name
Test status
Simulation time 52866789 ps
CPU time 1.95 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 209268 kb
Host smart-0bec97b0-c226-4165-bb8e-1df8f21426c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085822401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3085822401
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.636589049
Short name T168
Test name
Test status
Simulation time 134155972 ps
CPU time 1.96 seconds
Started May 21 02:56:27 PM PDT 24
Finished May 21 02:56:41 PM PDT 24
Peak memory 210336 kb
Host smart-03240d77-f17f-4032-a3b3-b65b73fb7a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636589049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.636589049
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1842136627
Short name T429
Test name
Test status
Simulation time 14029131 ps
CPU time 0.74 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:44 PM PDT 24
Peak memory 206016 kb
Host smart-d04412fd-1ab7-43e1-8c8b-fed6fbb75bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842136627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1842136627
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3960112674
Short name T284
Test name
Test status
Simulation time 1257958660 ps
CPU time 8.48 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 208896 kb
Host smart-5cbc77eb-2090-4607-8582-63dd78c837bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960112674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3960112674
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1103291739
Short name T876
Test name
Test status
Simulation time 422825813 ps
CPU time 4.17 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 214404 kb
Host smart-27e2c289-710d-4a2e-9653-0cd2e5674813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103291739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1103291739
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2117261541
Short name T531
Test name
Test status
Simulation time 223835951 ps
CPU time 3.73 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 208500 kb
Host smart-f68b55d3-68e3-4167-9269-24a0767453f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117261541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2117261541
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1945658554
Short name T134
Test name
Test status
Simulation time 38457834 ps
CPU time 2.9 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 214352 kb
Host smart-ba9a385b-9514-4722-9bbe-e35275452c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945658554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1945658554
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4011473624
Short name T560
Test name
Test status
Simulation time 7867759564 ps
CPU time 33.8 seconds
Started May 21 02:56:30 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 208556 kb
Host smart-4ac3a26c-bf6e-4937-8a8b-d72264c5582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011473624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4011473624
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1982822782
Short name T782
Test name
Test status
Simulation time 57562925 ps
CPU time 1.75 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:45 PM PDT 24
Peak memory 206968 kb
Host smart-2865373c-4056-47db-a189-af8b83c55124
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982822782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1982822782
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3916957305
Short name T483
Test name
Test status
Simulation time 182369538 ps
CPU time 2.97 seconds
Started May 21 02:56:33 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 207060 kb
Host smart-e76267c2-f902-4053-aceb-c1104dbf1173
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916957305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3916957305
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1486500143
Short name T404
Test name
Test status
Simulation time 364388171 ps
CPU time 3.05 seconds
Started May 21 02:56:30 PM PDT 24
Finished May 21 02:56:45 PM PDT 24
Peak memory 207340 kb
Host smart-bf2200db-bfa1-4f11-a788-628793e3e4f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486500143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1486500143
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1930900315
Short name T815
Test name
Test status
Simulation time 296599498 ps
CPU time 2.59 seconds
Started May 21 02:56:34 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 207552 kb
Host smart-4e040715-5ba5-42f2-b4ed-57229af877b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930900315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1930900315
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2527363335
Short name T480
Test name
Test status
Simulation time 65684280 ps
CPU time 2.72 seconds
Started May 21 02:56:33 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 208512 kb
Host smart-507b785f-72f5-4f35-aaad-5c82696b3722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527363335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2527363335
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3713259647
Short name T196
Test name
Test status
Simulation time 1102952761 ps
CPU time 41.92 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:57:31 PM PDT 24
Peak memory 222460 kb
Host smart-c6dcc7f7-5797-4349-9fb7-8281a3446c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713259647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3713259647
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2427621464
Short name T137
Test name
Test status
Simulation time 365639879 ps
CPU time 4.78 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 208996 kb
Host smart-6d8074ac-0126-4c49-bb10-31b4ae5fcdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427621464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2427621464
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.569946666
Short name T712
Test name
Test status
Simulation time 111276285 ps
CPU time 4.04 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 210316 kb
Host smart-c3318340-c945-4013-a5cb-cd62333e81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569946666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.569946666
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1932938490
Short name T521
Test name
Test status
Simulation time 67802258 ps
CPU time 0.8 seconds
Started May 21 02:56:33 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 206008 kb
Host smart-9528e7c1-f3aa-43f1-a1c2-ab189fe4192f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932938490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1932938490
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.427041325
Short name T420
Test name
Test status
Simulation time 68341421 ps
CPU time 4.09 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 215784 kb
Host smart-cb76950b-2800-4d89-8fa4-f91a399df201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427041325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.427041325
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3403322594
Short name T41
Test name
Test status
Simulation time 2255984096 ps
CPU time 8.51 seconds
Started May 21 02:56:33 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 221596 kb
Host smart-51b6ffec-7dcf-45f0-9c7d-2b143cb21a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403322594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3403322594
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2620847959
Short name T60
Test name
Test status
Simulation time 196585888 ps
CPU time 2.85 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 208228 kb
Host smart-109ae6bb-e798-43f3-86c8-2f80fa11bb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620847959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2620847959
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3289073061
Short name T604
Test name
Test status
Simulation time 92089457 ps
CPU time 4.39 seconds
Started May 21 02:56:33 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 222456 kb
Host smart-f07d7566-b937-410e-80c3-95fc40470be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289073061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3289073061
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2805150203
Short name T527
Test name
Test status
Simulation time 190849344 ps
CPU time 2.8 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 214352 kb
Host smart-fda27d2d-1703-45ac-8710-a8dd860e2643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805150203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2805150203
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3784069467
Short name T365
Test name
Test status
Simulation time 1882243089 ps
CPU time 28.63 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:57:13 PM PDT 24
Peak memory 209548 kb
Host smart-bfa48127-82c1-41ab-a860-3d803ffb8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784069467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3784069467
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.122324552
Short name T855
Test name
Test status
Simulation time 117575950 ps
CPU time 2.4 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 206916 kb
Host smart-d9c8ad74-d3f0-4f95-a46a-ecb66a7ed359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122324552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.122324552
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2000262170
Short name T564
Test name
Test status
Simulation time 91461061 ps
CPU time 3.78 seconds
Started May 21 02:56:30 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 207340 kb
Host smart-f2a47f1c-91a3-4b7e-b903-cc412ec32a94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000262170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2000262170
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1006788411
Short name T596
Test name
Test status
Simulation time 515060577 ps
CPU time 3.05 seconds
Started May 21 02:56:29 PM PDT 24
Finished May 21 02:56:44 PM PDT 24
Peak memory 209036 kb
Host smart-6eb8e63a-6c47-48e6-ae8c-fcd4a6694de7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006788411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1006788411
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4190710747
Short name T551
Test name
Test status
Simulation time 2221564027 ps
CPU time 11.73 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 209336 kb
Host smart-e183b344-8b88-4206-8481-243dbc8e8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190710747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4190710747
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1285532499
Short name T612
Test name
Test status
Simulation time 89438303 ps
CPU time 3.21 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:47 PM PDT 24
Peak memory 206744 kb
Host smart-39ef44a4-63f1-44a5-99d6-7bc3454ae5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285532499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1285532499
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3655692967
Short name T118
Test name
Test status
Simulation time 724245715 ps
CPU time 14.94 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 220252 kb
Host smart-878e3ebc-3ad6-4557-a91d-9f1be239fe3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655692967 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3655692967
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.939454845
Short name T708
Test name
Test status
Simulation time 910854540 ps
CPU time 19.9 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:57:08 PM PDT 24
Peak memory 209164 kb
Host smart-e3a649ce-cacc-43fa-aec2-e533802ed129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939454845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.939454845
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3986428005
Short name T190
Test name
Test status
Simulation time 88037330 ps
CPU time 2.24 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 210232 kb
Host smart-9d0dc1e3-0cf2-4f63-9e72-33d9d7f15ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986428005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3986428005
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3116057218
Short name T108
Test name
Test status
Simulation time 51349524 ps
CPU time 0.95 seconds
Started May 21 02:56:41 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 206196 kb
Host smart-e6a70d58-f345-4a87-b57e-3d323bd4605b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116057218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3116057218
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1252027844
Short name T829
Test name
Test status
Simulation time 123509328 ps
CPU time 2.42 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 210184 kb
Host smart-4a7327b5-5c3f-46de-a45f-c5dcbb5fd2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252027844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1252027844
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.649286585
Short name T216
Test name
Test status
Simulation time 553355616 ps
CPU time 5.51 seconds
Started May 21 02:56:41 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 214472 kb
Host smart-aeac3db7-b2e8-48de-8a5a-3924b23a2e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649286585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.649286585
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.4128166018
Short name T713
Test name
Test status
Simulation time 172425915 ps
CPU time 4.3 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 208916 kb
Host smart-c9ba59a9-d9ee-4e98-8795-ede0b50e1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128166018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4128166018
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4080100866
Short name T626
Test name
Test status
Simulation time 58574943 ps
CPU time 2.26 seconds
Started May 21 02:56:32 PM PDT 24
Finished May 21 02:56:46 PM PDT 24
Peak memory 206888 kb
Host smart-5c1e3e81-13d2-45a2-8894-91c65e0c377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080100866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4080100866
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.910057421
Short name T723
Test name
Test status
Simulation time 120908833 ps
CPU time 2.2 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 206880 kb
Host smart-9be8d065-e4fe-43ba-93c5-3e6f51b02f8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910057421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.910057421
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4139152590
Short name T811
Test name
Test status
Simulation time 215173057 ps
CPU time 3.81 seconds
Started May 21 02:56:41 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 208552 kb
Host smart-68d4dde3-e158-4e16-a9ea-08e4e1da99d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139152590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4139152590
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.325750599
Short name T691
Test name
Test status
Simulation time 226650200 ps
CPU time 7.81 seconds
Started May 21 02:56:35 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 208664 kb
Host smart-571e2996-9f4f-4b96-8d97-32157add5dc9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325750599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.325750599
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4174484856
Short name T366
Test name
Test status
Simulation time 523270331 ps
CPU time 4.03 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:51 PM PDT 24
Peak memory 209380 kb
Host smart-274ac0e3-e640-478a-897f-9bcff46b32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174484856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4174484856
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.945544744
Short name T654
Test name
Test status
Simulation time 14368182531 ps
CPU time 27.69 seconds
Started May 21 02:56:31 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 208432 kb
Host smart-654e997d-9228-464c-9562-e201d49db689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945544744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.945544744
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1617052542
Short name T563
Test name
Test status
Simulation time 264584697 ps
CPU time 7.54 seconds
Started May 21 02:56:36 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 209316 kb
Host smart-8e1718ca-da27-480e-903e-7466ec5cbc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617052542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1617052542
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2902880064
Short name T566
Test name
Test status
Simulation time 136794606 ps
CPU time 3.9 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:51 PM PDT 24
Peak memory 210108 kb
Host smart-3d75a081-3e24-4c59-8a49-5a9db9d5b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902880064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2902880064
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3418474188
Short name T430
Test name
Test status
Simulation time 10173828 ps
CPU time 0.81 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:48 PM PDT 24
Peak memory 205992 kb
Host smart-50e82b12-2231-41de-9855-51ae4ca97bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418474188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3418474188
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3080973390
Short name T831
Test name
Test status
Simulation time 336772917 ps
CPU time 3.63 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 209132 kb
Host smart-ea35ab88-3ea7-4656-98aa-b54821e6d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080973390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3080973390
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2626364299
Short name T614
Test name
Test status
Simulation time 20239133 ps
CPU time 1.71 seconds
Started May 21 02:56:45 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 207940 kb
Host smart-7611b565-1281-42a0-a9b2-5d5164b9da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626364299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2626364299
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1750691961
Short name T309
Test name
Test status
Simulation time 61511317 ps
CPU time 2.47 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 214372 kb
Host smart-c0e8a8e3-e69c-40d8-92fe-aff324cd4933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750691961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1750691961
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.516388602
Short name T36
Test name
Test status
Simulation time 145818997 ps
CPU time 1.52 seconds
Started May 21 02:56:45 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 214280 kb
Host smart-e5af449e-657a-4777-9166-2f9bc9161650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516388602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.516388602
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4253632751
Short name T5
Test name
Test status
Simulation time 2522145516 ps
CPU time 7.6 seconds
Started May 21 02:56:40 PM PDT 24
Finished May 21 02:56:58 PM PDT 24
Peak memory 220564 kb
Host smart-9eee7989-0401-429a-b1eb-a54086a1a265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253632751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4253632751
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2364025331
Short name T554
Test name
Test status
Simulation time 93123291 ps
CPU time 4.08 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 208980 kb
Host smart-6d2673fc-b400-4631-994e-36c6cbe070ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364025331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2364025331
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1192499127
Short name T84
Test name
Test status
Simulation time 752612366 ps
CPU time 5.78 seconds
Started May 21 02:56:36 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 208028 kb
Host smart-8bac416f-4539-46a3-a8d6-eae78429f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192499127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1192499127
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3077177272
Short name T869
Test name
Test status
Simulation time 29267998 ps
CPU time 2.28 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:51 PM PDT 24
Peak memory 208748 kb
Host smart-50bd45a6-3f93-4d51-aa7a-d634cb1565ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077177272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3077177272
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2066684868
Short name T766
Test name
Test status
Simulation time 54231497 ps
CPU time 2.83 seconds
Started May 21 02:56:37 PM PDT 24
Finished May 21 02:56:50 PM PDT 24
Peak memory 208188 kb
Host smart-7a62b21c-6387-42d1-8ff5-548cea7cb5e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066684868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2066684868
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3084475643
Short name T82
Test name
Test status
Simulation time 60611726 ps
CPU time 3.05 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 208164 kb
Host smart-c5b6ad1f-5565-4f25-9ef7-2e86c57cb587
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084475643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3084475643
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2689337585
Short name T499
Test name
Test status
Simulation time 160493801 ps
CPU time 2.96 seconds
Started May 21 02:56:36 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 218548 kb
Host smart-34e2ff57-448f-40a3-a9fe-6afdd37d2a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689337585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2689337585
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.70164919
Short name T709
Test name
Test status
Simulation time 819064317 ps
CPU time 3.01 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 206348 kb
Host smart-b4f74a6e-b90e-4499-966e-1de39ce79135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70164919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.70164919
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1870278353
Short name T194
Test name
Test status
Simulation time 524102478 ps
CPU time 18.72 seconds
Started May 21 02:56:36 PM PDT 24
Finished May 21 02:57:05 PM PDT 24
Peak memory 216440 kb
Host smart-9f1c0dc8-f571-4db2-a8fd-fb2262794642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870278353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1870278353
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2070201648
Short name T417
Test name
Test status
Simulation time 481098817 ps
CPU time 3.46 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:51 PM PDT 24
Peak memory 207732 kb
Host smart-36804dd0-c507-45ae-87fc-bf3628143c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070201648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2070201648
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2228757605
Short name T396
Test name
Test status
Simulation time 240564155 ps
CPU time 5.85 seconds
Started May 21 02:56:38 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 210820 kb
Host smart-386c0e34-8062-4569-ac68-a4a1e0348844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228757605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2228757605
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.283747897
Short name T441
Test name
Test status
Simulation time 32143342 ps
CPU time 0.82 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 205700 kb
Host smart-7c50918f-d9c0-4058-bfeb-44895992d2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283747897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.283747897
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1773113408
Short name T300
Test name
Test status
Simulation time 285706028 ps
CPU time 4.61 seconds
Started May 21 02:56:41 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 215464 kb
Host smart-2328683a-7e86-4a66-b635-c23b44903d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773113408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1773113408
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.912607949
Short name T214
Test name
Test status
Simulation time 58906580 ps
CPU time 2.66 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 220108 kb
Host smart-1810c7d7-031b-4ae6-a789-7e3b2877ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912607949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.912607949
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.984834235
Short name T591
Test name
Test status
Simulation time 426415488 ps
CPU time 3.9 seconds
Started May 21 02:56:42 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 209248 kb
Host smart-69d38e33-63b3-4f87-9940-62d992adf74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984834235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.984834235
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.859861143
Short name T878
Test name
Test status
Simulation time 212246172 ps
CPU time 3.83 seconds
Started May 21 02:56:48 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 219308 kb
Host smart-b8e89b71-0a0f-4751-92bc-32f1d265d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859861143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.859861143
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1108307082
Short name T883
Test name
Test status
Simulation time 203168158 ps
CPU time 2.44 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 214432 kb
Host smart-a3721f03-032b-4df4-9ad5-803408d96194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108307082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1108307082
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3351333392
Short name T786
Test name
Test status
Simulation time 142073086 ps
CPU time 2.6 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 217664 kb
Host smart-a460704e-5dca-45b7-a20f-9271c9c3e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351333392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3351333392
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1459715643
Short name T798
Test name
Test status
Simulation time 64610993 ps
CPU time 2.89 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 208732 kb
Host smart-20c2767c-6044-4d8a-a270-34b69162a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459715643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1459715643
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3107777562
Short name T778
Test name
Test status
Simulation time 67605373 ps
CPU time 2.83 seconds
Started May 21 02:56:39 PM PDT 24
Finished May 21 02:56:52 PM PDT 24
Peak memory 206856 kb
Host smart-687a97a6-aee3-49ad-bfce-cd524073e83d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107777562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3107777562
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1921493509
Short name T904
Test name
Test status
Simulation time 145540923 ps
CPU time 2.72 seconds
Started May 21 02:56:35 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 208760 kb
Host smart-23680165-e29b-4188-8d8b-653ff2793998
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921493509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1921493509
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.672049822
Short name T640
Test name
Test status
Simulation time 611030698 ps
CPU time 13.84 seconds
Started May 21 02:56:40 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 208056 kb
Host smart-4a60b1b5-a7e5-48fa-8f63-4c6d098afca7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672049822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.672049822
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.846473525
Short name T311
Test name
Test status
Simulation time 211502880 ps
CPU time 3.05 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 209168 kb
Host smart-415519cd-bead-4339-8c26-6356dbdf4ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846473525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.846473525
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1405604262
Short name T688
Test name
Test status
Simulation time 162439828 ps
CPU time 3.42 seconds
Started May 21 02:56:41 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 208448 kb
Host smart-996af2c8-65b6-4742-a700-91edd35556ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405604262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1405604262
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3244814667
Short name T69
Test name
Test status
Simulation time 230592330 ps
CPU time 11.26 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 215656 kb
Host smart-55aa1b49-b68f-4fe5-8815-98b7e18f28d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244814667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3244814667
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.923536590
Short name T380
Test name
Test status
Simulation time 280403988 ps
CPU time 7.21 seconds
Started May 21 02:56:42 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 207796 kb
Host smart-34b28ab3-5553-4e8e-9eaa-3c9ab38b2216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923536590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.923536590
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2506194241
Short name T174
Test name
Test status
Simulation time 173166253 ps
CPU time 2.72 seconds
Started May 21 02:56:42 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 210416 kb
Host smart-4381674a-702a-49a5-8800-2b8f26971a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506194241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2506194241
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3219234529
Short name T706
Test name
Test status
Simulation time 20590869 ps
CPU time 0.7 seconds
Started May 21 02:56:47 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 206000 kb
Host smart-9b498b22-5c24-4479-8cb9-e6754bb2b0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219234529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3219234529
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3674521344
Short name T371
Test name
Test status
Simulation time 89708371 ps
CPU time 5 seconds
Started May 21 02:56:44 PM PDT 24
Finished May 21 02:56:58 PM PDT 24
Peak memory 215208 kb
Host smart-b416d111-07bd-4e0a-8b6a-9b88eaa46e3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674521344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3674521344
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1920856634
Short name T386
Test name
Test status
Simulation time 644256362 ps
CPU time 12.33 seconds
Started May 21 02:56:47 PM PDT 24
Finished May 21 02:57:08 PM PDT 24
Peak memory 210208 kb
Host smart-38e8452c-0f57-4b7e-b750-6ae8972de102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920856634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1920856634
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3396946865
Short name T66
Test name
Test status
Simulation time 633380380 ps
CPU time 4.16 seconds
Started May 21 02:56:46 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 208952 kb
Host smart-ff40cf74-4fbf-40a2-af29-6505936c87a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396946865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3396946865
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1827352022
Short name T389
Test name
Test status
Simulation time 771031192 ps
CPU time 10.39 seconds
Started May 21 02:56:48 PM PDT 24
Finished May 21 02:57:06 PM PDT 24
Peak memory 209608 kb
Host smart-54584225-57c5-470f-836b-eb7c04371e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827352022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1827352022
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.987768047
Short name T690
Test name
Test status
Simulation time 80298451 ps
CPU time 3.07 seconds
Started May 21 02:56:48 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 221040 kb
Host smart-353322cc-386e-4502-8e76-69126423cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987768047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.987768047
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.69431439
Short name T762
Test name
Test status
Simulation time 169328762 ps
CPU time 2.39 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 209584 kb
Host smart-ac8275df-6835-4889-bc09-e2538deb83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69431439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.69431439
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1822467476
Short name T246
Test name
Test status
Simulation time 47764447 ps
CPU time 2.91 seconds
Started May 21 02:56:45 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 209132 kb
Host smart-f7191931-9194-4b39-b820-81b01216ebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822467476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1822467476
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1214072011
Short name T582
Test name
Test status
Simulation time 154202787 ps
CPU time 2.48 seconds
Started May 21 02:56:44 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 206176 kb
Host smart-783a8b97-f8a3-4224-862a-0e110ca177a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214072011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1214072011
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3788234717
Short name T112
Test name
Test status
Simulation time 102825984 ps
CPU time 3.64 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:55 PM PDT 24
Peak memory 208788 kb
Host smart-31106868-9850-4863-ac59-f5c4b97fe98b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788234717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3788234717
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3020177076
Short name T454
Test name
Test status
Simulation time 36981602 ps
CPU time 2.52 seconds
Started May 21 02:56:42 PM PDT 24
Finished May 21 02:56:54 PM PDT 24
Peak memory 206920 kb
Host smart-e8618997-d953-4716-93aa-535c8796c0ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020177076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3020177076
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2812666248
Short name T459
Test name
Test status
Simulation time 97978568 ps
CPU time 2.78 seconds
Started May 21 02:56:44 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 207060 kb
Host smart-d1b5c340-406e-4621-a2aa-b8dc4a779d69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812666248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2812666248
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.973101215
Short name T672
Test name
Test status
Simulation time 22023411 ps
CPU time 1.84 seconds
Started May 21 02:56:47 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 215560 kb
Host smart-e5b2288c-3435-427e-9fe0-3029e6f5e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973101215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.973101215
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4072445233
Short name T488
Test name
Test status
Simulation time 650003392 ps
CPU time 5.58 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 206684 kb
Host smart-44d5301b-b4ac-475e-89ab-b9e976b025fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072445233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4072445233
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2292678513
Short name T500
Test name
Test status
Simulation time 89259241 ps
CPU time 4.28 seconds
Started May 21 02:56:43 PM PDT 24
Finished May 21 02:56:56 PM PDT 24
Peak memory 214368 kb
Host smart-ae92ddff-23c6-447e-9ecd-992f237425bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292678513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2292678513
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4111521350
Short name T655
Test name
Test status
Simulation time 233433619 ps
CPU time 4.62 seconds
Started May 21 02:56:45 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 210952 kb
Host smart-41add937-1794-4021-aa2e-0b5fe1d77332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111521350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4111521350
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.147015424
Short name T428
Test name
Test status
Simulation time 27480274 ps
CPU time 0.81 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:44 PM PDT 24
Peak memory 205992 kb
Host smart-cad6582c-824c-47b0-bf4c-14557d970c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147015424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.147015424
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.492436267
Short name T858
Test name
Test status
Simulation time 598910230 ps
CPU time 18.17 seconds
Started May 21 02:54:43 PM PDT 24
Finished May 21 02:55:04 PM PDT 24
Peak memory 208884 kb
Host smart-f69ec01c-42f7-41ec-b151-ebdaeac0ddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492436267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.492436267
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1684338284
Short name T89
Test name
Test status
Simulation time 356285920 ps
CPU time 4.14 seconds
Started May 21 02:54:57 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 220088 kb
Host smart-5c924605-09e7-4a1e-9204-cd4e9eaaf9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684338284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1684338284
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2250367743
Short name T678
Test name
Test status
Simulation time 41481010 ps
CPU time 2.51 seconds
Started May 21 02:54:41 PM PDT 24
Finished May 21 02:54:47 PM PDT 24
Peak memory 221408 kb
Host smart-850439d9-9ec2-49b5-894f-f469849f52ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250367743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2250367743
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2180326762
Short name T54
Test name
Test status
Simulation time 178750905 ps
CPU time 4.22 seconds
Started May 21 02:54:42 PM PDT 24
Finished May 21 02:54:50 PM PDT 24
Peak memory 214364 kb
Host smart-006047fb-fea7-4a5c-911f-336a4fa6400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180326762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2180326762
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.564064523
Short name T320
Test name
Test status
Simulation time 355777371 ps
CPU time 4.55 seconds
Started May 21 02:54:38 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 209628 kb
Host smart-1174c326-614e-4d14-900a-ff3b5a051013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564064523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.564064523
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3661699973
Short name T45
Test name
Test status
Simulation time 1211007459 ps
CPU time 9.81 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:54 PM PDT 24
Peak memory 238092 kb
Host smart-4ea12562-f2aa-45b4-9b65-4003f96a84a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661699973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3661699973
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.297160501
Short name T135
Test name
Test status
Simulation time 80300019 ps
CPU time 1.92 seconds
Started May 21 02:54:35 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 206168 kb
Host smart-09b0756d-cc59-47b9-a2c8-cce5bd11ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297160501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.297160501
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3769944855
Short name T781
Test name
Test status
Simulation time 1191238154 ps
CPU time 3.69 seconds
Started May 21 02:54:34 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 209080 kb
Host smart-d29deb19-fd95-46fa-9a49-a20b83120945
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769944855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3769944855
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4135398709
Short name T85
Test name
Test status
Simulation time 81668497 ps
CPU time 3.42 seconds
Started May 21 02:54:37 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 206864 kb
Host smart-4920a82f-96a2-43cc-ba6e-a7cbb494594a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135398709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4135398709
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4166724882
Short name T803
Test name
Test status
Simulation time 37456882 ps
CPU time 2.25 seconds
Started May 21 02:54:34 PM PDT 24
Finished May 21 02:54:40 PM PDT 24
Peak memory 208992 kb
Host smart-547de666-3263-47f6-aa4d-df4109d6f47f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166724882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4166724882
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2884341801
Short name T872
Test name
Test status
Simulation time 448209731 ps
CPU time 6.28 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:49 PM PDT 24
Peak memory 207396 kb
Host smart-b61723f5-6a9e-451c-966a-605d6b33c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884341801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2884341801
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.370537296
Short name T518
Test name
Test status
Simulation time 241731322 ps
CPU time 4.15 seconds
Started May 21 02:54:34 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 206784 kb
Host smart-861f2121-961c-486f-bc79-04f6eee3a667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370537296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.370537296
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2210425696
Short name T369
Test name
Test status
Simulation time 1066869914 ps
CPU time 10.38 seconds
Started May 21 02:54:57 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 209612 kb
Host smart-faab34e0-1407-4fd7-bf97-718e58de0f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210425696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2210425696
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4278093620
Short name T193
Test name
Test status
Simulation time 157771100 ps
CPU time 2.85 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:47 PM PDT 24
Peak memory 207592 kb
Host smart-efd6f0fe-f296-421a-a189-400bea8331dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278093620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4278093620
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2952614390
Short name T61
Test name
Test status
Simulation time 944796794 ps
CPU time 23.72 seconds
Started May 21 02:54:41 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 211060 kb
Host smart-5d62556d-fd4b-4e03-b618-d00ab3de2d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952614390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2952614390
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4086488344
Short name T747
Test name
Test status
Simulation time 72184019 ps
CPU time 0.81 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:56:58 PM PDT 24
Peak memory 205932 kb
Host smart-0b388fad-84a5-4f27-b9af-d0bf7db943b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086488344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4086488344
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4139525594
Short name T351
Test name
Test status
Simulation time 202783262 ps
CPU time 2.6 seconds
Started May 21 02:56:47 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 215020 kb
Host smart-a6952396-f133-4de9-abff-efb4c88fc40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139525594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4139525594
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1340521465
Short name T753
Test name
Test status
Simulation time 308130832 ps
CPU time 2.66 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 219232 kb
Host smart-3af1f2ef-c85d-44b5-aa67-3e20864ada3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340521465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1340521465
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3554261521
Short name T73
Test name
Test status
Simulation time 466102584 ps
CPU time 3.71 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 207468 kb
Host smart-7cd70e09-9a54-4bf5-8d0a-5a617da4048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554261521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3554261521
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.484856905
Short name T286
Test name
Test status
Simulation time 95790632 ps
CPU time 2.69 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 222440 kb
Host smart-269a17ce-8daa-4e35-a10c-a4155ffe7cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484856905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.484856905
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3494986788
Short name T191
Test name
Test status
Simulation time 308045323 ps
CPU time 4.81 seconds
Started May 21 02:56:49 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 208872 kb
Host smart-fc71aead-d62f-4f50-844e-1bf6058e8ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494986788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3494986788
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.415967781
Short name T839
Test name
Test status
Simulation time 288197728 ps
CPU time 4.17 seconds
Started May 21 02:56:55 PM PDT 24
Finished May 21 02:57:05 PM PDT 24
Peak memory 208324 kb
Host smart-5d630a48-0b86-4177-80dc-8dc6bcd7abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415967781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.415967781
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2832653859
Short name T450
Test name
Test status
Simulation time 117609729 ps
CPU time 3.29 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 206820 kb
Host smart-5e42fed0-b844-4c32-840f-2ab064fbfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832653859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2832653859
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.528535974
Short name T617
Test name
Test status
Simulation time 122609207 ps
CPU time 3.74 seconds
Started May 21 02:56:48 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 206992 kb
Host smart-c520a224-dcb9-4cad-b509-989de38be7b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528535974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.528535974
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4151882051
Short name T671
Test name
Test status
Simulation time 37546715 ps
CPU time 2.41 seconds
Started May 21 02:56:49 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 206956 kb
Host smart-6eb805f6-5389-49db-8ff7-1fe84556ce24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151882051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4151882051
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1159679244
Short name T79
Test name
Test status
Simulation time 8507588995 ps
CPU time 49.2 seconds
Started May 21 02:56:49 PM PDT 24
Finished May 21 02:57:46 PM PDT 24
Peak memory 209212 kb
Host smart-5d041b4e-130b-4eab-a642-cd085f3bf0f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159679244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1159679244
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4068686515
Short name T295
Test name
Test status
Simulation time 125327181 ps
CPU time 3.17 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 214400 kb
Host smart-ed703b15-97ec-4ef7-a65f-3a959e2eb613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068686515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4068686515
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.573448325
Short name T875
Test name
Test status
Simulation time 146020987 ps
CPU time 3.73 seconds
Started May 21 02:56:52 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 206836 kb
Host smart-9e289edf-11e0-4266-bf65-f1979d4d8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573448325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.573448325
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.993181858
Short name T471
Test name
Test status
Simulation time 267802515 ps
CPU time 3.71 seconds
Started May 21 02:56:49 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 208172 kb
Host smart-7ff88e04-be79-4415-b0d4-debae69d7eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993181858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.993181858
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.482250456
Short name T848
Test name
Test status
Simulation time 36924449 ps
CPU time 0.78 seconds
Started May 21 02:56:59 PM PDT 24
Finished May 21 02:57:06 PM PDT 24
Peak memory 206024 kb
Host smart-ef31199a-d665-4896-87bc-2e28ac679a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482250456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.482250456
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.93210459
Short name T294
Test name
Test status
Simulation time 1931826834 ps
CPU time 106.23 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:58:44 PM PDT 24
Peak memory 222492 kb
Host smart-4464b325-ab69-442b-9510-ed7fa15be5d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93210459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.93210459
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.242700603
Short name T656
Test name
Test status
Simulation time 45699668 ps
CPU time 2.24 seconds
Started May 21 02:56:53 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 210020 kb
Host smart-c4e76abd-15d6-4c78-bcba-4c0663e2206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242700603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.242700603
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2042003377
Short name T330
Test name
Test status
Simulation time 117509152 ps
CPU time 4.27 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 209192 kb
Host smart-162861a4-03c1-4b9d-8bb1-52c72c9ca788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042003377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2042003377
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4000272755
Short name T289
Test name
Test status
Simulation time 113975582 ps
CPU time 2.56 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 214392 kb
Host smart-52e57c3c-92a6-4654-b0a2-2e03ce2311aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000272755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4000272755
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3743256423
Short name T791
Test name
Test status
Simulation time 87462344 ps
CPU time 4.2 seconds
Started May 21 02:56:52 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 214252 kb
Host smart-9a59ae60-13a6-41c6-95e6-33caa3595d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743256423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3743256423
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2483269472
Short name T795
Test name
Test status
Simulation time 505592582 ps
CPU time 4.55 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 209916 kb
Host smart-f6b2ec3c-522a-4b03-943c-6bb284462df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483269472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2483269472
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.4127220734
Short name T261
Test name
Test status
Simulation time 433355099 ps
CPU time 4.34 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 208164 kb
Host smart-c183d212-b54a-4250-8c91-b8f7e63ee8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127220734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.4127220734
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1832121120
Short name T268
Test name
Test status
Simulation time 82080989 ps
CPU time 3.55 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:01 PM PDT 24
Peak memory 208888 kb
Host smart-a6440ea1-40b1-4a1a-a7cc-c24e486ea0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832121120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1832121120
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.328959479
Short name T83
Test name
Test status
Simulation time 477465483 ps
CPU time 12.61 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 209024 kb
Host smart-8741acef-a2bb-4668-b700-ff2f09f117de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328959479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.328959479
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2647198290
Short name T447
Test name
Test status
Simulation time 4628030131 ps
CPU time 31.63 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 208528 kb
Host smart-a692f46c-1679-45d3-aa60-5d6834db14e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647198290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2647198290
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1866332548
Short name T802
Test name
Test status
Simulation time 1242455396 ps
CPU time 4.93 seconds
Started May 21 02:56:51 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 209084 kb
Host smart-a0ff056b-5ca6-49ce-aa7d-b7f0fdcc0b48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866332548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1866332548
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.917318096
Short name T363
Test name
Test status
Simulation time 117288183 ps
CPU time 4.61 seconds
Started May 21 02:56:59 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 215616 kb
Host smart-c6064d88-324e-4f07-8712-4c20c3c5be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917318096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.917318096
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2013769282
Short name T636
Test name
Test status
Simulation time 86615219 ps
CPU time 2.41 seconds
Started May 21 02:56:50 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 207888 kb
Host smart-a41b0cc2-ffe9-4c7b-ab53-5a86e58c8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013769282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2013769282
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2271441076
Short name T873
Test name
Test status
Simulation time 1796414112 ps
CPU time 30.82 seconds
Started May 21 02:56:56 PM PDT 24
Finished May 21 02:57:33 PM PDT 24
Peak memory 221004 kb
Host smart-19420029-b7da-4388-baf2-be384566b40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271441076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2271441076
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.529023137
Short name T299
Test name
Test status
Simulation time 1297825669 ps
CPU time 16.58 seconds
Started May 21 02:56:59 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 220268 kb
Host smart-59c5f220-cafa-4ce1-806c-a71c82aaadd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529023137 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.529023137
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2002611696
Short name T681
Test name
Test status
Simulation time 73538642 ps
CPU time 2.75 seconds
Started May 21 02:56:49 PM PDT 24
Finished May 21 02:56:59 PM PDT 24
Peak memory 208400 kb
Host smart-8901549d-97ea-4a7f-8470-0413a5945e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002611696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2002611696
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3160534869
Short name T675
Test name
Test status
Simulation time 112081883 ps
CPU time 2.86 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 210532 kb
Host smart-85b43744-ffec-430e-b5e7-5f5d74bcec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160534869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3160534869
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1678791860
Short name T502
Test name
Test status
Simulation time 17592392 ps
CPU time 1.03 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 206160 kb
Host smart-e0abf83a-4534-4c8a-8fd6-e64c1ea7d9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678791860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1678791860
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1708341495
Short name T400
Test name
Test status
Simulation time 560698539 ps
CPU time 2.64 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 214388 kb
Host smart-a71ae00b-fb24-4809-b308-b53b43ac50c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708341495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1708341495
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3334211284
Short name T497
Test name
Test status
Simulation time 254558110 ps
CPU time 2.19 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 218196 kb
Host smart-115a11d5-7f13-4aad-ac72-f839325df699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334211284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3334211284
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3768347221
Short name T100
Test name
Test status
Simulation time 698611463 ps
CPU time 5.54 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:06 PM PDT 24
Peak memory 208764 kb
Host smart-8f254b71-4f63-4218-a43b-d14682bac40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768347221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3768347221
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3331733568
Short name T271
Test name
Test status
Simulation time 134702452 ps
CPU time 3.93 seconds
Started May 21 02:56:58 PM PDT 24
Finished May 21 02:57:08 PM PDT 24
Peak memory 222492 kb
Host smart-2e46d351-3a8f-4440-a3c1-5819ce085ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331733568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3331733568
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1731312243
Short name T641
Test name
Test status
Simulation time 586504817 ps
CPU time 6.87 seconds
Started May 21 02:56:58 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 222592 kb
Host smart-d01c4f6d-3b16-4dd3-853b-149766a35bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731312243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1731312243
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.539213495
Short name T859
Test name
Test status
Simulation time 2434915010 ps
CPU time 35.54 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:35 PM PDT 24
Peak memory 208904 kb
Host smart-f272f365-5289-4feb-9300-6afb6e930806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539213495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.539213495
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1252272444
Short name T362
Test name
Test status
Simulation time 495349821 ps
CPU time 16.39 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 206880 kb
Host smart-cd17c826-3a02-4e9e-a610-955c0e1bd066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252272444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1252272444
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4126650813
Short name T668
Test name
Test status
Simulation time 35865059 ps
CPU time 2.45 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 207040 kb
Host smart-2b225323-8f6b-4b9e-a617-42a82fde50e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126650813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4126650813
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.222926663
Short name T505
Test name
Test status
Simulation time 537875064 ps
CPU time 3.83 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:04 PM PDT 24
Peak memory 208912 kb
Host smart-f129f094-963d-4ff6-ab27-f787dd1b1472
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222926663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.222926663
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2813897205
Short name T354
Test name
Test status
Simulation time 245703194 ps
CPU time 6.92 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:07 PM PDT 24
Peak memory 208548 kb
Host smart-06b95dc0-938a-4074-8d40-6d5f6ec57876
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813897205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2813897205
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1967076076
Short name T732
Test name
Test status
Simulation time 1000705198 ps
CPU time 4.77 seconds
Started May 21 02:56:53 PM PDT 24
Finished May 21 02:57:04 PM PDT 24
Peak memory 214420 kb
Host smart-c671974a-296f-49d8-8df8-851fa11e2f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967076076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1967076076
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.226880752
Short name T438
Test name
Test status
Simulation time 440010364 ps
CPU time 10.06 seconds
Started May 21 02:56:54 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 206644 kb
Host smart-217e2e37-050d-4004-bbd2-ca16daed8469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226880752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.226880752
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1167950105
Short name T892
Test name
Test status
Simulation time 4668197929 ps
CPU time 30.61 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:40 PM PDT 24
Peak memory 215176 kb
Host smart-74997143-aafd-428d-b080-c46d06f33312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167950105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1167950105
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1064906158
Short name T877
Test name
Test status
Simulation time 32126611 ps
CPU time 2.5 seconds
Started May 21 02:56:55 PM PDT 24
Finished May 21 02:57:04 PM PDT 24
Peak memory 207924 kb
Host smart-9e3ef455-ddf9-45fe-82d4-6c8d878c2782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064906158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1064906158
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1609288584
Short name T42
Test name
Test status
Simulation time 109747919 ps
CPU time 2.05 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 210496 kb
Host smart-26bd5d57-e17e-4f72-88d5-0e00390c45d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609288584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1609288584
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3294279026
Short name T532
Test name
Test status
Simulation time 12600327 ps
CPU time 0.81 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 206012 kb
Host smart-f355f15c-296e-41d8-91c2-db71354b9941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294279026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3294279026
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2066397821
Short name T27
Test name
Test status
Simulation time 121367256 ps
CPU time 3.72 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 214892 kb
Host smart-459e7d4b-9f93-427f-b228-1613160f6f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066397821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2066397821
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.225986971
Short name T777
Test name
Test status
Simulation time 1031803827 ps
CPU time 4.07 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 219804 kb
Host smart-c49d12eb-ab17-4a02-b161-1d58e33c2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225986971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.225986971
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2673192827
Short name T334
Test name
Test status
Simulation time 30514250 ps
CPU time 2.11 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 214416 kb
Host smart-ccfb810a-9090-4297-9bc1-999558654629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673192827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2673192827
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2879561812
Short name T292
Test name
Test status
Simulation time 243890471 ps
CPU time 2.43 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 214320 kb
Host smart-186c52e9-8a51-47bb-93c0-38495451d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879561812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2879561812
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2587424042
Short name T231
Test name
Test status
Simulation time 406364944 ps
CPU time 6 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:15 PM PDT 24
Peak memory 209660 kb
Host smart-798d1a09-e303-4d11-b2d4-6fbf485323a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587424042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2587424042
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.54204918
Short name T316
Test name
Test status
Simulation time 33843294 ps
CPU time 2.53 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 218176 kb
Host smart-f9b72282-44f3-4e01-bf09-81763089c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54204918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.54204918
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1350942335
Short name T467
Test name
Test status
Simulation time 89109926 ps
CPU time 3.46 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 208544 kb
Host smart-fba49d9d-3700-42ae-84a8-815b76ec5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350942335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1350942335
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3709120997
Short name T740
Test name
Test status
Simulation time 8800165631 ps
CPU time 51.42 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:58 PM PDT 24
Peak memory 209004 kb
Host smart-72fea680-50cd-400e-b629-13de8850ae6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709120997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3709120997
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1497751491
Short name T558
Test name
Test status
Simulation time 1652164506 ps
CPU time 31.61 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:41 PM PDT 24
Peak memory 208076 kb
Host smart-9079426e-0551-4263-99cc-6206d5d6237e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497751491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1497751491
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3676045486
Short name T602
Test name
Test status
Simulation time 252904843 ps
CPU time 6.47 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:15 PM PDT 24
Peak memory 209028 kb
Host smart-7971b86f-ced1-489a-9d0a-3a5b6b12473f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676045486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3676045486
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3335270624
Short name T509
Test name
Test status
Simulation time 19432419 ps
CPU time 1.6 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:13 PM PDT 24
Peak memory 208292 kb
Host smart-5dcaa951-731f-42cd-9a79-d19f6593ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335270624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3335270624
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2819120852
Short name T445
Test name
Test status
Simulation time 66941961 ps
CPU time 2.13 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 206788 kb
Host smart-efe9e7ad-dbc5-46b8-b308-512a6967f243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819120852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2819120852
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.212051138
Short name T267
Test name
Test status
Simulation time 316154567 ps
CPU time 8.55 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 214424 kb
Host smart-c8879711-4b48-4c50-a752-71107848fc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212051138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.212051138
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2672690220
Short name T606
Test name
Test status
Simulation time 369257291 ps
CPU time 4.84 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 209864 kb
Host smart-824f6763-4c7f-47a7-b20f-32f96e0a6713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672690220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2672690220
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3159986389
Short name T692
Test name
Test status
Simulation time 116664666 ps
CPU time 2.37 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:08 PM PDT 24
Peak memory 210020 kb
Host smart-130a74fc-ce74-4618-b6a4-1cb81e75f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159986389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3159986389
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2545248891
Short name T572
Test name
Test status
Simulation time 47284882 ps
CPU time 0.89 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 205968 kb
Host smart-f3d83225-4d33-4698-b954-feb02ce46be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545248891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2545248891
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2655352053
Short name T259
Test name
Test status
Simulation time 3593079757 ps
CPU time 14.09 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 215628 kb
Host smart-5a9335f2-28e4-40d4-a28c-8862900ac4bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655352053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2655352053
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1811177478
Short name T77
Test name
Test status
Simulation time 87326339 ps
CPU time 2.12 seconds
Started May 21 02:57:04 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 208640 kb
Host smart-d5f76eb8-a5ec-46f3-a80b-ee5b9d2da9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811177478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1811177478
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.948387662
Short name T98
Test name
Test status
Simulation time 82296360 ps
CPU time 3.66 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 208048 kb
Host smart-f77907aa-75be-4a01-ab10-3c28a1479fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948387662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.948387662
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3430354112
Short name T331
Test name
Test status
Simulation time 287543126 ps
CPU time 3.59 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 214348 kb
Host smart-2a6b526f-3bbf-4776-9538-cd9c298cc8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430354112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3430354112
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4021556483
Short name T801
Test name
Test status
Simulation time 184771256 ps
CPU time 3.48 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:13 PM PDT 24
Peak memory 208256 kb
Host smart-fddbf679-0853-4eb5-93e2-e2b9a5092e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021556483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4021556483
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2582603138
Short name T783
Test name
Test status
Simulation time 215487611 ps
CPU time 6.87 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 207484 kb
Host smart-43196f44-c3f1-4442-abbb-9a9d02c0dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582603138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2582603138
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2795440711
Short name T814
Test name
Test status
Simulation time 95056079 ps
CPU time 2.62 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 206184 kb
Host smart-faca53be-bb1e-486f-8c9e-5003541f8a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795440711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2795440711
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1025482712
Short name T469
Test name
Test status
Simulation time 1341394673 ps
CPU time 5.34 seconds
Started May 21 02:57:02 PM PDT 24
Finished May 21 02:57:14 PM PDT 24
Peak memory 207080 kb
Host smart-983c14b8-b26b-481e-8c27-a28ac044c1ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025482712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1025482712
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3524889629
Short name T513
Test name
Test status
Simulation time 2404830112 ps
CPU time 38.26 seconds
Started May 21 02:57:00 PM PDT 24
Finished May 21 02:57:45 PM PDT 24
Peak memory 208492 kb
Host smart-5b7a6c65-a3fa-4b45-bf1a-a1191993e999
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524889629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3524889629
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.246982571
Short name T792
Test name
Test status
Simulation time 340966824 ps
CPU time 5.34 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 208628 kb
Host smart-3905618b-2398-49bb-bfbc-06d8f2a65d1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246982571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.246982571
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3897157469
Short name T13
Test name
Test status
Simulation time 91689767 ps
CPU time 4.34 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:11 PM PDT 24
Peak memory 214360 kb
Host smart-34bd9789-c78d-488f-bac3-cbb00cfc5bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897157469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3897157469
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1661554983
Short name T463
Test name
Test status
Simulation time 21292193 ps
CPU time 1.81 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:09 PM PDT 24
Peak memory 207588 kb
Host smart-3100b358-58cf-4247-b73d-c68b7c2b2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661554983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1661554983
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3961562790
Short name T76
Test name
Test status
Simulation time 5066448148 ps
CPU time 31.79 seconds
Started May 21 02:57:03 PM PDT 24
Finished May 21 02:57:41 PM PDT 24
Peak memory 216180 kb
Host smart-87587e00-e4fa-4c9f-932b-02400e619403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961562790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3961562790
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2680120921
Short name T199
Test name
Test status
Simulation time 348752090 ps
CPU time 4.84 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:12 PM PDT 24
Peak memory 218468 kb
Host smart-4e1b234f-ce24-49fe-b9ae-5bddfdc61979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680120921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2680120921
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2334027934
Short name T508
Test name
Test status
Simulation time 297342616 ps
CPU time 2.78 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 210428 kb
Host smart-10c90e91-8fa5-4d46-b7b0-bff94fbddcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334027934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2334027934
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.751964311
Short name T851
Test name
Test status
Simulation time 37437863 ps
CPU time 0.72 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:13 PM PDT 24
Peak memory 205936 kb
Host smart-86b8cee9-0d89-4b1e-87ef-d3b8b0943d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751964311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.751964311
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1192698196
Short name T399
Test name
Test status
Simulation time 82276911 ps
CPU time 4.82 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 215592 kb
Host smart-79280b45-bfcd-4022-8ae2-4a985c48e044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192698196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1192698196
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4254472314
Short name T40
Test name
Test status
Simulation time 98204805 ps
CPU time 4.02 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:15 PM PDT 24
Peak memory 210456 kb
Host smart-85bce762-a151-4394-817e-928106292270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254472314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4254472314
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3162295545
Short name T555
Test name
Test status
Simulation time 418122282 ps
CPU time 10.6 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 208300 kb
Host smart-28a80699-48cf-4feb-bf51-0a21ff723877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162295545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3162295545
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1458790222
Short name T99
Test name
Test status
Simulation time 313361731 ps
CPU time 4.1 seconds
Started May 21 02:57:13 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 209844 kb
Host smart-a7967a68-1533-46df-9a5d-de822d3ad97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458790222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1458790222
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3958790990
Short name T642
Test name
Test status
Simulation time 601029624 ps
CPU time 4.43 seconds
Started May 21 02:57:08 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 222380 kb
Host smart-8ff15dac-efe3-4b08-aa78-e9bde91390bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958790990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3958790990
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1578892198
Short name T760
Test name
Test status
Simulation time 46623737 ps
CPU time 2.49 seconds
Started May 21 02:57:08 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 208308 kb
Host smart-c0cc4b3c-347e-48e0-ac81-8dc8269d6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578892198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1578892198
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2782780900
Short name T245
Test name
Test status
Simulation time 123027697 ps
CPU time 4.57 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 214448 kb
Host smart-8469587d-a4a8-474f-a3c9-1d16c7560426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782780900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2782780900
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1829920304
Short name T379
Test name
Test status
Simulation time 133767795 ps
CPU time 2.5 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:14 PM PDT 24
Peak memory 207020 kb
Host smart-c9162ccd-a969-4662-b4b7-95f944891457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829920304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1829920304
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1265767474
Short name T495
Test name
Test status
Simulation time 52862170 ps
CPU time 2.93 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 206924 kb
Host smart-2b604bbf-2284-43f8-bc77-445312081dd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265767474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1265767474
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1703559620
Short name T188
Test name
Test status
Simulation time 679043675 ps
CPU time 5.2 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 206836 kb
Host smart-624c60e7-9aa1-4fb4-8549-85b4b6fe068a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703559620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1703559620
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.621748692
Short name T581
Test name
Test status
Simulation time 1255923115 ps
CPU time 5.28 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 206912 kb
Host smart-60da9076-a052-4c2a-bb20-e4a40c9f79fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621748692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.621748692
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2279999007
Short name T482
Test name
Test status
Simulation time 82469744 ps
CPU time 2.66 seconds
Started May 21 02:57:08 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 208444 kb
Host smart-09ce03b7-b03b-4af3-9b0c-28ff9b166848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279999007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2279999007
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2686851435
Short name T906
Test name
Test status
Simulation time 202151893 ps
CPU time 2.37 seconds
Started May 21 02:57:01 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 206856 kb
Host smart-59288d67-790b-44dc-a643-49b5c378297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686851435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2686851435
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3353105318
Short name T845
Test name
Test status
Simulation time 2688240441 ps
CPU time 23.27 seconds
Started May 21 02:57:09 PM PDT 24
Finished May 21 02:57:37 PM PDT 24
Peak memory 220032 kb
Host smart-8a7c1d8d-d185-45fe-8a12-a6d3f07f27ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353105318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3353105318
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1579889831
Short name T757
Test name
Test status
Simulation time 591843326 ps
CPU time 6.1 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:24 PM PDT 24
Peak memory 214336 kb
Host smart-4115bc84-0f70-438e-acf3-17baff8e7d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579889831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1579889831
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3292468222
Short name T743
Test name
Test status
Simulation time 177562114 ps
CPU time 2.08 seconds
Started May 21 02:57:09 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 210168 kb
Host smart-42bc6bbc-06c9-4bc5-a4dc-2eac94a505ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292468222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3292468222
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3285032111
Short name T539
Test name
Test status
Simulation time 15791435 ps
CPU time 0.72 seconds
Started May 21 02:57:13 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 206016 kb
Host smart-238386fe-44d5-412e-8594-3038e32ea103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285032111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3285032111
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4222537105
Short name T411
Test name
Test status
Simulation time 82288920 ps
CPU time 4.74 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 222448 kb
Host smart-4e4bc77b-19cd-4201-8208-d3ea07008e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222537105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4222537105
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2169812942
Short name T733
Test name
Test status
Simulation time 39834200 ps
CPU time 2.48 seconds
Started May 21 02:57:10 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 208516 kb
Host smart-161bb166-5841-4226-aae5-49e4da1a6a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169812942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2169812942
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1307032090
Short name T868
Test name
Test status
Simulation time 84668971 ps
CPU time 3.56 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 209560 kb
Host smart-6365b228-5a0c-4318-8224-06bf05c3104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307032090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1307032090
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3487838133
Short name T874
Test name
Test status
Simulation time 267216139 ps
CPU time 3.71 seconds
Started May 21 02:57:09 PM PDT 24
Finished May 21 02:57:18 PM PDT 24
Peak memory 214464 kb
Host smart-c07e3114-059c-487f-8a35-a1fae8b81bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487838133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3487838133
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3200571642
Short name T821
Test name
Test status
Simulation time 283442654 ps
CPU time 2.64 seconds
Started May 21 02:57:09 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 214308 kb
Host smart-75bae87a-117a-4bb3-88fe-4e3a593ffc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200571642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3200571642
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2977295089
Short name T514
Test name
Test status
Simulation time 264558721 ps
CPU time 6.01 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 222448 kb
Host smart-234402b2-dcfd-4351-a5ac-f3556d73c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977295089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2977295089
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.837300502
Short name T374
Test name
Test status
Simulation time 124298977 ps
CPU time 5.57 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 214456 kb
Host smart-ea517c6c-8b7e-4cee-82f1-a948a4690957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837300502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.837300502
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3643243354
Short name T321
Test name
Test status
Simulation time 122484176 ps
CPU time 2.18 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:14 PM PDT 24
Peak memory 206928 kb
Host smart-71868010-bbad-4365-a49d-193336d654e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643243354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3643243354
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3673459894
Short name T899
Test name
Test status
Simulation time 4629590227 ps
CPU time 31.22 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:48 PM PDT 24
Peak memory 208688 kb
Host smart-2a2e6dc9-30a9-4c84-b8fb-4b3a0237cf96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673459894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3673459894
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2390930228
Short name T841
Test name
Test status
Simulation time 93765246 ps
CPU time 3.5 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:15 PM PDT 24
Peak memory 208584 kb
Host smart-8d1d043a-86bf-4e9e-a67a-f1a10d61a8da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390930228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2390930228
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.991621629
Short name T621
Test name
Test status
Simulation time 59306048 ps
CPU time 3.16 seconds
Started May 21 02:57:05 PM PDT 24
Finished May 21 02:57:14 PM PDT 24
Peak memory 208696 kb
Host smart-8892b2e6-d968-4354-8f03-543c6c8a855a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991621629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.991621629
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2944745899
Short name T538
Test name
Test status
Simulation time 1356334189 ps
CPU time 9.37 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 218268 kb
Host smart-703cf2bc-aa5c-439c-9e97-81ac9d8880fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944745899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2944745899
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3656745491
Short name T489
Test name
Test status
Simulation time 122437676 ps
CPU time 4.21 seconds
Started May 21 02:57:06 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 206820 kb
Host smart-9914cc47-f7de-4f74-82de-ef032f5afc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656745491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3656745491
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3690246493
Short name T182
Test name
Test status
Simulation time 1300770353 ps
CPU time 12.08 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:30 PM PDT 24
Peak memory 219588 kb
Host smart-87b7d327-53ac-41f0-9c00-727a1a45648b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690246493 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3690246493
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3551581871
Short name T285
Test name
Test status
Simulation time 4452993861 ps
CPU time 13.11 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 209776 kb
Host smart-3c19f7cd-eb38-4f1a-886d-fc863c9447cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551581871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3551581871
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1208676094
Short name T843
Test name
Test status
Simulation time 280672862 ps
CPU time 3.04 seconds
Started May 21 02:57:07 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 210560 kb
Host smart-3af7445d-5ea4-4a49-9b67-7c15ac8b56c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208676094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1208676094
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3366700317
Short name T808
Test name
Test status
Simulation time 12394428 ps
CPU time 0.95 seconds
Started May 21 02:57:11 PM PDT 24
Finished May 21 02:57:16 PM PDT 24
Peak memory 206148 kb
Host smart-7918cf6b-9633-4bd6-992d-d5a0c5539fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366700317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3366700317
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.124563998
Short name T258
Test name
Test status
Simulation time 7891088311 ps
CPU time 99.28 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:58:57 PM PDT 24
Peak memory 215644 kb
Host smart-b79a1583-5c92-4fe0-9e44-762c8561056a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124563998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.124563998
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1659974422
Short name T607
Test name
Test status
Simulation time 419024060 ps
CPU time 4.83 seconds
Started May 21 02:57:17 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 214780 kb
Host smart-43d15a2f-c2f5-4aba-93f9-ef5800e9e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659974422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1659974422
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3180022843
Short name T718
Test name
Test status
Simulation time 283152378 ps
CPU time 7.13 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 214348 kb
Host smart-1f323b22-96f4-4a0b-8d61-6fbb1f061fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180022843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3180022843
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.346463426
Short name T749
Test name
Test status
Simulation time 50360626 ps
CPU time 2.92 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:28 PM PDT 24
Peak memory 221268 kb
Host smart-5eaa1fd5-f90a-4795-8001-5a2d64987dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346463426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.346463426
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.632788425
Short name T631
Test name
Test status
Simulation time 544513475 ps
CPU time 5.6 seconds
Started May 21 02:57:15 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 215384 kb
Host smart-c3279049-b867-4e6a-b79d-31c801a141bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632788425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.632788425
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2872526460
Short name T903
Test name
Test status
Simulation time 114227056 ps
CPU time 3.96 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 220064 kb
Host smart-636eaf67-9b37-450f-a8b5-1597d3d5e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872526460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2872526460
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.118049566
Short name T358
Test name
Test status
Simulation time 98288378 ps
CPU time 4.01 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:20 PM PDT 24
Peak memory 209804 kb
Host smart-b9d9ef05-3134-4d0b-9ebb-fbeb70c46a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118049566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.118049566
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3970239612
Short name T485
Test name
Test status
Simulation time 202291924 ps
CPU time 5.86 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 208656 kb
Host smart-1a69f283-6ebd-4561-a746-ecfade31cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970239612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3970239612
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3567932440
Short name T833
Test name
Test status
Simulation time 620603277 ps
CPU time 6.77 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 208844 kb
Host smart-7d7619c2-dd5f-472f-ba64-f2a234e06a44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567932440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3567932440
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.780719511
Short name T819
Test name
Test status
Simulation time 102721988 ps
CPU time 4.28 seconds
Started May 21 02:57:15 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 208740 kb
Host smart-8734ebb5-ff5e-4c87-bf02-572ceb2a71b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780719511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.780719511
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3745285441
Short name T735
Test name
Test status
Simulation time 869421604 ps
CPU time 6.9 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 208840 kb
Host smart-49fb2b5b-2b59-4b06-a870-81f621c15c97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745285441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3745285441
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2061443259
Short name T721
Test name
Test status
Simulation time 79146652 ps
CPU time 3.76 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 218236 kb
Host smart-f5fd7c43-331d-45ff-b0c4-e4899692cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061443259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2061443259
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1809578624
Short name T696
Test name
Test status
Simulation time 191351014 ps
CPU time 2.63 seconds
Started May 21 02:57:17 PM PDT 24
Finished May 21 02:57:24 PM PDT 24
Peak memory 206940 kb
Host smart-518f7b19-fe45-44d4-9704-2b29ebbee247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809578624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1809578624
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.506433665
Short name T683
Test name
Test status
Simulation time 254779455 ps
CPU time 3.08 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 208144 kb
Host smart-37c0c570-00cf-40c6-af93-e28320d6cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506433665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.506433665
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.645414886
Short name T793
Test name
Test status
Simulation time 53121967 ps
CPU time 1.1 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:17 PM PDT 24
Peak memory 208664 kb
Host smart-83bbec21-9808-41a1-a51e-b185e93ca977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645414886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.645414886
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4160880940
Short name T847
Test name
Test status
Simulation time 259638192 ps
CPU time 0.88 seconds
Started May 21 02:57:19 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 205992 kb
Host smart-34509b86-c8ab-4484-a092-dbba3983186f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160880940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4160880940
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2104403914
Short name T825
Test name
Test status
Simulation time 59021630 ps
CPU time 2.31 seconds
Started May 21 02:57:13 PM PDT 24
Finished May 21 02:57:19 PM PDT 24
Peak memory 217256 kb
Host smart-e7fcebd1-09af-41d3-a08a-2b277d6be64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104403914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2104403914
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.989608553
Short name T620
Test name
Test status
Simulation time 90287478 ps
CPU time 2.18 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:28 PM PDT 24
Peak memory 214416 kb
Host smart-2b378722-12b9-49c3-b9d2-50c320a3010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989608553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.989608553
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3676349904
Short name T376
Test name
Test status
Simulation time 124244053 ps
CPU time 2.96 seconds
Started May 21 02:57:14 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 220992 kb
Host smart-e7c71952-1a86-4cad-ab48-7b86aeb256cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676349904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3676349904
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3007156750
Short name T274
Test name
Test status
Simulation time 249380500 ps
CPU time 5.35 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 222452 kb
Host smart-4167a046-3270-4864-8c32-6a54e8d4e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007156750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3007156750
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3792041850
Short name T577
Test name
Test status
Simulation time 68192214 ps
CPU time 3.14 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 209444 kb
Host smart-4a62ce8e-49c5-4383-a85c-ccf0b8259094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792041850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3792041850
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2445649464
Short name T328
Test name
Test status
Simulation time 62814726 ps
CPU time 4.23 seconds
Started May 21 02:57:19 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 210240 kb
Host smart-8d8b189e-3f87-4184-861f-e5efbda61ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445649464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2445649464
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4107497611
Short name T725
Test name
Test status
Simulation time 379372132 ps
CPU time 3.43 seconds
Started May 21 02:57:12 PM PDT 24
Finished May 21 02:57:20 PM PDT 24
Peak memory 208588 kb
Host smart-dad76e36-f735-43e2-b9aa-cc9f193b896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107497611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4107497611
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1728792194
Short name T773
Test name
Test status
Simulation time 913507302 ps
CPU time 3.07 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 206972 kb
Host smart-d25cccc5-976a-4641-a45a-b96df13a70d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728792194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1728792194
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1284028471
Short name T327
Test name
Test status
Simulation time 190806106 ps
CPU time 2.71 seconds
Started May 21 02:57:17 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 208532 kb
Host smart-7bb3dbdd-da0c-4a69-8018-c271d92d55e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284028471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1284028471
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2116471842
Short name T574
Test name
Test status
Simulation time 80414669 ps
CPU time 2.49 seconds
Started May 21 02:57:13 PM PDT 24
Finished May 21 02:57:19 PM PDT 24
Peak memory 207124 kb
Host smart-2b783820-c004-4b84-a74d-94cc0e2ef2d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116471842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2116471842
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2067621498
Short name T616
Test name
Test status
Simulation time 158286352 ps
CPU time 3.93 seconds
Started May 21 02:57:13 PM PDT 24
Finished May 21 02:57:22 PM PDT 24
Peak memory 209560 kb
Host smart-43cdf7e2-ce75-41eb-95e0-638461499879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067621498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2067621498
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3811102278
Short name T637
Test name
Test status
Simulation time 68382141 ps
CPU time 2.22 seconds
Started May 21 02:57:15 PM PDT 24
Finished May 21 02:57:21 PM PDT 24
Peak memory 206676 kb
Host smart-bd3fa639-b9c2-4356-a892-35c3f79d51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811102278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3811102278
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2974516533
Short name T356
Test name
Test status
Simulation time 1538833009 ps
CPU time 10.18 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:30 PM PDT 24
Peak memory 219700 kb
Host smart-62494012-0320-42e6-86bf-51e78f12855a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974516533 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2974516533
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3725797107
Short name T639
Test name
Test status
Simulation time 1552322404 ps
CPU time 36.63 seconds
Started May 21 02:57:15 PM PDT 24
Finished May 21 02:57:56 PM PDT 24
Peak memory 209888 kb
Host smart-03bdaaaa-5047-4a03-9d45-f8dc3943c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725797107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3725797107
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3020542795
Short name T667
Test name
Test status
Simulation time 42013051 ps
CPU time 1.98 seconds
Started May 21 02:57:16 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 209932 kb
Host smart-75862816-1897-4000-bb48-c3cd59ef02d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020542795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3020542795
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2001581799
Short name T106
Test name
Test status
Simulation time 27631599 ps
CPU time 0.7 seconds
Started May 21 02:57:17 PM PDT 24
Finished May 21 02:57:23 PM PDT 24
Peak memory 206008 kb
Host smart-4c9d3ddd-fda5-499a-b06c-f77b54cc684c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001581799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2001581799
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3284186297
Short name T111
Test name
Test status
Simulation time 42009932 ps
CPU time 2.14 seconds
Started May 21 02:57:21 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 209856 kb
Host smart-2f9592eb-9221-4bc9-9149-0cc1441e27bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284186297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3284186297
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3379947828
Short name T468
Test name
Test status
Simulation time 315608319 ps
CPU time 3.51 seconds
Started May 21 02:57:19 PM PDT 24
Finished May 21 02:57:28 PM PDT 24
Peak memory 221084 kb
Host smart-3c5228f4-2b1b-4d62-9591-9c3f9725db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379947828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3379947828
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.50486801
Short name T233
Test name
Test status
Simulation time 113409771 ps
CPU time 5.06 seconds
Started May 21 02:57:19 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 214312 kb
Host smart-9bced475-23da-4fdc-81e3-a456bbece0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50486801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.50486801
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2693048846
Short name T378
Test name
Test status
Simulation time 151926350 ps
CPU time 6.35 seconds
Started May 21 02:57:21 PM PDT 24
Finished May 21 02:57:34 PM PDT 24
Peak memory 209072 kb
Host smart-f444c05d-4eac-47d5-a185-0f48a5a7a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693048846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2693048846
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1025389980
Short name T525
Test name
Test status
Simulation time 149098936 ps
CPU time 4.19 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:31 PM PDT 24
Peak memory 208520 kb
Host smart-0eae9173-0b1c-4823-a946-3687dbe876db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025389980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1025389980
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3443921110
Short name T477
Test name
Test status
Simulation time 101294456 ps
CPU time 3.02 seconds
Started May 21 02:57:18 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 208096 kb
Host smart-ebba983e-f0d7-4d78-8870-ef0a45fcab42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443921110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3443921110
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4019426358
Short name T117
Test name
Test status
Simulation time 1071371576 ps
CPU time 20.19 seconds
Started May 21 02:57:17 PM PDT 24
Finished May 21 02:57:42 PM PDT 24
Peak memory 208236 kb
Host smart-47773f12-1ad3-46e9-809b-2209292b88a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019426358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4019426358
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3224964296
Short name T679
Test name
Test status
Simulation time 3185258841 ps
CPU time 19.82 seconds
Started May 21 02:57:20 PM PDT 24
Finished May 21 02:57:46 PM PDT 24
Peak memory 208132 kb
Host smart-b736822b-2a42-420e-ba79-282c754fbdae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224964296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3224964296
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4266837790
Short name T684
Test name
Test status
Simulation time 244703640 ps
CPU time 4.61 seconds
Started May 21 02:57:18 PM PDT 24
Finished May 21 02:57:28 PM PDT 24
Peak memory 208712 kb
Host smart-3c68088e-b3eb-4532-a596-f895d99ec61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266837790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4266837790
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.122568013
Short name T686
Test name
Test status
Simulation time 137778314 ps
CPU time 4.32 seconds
Started May 21 02:57:18 PM PDT 24
Finished May 21 02:57:27 PM PDT 24
Peak memory 207980 kb
Host smart-35024b24-a8e1-40b8-a307-d99336f3be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122568013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.122568013
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3178142129
Short name T340
Test name
Test status
Simulation time 2826711321 ps
CPU time 25.82 seconds
Started May 21 02:57:19 PM PDT 24
Finished May 21 02:57:50 PM PDT 24
Peak memory 221652 kb
Host smart-4ce8b264-5501-47c2-8de4-1c0cd0579aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178142129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3178142129
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.403059592
Short name T702
Test name
Test status
Simulation time 727840897 ps
CPU time 15.33 seconds
Started May 21 02:57:21 PM PDT 24
Finished May 21 02:57:43 PM PDT 24
Peak memory 220300 kb
Host smart-6bca65a8-a1ae-4e42-877b-604f09ea2695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403059592 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.403059592
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1500312759
Short name T507
Test name
Test status
Simulation time 65774613 ps
CPU time 3.28 seconds
Started May 21 02:57:18 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 209376 kb
Host smart-a4855033-3094-48c9-ba94-413af00ae3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500312759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1500312759
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4002793206
Short name T494
Test name
Test status
Simulation time 275189341 ps
CPU time 3.18 seconds
Started May 21 02:57:18 PM PDT 24
Finished May 21 02:57:26 PM PDT 24
Peak memory 210036 kb
Host smart-94da5e45-bb25-496e-8e64-10444199063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002793206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4002793206
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.49136724
Short name T545
Test name
Test status
Simulation time 44359544 ps
CPU time 0.85 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:54:48 PM PDT 24
Peak memory 205952 kb
Host smart-8abda665-3901-4eb0-b9ac-68b5ce8bacb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49136724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.49136724
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4287122247
Short name T323
Test name
Test status
Simulation time 202938660 ps
CPU time 4 seconds
Started May 21 02:54:43 PM PDT 24
Finished May 21 02:54:50 PM PDT 24
Peak memory 215148 kb
Host smart-22996df3-95e7-4b6c-8864-2070c09c1193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287122247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4287122247
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1736902700
Short name T836
Test name
Test status
Simulation time 139479632 ps
CPU time 2.16 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 208096 kb
Host smart-51380ec5-c41e-4225-9543-322628d0a9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736902700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1736902700
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2924443649
Short name T110
Test name
Test status
Simulation time 31863908 ps
CPU time 2.06 seconds
Started May 21 02:54:40 PM PDT 24
Finished May 21 02:54:46 PM PDT 24
Peak memory 214328 kb
Host smart-0db31820-41d3-4d0c-a30b-91cd294e19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924443649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2924443649
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.659477859
Short name T290
Test name
Test status
Simulation time 166490197 ps
CPU time 3.99 seconds
Started May 21 02:54:42 PM PDT 24
Finished May 21 02:54:49 PM PDT 24
Peak memory 214324 kb
Host smart-0d36dbe4-168d-41db-9875-06d647f09b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659477859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.659477859
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2458682795
Short name T59
Test name
Test status
Simulation time 155891493 ps
CPU time 2.99 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:04 PM PDT 24
Peak memory 220416 kb
Host smart-c7237527-8423-4070-85fa-c0b84cc108e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458682795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2458682795
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3050742783
Short name T81
Test name
Test status
Simulation time 219896013 ps
CPU time 7 seconds
Started May 21 02:54:41 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 208900 kb
Host smart-5c129f9a-f30e-4506-b20e-f2b2fab299ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050742783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3050742783
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3829535094
Short name T799
Test name
Test status
Simulation time 995726098 ps
CPU time 6.91 seconds
Started May 21 02:54:57 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 206928 kb
Host smart-1a988bfe-ab0a-45b6-bba2-8a2860709f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829535094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3829535094
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1493709598
Short name T559
Test name
Test status
Simulation time 194188147 ps
CPU time 2.54 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:03 PM PDT 24
Peak memory 206984 kb
Host smart-2f6dbfff-b1c6-4d51-ab79-81f7f2475849
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493709598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1493709598
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1760513948
Short name T322
Test name
Test status
Simulation time 979526743 ps
CPU time 21.11 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:21 PM PDT 24
Peak memory 209028 kb
Host smart-a46bdab8-588f-432a-9798-aba8aaec9a84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760513948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1760513948
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1852738120
Short name T533
Test name
Test status
Simulation time 949626283 ps
CPU time 21.39 seconds
Started May 21 02:54:42 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 208192 kb
Host smart-c89318e8-8ce2-444f-a7d2-e2814756337b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852738120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1852738120
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.891808574
Short name T423
Test name
Test status
Simulation time 50684206 ps
CPU time 2.53 seconds
Started May 21 02:54:47 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 209272 kb
Host smart-eeaca94d-bf64-47bb-a1a8-9df45efb1426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891808574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.891808574
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.279933779
Short name T455
Test name
Test status
Simulation time 58257795 ps
CPU time 2.31 seconds
Started May 21 02:54:43 PM PDT 24
Finished May 21 02:54:48 PM PDT 24
Peak memory 206500 kb
Host smart-bda9c5eb-bbf9-419e-a38e-3b98649ee8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279933779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.279933779
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2496265061
Short name T65
Test name
Test status
Simulation time 2846627625 ps
CPU time 22.04 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:55:10 PM PDT 24
Peak memory 215224 kb
Host smart-a21aceab-b4b2-4959-920a-08bb9e20b531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496265061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2496265061
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4089012037
Short name T888
Test name
Test status
Simulation time 1022084057 ps
CPU time 16.91 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:55:05 PM PDT 24
Peak memory 222624 kb
Host smart-e6667fab-ce0a-4943-9780-32031265daec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089012037 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4089012037
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3670092072
Short name T776
Test name
Test status
Simulation time 29733925 ps
CPU time 2.41 seconds
Started May 21 02:54:42 PM PDT 24
Finished May 21 02:54:48 PM PDT 24
Peak memory 207396 kb
Host smart-4fdfcc12-1a85-4ca6-820a-da8feaee3042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670092072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3670092072
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3691460700
Short name T448
Test name
Test status
Simulation time 313370255 ps
CPU time 5.09 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 210508 kb
Host smart-30ea9390-f4fb-43bf-92a3-0e00c109f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691460700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3691460700
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.734478284
Short name T426
Test name
Test status
Simulation time 15554188 ps
CPU time 0.75 seconds
Started May 21 02:54:53 PM PDT 24
Finished May 21 02:54:57 PM PDT 24
Peak memory 205984 kb
Host smart-83df0e8a-c661-4cdd-b4ad-5b8d974d6e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734478284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.734478284
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4133529254
Short name T242
Test name
Test status
Simulation time 1224159028 ps
CPU time 9.45 seconds
Started May 21 02:54:48 PM PDT 24
Finished May 21 02:54:59 PM PDT 24
Peak memory 214372 kb
Host smart-666761b0-7b4a-4976-810a-518154270cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133529254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4133529254
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.720865194
Short name T853
Test name
Test status
Simulation time 106851827 ps
CPU time 4.7 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:04 PM PDT 24
Peak memory 221628 kb
Host smart-24e90c1b-3ade-49b3-8dac-7ab148714b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720865194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.720865194
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3629595257
Short name T74
Test name
Test status
Simulation time 506503447 ps
CPU time 3.53 seconds
Started May 21 02:54:47 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 209160 kb
Host smart-890abe0e-c6db-4aec-96cf-d02dbf27116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629595257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3629595257
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.775216702
Short name T710
Test name
Test status
Simulation time 50640785 ps
CPU time 2.21 seconds
Started May 21 02:54:59 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 214416 kb
Host smart-ad3aa659-0788-4fc0-b3dc-d41b62dfb343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775216702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.775216702
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2809836486
Short name T93
Test name
Test status
Simulation time 1155479634 ps
CPU time 2.62 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:01 PM PDT 24
Peak memory 214320 kb
Host smart-4a6dc8e3-248f-466c-84ec-c0521a71f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809836486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2809836486
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.932797148
Short name T254
Test name
Test status
Simulation time 283399903 ps
CPU time 3.4 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:01 PM PDT 24
Peak memory 222560 kb
Host smart-aa22e338-69d9-4fe5-bba0-48f0fa73918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932797148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.932797148
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.710754508
Short name T314
Test name
Test status
Simulation time 2383849184 ps
CPU time 53.53 seconds
Started May 21 02:54:48 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 209384 kb
Host smart-2f3f3f6f-8e8a-457d-bd41-47f8684daf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710754508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.710754508
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2309915226
Short name T669
Test name
Test status
Simulation time 45552243 ps
CPU time 2.39 seconds
Started May 21 02:54:47 PM PDT 24
Finished May 21 02:54:51 PM PDT 24
Peak memory 206892 kb
Host smart-157bf491-468d-497e-9e5f-374c82cd2ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309915226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2309915226
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.204700687
Short name T796
Test name
Test status
Simulation time 719534894 ps
CPU time 7.83 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:54:56 PM PDT 24
Peak memory 208244 kb
Host smart-bf19cc3a-af6a-446b-909e-d4b99ba916ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204700687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.204700687
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.54427664
Short name T842
Test name
Test status
Simulation time 160447937 ps
CPU time 4.03 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:54:52 PM PDT 24
Peak memory 208772 kb
Host smart-50ff0900-8459-4d22-b425-a9005e504155
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54427664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.54427664
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.924452736
Short name T701
Test name
Test status
Simulation time 75527186 ps
CPU time 1.97 seconds
Started May 21 02:54:47 PM PDT 24
Finished May 21 02:54:51 PM PDT 24
Peak memory 207116 kb
Host smart-bd62f958-e7a7-4d00-9034-aa9c8685539c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924452736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.924452736
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.277111032
Short name T279
Test name
Test status
Simulation time 256450418 ps
CPU time 3.86 seconds
Started May 21 02:54:58 PM PDT 24
Finished May 21 02:55:07 PM PDT 24
Peak memory 214428 kb
Host smart-443864a9-61be-4539-adda-69d7932f6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277111032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.277111032
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3525793973
Short name T440
Test name
Test status
Simulation time 161899088 ps
CPU time 2.55 seconds
Started May 21 02:54:46 PM PDT 24
Finished May 21 02:54:51 PM PDT 24
Peak memory 208036 kb
Host smart-8fd135b5-1184-44f7-b3cf-642b9cf4b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525793973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3525793973
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3466463482
Short name T764
Test name
Test status
Simulation time 3000790524 ps
CPU time 32.7 seconds
Started May 21 02:54:58 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 215736 kb
Host smart-7ebdc1ad-890e-4832-8bba-757f54b3d0bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466463482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3466463482
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2198895345
Short name T658
Test name
Test status
Simulation time 185593097 ps
CPU time 7.58 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 218424 kb
Host smart-ab4da23c-3faf-41fe-a5f5-33647640bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198895345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2198895345
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1738454902
Short name T746
Test name
Test status
Simulation time 198046100 ps
CPU time 2.57 seconds
Started May 21 02:54:52 PM PDT 24
Finished May 21 02:54:57 PM PDT 24
Peak memory 210152 kb
Host smart-0bf1ced2-619f-4e4f-9dc6-45c031cec256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738454902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1738454902
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2722512738
Short name T141
Test name
Test status
Simulation time 39828557 ps
CPU time 0.9 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:00 PM PDT 24
Peak memory 205996 kb
Host smart-96e84433-b2d0-474d-a2e2-4b48ae1c0090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722512738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2722512738
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3168127036
Short name T339
Test name
Test status
Simulation time 924915472 ps
CPU time 5.37 seconds
Started May 21 02:54:51 PM PDT 24
Finished May 21 02:54:57 PM PDT 24
Peak memory 214372 kb
Host smart-a0bed6a1-a574-4e34-80d5-293b0b809a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168127036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3168127036
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1656025923
Short name T39
Test name
Test status
Simulation time 96158241 ps
CPU time 4.23 seconds
Started May 21 02:54:56 PM PDT 24
Finished May 21 02:55:05 PM PDT 24
Peak memory 218332 kb
Host smart-86e0977b-1e8f-4c39-a208-c05ac8eb92f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656025923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1656025923
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4283228474
Short name T674
Test name
Test status
Simulation time 78141116 ps
CPU time 3.56 seconds
Started May 21 02:54:58 PM PDT 24
Finished May 21 02:55:07 PM PDT 24
Peak memory 208384 kb
Host smart-6374c163-313a-4fa7-a03b-ec850cb1324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283228474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4283228474
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.70701094
Short name T479
Test name
Test status
Simulation time 6953090292 ps
CPU time 44.47 seconds
Started May 21 02:54:53 PM PDT 24
Finished May 21 02:55:42 PM PDT 24
Peak memory 219272 kb
Host smart-e65e4e1b-fc98-4c0c-ac33-5f6a39aa0bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70701094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.70701094
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_random.1416015887
Short name T276
Test name
Test status
Simulation time 177392985 ps
CPU time 4.08 seconds
Started May 21 02:54:52 PM PDT 24
Finished May 21 02:54:58 PM PDT 24
Peak memory 210124 kb
Host smart-f238d103-cde0-4dca-8754-80d07beb7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416015887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1416015887
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.963931927
Short name T714
Test name
Test status
Simulation time 299870338 ps
CPU time 3.89 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 208576 kb
Host smart-b7ef20e0-190c-470a-bab2-6ccb7b909915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963931927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.963931927
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1012299234
Short name T302
Test name
Test status
Simulation time 102856040 ps
CPU time 2.61 seconds
Started May 21 02:54:52 PM PDT 24
Finished May 21 02:54:56 PM PDT 24
Peak memory 206888 kb
Host smart-618c644a-3e0a-4f98-9a88-55c3523b83ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012299234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1012299234
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3286479828
Short name T575
Test name
Test status
Simulation time 231023233 ps
CPU time 4.86 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 206904 kb
Host smart-995c7d9e-00c1-49f3-bea4-b8ebf4b802b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286479828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3286479828
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.364410850
Short name T114
Test name
Test status
Simulation time 96037679 ps
CPU time 3.26 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 208968 kb
Host smart-655b56e3-0ae2-4990-a14d-4992db9e1b47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364410850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.364410850
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1829212450
Short name T898
Test name
Test status
Simulation time 1202582099 ps
CPU time 22.82 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 208544 kb
Host smart-445a14a0-5d47-4c10-a0d0-ee6584f82404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829212450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1829212450
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3113010289
Short name T599
Test name
Test status
Simulation time 127289675 ps
CPU time 3.33 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 208424 kb
Host smart-3a4adddc-e528-446d-b7eb-e5df4398177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113010289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3113010289
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4195354456
Short name T388
Test name
Test status
Simulation time 200409844 ps
CPU time 7.04 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 219752 kb
Host smart-4c8302f2-5295-4970-9ecc-35ea49353223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195354456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4195354456
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.779539397
Short name T645
Test name
Test status
Simulation time 339925037 ps
CPU time 9.54 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 209848 kb
Host smart-ab4241c0-6229-498f-81b9-208aa9e78229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779539397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.779539397
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.617258389
Short name T865
Test name
Test status
Simulation time 268226556 ps
CPU time 2.32 seconds
Started May 21 02:54:54 PM PDT 24
Finished May 21 02:55:01 PM PDT 24
Peak memory 210588 kb
Host smart-cf6f804e-6bd9-4fe2-9926-ce4eaddd60d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617258389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.617258389
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3312093376
Short name T465
Test name
Test status
Simulation time 17030193 ps
CPU time 0.95 seconds
Started May 21 02:55:03 PM PDT 24
Finished May 21 02:55:10 PM PDT 24
Peak memory 206148 kb
Host smart-8d85a608-e0d1-484f-8dd7-3ac9ab1a2b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312093376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3312093376
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3193921805
Short name T144
Test name
Test status
Simulation time 232637095 ps
CPU time 3.85 seconds
Started May 21 02:54:57 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 214372 kb
Host smart-ba9f2fa5-b5fb-42a5-b9d0-a4335ae53105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193921805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3193921805
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.384063911
Short name T439
Test name
Test status
Simulation time 52526771 ps
CPU time 1.35 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 207488 kb
Host smart-57bf0452-09f5-499f-9a94-d9cb54eca3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384063911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.384063911
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3781248170
Short name T291
Test name
Test status
Simulation time 163168039 ps
CPU time 3.56 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 221680 kb
Host smart-736e96ae-7091-4373-a7b3-6b24b90f4410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781248170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3781248170
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1671163943
Short name T218
Test name
Test status
Simulation time 72821677 ps
CPU time 3.3 seconds
Started May 21 02:55:03 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 214292 kb
Host smart-fdf14708-2d03-49d2-b951-9bfbc59d6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671163943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1671163943
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1131261168
Short name T784
Test name
Test status
Simulation time 609564909 ps
CPU time 6.18 seconds
Started May 21 02:54:52 PM PDT 24
Finished May 21 02:55:00 PM PDT 24
Peak memory 214372 kb
Host smart-ac1aa063-e29f-424a-87b6-537f883e59c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131261168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1131261168
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.83859246
Short name T522
Test name
Test status
Simulation time 6122197238 ps
CPU time 61.67 seconds
Started May 21 02:54:53 PM PDT 24
Finished May 21 02:55:59 PM PDT 24
Peak memory 208160 kb
Host smart-4fb72208-f1e3-4e5a-9151-f73c02ade28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83859246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.83859246
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3874635075
Short name T788
Test name
Test status
Simulation time 69468765 ps
CPU time 3.57 seconds
Started May 21 02:54:59 PM PDT 24
Finished May 21 02:55:07 PM PDT 24
Peak memory 208880 kb
Host smart-8e2c1361-f209-47f6-89c9-daaaa4eccfbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874635075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3874635075
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2160584575
Short name T834
Test name
Test status
Simulation time 84120242 ps
CPU time 2.39 seconds
Started May 21 02:54:53 PM PDT 24
Finished May 21 02:54:58 PM PDT 24
Peak memory 207060 kb
Host smart-6f662c16-fa9d-42dd-8394-5f65a86ccfd7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160584575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2160584575
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1069931508
Short name T862
Test name
Test status
Simulation time 301238412 ps
CPU time 3.13 seconds
Started May 21 02:54:58 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 208748 kb
Host smart-2a247a12-d386-4f8e-9048-8bc58cc7003e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069931508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1069931508
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2413293660
Short name T754
Test name
Test status
Simulation time 186095078 ps
CPU time 4.39 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 210004 kb
Host smart-9618a717-08cb-453b-8428-5242b0a1c6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413293660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2413293660
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.48360128
Short name T536
Test name
Test status
Simulation time 172458081 ps
CPU time 4.67 seconds
Started May 21 02:54:55 PM PDT 24
Finished May 21 02:55:04 PM PDT 24
Peak memory 206704 kb
Host smart-c505290c-5805-4b42-96a7-1403353ffdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48360128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.48360128
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1435273757
Short name T503
Test name
Test status
Simulation time 413749951 ps
CPU time 7.13 seconds
Started May 21 02:54:59 PM PDT 24
Finished May 21 02:55:11 PM PDT 24
Peak memory 219104 kb
Host smart-a9ed2839-1c30-4d11-a35a-1e719d0188aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435273757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1435273757
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3611306108
Short name T70
Test name
Test status
Simulation time 111302382 ps
CPU time 7.54 seconds
Started May 21 02:55:01 PM PDT 24
Finished May 21 02:55:13 PM PDT 24
Peak memory 220200 kb
Host smart-53932a6c-b2ab-456f-996b-152938e40f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611306108 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3611306108
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2454610835
Short name T443
Test name
Test status
Simulation time 166699460 ps
CPU time 5.42 seconds
Started May 21 02:54:59 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 218204 kb
Host smart-503ef3c5-a2f7-41c4-9784-67aaaad7961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454610835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2454610835
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3380510877
Short name T879
Test name
Test status
Simulation time 29381198 ps
CPU time 0.91 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:13 PM PDT 24
Peak memory 206120 kb
Host smart-589c87bc-41bb-4408-8367-df34c74d4475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380510877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3380510877
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1866012180
Short name T359
Test name
Test status
Simulation time 78302717 ps
CPU time 3.31 seconds
Started May 21 02:55:03 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 218452 kb
Host smart-0f26c574-88e1-436b-80c7-fe4cd2b5e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866012180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1866012180
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3039929968
Short name T18
Test name
Test status
Simulation time 301417220 ps
CPU time 4.98 seconds
Started May 21 02:55:01 PM PDT 24
Finished May 21 02:55:11 PM PDT 24
Peak memory 222568 kb
Host smart-d9ce73bd-2e96-4b79-aa5e-688a09010936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039929968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3039929968
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3851785145
Short name T34
Test name
Test status
Simulation time 93377431 ps
CPU time 4.87 seconds
Started May 21 02:55:06 PM PDT 24
Finished May 21 02:55:17 PM PDT 24
Peak memory 214316 kb
Host smart-f55ca3c9-8db1-446b-95b6-71e000a6e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851785145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3851785145
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1651301445
Short name T215
Test name
Test status
Simulation time 194208196 ps
CPU time 2.09 seconds
Started May 21 02:55:01 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 214408 kb
Host smart-3b36f39f-6bc1-42ad-86f7-6aaf087ef0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651301445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1651301445
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1694006414
Short name T523
Test name
Test status
Simulation time 181735470 ps
CPU time 2.75 seconds
Started May 21 02:55:04 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 207516 kb
Host smart-da04b8c0-7a2c-4cee-8619-43a7db0dc79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694006414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1694006414
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2213828967
Short name T830
Test name
Test status
Simulation time 50536940 ps
CPU time 2.6 seconds
Started May 21 02:54:59 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 207096 kb
Host smart-fd98dd0e-538c-4bbe-85cf-158ec10f5a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213828967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2213828967
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2561454337
Short name T785
Test name
Test status
Simulation time 1317759383 ps
CPU time 17.2 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:28 PM PDT 24
Peak memory 208316 kb
Host smart-084570f1-4e88-4aa5-af2f-b3b4a0fc87ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561454337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2561454337
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.888063916
Short name T540
Test name
Test status
Simulation time 443701663 ps
CPU time 4.65 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 208908 kb
Host smart-c1b46db8-633a-4c04-8757-9ac6b5f37ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888063916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.888063916
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2144235238
Short name T663
Test name
Test status
Simulation time 184338078 ps
CPU time 2.83 seconds
Started May 21 02:55:03 PM PDT 24
Finished May 21 02:55:12 PM PDT 24
Peak memory 208440 kb
Host smart-b011005c-f27d-4f49-9afa-bcb25f462ae5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144235238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2144235238
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3464907659
Short name T705
Test name
Test status
Simulation time 92919661 ps
CPU time 3.05 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 209252 kb
Host smart-b12c6318-1a44-403f-be29-c2de4eeeee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464907659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3464907659
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3756977494
Short name T703
Test name
Test status
Simulation time 797936013 ps
CPU time 2.99 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 206872 kb
Host smart-6d325cc3-8d42-41e8-9f2b-3f7531536a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756977494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3756977494
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1091900900
Short name T343
Test name
Test status
Simulation time 2613118619 ps
CPU time 27.23 seconds
Started May 21 02:55:05 PM PDT 24
Finished May 21 02:55:38 PM PDT 24
Peak memory 222832 kb
Host smart-51cbb3e4-c4cf-432d-a84b-e5aeae38118d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091900900 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1091900900
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1928783083
Short name T866
Test name
Test status
Simulation time 352622060 ps
CPU time 4.98 seconds
Started May 21 02:55:01 PM PDT 24
Finished May 21 02:55:11 PM PDT 24
Peak memory 219712 kb
Host smart-1fb02e63-5d73-4231-a416-cd519edbc55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928783083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1928783083
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.111757238
Short name T37
Test name
Test status
Simulation time 1142248397 ps
CPU time 2.9 seconds
Started May 21 02:55:00 PM PDT 24
Finished May 21 02:55:07 PM PDT 24
Peak memory 209876 kb
Host smart-6e5c4275-2ae9-4605-89b1-dd0eafdaade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111757238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.111757238
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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