Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	47	1			T46	1		T47	2		T48	1
auto[OpGenId]	16	1			T68	1		T21	1		T63	1
auto[OpGenSwOut]	19	1			T58	1		T62	1		T213	1
auto[OpGenHwOut]	10	1			T6	1		T7	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1664	1			T17	3		T46	3		T113	1
auto[StInit]	91	1			T46	1		T20	1		T42	1
auto[StCreatorRootKey]	54	1			T46	2		T38	1		T61	1
auto[StOwnerIntKey]	37	1			T113	1		T64	1		T66	1
auto[StOwnerKey]	39	1			T36	1		T37	1		T41	1
auto[StDisabled]	479	1			T17	7		T46	4		T113	2
auto[StInvalid]	49	1			T35	1		T56	1		T57	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3402

1

T1

1

T2

1

T3

1

auto[1]

92

1

T46

1

T68

1

T58

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1661	1			T17	3		T46	3		T113	1
auto[StReset]	auto[1]	3	1			T31	1		T54	1		T55	1
auto[StInit]	auto[0]	47	1			T46	1		T20	1		T42	1
auto[StInit]	auto[1]	44	1			T58	1		T21	1		T47	2
auto[StCreatorRootKey]	auto[0]	36	1			T46	1		T38	1		T61	1
auto[StCreatorRootKey]	auto[1]	18	1			T46	1		T62	1		T63	2
auto[StOwnerIntKey]	auto[0]	25	1			T113	1		T64	1		T66	1
auto[StOwnerIntKey]	auto[1]	12	1			T48	1		T9	1		T67	1
auto[StOwnerKey]	auto[0]	32	1			T36	1		T37	1		T41	1
auto[StOwnerKey]	auto[1]	7	1			T68	1		T143	1		T214	1
auto[StDisabled]	auto[0]	471	1			T17	7		T46	4		T113	2
auto[StDisabled]	auto[1]	8	1			T63	1		T74	1		T76	1
auto[StInvalid]	auto[0]	49	1			T35	1		T56	1		T57	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T31	1		T54	1		T55	1
auto[StInit]	auto[OpAdvance]	20	1			T47	2		T75	1		T215	1
auto[StInit]	auto[OpGenId]	10	1			T21	1		T213	1		T138	1
auto[StInit]	auto[OpGenSwOut]	10	1			T58	1		T216	1		T181	1
auto[StInit]	auto[OpGenHwOut]	4	1			T8	1		T185	1		T217	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T46	1		T63	1		T218	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T63	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T62	1		T213	1		T219	1
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T48	1		T9	1		T182	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T67	1		T188	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T89	1		T220	1		T221	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T143	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	3	1			T68	1		T222	1		T223	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T224	1		T225	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T214	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	4	1			T63	1		T74	1		T76	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T77	1		T226	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T6	1		T7	1		-	-