Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4798

1

T1

4

T2

11

T3

8

auto[1]

571

1

T3

5

T17

1

T45

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4798

1

T1

4

T2

11

T3

8

auto[1]

571

1

T3

5

T17

1

T45

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4831

1

T1

4

T2

11

T3

13

auto[1]

538

1

T45

1

T46

2

T212

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4831

1

T1

4

T2

11

T3

13

auto[1]

538

1

T45

1

T46

2

T212

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	384	1			T4	6		T5	3		T17	2
auto[OpGenId]	1140	1			T1	2		T4	1		T5	2
auto[OpGenSwOut]	1198	1			T1	1		T4	1		T5	4
auto[OpGenHwOut]	2575	1			T1	1		T2	11		T3	13
auto[OpDisable]	72	1			T17	1		T49	1		T50	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	384	1			T4	6		T5	3		T17	2
auto[OpGenId]	1140	1			T1	2		T4	1		T5	2
auto[OpGenSwOut]	1198	1			T1	1		T4	1		T5	4
auto[OpGenHwOut]	2575	1			T1	1		T2	11		T3	13
auto[OpDisable]	72	1			T17	1		T49	1		T50	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4797

1

T1

3

T2

6

T3

13

auto[1]

572

1

T1

1

T2

5

T15

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4797

1

T1

3

T2

6

T3

13

auto[1]

572

1

T1

1

T2

5

T15

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5103

1

T1

4

T2

11

T3

13

auto[1]

266

1

T4

8

T5

7

T150

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1833	1			T1	1		T2	3		T3	5
auto[1]	727	1			T1	1		T2	1		T3	2
auto[2]	715	1			T1	1		T2	4		T3	3
auto[3]	644	1			T1	1		T2	2		T3	1
auto[4]	354	1			T15	1		T17	4		T24	1
auto[5]	334	1			T3	1		T4	2		T5	4
auto[6]	379	1			T3	1		T4	4		T5	1
auto[7]	383	1			T2	1		T15	2		T17	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1450	1			T2	1		T3	2		T15	3
clear_one[1]	727	1			T1	1		T2	1		T3	2
clear_one[2]	715	1			T1	1		T2	4		T3	3
clear_one[3]	644	1			T1	1		T2	2		T3	1
clear_none	1833	1			T1	1		T2	3		T3	5

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1016	1			T2	3		T3	5		T15	4
auto[StInit]	640	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	563	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	543	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	471	1			T2	1		T3	1		T15	1
auto[StDisabled]	1855	1			T1	1		T2	4		T3	4
auto[StInvalid]	281	1			T35	4		T56	7		T57	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1016	1			T2	3		T3	5		T15	4
auto[StInit]	640	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	563	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	543	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	471	1			T2	1		T3	1		T15	1
auto[StDisabled]	1855	1			T1	1		T2	4		T3	4
auto[StInvalid]	281	1			T35	4		T56	7		T57	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[0] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	4
[auto[5] - auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	4
[auto[5] - auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	6
[auto[5] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T4	1		T232	1		T233	1
auto[0]	auto[StReset]	auto[OpGenId]	155	1			T46	2		T38	1		T50	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	155	1			T45	1		T150	1		T58	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	255	1			T2	1		T3	2		T15	2
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T17	1		T95	1		T141	1
auto[0]	auto[StInit]	auto[OpGenId]	96	1			T5	1		T17	1		T19	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	87	1			T17	2		T152	1		T102	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	168	1			T1	1		T15	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T95	1		T234	1		T72	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T17	1		T46	1		T235	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	55	1			T5	1		T68	1		T80	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	74	1			T5	1		T207	1		T211	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T95	2		T236	1		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T113	1		T59	1		T47	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	36	1			T46	1		T73	1		T95	3
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	63	1			T206	1		T212	1		T68	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T95	1		T106	1		T238	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	25	1			T93	1		T234	1		T47	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T69	1		T71	1		T79	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T3	1		T15	1		T121	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T95	1		T63	1		T239	1
auto[0]	auto[StDisabled]	auto[OpGenId]	71	1			T114	1		T240	1		T59	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T17	1		T46	1		T65	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	179	1			T2	2		T3	2		T15	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T17	1		T70	1		T241	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T52	1		T101	1		T242	1
auto[0]	auto[StInvalid]	auto[OpGenId]	16	1			T57	1		T243	1		T104	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	22	1			T57	1		T103	2		T244	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T56	2		T51	1		T53	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T245	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T151	1		T246	1		T133	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T150	1		T59	1		T243	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T3	1		T15	1		T151	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T4	1		T205	1		T245	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T63	1		T213	1		T247	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T45	1		T38	1		T248	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T249	1		T250	1		T63	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T4	1		T152	1		T75	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T59	1		T47	1		T251	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T240	1		T140	1		T72	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T15	1		T252	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T114	1		T59	1		T47	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T209	1		T152	2		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T70	1		T254	1		T201	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T255	1		T256	1		T257	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T142	1		T258	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T59	1		T34	1		T76	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T260	1		T63	1		T197	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T59	1		T261	1		T94	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T262	1		T152	1		T142	1
auto[1]	auto[StDisabled]	auto[OpGenId]	58	1			T1	1		T17	1		T152	3
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T69	1		T248	1		T152	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T2	1		T3	1		T17	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T50	1		T246	1		T197	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T101	1		T263	2		T264	1
auto[1]	auto[StInvalid]	auto[OpGenId]	21	1			T57	1		T101	2		T103	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T56	1		T265	2		T266	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T267	2		T268	1		T269	2
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T142	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T91	1		T39	1		T270	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T59	1		T25	1		T271	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	39	1			T2	1		T252	1		T265	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T105	1		T63	1		T134	1
auto[2]	auto[StInit]	auto[OpGenId]	6	1			T272	1		T237	1		T135	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T59	1		T47	1		T213	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	30	1			T2	1		T3	1		T273	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T4	2		T5	1		T102	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T17	1		T63	1		T75	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T17	1		T197	1		T239	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T210	1		T208	1		T116	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T63	1		T274	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T1	1		T5	1		T26	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	22	1			T4	1		T114	1		T102	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T2	1		T3	1		T17	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T276	1		T277	1		T192	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T17	1		T102	1		T278	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T17	1		T113	1		T70	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T2	1		T212	1		T59	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	20	1			T102	1		T97	1		T47	1
auto[2]	auto[StDisabled]	auto[OpGenId]	66	1			T150	1		T114	1		T59	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T5	1		T151	1		T59	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T3	1		T15	1		T212	2
auto[2]	auto[StDisabled]	auto[OpDisable]	13	1			T59	2		T197	1		T75	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T56	1		T279	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T51	1		T266	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T56	1		T101	1		T104	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T35	1		T51	1		T52	1
auto[3]	auto[StReset]	auto[OpAdvance]	2	1			T282	2		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T205	1		T59	1		T25	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T59	1		T91	1		T47	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	50	1			T3	1		T211	1		T59	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T282	1		T78	1		T283	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T47	1		T79	1		T99	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	9	1			T151	1		T71	1		T284	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T24	1		T211	1		T59	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T285	1		T223	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T35	1		T64	1		T39	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T1	1		T136	1		T142	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T2	1		T81	1		T96	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T45	1		T63	1		T258	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T136	1		T59	1		T235	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	26	1			T150	2		T39	1		T47	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T15	1		T210	1		T116	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T47	1		T287	3		T135	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	8	1			T197	1		T216	1		T214	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T209	1		T197	1		T288	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T46	1		T211	1		T73	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	12	1			T141	2		T277	1		T289	1
auto[3]	auto[StDisabled]	auto[OpGenId]	40	1			T59	1		T253	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T207	1		T59	2		T235	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	133	1			T2	1		T46	1		T116	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T49	1		T290	1		T291	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T266	1		T292	1		T293	2
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T56	1		T53	2		T243	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T243	1		T267	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T52	1		T265	1		T243	1
auto[4]	auto[StReset]	auto[OpGenId]	13	1			T38	1		T21	1		T39	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T240	1		T75	1		T199	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	17	1			T211	1		T295	1		T296	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T24	1		T297	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T133	1		T298	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T26	1		T75	1		T299	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T296	1		T75	1		T76	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T59	1		T75	1		T138	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T253	1		T271	1		T67	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T114	1		T209	1		T213	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T121	1		T59	1		T300	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T301	1		T302	1		T303	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T59	1		T72	1		T304	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T305	1		T213	1		T239	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T121	1		T252	1		T96	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T306	1		T226	1		T90	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	3	1			T201	1		T307	1		T221	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T17	1		T63	1		T228	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T235	1		T255	1		T257	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	20	1			T47	1		T79	1		T63	1
auto[4]	auto[StDisabled]	auto[OpGenId]	20	1			T17	1		T140	1		T79	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T17	2		T59	1		T71	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T15	1		T210	1		T248	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T47	1		T84	1		T306	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T293	2		T308	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T308	1		T309	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T311	1		T312	1		T313	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T35	1		T314	1		T315	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T134	1		T213	1		T135	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T47	1		T276	1		T316	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T317	1		T318	1		T319	2
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T59	1		T260	1		T76	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T320	1		T321	1		T322	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T50	1		T255	1		T323	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T74	1		T199	1		T324	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	2	1			T278	1		T325	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T59	1		T323	1		T67	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T3	1		T326	1		T327	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T328	1		T322	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T79	1		T72	1		T329	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T330	1		T86	1		T331	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T332	1		T333	1		T244	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T59	1		T47	1		T275	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T150	1		T335	1		T336	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T210	1		T114	1		T116	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	8	1			T4	1		T5	2		T59	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T71	2		T63	1		T337	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T5	1		T59	1		T276	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T4	1		T5	1		T59	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T73	1		T67	1		T289	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T313	1		T338	1		T339	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T242	1		T264	1		T340	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T56	1		T341	1		T342	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T53	1		T100	1		T343	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T24	1		T58	1		T246	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	14	1			T240	1		T59	1		T21	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	26	1			T3	1		T113	1		T332	2
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T48	1		T246	1		T67	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	9	1			T344	1		T239	2		T345	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T24	2		T25	1		T332	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T59	1		T346	1		T347	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	2	1			T17	1		T197	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T79	1		T75	1		T83	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T212	1		T348	1		T332	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T277	1		T349	1		T350	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T71	1		T133	1		T75	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T151	2		T239	1		T198	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T80	1		T151	1		T317	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T226	1		T55	1		T351	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T17	1		T136	1		T47	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T151	1		T352	1		T353	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T240	1		T59	1		T300	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T46	1		T117	1		T287	2
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T4	1		T95	1		T354	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T5	1		T50	1		T59	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T4	3		T17	1		T212	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T134	1		T213	1		T67	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	6	1			T35	2		T355	2		T309	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T266	1		T100	1		T343	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T100	1		T356	1		T357	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T266	1		T340	1		T358	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T63	1		T75	1		T274	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	17	1			T271	1		T272	1		T213	2
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T2	1		T15	1		T273	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T359	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T75	1		T109	1		T198	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T360	1		T55	1		T361	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T24	1		T118	1		T97	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T48	1		T362	1		T363	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T239	1		T135	1		T306	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T226	1		T303	1		T364	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T19	1		T65	1		T139	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T245	2		T284	1		T365	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T246	1		T138	1		T282	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T72	1		T76	1		T366	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T205	1		T367	1		T348	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T91	1		T72	1		T368	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T282	2		T331	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T59	1		T282	1		T370	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T287	2		T63	1		T333	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T17	1		T139	1		T276	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T102	1		T139	1		T140	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T248	1		T235	1		T352	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	97	1			T15	1		T210	1		T211	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T299	1		T331	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T265	1		T372	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	9	1			T52	1		T373	1		T374	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T53	1		T375	1		T376	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T57	1		T279	1		T356	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1450

1

T2

1

T3

2

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

433

1

T3

2

T15

1

T4

2

clear_one[1]

auto[0]

auto[0]

auto[1]

119

1

T1

1

T2

1

T15

1

clear_one[1]

auto[0]

auto[1]

auto[0]

126

1

T212

1

T262

1

T59

2

clear_one[1]

auto[0]

auto[1]

auto[1]

49

1

T59

1

T377

1

T71

2

clear_one[2]

auto[0]

auto[0]

auto[0]

399

1

T1

1

T2

2

T3

1

clear_one[2]

auto[0]

auto[0]

auto[1]

128

1

T2

2

T15

1

T208

1

clear_one[2]

auto[1]

auto[0]

auto[0]

146

1

T3

2

T17

1

T210

1

clear_one[2]

auto[1]

auto[0]

auto[1]

42

1

T59

2

T271

1

T26

1

clear_one[3]

auto[0]

auto[0]

auto[0]

389

1

T1

1

T2

2

T3

1

clear_one[3]

auto[0]

auto[1]

auto[0]

111

1

T207

1

T209

1

T317

1

clear_one[3]

auto[1]

auto[0]

auto[0]

109

1

T210

1

T49

1

T46

2

clear_one[3]

auto[1]

auto[1]

auto[0]

35

1

T45

1

T73

1

T59

1

clear_none

auto[0]

auto[0]

auto[0]

1302

1

T1

1

T2

1

T3

2

clear_none

auto[0]

auto[0]

auto[1]

141

1

T2

2

T15

2

T206

1

clear_none

auto[0]

auto[1]

auto[0]

122

1

T46

1

T212

1

T73

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T117

1

T253

1

T271

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T3

3

T210

1

T46

1

clear_none

auto[1]

auto[0]

auto[1]

32

1

T59

1

T95

8

T79

1

clear_none

auto[1]

auto[1]

auto[0]

34

1

T46

1

T207

1

T68

1

clear_none

auto[1]

auto[1]

auto[1]

32

1

T59

1

T95

9

T141

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1382	1			T2	1		T3	2		T15	3
clear_all	auto[1]	68	1			T4	4		T5	4		T151	3
clear_one[1]	auto[0]	669	1			T1	1		T2	1		T3	2
clear_one[1]	auto[1]	58	1			T4	1		T152	8		T141	2
clear_one[2]	auto[0]	683	1			T1	1		T2	4		T3	3
clear_one[2]	auto[1]	32	1			T4	2		T5	1		T97	1
clear_one[3]	auto[0]	627	1			T1	1		T2	2		T3	1
clear_one[3]	auto[1]	17	1			T150	1		T141	3		T287	3
clear_none	auto[0]	1742	1			T1	1		T2	3		T3	5
clear_none	auto[1]	91	1			T4	1		T5	2		T152	1