Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11396

1

T1

8

T2

13

T3

16

auto[Attestation]

7801

1

T1

16

T2

3

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2803	1			T1	4		T4	1		T5	9
auto[Aes]	3412	1			T1	1		T3	21		T4	4
auto[Kmac]	3466	1			T1	5		T4	3		T5	7
auto[Otbn]	3513	1			T1	4		T2	16		T15	19

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7811	1			T1	8		T2	8		T3	8
auto[OpGenId]	6003	1			T1	10		T4	3		T5	10
auto[OpGenSwOut]	6073	1			T1	8		T4	3		T5	15
auto[OpGenHwOut]	7121	1			T1	6		T2	16		T3	21
auto[OpDisable]	148	1			T17	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10882

1

T1

14

T2

8

T3

8

auto[OpDoneFail]

16274

1

T1

18

T2

16

T3

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6442	1			T1	1		T2	9		T3	14
auto[StInit]	3923	1			T1	6		T2	2		T3	2
auto[StCreatorRootKey]	3264	1			T1	3		T2	2		T3	2
auto[StOwnerIntKey]	2904	1			T1	6		T2	2		T3	2
auto[StOwnerKey]	2461	1			T1	3		T2	2		T3	2
auto[StDisabled]	8162	1			T1	13		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T16	1		T24	3		T46	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T1	1		T24	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	98	1			T1	1		T5	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T5	1		T17	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T17	1		T113	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T16	1		T150	2		T114	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	357	1			T16	1		T136	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T17	1		T19	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	92	1			T17	1		T19	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T204	1		T65	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T17	1		T98	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	219	1			T17	1		T46	2		T206	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	361	1			T16	3		T24	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	98	1			T19	1		T24	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	69	1			T17	1		T46	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T17	1		T36	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	69	1			T4	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	206	1			T19	1		T46	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	329	1			T16	1		T136	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T17	1		T136	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T49	1		T46	2		T114	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T4	1		T16	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T5	1		T37	1		T113	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	238	1			T5	2		T17	3		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	75	1			T46	2		T59	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T17	1		T36	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	92	1			T36	1		T119	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	79	1			T1	1		T113	1		T114	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T5	1		T17	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	233	1			T17	2		T113	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T59	3		T79	2		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T24	1		T46	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T17	1		T136	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T5	1		T17	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T19	1		T37	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	228	1			T17	3		T208	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T46	2		T114	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	97	1			T1	1		T4	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T136	1		T150	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T5	1		T206	1		T113	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T1	1		T17	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	239	1			T1	2		T5	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T114	3		T71	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	126	1			T19	1		T45	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T16	1		T41	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T5	1		T49	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T17	1		T19	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	224	1			T1	1		T5	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	288	1			T24	1		T45	1		T113	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T24	1		T68	1		T59	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	98	1			T5	2		T46	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T206	1		T66	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	43	1			T46	1		T207	1		T150	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	189	1			T1	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	395	1			T3	13		T24	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	104	1			T5	1		T46	2		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	116	1			T3	1		T210	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	104	1			T208	1		T205	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T1	1		T4	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	323	1			T3	2		T17	1		T210	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	522	1			T24	2		T36	2		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	133	1			T17	1		T24	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T46	1		T113	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T36	1		T68	1		T151	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T136	1		T36	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	268	1			T5	2		T17	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	489	1			T2	8		T15	11		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T1	2		T2	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T208	1		T46	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T2	1		T15	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	77	1			T15	1		T46	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	288	1			T2	3		T15	3		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T46	3		T59	3		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T24	1		T46	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T35	1		T37	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T46	1		T205	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T19	1		T36	1		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	195	1			T5	2		T208	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	55	1			T46	3		T71	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T3	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T17	1		T36	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T3	1		T17	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T3	1		T4	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	288	1			T3	2		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	48	1			T59	1		T47	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T24	1		T208	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T19	1		T45	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T206	1		T64	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T136	1		T45	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	272	1			T1	1		T4	1		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	45	1			T46	1		T59	5		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T15	1		T24	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T2	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T206	1		T150	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	99	1			T2	1		T4	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	283	1			T1	1		T2	1		T15	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T1	1		T5	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	627	1			T1	1		T16	2		T24	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T17	1		T19	1		T98	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	700	1			T16	1		T17	3		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	202	1			T4	1		T5	1		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	683	1			T16	3		T19	2		T24	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T4	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	694	1			T5	2		T16	1		T17	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	214	1			T1	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	418	1			T17	3		T36	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	205	1			T5	1		T17	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	407	1			T17	3		T24	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T1	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	426	1			T1	3		T4	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	217	1			T5	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	430	1			T1	1		T5	2		T19	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T5	2		T46	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	604	1			T1	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	296	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	836	1			T3	15		T5	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T136	1		T36	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	938	1			T5	2		T17	2		T24	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T2	1		T15	2		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	909	1			T1	2		T2	12		T15	14
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	171	1			T19	1		T35	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	375	1			T5	2		T24	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T3	2		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	479	1			T3	3		T4	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T19	1		T136	1		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	461	1			T1	1		T4	1		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T2	2		T15	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	482	1			T1	1		T2	1		T15	2