Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33271

1

T1

35

T2

27

T3

32

auto[1]

242

1

T4

3

T5

9

T150

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33280	1			T1	35		T2	27		T3	32
auto[134217728:268435455]	4	1			T404	1		T405	1		T233	1
auto[268435456:402653183]	12	1			T5	1		T95	1		T140	1
auto[402653184:536870911]	12	1			T141	1		T245	1		T282	2
auto[536870912:671088639]	3	1			T141	1		T233	1		T406	1
auto[671088640:805306367]	8	1			T5	1		T95	1		T256	1
auto[805306368:939524095]	12	1			T4	1		T151	1		T95	2
auto[939524096:1073741823]	5	1			T140	1		T141	1		T287	1
auto[1073741824:1207959551]	4	1			T152	1		T407	1		T283	1
auto[1207959552:1342177279]	9	1			T151	1		T140	1		T141	1
auto[1342177280:1476395007]	7	1			T405	1		T386	1		T233	1
auto[1476395008:1610612735]	9	1			T256	2		T404	1		T349	1
auto[1610612736:1744830463]	7	1			T151	1		T95	1		T349	1
auto[1744830464:1879048191]	5	1			T95	1		T256	1		T408	1
auto[1879048192:2013265919]	9	1			T95	1		T256	1		T282	1
auto[2013265920:2147483647]	9	1			T5	1		T256	2		T233	1
auto[2147483648:2281701375]	3	1			T150	1		T407	1		T409	1
auto[2281701376:2415919103]	4	1			T287	1		T282	1		T410	1
auto[2415919104:2550136831]	10	1			T95	2		T97	1		T139	1
auto[2550136832:2684354559]	7	1			T5	1		T404	1		T302	1
auto[2684354560:2818572287]	13	1			T151	1		T95	3		T287	1
auto[2818572288:2952790015]	7	1			T5	1		T152	1		T139	1
auto[2952790016:3087007743]	8	1			T4	1		T151	1		T256	1
auto[3087007744:3221225471]	7	1			T95	1		T139	1		T142	1
auto[3221225472:3355443199]	6	1			T95	1		T141	1		T406	1
auto[3355443200:3489660927]	10	1			T151	1		T95	1		T141	3
auto[3489660928:3623878655]	10	1			T152	1		T232	1		T404	1
auto[3623878656:3758096383]	6	1			T4	1		T5	1		T151	1
auto[3758096384:3892314111]	7	1			T139	1		T302	2		T411	2
auto[3892314112:4026531839]	4	1			T141	1		T386	1		T412	1
auto[4026531840:4160749567]	7	1			T5	1		T151	2		T141	1
auto[4160749568:4294967295]	9	1			T151	2		T95	1		T287	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33271	1			T1	35		T2	27		T3	32
auto[0:134217727]	auto[1]	9	1			T5	2		T282	1		T359	1
auto[134217728:268435455]	auto[1]	4	1			T404	1		T405	1		T233	1
auto[268435456:402653183]	auto[1]	12	1			T5	1		T95	1		T140	1
auto[402653184:536870911]	auto[1]	12	1			T141	1		T245	1		T282	2
auto[536870912:671088639]	auto[1]	3	1			T141	1		T233	1		T406	1
auto[671088640:805306367]	auto[1]	8	1			T5	1		T95	1		T256	1
auto[805306368:939524095]	auto[1]	12	1			T4	1		T151	1		T95	2
auto[939524096:1073741823]	auto[1]	5	1			T140	1		T141	1		T287	1
auto[1073741824:1207959551]	auto[1]	4	1			T152	1		T407	1		T283	1
auto[1207959552:1342177279]	auto[1]	9	1			T151	1		T140	1		T141	1
auto[1342177280:1476395007]	auto[1]	7	1			T405	1		T386	1		T233	1
auto[1476395008:1610612735]	auto[1]	9	1			T256	2		T404	1		T349	1
auto[1610612736:1744830463]	auto[1]	7	1			T151	1		T95	1		T349	1
auto[1744830464:1879048191]	auto[1]	5	1			T95	1		T256	1		T408	1
auto[1879048192:2013265919]	auto[1]	9	1			T95	1		T256	1		T282	1
auto[2013265920:2147483647]	auto[1]	9	1			T5	1		T256	2		T233	1
auto[2147483648:2281701375]	auto[1]	3	1			T150	1		T407	1		T409	1
auto[2281701376:2415919103]	auto[1]	4	1			T287	1		T282	1		T410	1
auto[2415919104:2550136831]	auto[1]	10	1			T95	2		T97	1		T139	1
auto[2550136832:2684354559]	auto[1]	7	1			T5	1		T404	1		T302	1
auto[2684354560:2818572287]	auto[1]	13	1			T151	1		T95	3		T287	1
auto[2818572288:2952790015]	auto[1]	7	1			T5	1		T152	1		T139	1
auto[2952790016:3087007743]	auto[1]	8	1			T4	1		T151	1		T256	1
auto[3087007744:3221225471]	auto[1]	7	1			T95	1		T139	1		T142	1
auto[3221225472:3355443199]	auto[1]	6	1			T95	1		T141	1		T406	1
auto[3355443200:3489660927]	auto[1]	10	1			T151	1		T95	1		T141	3
auto[3489660928:3623878655]	auto[1]	10	1			T152	1		T232	1		T404	1
auto[3623878656:3758096383]	auto[1]	6	1			T4	1		T5	1		T151	1
auto[3758096384:3892314111]	auto[1]	7	1			T139	1		T302	2		T411	2
auto[3892314112:4026531839]	auto[1]	4	1			T141	1		T386	1		T412	1
auto[4026531840:4160749567]	auto[1]	7	1			T5	1		T151	2		T141	1
auto[4160749568:4294967295]	auto[1]	9	1			T151	2		T95	1		T287	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1539

1

T1

2

T4

4

T5

1

auto[1]

1725

1

T1

1

T4

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T209	1		T59	2		T53	1
auto[134217728:268435455]	98	1			T46	1		T50	1		T58	1
auto[268435456:402653183]	102	1			T113	1		T50	1		T65	1
auto[402653184:536870911]	90	1			T24	1		T45	2		T56	1
auto[536870912:671088639]	106	1			T46	2		T38	1		T150	1
auto[671088640:805306367]	104	1			T24	1		T59	3		T53	1
auto[805306368:939524095]	116	1			T45	1		T49	1		T46	1
auto[939524096:1073741823]	94	1			T80	1		T240	1		T234	2
auto[1073741824:1207959551]	110	1			T46	3		T113	2		T64	1
auto[1207959552:1342177279]	98	1			T5	1		T24	2		T46	1
auto[1342177280:1476395007]	108	1			T136	1		T46	1		T69	1
auto[1476395008:1610612735]	106	1			T4	1		T114	1		T205	1
auto[1610612736:1744830463]	119	1			T45	1		T46	1		T206	1
auto[1744830464:1879048191]	86	1			T17	1		T114	2		T51	1
auto[1879048192:2013265919]	102	1			T4	1		T68	1		T57	1
auto[2013265920:2147483647]	80	1			T1	2		T136	1		T117	1
auto[2147483648:2281701375]	122	1			T4	1		T19	1		T24	1
auto[2281701376:2415919103]	91	1			T4	1		T17	1		T24	1
auto[2415919104:2550136831]	97	1			T5	1		T19	1		T46	1
auto[2550136832:2684354559]	97	1			T5	1		T46	1		T113	1
auto[2684354560:2818572287]	105	1			T1	1		T5	1		T49	1
auto[2818572288:2952790015]	109	1			T17	1		T19	1		T206	1
auto[2952790016:3087007743]	112	1			T17	1		T46	1		T113	1
auto[3087007744:3221225471]	117	1			T17	1		T24	2		T46	2
auto[3221225472:3355443199]	106	1			T57	1		T114	1		T151	1
auto[3355443200:3489660927]	83	1			T4	1		T49	1		T113	1
auto[3489660928:3623878655]	111	1			T19	1		T136	1		T46	1
auto[3623878656:3758096383]	101	1			T17	1		T57	1		T151	1
auto[3758096384:3892314111]	105	1			T4	1		T24	1		T46	1
auto[3892314112:4026531839]	87	1			T206	1		T64	1		T151	1
auto[4026531840:4160749567]	93	1			T38	1		T114	2		T58	1
auto[4160749568:4294967295]	109	1			T17	1		T46	2		T206	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T53	1		T21	1		T256	1
auto[0:134217727]	auto[1]	44	1			T209	1		T59	2		T47	1
auto[134217728:268435455]	auto[0]	43	1			T46	1		T50	1		T151	1
auto[134217728:268435455]	auto[1]	55	1			T58	1		T377	1		T335	1
auto[268435456:402653183]	auto[0]	44	1			T50	1		T59	1		T39	1
auto[268435456:402653183]	auto[1]	58	1			T113	1		T65	1		T58	1
auto[402653184:536870911]	auto[0]	43	1			T24	1		T45	1		T68	1
auto[402653184:536870911]	auto[1]	47	1			T45	1		T56	1		T114	1
auto[536870912:671088639]	auto[0]	54	1			T46	1		T38	1		T117	1
auto[536870912:671088639]	auto[1]	52	1			T46	1		T150	1		T59	1
auto[671088640:805306367]	auto[0]	55	1			T24	1		T59	1		T53	1
auto[671088640:805306367]	auto[1]	49	1			T59	2		T97	1		T320	1
auto[805306368:939524095]	auto[0]	62	1			T49	1		T101	1		T48	1
auto[805306368:939524095]	auto[1]	54	1			T45	1		T46	1		T80	1
auto[939524096:1073741823]	auto[0]	41	1			T234	1		T271	1		T79	1
auto[939524096:1073741823]	auto[1]	53	1			T80	1		T240	1		T234	1
auto[1073741824:1207959551]	auto[0]	52	1			T46	1		T113	1		T64	1
auto[1073741824:1207959551]	auto[1]	58	1			T46	2		T113	1		T68	1
auto[1207959552:1342177279]	auto[0]	44	1			T24	2		T113	1		T114	1
auto[1207959552:1342177279]	auto[1]	54	1			T5	1		T46	1		T150	1
auto[1342177280:1476395007]	auto[0]	51	1			T69	1		T58	1		T59	2
auto[1342177280:1476395007]	auto[1]	57	1			T136	1		T46	1		T59	3
auto[1476395008:1610612735]	auto[0]	45	1			T4	1		T240	1		T336	1
auto[1476395008:1610612735]	auto[1]	61	1			T114	1		T205	1		T59	1
auto[1610612736:1744830463]	auto[0]	53	1			T45	1		T59	2		T265	1
auto[1610612736:1744830463]	auto[1]	66	1			T46	1		T206	1		T64	1
auto[1744830464:1879048191]	auto[0]	43	1			T114	1		T51	1		T60	1
auto[1744830464:1879048191]	auto[1]	43	1			T17	1		T114	1		T265	1
auto[1879048192:2013265919]	auto[0]	55	1			T51	1		T59	1		T91	1
auto[1879048192:2013265919]	auto[1]	47	1			T4	1		T68	1		T57	1
auto[2013265920:2147483647]	auto[0]	33	1			T1	1		T59	2		T271	1
auto[2013265920:2147483647]	auto[1]	47	1			T1	1		T136	1		T117	1
auto[2147483648:2281701375]	auto[0]	44	1			T4	1		T19	1		T136	1
auto[2147483648:2281701375]	auto[1]	78	1			T24	1		T113	1		T205	1
auto[2281701376:2415919103]	auto[0]	33	1			T24	1		T46	1		T59	2
auto[2281701376:2415919103]	auto[1]	58	1			T4	1		T17	1		T69	1
auto[2415919104:2550136831]	auto[0]	51	1			T5	1		T56	1		T58	1
auto[2415919104:2550136831]	auto[1]	46	1			T19	1		T46	1		T51	1
auto[2550136832:2684354559]	auto[0]	56	1			T46	1		T113	1		T68	1
auto[2550136832:2684354559]	auto[1]	41	1			T5	1		T63	1		T413	1
auto[2684354560:2818572287]	auto[0]	36	1			T1	1		T118	1		T59	3
auto[2684354560:2818572287]	auto[1]	69	1			T5	1		T49	1		T46	1
auto[2818572288:2952790015]	auto[0]	63	1			T17	1		T117	1		T52	1
auto[2818572288:2952790015]	auto[1]	46	1			T19	1		T206	1		T50	1
auto[2952790016:3087007743]	auto[0]	56	1			T46	1		T113	1		T151	1
auto[2952790016:3087007743]	auto[1]	56	1			T17	1		T64	1		T114	1
auto[3087007744:3221225471]	auto[0]	52	1			T24	1		T46	1		T51	1
auto[3087007744:3221225471]	auto[1]	65	1			T17	1		T24	1		T46	1
auto[3221225472:3355443199]	auto[0]	52	1			T151	1		T59	1		T265	1
auto[3221225472:3355443199]	auto[1]	54	1			T57	1		T114	1		T240	1
auto[3355443200:3489660927]	auto[0]	42	1			T4	1		T150	1		T50	1
auto[3355443200:3489660927]	auto[1]	41	1			T49	1		T113	1		T81	1
auto[3489660928:3623878655]	auto[0]	58	1			T56	1		T64	1		T59	3
auto[3489660928:3623878655]	auto[1]	53	1			T19	1		T136	1		T46	1
auto[3623878656:3758096383]	auto[0]	38	1			T17	1		T151	1		T72	1
auto[3623878656:3758096383]	auto[1]	63	1			T57	1		T240	1		T59	1
auto[3758096384:3892314111]	auto[0]	50	1			T4	1		T24	1		T68	1
auto[3758096384:3892314111]	auto[1]	55	1			T46	1		T150	1		T57	1
auto[3892314112:4026531839]	auto[0]	43	1			T59	1		T265	2		T260	1
auto[3892314112:4026531839]	auto[1]	44	1			T206	1		T64	1		T151	1
auto[4026531840:4160749567]	auto[0]	41	1			T114	2		T58	1		T59	2
auto[4026531840:4160749567]	auto[1]	52	1			T38	1		T152	1		T39	1
auto[4160749568:4294967295]	auto[0]	50	1			T46	1		T206	1		T114	1
auto[4160749568:4294967295]	auto[1]	59	1			T17	1		T46	1		T206	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1516

1

T1

2

T4

3

T5

2

auto[1]

1748

1

T1

1

T4

3

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T4	1		T113	1		T114	1
auto[134217728:268435455]	104	1			T5	1		T46	1		T113	2
auto[268435456:402653183]	111	1			T5	1		T19	1		T46	1
auto[402653184:536870911]	101	1			T136	1		T114	1		T65	1
auto[536870912:671088639]	109	1			T1	1		T45	1		T46	1
auto[671088640:805306367]	109	1			T46	3		T68	1		T114	1
auto[805306368:939524095]	92	1			T24	1		T46	1		T64	1
auto[939524096:1073741823]	100	1			T17	1		T68	1		T262	1
auto[1073741824:1207959551]	85	1			T45	1		T150	1		T58	1
auto[1207959552:1342177279]	90	1			T24	1		T46	1		T206	1
auto[1342177280:1476395007]	102	1			T24	1		T206	1		T68	1
auto[1476395008:1610612735]	82	1			T4	1		T17	1		T24	1
auto[1610612736:1744830463]	118	1			T1	1		T136	1		T46	2
auto[1744830464:1879048191]	97	1			T46	1		T113	1		T64	1
auto[1879048192:2013265919]	104	1			T24	1		T49	1		T46	1
auto[2013265920:2147483647]	95	1			T136	1		T45	1		T49	1
auto[2147483648:2281701375]	110	1			T19	1		T46	1		T150	1
auto[2281701376:2415919103]	80	1			T17	1		T113	1		T58	1
auto[2415919104:2550136831]	117	1			T5	1		T113	1		T68	2
auto[2550136832:2684354559]	92	1			T57	1		T262	1		T240	1
auto[2684354560:2818572287]	93	1			T17	1		T45	1		T46	2
auto[2818572288:2952790015]	86	1			T136	1		T46	1		T64	1
auto[2952790016:3087007743]	104	1			T4	1		T24	1		T151	1
auto[3087007744:3221225471]	98	1			T4	1		T17	1		T24	1
auto[3221225472:3355443199]	105	1			T45	1		T46	2		T206	1
auto[3355443200:3489660927]	120	1			T4	2		T5	1		T19	1
auto[3489660928:3623878655]	95	1			T49	1		T113	1		T38	1
auto[3623878656:3758096383]	119	1			T17	2		T19	1		T114	1
auto[3758096384:3892314111]	99	1			T113	1		T114	2		T118	1
auto[3892314112:4026531839]	109	1			T56	1		T114	1		T118	1
auto[4026531840:4160749567]	115	1			T24	1		T46	1		T38	1
auto[4160749568:4294967295]	112	1			T1	1		T24	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T4	1		T113	1		T114	1
auto[0:134217727]	auto[1]	52	1			T151	1		T240	1		T59	1
auto[134217728:268435455]	auto[0]	44	1			T5	1		T59	1		T52	2
auto[134217728:268435455]	auto[1]	60	1			T46	1		T113	2		T50	1
auto[268435456:402653183]	auto[0]	51	1			T59	1		T265	1		T152	1
auto[268435456:402653183]	auto[1]	60	1			T5	1		T19	1		T46	1
auto[402653184:536870911]	auto[0]	47	1			T136	1		T240	1		T59	1
auto[402653184:536870911]	auto[1]	54	1			T114	1		T65	1		T80	1
auto[536870912:671088639]	auto[0]	50	1			T1	1		T45	1		T114	1
auto[536870912:671088639]	auto[1]	59	1			T46	1		T69	1		T117	1
auto[671088640:805306367]	auto[0]	49	1			T46	1		T68	1		T205	1
auto[671088640:805306367]	auto[1]	60	1			T46	2		T114	1		T209	1
auto[805306368:939524095]	auto[0]	44	1			T51	1		T59	2		T21	1
auto[805306368:939524095]	auto[1]	48	1			T24	1		T46	1		T64	1
auto[939524096:1073741823]	auto[0]	40	1			T17	1		T414	1		T97	1
auto[939524096:1073741823]	auto[1]	60	1			T68	1		T262	1		T59	1
auto[1073741824:1207959551]	auto[0]	35	1			T150	1		T352	1		T48	1
auto[1073741824:1207959551]	auto[1]	50	1			T45	1		T58	1		T59	1
auto[1207959552:1342177279]	auto[0]	37	1			T24	1		T114	1		T58	1
auto[1207959552:1342177279]	auto[1]	53	1			T46	1		T206	1		T59	1
auto[1342177280:1476395007]	auto[0]	37	1			T24	1		T68	1		T59	1
auto[1342177280:1476395007]	auto[1]	65	1			T206	1		T205	1		T117	1
auto[1476395008:1610612735]	auto[0]	41	1			T24	1		T56	1		T80	1
auto[1476395008:1610612735]	auto[1]	41	1			T4	1		T17	1		T150	1
auto[1610612736:1744830463]	auto[0]	53	1			T46	1		T151	1		T59	1
auto[1610612736:1744830463]	auto[1]	65	1			T1	1		T136	1		T46	1
auto[1744830464:1879048191]	auto[0]	45	1			T46	1		T113	1		T64	1
auto[1744830464:1879048191]	auto[1]	52	1			T80	1		T240	1		T59	1
auto[1879048192:2013265919]	auto[0]	51	1			T24	1		T46	1		T50	1
auto[1879048192:2013265919]	auto[1]	53	1			T49	1		T64	2		T59	1
auto[2013265920:2147483647]	auto[0]	47	1			T136	1		T45	1		T56	1
auto[2013265920:2147483647]	auto[1]	48	1			T49	1		T336	1		T34	1
auto[2147483648:2281701375]	auto[0]	57	1			T46	1		T59	2		T53	1
auto[2147483648:2281701375]	auto[1]	53	1			T19	1		T150	1		T65	1
auto[2281701376:2415919103]	auto[0]	25	1			T17	1		T58	1		T59	2
auto[2281701376:2415919103]	auto[1]	55	1			T113	1		T47	2		T71	1
auto[2415919104:2550136831]	auto[0]	56	1			T113	1		T68	2		T151	1
auto[2415919104:2550136831]	auto[1]	61	1			T5	1		T69	1		T151	1
auto[2550136832:2684354559]	auto[0]	39	1			T262	1		T240	1		T141	1
auto[2550136832:2684354559]	auto[1]	53	1			T57	1		T59	1		T97	1
auto[2684354560:2818572287]	auto[0]	45	1			T45	1		T69	1		T97	1
auto[2684354560:2818572287]	auto[1]	48	1			T17	1		T46	2		T114	1
auto[2818572288:2952790015]	auto[0]	44	1			T46	1		T51	1		T59	2
auto[2818572288:2952790015]	auto[1]	42	1			T136	1		T64	1		T150	1
auto[2952790016:3087007743]	auto[0]	48	1			T24	1		T59	1		T25	1
auto[2952790016:3087007743]	auto[1]	56	1			T4	1		T151	1		T59	2
auto[3087007744:3221225471]	auto[0]	43	1			T4	1		T17	1		T59	3
auto[3087007744:3221225471]	auto[1]	55	1			T24	1		T58	1		T81	1
auto[3221225472:3355443199]	auto[0]	57	1			T46	1		T262	1		T59	1
auto[3221225472:3355443199]	auto[1]	48	1			T45	1		T46	1		T206	1
auto[3355443200:3489660927]	auto[0]	63	1			T4	1		T5	1		T19	1
auto[3355443200:3489660927]	auto[1]	57	1			T4	1		T46	1		T120	1
auto[3489660928:3623878655]	auto[0]	52	1			T49	1		T113	1		T151	1
auto[3489660928:3623878655]	auto[1]	43	1			T38	1		T59	2		T21	1
auto[3623878656:3758096383]	auto[0]	49	1			T17	1		T51	1		T59	2
auto[3623878656:3758096383]	auto[1]	70	1			T17	1		T19	1		T114	1
auto[3758096384:3892314111]	auto[0]	46	1			T113	1		T114	2		T118	1
auto[3758096384:3892314111]	auto[1]	53	1			T30	1		T39	1		T47	1
auto[3892314112:4026531839]	auto[0]	54	1			T151	1		T59	2		T139	1
auto[3892314112:4026531839]	auto[1]	55	1			T56	1		T114	1		T118	1
auto[4026531840:4160749567]	auto[0]	51	1			T46	1		T58	1		T265	1
auto[4026531840:4160749567]	auto[1]	64	1			T24	1		T38	1		T57	1
auto[4160749568:4294967295]	auto[0]	57	1			T1	1		T24	1		T51	1
auto[4160749568:4294967295]	auto[1]	55	1			T117	1		T209	1		T59	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1528

1

T1

1

T4

3

T5

1

auto[1]

1736

1

T1

2

T4

3

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	82	1			T240	1		T59	2		T52	1
auto[134217728:268435455]	99	1			T114	1		T209	1		T240	1
auto[268435456:402653183]	115	1			T136	1		T206	1		T68	1
auto[402653184:536870911]	98	1			T46	2		T206	1		T205	1
auto[536870912:671088639]	102	1			T1	1		T17	1		T45	1
auto[671088640:805306367]	116	1			T4	1		T136	1		T56	1
auto[805306368:939524095]	115	1			T19	1		T24	1		T49	1
auto[939524096:1073741823]	93	1			T4	1		T24	1		T46	2
auto[1073741824:1207959551]	98	1			T46	1		T56	1		T262	1
auto[1207959552:1342177279]	110	1			T17	2		T19	1		T24	1
auto[1342177280:1476395007]	94	1			T4	1		T19	1		T68	1
auto[1476395008:1610612735]	110	1			T17	1		T24	1		T45	2
auto[1610612736:1744830463]	82	1			T5	1		T113	1		T70	1
auto[1744830464:1879048191]	106	1			T46	2		T206	1		T38	1
auto[1879048192:2013265919]	91	1			T46	1		T38	1		T150	1
auto[2013265920:2147483647]	108	1			T5	1		T49	1		T114	1
auto[2147483648:2281701375]	107	1			T4	1		T5	1		T45	2
auto[2281701376:2415919103]	92	1			T19	1		T64	1		T150	1
auto[2415919104:2550136831]	103	1			T46	1		T50	1		T114	1
auto[2550136832:2684354559]	124	1			T4	1		T24	1		T136	1
auto[2684354560:2818572287]	104	1			T17	1		T113	1		T151	1
auto[2818572288:2952790015]	97	1			T17	1		T46	3		T206	1
auto[2952790016:3087007743]	83	1			T24	1		T46	2		T206	1
auto[3087007744:3221225471]	121	1			T24	1		T49	1		T46	2
auto[3221225472:3355443199]	105	1			T5	1		T24	1		T113	1
auto[3355443200:3489660927]	110	1			T1	1		T113	3		T114	1
auto[3489660928:3623878655]	84	1			T136	1		T151	1		T59	1
auto[3623878656:3758096383]	106	1			T1	1		T46	2		T64	1
auto[3758096384:3892314111]	103	1			T4	1		T17	1		T64	1
auto[3892314112:4026531839]	99	1			T57	1		T114	1		T205	1
auto[4026531840:4160749567]	100	1			T56	1		T68	1		T114	1
auto[4160749568:4294967295]	107	1			T24	1		T209	1		T59	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T240	1		T52	1		T28	1
auto[0:134217727]	auto[1]	38	1			T59	2		T71	1		T63	1
auto[134217728:268435455]	auto[0]	48	1			T59	1		T53	1		T272	1
auto[134217728:268435455]	auto[1]	51	1			T114	1		T209	1		T240	1
auto[268435456:402653183]	auto[0]	57	1			T136	1		T117	1		T59	1
auto[268435456:402653183]	auto[1]	58	1			T206	1		T68	1		T140	1
auto[402653184:536870911]	auto[0]	47	1			T206	1		T205	1		T73	1
auto[402653184:536870911]	auto[1]	51	1			T46	2		T151	1		T59	2
auto[536870912:671088639]	auto[0]	56	1			T45	1		T113	1		T240	1
auto[536870912:671088639]	auto[1]	46	1			T1	1		T17	1		T68	1
auto[671088640:805306367]	auto[0]	44	1			T4	1		T56	1		T64	1
auto[671088640:805306367]	auto[1]	72	1			T136	1		T57	1		T69	1
auto[805306368:939524095]	auto[0]	63	1			T46	2		T50	1		T25	1
auto[805306368:939524095]	auto[1]	52	1			T19	1		T24	1		T49	1
auto[939524096:1073741823]	auto[0]	49	1			T4	1		T24	1		T262	1
auto[939524096:1073741823]	auto[1]	44	1			T46	2		T266	1		T71	1
auto[1073741824:1207959551]	auto[0]	49	1			T56	1		T265	2		T414	1
auto[1073741824:1207959551]	auto[1]	49	1			T46	1		T262	1		T59	1
auto[1207959552:1342177279]	auto[0]	49	1			T17	2		T24	1		T58	1
auto[1207959552:1342177279]	auto[1]	61	1			T19	1		T64	1		T65	1
auto[1342177280:1476395007]	auto[0]	44	1			T19	1		T68	1		T65	1
auto[1342177280:1476395007]	auto[1]	50	1			T4	1		T50	1		T117	1
auto[1476395008:1610612735]	auto[0]	45	1			T24	1		T46	1		T113	1
auto[1476395008:1610612735]	auto[1]	65	1			T17	1		T45	2		T80	1
auto[1610612736:1744830463]	auto[0]	44	1			T113	1		T151	1		T59	3
auto[1610612736:1744830463]	auto[1]	38	1			T5	1		T70	1		T47	1
auto[1744830464:1879048191]	auto[0]	51	1			T46	2		T38	1		T114	1
auto[1744830464:1879048191]	auto[1]	55	1			T206	1		T114	1		T117	1
auto[1879048192:2013265919]	auto[0]	43	1			T271	1		T243	1		T287	1
auto[1879048192:2013265919]	auto[1]	48	1			T46	1		T38	1		T150	1
auto[2013265920:2147483647]	auto[0]	45	1			T49	1		T114	1		T52	1
auto[2013265920:2147483647]	auto[1]	63	1			T5	1		T80	1		T117	1
auto[2147483648:2281701375]	auto[0]	57	1			T45	1		T58	1		T205	1
auto[2147483648:2281701375]	auto[1]	50	1			T4	1		T5	1		T45	1
auto[2281701376:2415919103]	auto[0]	45	1			T64	1		T150	1		T68	1
auto[2281701376:2415919103]	auto[1]	47	1			T19	1		T51	1		T270	1
auto[2415919104:2550136831]	auto[0]	43	1			T50	1		T114	1		T415	1
auto[2415919104:2550136831]	auto[1]	60	1			T46	1		T234	1		T47	1
auto[2550136832:2684354559]	auto[0]	58	1			T4	1		T24	1		T118	1
auto[2550136832:2684354559]	auto[1]	66	1			T136	1		T50	1		T114	1
auto[2684354560:2818572287]	auto[0]	59	1			T59	1		T53	1		T60	1
auto[2684354560:2818572287]	auto[1]	45	1			T17	1		T113	1		T151	1
auto[2818572288:2952790015]	auto[0]	48	1			T46	1		T51	1		T117	1
auto[2818572288:2952790015]	auto[1]	49	1			T17	1		T46	2		T206	1
auto[2952790016:3087007743]	auto[0]	40	1			T24	1		T46	2		T51	1
auto[2952790016:3087007743]	auto[1]	43	1			T206	1		T118	1		T25	1
auto[3087007744:3221225471]	auto[0]	50	1			T24	1		T59	2		T53	1
auto[3087007744:3221225471]	auto[1]	71	1			T49	1		T46	2		T150	1
auto[3221225472:3355443199]	auto[0]	40	1			T5	1		T113	1		T51	1
auto[3221225472:3355443199]	auto[1]	65	1			T24	1		T240	1		T59	4
auto[3355443200:3489660927]	auto[0]	53	1			T1	1		T113	1		T114	1
auto[3355443200:3489660927]	auto[1]	57	1			T113	2		T59	1		T266	1
auto[3489660928:3623878655]	auto[0]	48	1			T136	1		T151	1		T59	1
auto[3489660928:3623878655]	auto[1]	36	1			T71	1		T246	1		T75	1
auto[3623878656:3758096383]	auto[0]	45	1			T46	2		T58	1		T71	1
auto[3623878656:3758096383]	auto[1]	61	1			T1	1		T64	1		T120	1
auto[3758096384:3892314111]	auto[0]	39	1			T17	1		T150	1		T59	1
auto[3758096384:3892314111]	auto[1]	64	1			T4	1		T64	1		T69	1
auto[3892314112:4026531839]	auto[0]	35	1			T114	1		T91	1		T270	1
auto[3892314112:4026531839]	auto[1]	64	1			T57	1		T205	1		T59	2
auto[4026531840:4160749567]	auto[0]	50	1			T68	1		T114	1		T59	1
auto[4026531840:4160749567]	auto[1]	50	1			T56	1		T51	1		T58	1
auto[4160749568:4294967295]	auto[0]	40	1			T59	1		T102	1		T95	1
auto[4160749568:4294967295]	auto[1]	67	1			T24	1		T209	1		T59	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1541

1

T4

2

T5

1

T17

3

auto[1]

1722

1

T1

3

T4

4

T5

3