Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2908

1

T1

3

T4

6

T5

4

auto[1]

264

1

T4

8

T5

9

T150

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T136	1		T118	1		T152	1
auto[134217728:268435455]	101	1			T45	1		T49	1		T117	1
auto[268435456:402653183]	102	1			T4	1		T24	1		T206	1
auto[402653184:536870911]	93	1			T5	1		T46	2		T150	1
auto[536870912:671088639]	89	1			T49	1		T205	1		T117	1
auto[671088640:805306367]	103	1			T17	1		T50	1		T51	1
auto[805306368:939524095]	107	1			T19	1		T113	1		T150	1
auto[939524096:1073741823]	99	1			T4	1		T45	1		T151	1
auto[1073741824:1207959551]	101	1			T5	1		T64	1		T117	1
auto[1207959552:1342177279]	94	1			T4	1		T24	1		T57	1
auto[1342177280:1476395007]	94	1			T4	1		T17	1		T114	1
auto[1476395008:1610612735]	84	1			T5	1		T136	1		T45	1
auto[1610612736:1744830463]	103	1			T4	1		T19	1		T46	1
auto[1744830464:1879048191]	102	1			T4	1		T17	1		T136	1
auto[1879048192:2013265919]	90	1			T5	1		T24	1		T46	1
auto[2013265920:2147483647]	92	1			T5	1		T46	1		T65	1
auto[2147483648:2281701375]	107	1			T5	1		T206	1		T150	1
auto[2281701376:2415919103]	88	1			T5	1		T17	1		T46	1
auto[2415919104:2550136831]	105	1			T1	1		T17	1		T46	1
auto[2550136832:2684354559]	92	1			T1	1		T5	2		T206	1
auto[2684354560:2818572287]	114	1			T1	1		T4	1		T24	1
auto[2818572288:2952790015]	99	1			T17	1		T24	2		T38	1
auto[2952790016:3087007743]	91	1			T5	2		T24	1		T46	2
auto[3087007744:3221225471]	109	1			T4	2		T24	1		T151	1
auto[3221225472:3355443199]	121	1			T136	1		T45	1		T46	3
auto[3355443200:3489660927]	117	1			T4	1		T5	1		T19	1
auto[3489660928:3623878655]	100	1			T19	1		T206	1		T57	1
auto[3623878656:3758096383]	83	1			T51	1		T95	1		T256	1
auto[3758096384:3892314111]	113	1			T4	2		T5	1		T113	1
auto[3892314112:4026531839]	95	1			T17	1		T50	1		T65	1
auto[4026531840:4160749567]	92	1			T4	2		T45	1		T46	1
auto[4160749568:4294967295]	99	1			T46	1		T113	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	82	1			T136	1		T118	1		T352	1
auto[0:134217727]	auto[1]	11	1			T152	1		T139	2		T232	1
auto[134217728:268435455]	auto[0]	92	1			T45	1		T49	1		T117	1
auto[134217728:268435455]	auto[1]	9	1			T152	1		T95	2		T287	1
auto[268435456:402653183]	auto[0]	97	1			T4	1		T24	1		T206	1
auto[268435456:402653183]	auto[1]	5	1			T410	1		T422	1		T427	2
auto[402653184:536870911]	auto[0]	75	1			T5	1		T46	2		T150	1
auto[402653184:536870911]	auto[1]	18	1			T151	1		T95	1		T287	1
auto[536870912:671088639]	auto[0]	80	1			T49	1		T205	1		T117	1
auto[536870912:671088639]	auto[1]	9	1			T95	1		T404	1		T233	1
auto[671088640:805306367]	auto[0]	94	1			T17	1		T50	1		T51	1
auto[671088640:805306367]	auto[1]	9	1			T282	1		T407	1		T422	1
auto[805306368:939524095]	auto[0]	100	1			T19	1		T113	1		T150	1
auto[805306368:939524095]	auto[1]	7	1			T140	1		T141	1		T405	1
auto[939524096:1073741823]	auto[0]	94	1			T4	1		T45	1		T209	1
auto[939524096:1073741823]	auto[1]	5	1			T151	1		T410	1		T408	1
auto[1073741824:1207959551]	auto[0]	97	1			T64	1		T117	1		T262	1
auto[1073741824:1207959551]	auto[1]	4	1			T5	1		T404	1		T359	1
auto[1207959552:1342177279]	auto[0]	84	1			T24	1		T57	1		T59	2
auto[1207959552:1342177279]	auto[1]	10	1			T4	1		T95	1		T139	1
auto[1342177280:1476395007]	auto[0]	84	1			T17	1		T114	1		T69	1
auto[1342177280:1476395007]	auto[1]	10	1			T4	1		T95	1		T139	1
auto[1476395008:1610612735]	auto[0]	77	1			T5	1		T136	1		T45	1
auto[1476395008:1610612735]	auto[1]	7	1			T151	1		T328	2		T410	1
auto[1610612736:1744830463]	auto[0]	93	1			T19	1		T46	1		T113	1
auto[1610612736:1744830463]	auto[1]	10	1			T4	1		T256	1		T141	2
auto[1744830464:1879048191]	auto[0]	95	1			T4	1		T17	1		T136	1
auto[1744830464:1879048191]	auto[1]	7	1			T359	1		T334	1		T420	2
auto[1879048192:2013265919]	auto[0]	83	1			T5	1		T24	1		T46	1
auto[1879048192:2013265919]	auto[1]	7	1			T404	1		T386	1		T407	1
auto[2013265920:2147483647]	auto[0]	88	1			T46	1		T65	1		T151	1
auto[2013265920:2147483647]	auto[1]	4	1			T5	1		T352	1		T328	1
auto[2147483648:2281701375]	auto[0]	98	1			T206	1		T58	2		T70	1
auto[2147483648:2281701375]	auto[1]	9	1			T5	1		T150	1		T95	1
auto[2281701376:2415919103]	auto[0]	76	1			T17	1		T46	1		T113	1
auto[2281701376:2415919103]	auto[1]	12	1			T5	1		T139	1		T141	1
auto[2415919104:2550136831]	auto[0]	99	1			T1	1		T17	1		T46	1
auto[2415919104:2550136831]	auto[1]	6	1			T287	1		T245	1		T405	1
auto[2550136832:2684354559]	auto[0]	85	1			T1	1		T206	1		T113	1
auto[2550136832:2684354559]	auto[1]	7	1			T5	2		T141	1		T282	1
auto[2684354560:2818572287]	auto[0]	104	1			T1	1		T4	1		T24	1
auto[2684354560:2818572287]	auto[1]	10	1			T95	1		T287	1		T232	1
auto[2818572288:2952790015]	auto[0]	95	1			T17	1		T24	2		T38	1
auto[2818572288:2952790015]	auto[1]	4	1			T232	1		T407	1		T411	2
auto[2952790016:3087007743]	auto[0]	82	1			T5	1		T24	1		T46	2
auto[2952790016:3087007743]	auto[1]	9	1			T5	1		T151	1		T152	1
auto[3087007744:3221225471]	auto[0]	96	1			T24	1		T240	1		T59	1
auto[3087007744:3221225471]	auto[1]	13	1			T4	2		T151	1		T152	2
auto[3221225472:3355443199]	auto[0]	114	1			T136	1		T45	1		T46	3
auto[3221225472:3355443199]	auto[1]	7	1			T150	1		T97	1		T302	1
auto[3355443200:3489660927]	auto[0]	109	1			T19	1		T24	1		T46	2
auto[3355443200:3489660927]	auto[1]	8	1			T4	1		T5	1		T151	1
auto[3489660928:3623878655]	auto[0]	93	1			T19	1		T206	1		T57	1
auto[3489660928:3623878655]	auto[1]	7	1			T139	1		T141	1		T419	1
auto[3623878656:3758096383]	auto[0]	79	1			T51	1		T256	1		T415	1
auto[3623878656:3758096383]	auto[1]	4	1			T95	1		T287	1		T359	1
auto[3758096384:3892314111]	auto[0]	103	1			T4	1		T113	1		T64	1
auto[3758096384:3892314111]	auto[1]	10	1			T4	1		T5	1		T152	2
auto[3892314112:4026531839]	auto[0]	87	1			T17	1		T50	1		T65	1
auto[3892314112:4026531839]	auto[1]	8	1			T139	1		T352	1		T404	1
auto[4026531840:4160749567]	auto[0]	84	1			T4	1		T45	1		T46	1
auto[4026531840:4160749567]	auto[1]	8	1			T4	1		T152	1		T95	1
auto[4160749568:4294967295]	auto[0]	89	1			T46	1		T113	1		T50	1
auto[4160749568:4294967295]	auto[1]	10	1			T151	1		T95	1		T139	1