Unified Coverage Report :: Group Instance : sealing_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1542

1

T4

3

T5

1

T17

3

auto[1]

1722

1

T1

3

T4

3

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T113	1		T114	1		T117	1
auto[134217728:268435455]	114	1			T1	1		T46	1		T113	1
auto[268435456:402653183]	102	1			T46	1		T206	1		T69	1
auto[402653184:536870911]	101	1			T17	1		T24	2		T38	1
auto[536870912:671088639]	96	1			T4	1		T19	1		T46	1
auto[671088640:805306367]	87	1			T4	1		T24	1		T240	1
auto[805306368:939524095]	102	1			T1	1		T45	1		T206	1
auto[939524096:1073741823]	109	1			T1	1		T19	1		T46	1
auto[1073741824:1207959551]	105	1			T19	1		T64	1		T68	1
auto[1207959552:1342177279]	107	1			T45	1		T49	1		T46	1
auto[1342177280:1476395007]	101	1			T5	1		T17	1		T136	1
auto[1476395008:1610612735]	102	1			T46	1		T68	1		T114	1
auto[1610612736:1744830463]	87	1			T4	1		T17	1		T46	1
auto[1744830464:1879048191]	92	1			T56	1		T64	1		T59	1
auto[1879048192:2013265919]	111	1			T57	1		T117	1		T59	4
auto[2013265920:2147483647]	105	1			T5	1		T24	3		T136	1
auto[2147483648:2281701375]	101	1			T17	1		T51	1		T240	1
auto[2281701376:2415919103]	91	1			T17	1		T46	2		T150	1
auto[2415919104:2550136831]	95	1			T19	1		T206	1		T68	1
auto[2550136832:2684354559]	99	1			T46	2		T206	1		T59	2
auto[2684354560:2818572287]	99	1			T24	1		T57	1		T51	1
auto[2818572288:2952790015]	102	1			T24	1		T113	1		T57	1
auto[2952790016:3087007743]	125	1			T45	1		T113	1		T114	1
auto[3087007744:3221225471]	86	1			T5	1		T17	2		T46	1
auto[3221225472:3355443199]	109	1			T46	1		T113	1		T38	1
auto[3355443200:3489660927]	97	1			T4	1		T46	1		T206	1
auto[3489660928:3623878655]	94	1			T150	1		T114	1		T205	1
auto[3623878656:3758096383]	114	1			T4	2		T136	1		T46	2
auto[3758096384:3892314111]	104	1			T5	1		T46	2		T113	2
auto[3892314112:4026531839]	122	1			T45	1		T46	1		T64	1
auto[4026531840:4160749567]	112	1			T136	1		T45	1		T56	1
auto[4160749568:4294967295]	107	1			T24	1		T265	1		T152	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T151	1		T265	1		T97	1
auto[0:134217727]	auto[1]	47	1			T113	1		T114	1		T117	1
auto[134217728:268435455]	auto[0]	61	1			T56	1		T68	1		T52	1
auto[134217728:268435455]	auto[1]	53	1			T1	1		T46	1		T113	1
auto[268435456:402653183]	auto[0]	51	1			T51	1		T25	1		T47	2
auto[268435456:402653183]	auto[1]	51	1			T46	1		T206	1		T69	1
auto[402653184:536870911]	auto[0]	41	1			T17	1		T24	1		T117	1
auto[402653184:536870911]	auto[1]	60	1			T24	1		T38	1		T69	1
auto[536870912:671088639]	auto[0]	49	1			T4	1		T46	1		T59	2
auto[536870912:671088639]	auto[1]	47	1			T19	1		T50	1		T57	1
auto[671088640:805306367]	auto[0]	33	1			T240	1		T59	1		T234	1
auto[671088640:805306367]	auto[1]	54	1			T4	1		T24	1		T59	1
auto[805306368:939524095]	auto[0]	44	1			T45	1		T113	1		T205	1
auto[805306368:939524095]	auto[1]	58	1			T1	1		T206	1		T114	1
auto[939524096:1073741823]	auto[0]	54	1			T150	1		T114	1		T59	1
auto[939524096:1073741823]	auto[1]	55	1			T1	1		T19	1		T46	1
auto[1073741824:1207959551]	auto[0]	44	1			T19	1		T68	1		T59	2
auto[1073741824:1207959551]	auto[1]	61	1			T64	1		T50	1		T151	1
auto[1207959552:1342177279]	auto[0]	51	1			T45	1		T49	1		T151	1
auto[1207959552:1342177279]	auto[1]	56	1			T46	1		T240	1		T59	1
auto[1342177280:1476395007]	auto[0]	54	1			T64	1		T51	1		T59	2
auto[1342177280:1476395007]	auto[1]	47	1			T5	1		T17	1		T136	1
auto[1476395008:1610612735]	auto[0]	50	1			T46	1		T51	1		T58	1
auto[1476395008:1610612735]	auto[1]	52	1			T68	1		T114	1		T209	1
auto[1610612736:1744830463]	auto[0]	37	1			T17	1		T46	1		T140	1
auto[1610612736:1744830463]	auto[1]	50	1			T4	1		T58	1		T59	1
auto[1744830464:1879048191]	auto[0]	49	1			T56	1		T64	1		T265	1
auto[1744830464:1879048191]	auto[1]	43	1			T59	1		T39	1		T243	1
auto[1879048192:2013265919]	auto[0]	56	1			T117	1		T59	2		T21	1
auto[1879048192:2013265919]	auto[1]	55	1			T57	1		T59	2		T266	1
auto[2013265920:2147483647]	auto[0]	59	1			T5	1		T24	2		T136	1
auto[2013265920:2147483647]	auto[1]	46	1			T24	1		T49	1		T46	1
auto[2147483648:2281701375]	auto[0]	50	1			T17	1		T51	1		T59	1
auto[2147483648:2281701375]	auto[1]	51	1			T240	1		T59	2		T414	1
auto[2281701376:2415919103]	auto[0]	39	1			T150	1		T65	1		T71	1
auto[2281701376:2415919103]	auto[1]	52	1			T17	1		T46	2		T59	1
auto[2415919104:2550136831]	auto[0]	47	1			T68	1		T265	1		T256	1
auto[2415919104:2550136831]	auto[1]	48	1			T19	1		T206	1		T73	1
auto[2550136832:2684354559]	auto[0]	48	1			T59	1		T52	2		T101	1
auto[2550136832:2684354559]	auto[1]	51	1			T46	2		T206	1		T59	1
auto[2684354560:2818572287]	auto[0]	47	1			T24	1		T51	1		T59	2
auto[2684354560:2818572287]	auto[1]	52	1			T57	1		T117	2		T59	1
auto[2818572288:2952790015]	auto[0]	48	1			T24	1		T114	1		T52	1
auto[2818572288:2952790015]	auto[1]	54	1			T113	1		T57	1		T114	1
auto[2952790016:3087007743]	auto[0]	63	1			T113	1		T114	1		T59	3
auto[2952790016:3087007743]	auto[1]	62	1			T45	1		T59	1		T266	1
auto[3087007744:3221225471]	auto[0]	31	1			T59	2		T25	1		T140	1
auto[3087007744:3221225471]	auto[1]	55	1			T5	1		T17	2		T46	1
auto[3221225472:3355443199]	auto[0]	41	1			T46	1		T113	1		T114	1
auto[3221225472:3355443199]	auto[1]	68	1			T38	1		T59	1		T139	1
auto[3355443200:3489660927]	auto[0]	46	1			T59	2		T39	1		T47	2
auto[3355443200:3489660927]	auto[1]	51	1			T4	1		T46	1		T206	1
auto[3489660928:3623878655]	auto[0]	46	1			T114	1		T262	1		T240	1
auto[3489660928:3623878655]	auto[1]	48	1			T150	1		T205	1		T59	1
auto[3623878656:3758096383]	auto[0]	62	1			T4	2		T136	1		T46	2
auto[3623878656:3758096383]	auto[1]	52	1			T59	1		T53	1		T266	1
auto[3758096384:3892314111]	auto[0]	47	1			T46	2		T113	1		T50	1
auto[3758096384:3892314111]	auto[1]	57	1			T5	1		T113	1		T59	2
auto[3892314112:4026531839]	auto[0]	49	1			T45	1		T46	1		T68	1
auto[3892314112:4026531839]	auto[1]	73	1			T64	1		T80	1		T151	1
auto[4026531840:4160749567]	auto[0]	54	1			T45	1		T114	1		T58	1
auto[4026531840:4160749567]	auto[1]	58	1			T136	1		T56	1		T69	1
auto[4160749568:4294967295]	auto[0]	52	1			T24	1		T265	1		T21	1
auto[4160749568:4294967295]	auto[1]	55	1			T152	1		T352	1		T71	2