Unified Coverage Report :: Group Instance : attest_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1515

1

T1

1

T4

4

T5

1

auto[1]

1747

1

T1

2

T4

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T4	1		T46	3		T113	1
auto[134217728:268435455]	90	1			T136	1		T45	1		T113	1
auto[268435456:402653183]	109	1			T24	1		T59	3		T140	1
auto[402653184:536870911]	108	1			T46	1		T206	1		T68	1
auto[536870912:671088639]	89	1			T5	1		T17	1		T64	1
auto[671088640:805306367]	115	1			T4	1		T5	1		T17	1
auto[805306368:939524095]	113	1			T206	1		T64	1		T50	1
auto[939524096:1073741823]	95	1			T1	1		T24	1		T68	1
auto[1073741824:1207959551]	112	1			T4	2		T19	1		T45	1
auto[1207959552:1342177279]	96	1			T17	1		T46	1		T64	1
auto[1342177280:1476395007]	88	1			T46	1		T113	1		T150	1
auto[1476395008:1610612735]	111	1			T5	1		T46	2		T64	1
auto[1610612736:1744830463]	107	1			T17	1		T46	2		T113	1
auto[1744830464:1879048191]	97	1			T24	1		T206	1		T114	1
auto[1879048192:2013265919]	116	1			T19	1		T136	1		T46	1
auto[2013265920:2147483647]	99	1			T24	2		T45	1		T49	1
auto[2147483648:2281701375]	92	1			T1	1		T17	1		T117	1
auto[2281701376:2415919103]	104	1			T46	1		T114	1		T80	1
auto[2415919104:2550136831]	100	1			T46	1		T120	1		T240	1
auto[2550136832:2684354559]	97	1			T136	1		T58	1		T59	6
auto[2684354560:2818572287]	99	1			T5	1		T57	1		T240	2
auto[2818572288:2952790015]	102	1			T113	1		T69	1		T205	1
auto[2952790016:3087007743]	99	1			T206	1		T113	1		T58	1
auto[3087007744:3221225471]	117	1			T136	1		T49	1		T58	1
auto[3221225472:3355443199]	104	1			T4	2		T49	1		T46	2
auto[3355443200:3489660927]	85	1			T19	2		T45	1		T46	1
auto[3489660928:3623878655]	94	1			T46	1		T150	1		T114	3
auto[3623878656:3758096383]	103	1			T17	1		T64	1		T114	1
auto[3758096384:3892314111]	100	1			T206	1		T59	2		T47	1
auto[3892314112:4026531839]	119	1			T1	1		T17	1		T45	1
auto[4026531840:4160749567]	100	1			T24	2		T46	1		T114	1
auto[4160749568:4294967295]	102	1			T24	2		T50	2		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T46	1		T150	1		T65	1
auto[0:134217727]	auto[1]	55	1			T4	1		T46	2		T113	1
auto[134217728:268435455]	auto[0]	44	1			T136	1		T113	1		T240	1
auto[134217728:268435455]	auto[1]	46	1			T45	1		T38	1		T117	1
auto[268435456:402653183]	auto[0]	56	1			T24	1		T59	3		T140	1
auto[268435456:402653183]	auto[1]	53	1			T47	1		T79	1		T72	3
auto[402653184:536870911]	auto[0]	43	1			T68	1		T59	2		T47	1
auto[402653184:536870911]	auto[1]	65	1			T46	1		T206	1		T65	1
auto[536870912:671088639]	auto[0]	40	1			T64	1		T58	1		T205	1
auto[536870912:671088639]	auto[1]	49	1			T5	1		T17	1		T205	1
auto[671088640:805306367]	auto[0]	51	1			T4	1		T5	1		T59	1
auto[671088640:805306367]	auto[1]	64	1			T17	1		T46	1		T56	1
auto[805306368:939524095]	auto[0]	54	1			T50	1		T59	2		T28	1
auto[805306368:939524095]	auto[1]	59	1			T206	1		T64	1		T65	1
auto[939524096:1073741823]	auto[0]	51	1			T1	1		T24	1		T68	1
auto[939524096:1073741823]	auto[1]	44	1			T262	1		T30	1		T59	1
auto[1073741824:1207959551]	auto[0]	45	1			T4	2		T45	1		T46	1
auto[1073741824:1207959551]	auto[1]	67	1			T19	1		T68	1		T114	1
auto[1207959552:1342177279]	auto[0]	50	1			T17	1		T64	1		T59	4
auto[1207959552:1342177279]	auto[1]	46	1			T46	1		T240	2		T59	1
auto[1342177280:1476395007]	auto[0]	42	1			T46	1		T150	1		T59	1
auto[1342177280:1476395007]	auto[1]	46	1			T113	1		T151	1		T97	1
auto[1476395008:1610612735]	auto[0]	52	1			T151	1		T59	1		T53	1
auto[1476395008:1610612735]	auto[1]	59	1			T5	1		T46	2		T64	1
auto[1610612736:1744830463]	auto[0]	39	1			T17	1		T46	2		T52	1
auto[1610612736:1744830463]	auto[1]	68	1			T113	1		T150	1		T57	1
auto[1744830464:1879048191]	auto[0]	43	1			T24	1		T80	1		T59	1
auto[1744830464:1879048191]	auto[1]	54	1			T206	1		T114	1		T73	1
auto[1879048192:2013265919]	auto[0]	60	1			T19	1		T136	1		T51	2
auto[1879048192:2013265919]	auto[1]	56	1			T46	1		T209	1		T59	1
auto[2013265920:2147483647]	auto[0]	51	1			T24	2		T49	1		T56	1
auto[2013265920:2147483647]	auto[1]	48	1			T45	1		T80	1		T59	1
auto[2147483648:2281701375]	auto[0]	47	1			T240	1		T59	2		T265	1
auto[2147483648:2281701375]	auto[1]	45	1			T1	1		T17	1		T117	1
auto[2281701376:2415919103]	auto[0]	53	1			T46	1		T114	1		T265	1
auto[2281701376:2415919103]	auto[1]	51	1			T80	1		T70	1		T59	1
auto[2415919104:2550136831]	auto[0]	48	1			T240	1		T352	1		T48	1
auto[2415919104:2550136831]	auto[1]	52	1			T46	1		T120	1		T59	1
auto[2550136832:2684354559]	auto[0]	45	1			T59	2		T101	1		T243	1
auto[2550136832:2684354559]	auto[1]	52	1			T136	1		T58	1		T59	4
auto[2684354560:2818572287]	auto[0]	44	1			T240	2		T59	1		T62	1
auto[2684354560:2818572287]	auto[1]	55	1			T5	1		T57	1		T59	1
auto[2818572288:2952790015]	auto[0]	60	1			T113	1		T205	1		T59	2
auto[2818572288:2952790015]	auto[1]	42	1			T69	1		T240	1		T265	1
auto[2952790016:3087007743]	auto[0]	44	1			T113	1		T59	1		T265	1
auto[2952790016:3087007743]	auto[1]	55	1			T206	1		T58	1		T59	2
auto[3087007744:3221225471]	auto[0]	46	1			T262	1		T59	1		T95	1
auto[3087007744:3221225471]	auto[1]	71	1			T136	1		T49	1		T58	1
auto[3221225472:3355443199]	auto[0]	53	1			T4	1		T56	1		T59	1
auto[3221225472:3355443199]	auto[1]	51	1			T4	1		T49	1		T46	2
auto[3355443200:3489660927]	auto[0]	33	1			T45	1		T58	1		T52	1
auto[3355443200:3489660927]	auto[1]	52	1			T19	2		T46	1		T287	1
auto[3489660928:3623878655]	auto[0]	39	1			T21	1		T79	1		T63	2
auto[3489660928:3623878655]	auto[1]	55	1			T46	1		T150	1		T114	3
auto[3623878656:3758096383]	auto[0]	42	1			T114	1		T58	1		T59	1
auto[3623878656:3758096383]	auto[1]	61	1			T17	1		T64	1		T120	1
auto[3758096384:3892314111]	auto[0]	43	1			T59	2		T62	1		T79	2
auto[3758096384:3892314111]	auto[1]	57	1			T206	1		T47	1		T71	2
auto[3892314112:4026531839]	auto[0]	61	1			T113	1		T68	1		T59	2
auto[3892314112:4026531839]	auto[1]	58	1			T1	1		T17	1		T45	1
auto[4026531840:4160749567]	auto[0]	44	1			T24	1		T46	1		T114	1
auto[4026531840:4160749567]	auto[1]	56	1			T24	1		T59	1		T102	1
auto[4160749568:4294967295]	auto[0]	47	1			T24	1		T50	1		T51	1
auto[4160749568:4294967295]	auto[1]	55	1			T24	1		T50	1		T57	1