Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6948

1

T1

12

T4

12

T5

8

auto[1]

252

1

T4

2

T5

7

T151

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2917	1			T1	5		T4	4		T5	4
auto[134217728:268435455]	162	1			T5	1		T136	1		T46	1
auto[268435456:402653183]	160	1			T1	1		T4	1		T5	1
auto[402653184:536870911]	141	1			T24	1		T136	1		T45	1
auto[536870912:671088639]	166	1			T4	1		T24	1		T49	1
auto[671088640:805306367]	146	1			T1	1		T4	2		T5	1
auto[805306368:939524095]	153	1			T1	1		T51	1		T80	1
auto[939524096:1073741823]	121	1			T5	1		T17	2		T24	1
auto[1073741824:1207959551]	147	1			T46	1		T56	1		T114	1
auto[1207959552:1342177279]	142	1			T4	1		T5	1		T17	1
auto[1342177280:1476395007]	154	1			T19	1		T46	2		T206	1
auto[1476395008:1610612735]	114	1			T24	1		T113	1		T56	1
auto[1610612736:1744830463]	122	1			T1	1		T4	1		T5	1
auto[1744830464:1879048191]	132	1			T4	1		T136	1		T46	2
auto[1879048192:2013265919]	111	1			T1	1		T19	1		T46	1
auto[2013265920:2147483647]	149	1			T4	1		T206	1		T38	1
auto[2147483648:2281701375]	138	1			T19	2		T24	1		T206	1
auto[2281701376:2415919103]	138	1			T46	1		T206	1		T205	1
auto[2415919104:2550136831]	134	1			T46	1		T113	1		T114	1
auto[2550136832:2684354559]	126	1			T80	2		T151	1		T209	1
auto[2684354560:2818572287]	119	1			T5	2		T17	1		T19	1
auto[2818572288:2952790015]	139	1			T4	1		T5	1		T17	1
auto[2952790016:3087007743]	133	1			T5	1		T24	2		T113	1
auto[3087007744:3221225471]	135	1			T1	1		T17	1		T24	1
auto[3221225472:3355443199]	136	1			T24	1		T45	1		T206	1
auto[3355443200:3489660927]	128	1			T19	1		T24	1		T46	1
auto[3489660928:3623878655]	137	1			T5	1		T17	1		T45	1
auto[3623878656:3758096383]	112	1			T17	1		T45	1		T113	1
auto[3758096384:3892314111]	132	1			T45	1		T59	3		T21	1
auto[3892314112:4026531839]	146	1			T206	3		T113	1		T151	1
auto[4026531840:4160749567]	172	1			T4	1		T17	1		T24	1
auto[4160749568:4294967295]	138	1			T1	1		T19	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2906	1			T1	5		T4	4		T5	3
auto[0:134217727]	auto[1]	11	1			T5	1		T151	1		T141	1
auto[134217728:268435455]	auto[0]	150	1			T5	1		T136	1		T46	1
auto[134217728:268435455]	auto[1]	12	1			T152	1		T141	1		T287	1
auto[268435456:402653183]	auto[0]	152	1			T1	1		T4	1		T24	1
auto[268435456:402653183]	auto[1]	8	1			T5	1		T386	1		T407	2
auto[402653184:536870911]	auto[0]	128	1			T24	1		T136	1		T45	1
auto[402653184:536870911]	auto[1]	13	1			T151	1		T141	2		T287	1
auto[536870912:671088639]	auto[0]	159	1			T4	1		T24	1		T49	1
auto[536870912:671088639]	auto[1]	7	1			T141	1		T245	1		T416	1
auto[671088640:805306367]	auto[0]	131	1			T1	1		T4	2		T17	1
auto[671088640:805306367]	auto[1]	15	1			T5	1		T151	1		T95	1
auto[805306368:939524095]	auto[0]	149	1			T1	1		T51	1		T80	1
auto[805306368:939524095]	auto[1]	4	1			T328	1		T408	1		T417	1
auto[939524096:1073741823]	auto[0]	114	1			T5	1		T17	2		T24	1
auto[939524096:1073741823]	auto[1]	7	1			T141	1		T282	1		T283	1
auto[1073741824:1207959551]	auto[0]	139	1			T46	1		T56	1		T114	1
auto[1073741824:1207959551]	auto[1]	8	1			T151	1		T95	1		T245	1
auto[1207959552:1342177279]	auto[0]	133	1			T4	1		T5	1		T17	1
auto[1207959552:1342177279]	auto[1]	9	1			T256	2		T404	1		T328	1
auto[1342177280:1476395007]	auto[0]	148	1			T19	1		T46	2		T206	1
auto[1342177280:1476395007]	auto[1]	6	1			T95	1		T418	1		T409	1
auto[1476395008:1610612735]	auto[0]	108	1			T24	1		T113	1		T56	1
auto[1476395008:1610612735]	auto[1]	6	1			T152	1		T95	1		T282	2
auto[1610612736:1744830463]	auto[0]	112	1			T1	1		T19	1		T206	1
auto[1610612736:1744830463]	auto[1]	10	1			T4	1		T5	1		T95	1
auto[1744830464:1879048191]	auto[0]	126	1			T4	1		T136	1		T46	2
auto[1744830464:1879048191]	auto[1]	6	1			T152	1		T95	1		T141	1
auto[1879048192:2013265919]	auto[0]	105	1			T1	1		T19	1		T46	1
auto[1879048192:2013265919]	auto[1]	6	1			T97	1		T302	1		T386	1
auto[2013265920:2147483647]	auto[0]	144	1			T4	1		T206	1		T38	1
auto[2013265920:2147483647]	auto[1]	5	1			T95	1		T287	1		T419	1
auto[2147483648:2281701375]	auto[0]	124	1			T19	2		T24	1		T206	1
auto[2147483648:2281701375]	auto[1]	14	1			T141	2		T232	1		T410	2
auto[2281701376:2415919103]	auto[0]	133	1			T46	1		T206	1		T205	1
auto[2281701376:2415919103]	auto[1]	5	1			T359	1		T418	1		T420	1
auto[2415919104:2550136831]	auto[0]	128	1			T46	1		T113	1		T114	1
auto[2415919104:2550136831]	auto[1]	6	1			T95	2		T282	1		T359	1
auto[2550136832:2684354559]	auto[0]	122	1			T80	2		T209	1		T59	3
auto[2550136832:2684354559]	auto[1]	4	1			T151	1		T386	1		T233	1
auto[2684354560:2818572287]	auto[0]	112	1			T5	1		T17	1		T19	1
auto[2684354560:2818572287]	auto[1]	7	1			T5	1		T95	1		T141	1
auto[2818572288:2952790015]	auto[0]	124	1			T17	1		T19	1		T35	1
auto[2818572288:2952790015]	auto[1]	15	1			T4	1		T5	1		T139	1
auto[2952790016:3087007743]	auto[0]	123	1			T5	1		T24	2		T113	1
auto[2952790016:3087007743]	auto[1]	10	1			T95	2		T139	1		T245	1
auto[3087007744:3221225471]	auto[0]	130	1			T1	1		T17	1		T24	1
auto[3087007744:3221225471]	auto[1]	5	1			T95	1		T352	1		T404	1
auto[3221225472:3355443199]	auto[0]	131	1			T24	1		T45	1		T206	1
auto[3221225472:3355443199]	auto[1]	5	1			T410	2		T421	1		T233	1
auto[3355443200:3489660927]	auto[0]	118	1			T19	1		T24	1		T46	1
auto[3355443200:3489660927]	auto[1]	10	1			T151	2		T245	1		T404	1
auto[3489660928:3623878655]	auto[0]	133	1			T17	1		T45	1		T46	2
auto[3489660928:3623878655]	auto[1]	4	1			T5	1		T410	1		T359	1
auto[3623878656:3758096383]	auto[0]	107	1			T17	1		T45	1		T113	1
auto[3623878656:3758096383]	auto[1]	5	1			T386	1		T412	1		T420	2
auto[3758096384:3892314111]	auto[0]	124	1			T45	1		T59	3		T21	1
auto[3758096384:3892314111]	auto[1]	8	1			T139	1		T141	1		T328	1
auto[3892314112:4026531839]	auto[0]	141	1			T206	3		T113	1		T151	1
auto[3892314112:4026531839]	auto[1]	5	1			T95	1		T404	1		T405	1
auto[4026531840:4160749567]	auto[0]	162	1			T4	1		T17	1		T24	1
auto[4026531840:4160749567]	auto[1]	10	1			T152	1		T139	1		T141	1
auto[4160749568:4294967295]	auto[0]	132	1			T1	1		T19	1		T24	1
auto[4160749568:4294967295]	auto[1]	6	1			T151	1		T139	1		T422	1