Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4318

1

T1

6

T4

8

T5

4

auto[1]

2206

1

T4

4

T5

4

T17

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	156	1			T17	2		T68	2		T58	2
auto[134217728:268435455]	212	1			T17	2		T64	2		T50	2
auto[268435456:402653183]	174	1			T49	2		T205	2		T209	2
auto[402653184:536870911]	204	1			T5	2		T17	2		T113	2
auto[536870912:671088639]	200	1			T45	2		T38	2		T240	6
auto[671088640:805306367]	188	1			T1	2		T4	2		T17	2
auto[805306368:939524095]	152	1			T46	2		T117	2		T151	2
auto[939524096:1073741823]	214	1			T136	2		T50	2		T57	2
auto[1073741824:1207959551]	186	1			T113	2		T64	2		T150	4
auto[1207959552:1342177279]	208	1			T17	2		T24	2		T46	4
auto[1342177280:1476395007]	212	1			T19	2		T46	4		T150	2
auto[1476395008:1610612735]	228	1			T46	4		T80	2		T117	2
auto[1610612736:1744830463]	190	1			T4	2		T24	2		T206	2
auto[1744830464:1879048191]	266	1			T1	2		T24	2		T49	2
auto[1879048192:2013265919]	238	1			T17	2		T113	2		T68	2
auto[2013265920:2147483647]	186	1			T4	4		T46	2		T114	2
auto[2147483648:2281701375]	228	1			T19	2		T56	2		T51	2
auto[2281701376:2415919103]	236	1			T5	4		T19	2		T46	4
auto[2415919104:2550136831]	236	1			T46	2		T114	4		T51	2
auto[2550136832:2684354559]	212	1			T136	2		T46	2		T206	4
auto[2684354560:2818572287]	190	1			T46	2		T65	2		T58	2
auto[2818572288:2952790015]	200	1			T1	2		T4	2		T5	2
auto[2952790016:3087007743]	196	1			T24	2		T113	2		T114	2
auto[3087007744:3221225471]	216	1			T24	4		T46	2		T56	2
auto[3221225472:3355443199]	204	1			T24	2		T45	2		T46	4
auto[3355443200:3489660927]	192	1			T113	2		T59	4		T102	2
auto[3489660928:3623878655]	174	1			T24	2		T136	2		T46	4
auto[3623878656:3758096383]	180	1			T46	2		T80	2		T117	2
auto[3758096384:3892314111]	186	1			T38	2		T114	2		T58	2
auto[3892314112:4026531839]	206	1			T136	2		T113	2		T150	2
auto[4026531840:4160749567]	210	1			T49	2		T68	2		T50	2
auto[4160749568:4294967295]	244	1			T4	2		T19	2		T24	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T151	2		T53	2		T47	2
auto[0:134217727]	auto[1]	58	1			T17	2		T68	2		T58	2
auto[134217728:268435455]	auto[0]	134	1			T17	2		T64	2		T59	2
auto[134217728:268435455]	auto[1]	78	1			T50	2		T243	2		T71	2
auto[268435456:402653183]	auto[0]	120	1			T205	2		T209	2		T59	4
auto[268435456:402653183]	auto[1]	54	1			T49	2		T47	2		T232	4
auto[402653184:536870911]	auto[0]	138	1			T113	2		T68	2		T50	2
auto[402653184:536870911]	auto[1]	66	1			T5	2		T17	2		T140	2
auto[536870912:671088639]	auto[0]	128	1			T240	4		T59	4		T81	2
auto[536870912:671088639]	auto[1]	72	1			T45	2		T38	2		T240	2
auto[671088640:805306367]	auto[0]	136	1			T1	2		T4	2		T64	2
auto[671088640:805306367]	auto[1]	52	1			T17	2		T45	4		T414	2
auto[805306368:939524095]	auto[0]	98	1			T117	2		T151	2		T59	2
auto[805306368:939524095]	auto[1]	54	1			T46	2		T139	2		T47	2
auto[939524096:1073741823]	auto[0]	132	1			T136	2		T50	2		T205	2
auto[939524096:1073741823]	auto[1]	82	1			T57	2		T58	2		T352	2
auto[1073741824:1207959551]	auto[0]	122	1			T113	2		T64	2		T150	4
auto[1073741824:1207959551]	auto[1]	64	1			T91	2		T63	2		T237	2
auto[1207959552:1342177279]	auto[0]	148	1			T17	2		T46	4		T206	2
auto[1207959552:1342177279]	auto[1]	60	1			T24	2		T65	2		T262	2
auto[1342177280:1476395007]	auto[0]	134	1			T19	2		T150	2		T114	4
auto[1342177280:1476395007]	auto[1]	78	1			T46	4		T59	2		T414	2
auto[1476395008:1610612735]	auto[0]	146	1			T46	2		T117	2		T240	2
auto[1476395008:1610612735]	auto[1]	82	1			T46	2		T80	2		T79	2
auto[1610612736:1744830463]	auto[0]	124	1			T24	2		T206	2		T51	4
auto[1610612736:1744830463]	auto[1]	66	1			T4	2		T113	2		T56	2
auto[1744830464:1879048191]	auto[0]	180	1			T1	2		T24	2		T240	2
auto[1744830464:1879048191]	auto[1]	86	1			T49	2		T59	2		T91	2
auto[1879048192:2013265919]	auto[0]	158	1			T17	2		T113	2		T68	2
auto[1879048192:2013265919]	auto[1]	80	1			T209	2		T265	2		T95	2
auto[2013265920:2147483647]	auto[0]	102	1			T4	2		T46	2		T114	2
auto[2013265920:2147483647]	auto[1]	84	1			T4	2		T59	2		T53	2
auto[2147483648:2281701375]	auto[0]	156	1			T19	2		T51	2		T59	2
auto[2147483648:2281701375]	auto[1]	72	1			T56	2		T151	2		T91	2
auto[2281701376:2415919103]	auto[0]	164	1			T5	2		T19	2		T46	4
auto[2281701376:2415919103]	auto[1]	72	1			T5	2		T287	2		T34	2
auto[2415919104:2550136831]	auto[0]	146	1			T114	2		T51	2		T59	2
auto[2415919104:2550136831]	auto[1]	90	1			T46	2		T114	2		T70	2
auto[2550136832:2684354559]	auto[0]	158	1			T136	2		T46	2		T206	2
auto[2550136832:2684354559]	auto[1]	54	1			T206	2		T151	2		T377	2
auto[2684354560:2818572287]	auto[0]	142	1			T65	2		T58	2		T352	2
auto[2684354560:2818572287]	auto[1]	48	1			T46	2		T59	2		T197	2
auto[2818572288:2952790015]	auto[0]	136	1			T1	2		T4	2		T5	2
auto[2818572288:2952790015]	auto[1]	64	1			T46	2		T113	2		T118	2
auto[2952790016:3087007743]	auto[0]	118	1			T24	2		T114	2		T240	2
auto[2952790016:3087007743]	auto[1]	78	1			T113	2		T60	2		T39	2
auto[3087007744:3221225471]	auto[0]	132	1			T24	2		T46	2		T68	2
auto[3087007744:3221225471]	auto[1]	84	1			T24	2		T56	2		T117	2
auto[3221225472:3355443199]	auto[0]	138	1			T24	2		T46	4		T114	2
auto[3221225472:3355443199]	auto[1]	66	1			T45	2		T57	2		T69	2
auto[3355443200:3489660927]	auto[0]	126	1			T59	2		T102	2		T71	2
auto[3355443200:3489660927]	auto[1]	66	1			T113	2		T59	2		T47	2
auto[3489660928:3623878655]	auto[0]	118	1			T24	2		T46	4		T59	12
auto[3489660928:3623878655]	auto[1]	56	1			T136	2		T59	2		T79	2
auto[3623878656:3758096383]	auto[0]	130	1			T46	2		T80	2		T117	2
auto[3623878656:3758096383]	auto[1]	50	1			T59	2		T101	2		T47	2
auto[3758096384:3892314111]	auto[0]	124	1			T114	2		T58	2		T59	4
auto[3758096384:3892314111]	auto[1]	62	1			T38	2		T101	2		T47	2
auto[3892314112:4026531839]	auto[0]	126	1			T150	2		T30	2		T377	2
auto[3892314112:4026531839]	auto[1]	80	1			T136	2		T113	2		T415	2
auto[4026531840:4160749567]	auto[0]	140	1			T68	2		T57	2		T69	2
auto[4026531840:4160749567]	auto[1]	70	1			T49	2		T50	2		T103	2
auto[4160749568:4294967295]	auto[0]	166	1			T4	2		T24	2		T45	2
auto[4160749568:4294967295]	auto[1]	78	1			T19	2		T46	2		T205	2