Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.04 98.07 98.61 100.00 99.02 98.41 91.14


Total test records in report: 1081
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T1007 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1676340408 May 23 03:39:19 PM PDT 24 May 23 03:39:31 PM PDT 24 109313649 ps
T1008 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2969438194 May 23 03:39:18 PM PDT 24 May 23 03:39:28 PM PDT 24 60565211 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2326369276 May 23 03:38:57 PM PDT 24 May 23 03:39:12 PM PDT 24 835911895 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3998882841 May 23 03:39:09 PM PDT 24 May 23 03:39:27 PM PDT 24 1832753163 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1959964640 May 23 03:39:02 PM PDT 24 May 23 03:39:09 PM PDT 24 27165081 ps
T1012 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2700081704 May 23 03:39:10 PM PDT 24 May 23 03:39:19 PM PDT 24 1019895936 ps
T1013 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3634073512 May 23 03:39:18 PM PDT 24 May 23 03:39:28 PM PDT 24 18222185 ps
T1014 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3072073758 May 23 03:39:24 PM PDT 24 May 23 03:39:35 PM PDT 24 28220697 ps
T1015 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3300348134 May 23 03:39:19 PM PDT 24 May 23 03:39:31 PM PDT 24 39360053 ps
T1016 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3681838179 May 23 03:38:57 PM PDT 24 May 23 03:39:03 PM PDT 24 42819922 ps
T1017 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3814478352 May 23 03:39:11 PM PDT 24 May 23 03:39:20 PM PDT 24 325016464 ps
T162 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2815442173 May 23 03:39:03 PM PDT 24 May 23 03:39:14 PM PDT 24 214785496 ps
T1018 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2364462787 May 23 03:39:11 PM PDT 24 May 23 03:39:25 PM PDT 24 228102127 ps
T1019 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.129794788 May 23 03:39:22 PM PDT 24 May 23 03:39:32 PM PDT 24 17668644 ps
T1020 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3965712819 May 23 03:39:19 PM PDT 24 May 23 03:39:36 PM PDT 24 213635034 ps
T155 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1119935715 May 23 03:39:05 PM PDT 24 May 23 03:39:16 PM PDT 24 114017630 ps
T1021 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3702812289 May 23 03:39:15 PM PDT 24 May 23 03:39:24 PM PDT 24 12487517 ps
T1022 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.835652809 May 23 03:39:19 PM PDT 24 May 23 03:39:29 PM PDT 24 53326993 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3012637396 May 23 03:39:08 PM PDT 24 May 23 03:39:18 PM PDT 24 854177963 ps
T1024 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.528659820 May 23 03:39:04 PM PDT 24 May 23 03:39:13 PM PDT 24 211637984 ps
T1025 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2630167341 May 23 03:39:04 PM PDT 24 May 23 03:39:22 PM PDT 24 1279252683 ps
T1026 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3734535716 May 23 03:39:07 PM PDT 24 May 23 03:39:15 PM PDT 24 138341246 ps
T1027 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2088282861 May 23 03:39:23 PM PDT 24 May 23 03:39:34 PM PDT 24 12396734 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.152787428 May 23 03:39:11 PM PDT 24 May 23 03:39:24 PM PDT 24 269124299 ps
T165 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1263573715 May 23 03:39:10 PM PDT 24 May 23 03:39:18 PM PDT 24 55110243 ps
T1029 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1364625894 May 23 03:39:23 PM PDT 24 May 23 03:39:34 PM PDT 24 8972430 ps
T1030 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.232623602 May 23 03:39:05 PM PDT 24 May 23 03:39:13 PM PDT 24 94287253 ps
T1031 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1285045374 May 23 03:39:22 PM PDT 24 May 23 03:39:32 PM PDT 24 36569116 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1340732274 May 23 03:38:55 PM PDT 24 May 23 03:39:01 PM PDT 24 38362552 ps
T1033 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.461683764 May 23 03:39:12 PM PDT 24 May 23 03:39:24 PM PDT 24 226258361 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2721734246 May 23 03:39:15 PM PDT 24 May 23 03:39:24 PM PDT 24 16800792 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3160111398 May 23 03:39:19 PM PDT 24 May 23 03:39:30 PM PDT 24 35737322 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3203890010 May 23 03:39:03 PM PDT 24 May 23 03:39:10 PM PDT 24 97164697 ps
T1037 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1311876357 May 23 03:39:08 PM PDT 24 May 23 03:39:16 PM PDT 24 105170322 ps
T1038 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1282120 May 23 03:38:55 PM PDT 24 May 23 03:39:04 PM PDT 24 319395979 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2924039067 May 23 03:39:07 PM PDT 24 May 23 03:39:14 PM PDT 24 117581027 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3579973911 May 23 03:39:11 PM PDT 24 May 23 03:39:19 PM PDT 24 85351704 ps
T1041 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2772228152 May 23 03:39:19 PM PDT 24 May 23 03:39:30 PM PDT 24 10998315 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1341631653 May 23 03:39:13 PM PDT 24 May 23 03:39:23 PM PDT 24 525812049 ps
T1043 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3466464231 May 23 03:39:13 PM PDT 24 May 23 03:39:21 PM PDT 24 10761389 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2623818593 May 23 03:39:04 PM PDT 24 May 23 03:39:10 PM PDT 24 118004170 ps
T173 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3638229929 May 23 03:38:58 PM PDT 24 May 23 03:39:06 PM PDT 24 188983555 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1627643718 May 23 03:39:12 PM PDT 24 May 23 03:39:34 PM PDT 24 420578597 ps
T1046 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3640342074 May 23 03:39:13 PM PDT 24 May 23 03:39:23 PM PDT 24 34152590 ps
T168 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1860418378 May 23 03:39:09 PM PDT 24 May 23 03:39:16 PM PDT 24 71647311 ps
T1047 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2094854766 May 23 03:39:01 PM PDT 24 May 23 03:39:09 PM PDT 24 102683704 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2104571072 May 23 03:38:58 PM PDT 24 May 23 03:39:04 PM PDT 24 13813312 ps
T1049 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2829827937 May 23 03:39:15 PM PDT 24 May 23 03:39:23 PM PDT 24 16291663 ps
T1050 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2157799679 May 23 03:39:07 PM PDT 24 May 23 03:39:22 PM PDT 24 1759988882 ps
T1051 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3402790679 May 23 03:39:00 PM PDT 24 May 23 03:39:08 PM PDT 24 432802801 ps
T1052 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1209454884 May 23 03:39:12 PM PDT 24 May 23 03:39:21 PM PDT 24 28578970 ps
T1053 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2209892225 May 23 03:39:00 PM PDT 24 May 23 03:39:10 PM PDT 24 94128394 ps
T1054 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3927931425 May 23 03:39:11 PM PDT 24 May 23 03:39:19 PM PDT 24 20802351 ps
T1055 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.27020515 May 23 03:39:06 PM PDT 24 May 23 03:39:13 PM PDT 24 76190044 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1499539526 May 23 03:39:15 PM PDT 24 May 23 03:39:26 PM PDT 24 76350135 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.415146010 May 23 03:39:20 PM PDT 24 May 23 03:39:30 PM PDT 24 137585649 ps
T1058 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.860993584 May 23 03:39:17 PM PDT 24 May 23 03:39:27 PM PDT 24 140003338 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2223053896 May 23 03:39:14 PM PDT 24 May 23 03:39:24 PM PDT 24 410611836 ps
T1060 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1234264559 May 23 03:39:10 PM PDT 24 May 23 03:39:17 PM PDT 24 315178224 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.364236533 May 23 03:39:04 PM PDT 24 May 23 03:39:10 PM PDT 24 18868368 ps
T1062 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1433368577 May 23 03:39:17 PM PDT 24 May 23 03:39:27 PM PDT 24 42332932 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3067096173 May 23 03:39:15 PM PDT 24 May 23 03:39:25 PM PDT 24 202486408 ps
T1064 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1325885015 May 23 03:39:22 PM PDT 24 May 23 03:39:34 PM PDT 24 137361989 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1453638777 May 23 03:39:15 PM PDT 24 May 23 03:39:25 PM PDT 24 66695223 ps
T1066 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2925067293 May 23 03:39:27 PM PDT 24 May 23 03:39:38 PM PDT 24 82963198 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3357545384 May 23 03:39:01 PM PDT 24 May 23 03:39:10 PM PDT 24 119045942 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3276435899 May 23 03:39:00 PM PDT 24 May 23 03:39:06 PM PDT 24 48031563 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.733546264 May 23 03:39:09 PM PDT 24 May 23 03:39:16 PM PDT 24 54964842 ps
T1070 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2655705553 May 23 03:39:16 PM PDT 24 May 23 03:39:25 PM PDT 24 34155910 ps
T1071 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3453510431 May 23 03:39:13 PM PDT 24 May 23 03:39:22 PM PDT 24 41291668 ps
T1072 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.165832577 May 23 03:39:14 PM PDT 24 May 23 03:39:24 PM PDT 24 81493222 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.724814058 May 23 03:39:19 PM PDT 24 May 23 03:39:43 PM PDT 24 2089519493 ps
T1074 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4054841458 May 23 03:39:12 PM PDT 24 May 23 03:39:23 PM PDT 24 256783347 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.68253879 May 23 03:39:01 PM PDT 24 May 23 03:39:15 PM PDT 24 469593928 ps
T1076 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.195553281 May 23 03:38:58 PM PDT 24 May 23 03:39:05 PM PDT 24 47519918 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3322540492 May 23 03:38:59 PM PDT 24 May 23 03:39:13 PM PDT 24 900155613 ps
T178 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3305860467 May 23 03:38:54 PM PDT 24 May 23 03:39:03 PM PDT 24 542816958 ps
T1078 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.831156720 May 23 03:39:23 PM PDT 24 May 23 03:39:33 PM PDT 24 30349699 ps
T1079 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2678881904 May 23 03:39:00 PM PDT 24 May 23 03:39:07 PM PDT 24 15165312 ps
T1080 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.845361746 May 23 03:39:11 PM PDT 24 May 23 03:39:19 PM PDT 24 153421960 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3082632356 May 23 03:39:10 PM PDT 24 May 23 03:39:16 PM PDT 24 10491112 ps

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1950065656
Short name T17
Test name
Test status
Simulation time 427955227 ps
CPU time 16.5 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:42 PM PDT 24
Peak memory 219436 kb
Host smart-ca6df844-2647-4cb1-851b-80bb885c126b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950065656 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1950065656
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.420808826
Short name T59
Test name
Test status
Simulation time 1774946513 ps
CPU time 65.7 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:48:03 PM PDT 24
Peak memory 222440 kb
Host smart-68847f3c-8560-4bd9-9e5f-a34f00dc99c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420808826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.420808826
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1302338510
Short name T46
Test name
Test status
Simulation time 3572736157 ps
CPU time 28.67 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 222608 kb
Host smart-017653a2-dcd8-4713-b08a-9ff791abe227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302338510 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1302338510
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3586259021
Short name T12
Test name
Test status
Simulation time 532762389 ps
CPU time 8.97 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 237252 kb
Host smart-99265a15-bbb1-473f-8477-37b1885edef3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586259021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3586259021
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3337870955
Short name T63
Test name
Test status
Simulation time 857191491 ps
CPU time 31.7 seconds
Started May 23 03:46:46 PM PDT 24
Finished May 23 03:47:48 PM PDT 24
Peak memory 217236 kb
Host smart-88f855a0-e2aa-4a1b-a880-22fb7cbe620f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337870955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3337870955
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1582687708
Short name T9
Test name
Test status
Simulation time 403659614 ps
CPU time 4.89 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:28 PM PDT 24
Peak memory 221108 kb
Host smart-d07a2117-4129-4b31-bf34-a60b1289e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582687708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1582687708
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4258535296
Short name T110
Test name
Test status
Simulation time 1600026349 ps
CPU time 5.44 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 210668 kb
Host smart-d1424add-987f-40ad-89df-895d01673d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258535296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4258535296
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4079355125
Short name T95
Test name
Test status
Simulation time 557348073 ps
CPU time 15.02 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:41 PM PDT 24
Peak memory 222504 kb
Host smart-13df1b01-09ef-4378-a9cf-0a7442b15545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079355125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4079355125
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2063391384
Short name T124
Test name
Test status
Simulation time 1356337315 ps
CPU time 10.37 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:42 PM PDT 24
Peak memory 214444 kb
Host smart-579f2ae5-ada1-41a0-9ecd-e4485e41c8af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063391384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2063391384
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4221331515
Short name T52
Test name
Test status
Simulation time 85465308 ps
CPU time 4.27 seconds
Started May 23 03:46:48 PM PDT 24
Finished May 23 03:47:22 PM PDT 24
Peak memory 214328 kb
Host smart-79616e22-b515-4fd4-bf75-151981ab0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221331515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4221331515
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.260616656
Short name T89
Test name
Test status
Simulation time 487042483 ps
CPU time 18.81 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:47:08 PM PDT 24
Peak memory 222540 kb
Host smart-a412e487-70af-42dd-98f7-f5e591563b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260616656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.260616656
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1819246927
Short name T24
Test name
Test status
Simulation time 495726004 ps
CPU time 5.68 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 221176 kb
Host smart-abcc4f8b-1f44-4a15-83cc-b971cb94020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819246927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1819246927
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.795396243
Short name T141
Test name
Test status
Simulation time 574822249 ps
CPU time 14.45 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 214392 kb
Host smart-aa9829e0-3f7e-43ce-9175-c247e75b2f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795396243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.795396243
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1964567988
Short name T47
Test name
Test status
Simulation time 1768237496 ps
CPU time 39.93 seconds
Started May 23 03:45:58 PM PDT 24
Finished May 23 03:47:06 PM PDT 24
Peak memory 215124 kb
Host smart-d0430b65-52e4-41ba-9d1a-7f465c7e133a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964567988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1964567988
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.862732981
Short name T5
Test name
Test status
Simulation time 65985979 ps
CPU time 4.42 seconds
Started May 23 03:45:13 PM PDT 24
Finished May 23 03:45:35 PM PDT 24
Peak memory 214464 kb
Host smart-baf0a834-93c3-4f63-9726-f88342b0ca0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862732981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.862732981
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3581243103
Short name T113
Test name
Test status
Simulation time 1261858975 ps
CPU time 15.26 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 222656 kb
Host smart-57a19e7a-5293-4e51-a981-d17f781ac045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581243103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3581243103
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4273747071
Short name T151
Test name
Test status
Simulation time 145933129 ps
CPU time 8.4 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 214776 kb
Host smart-51e0e537-24b0-441f-865d-3c9b1fb9e417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273747071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4273747071
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3500555562
Short name T25
Test name
Test status
Simulation time 1326327481 ps
CPU time 31.34 seconds
Started May 23 03:46:51 PM PDT 24
Finished May 23 03:47:52 PM PDT 24
Peak memory 222352 kb
Host smart-f6bfcc4b-fb7f-4b26-8640-1931c08eada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500555562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3500555562
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.848179234
Short name T75
Test name
Test status
Simulation time 15951423253 ps
CPU time 353.12 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:51:14 PM PDT 24
Peak memory 216988 kb
Host smart-5f7cf69b-9610-465a-b78e-7d6faaed6e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848179234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.848179234
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.414788662
Short name T422
Test name
Test status
Simulation time 7844071554 ps
CPU time 107.98 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:47:49 PM PDT 24
Peak memory 214484 kb
Host smart-ea1f8fc6-b14e-4ca6-838a-a411ebf73ff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414788662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.414788662
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1115224258
Short name T213
Test name
Test status
Simulation time 11321240679 ps
CPU time 86.49 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:46:46 PM PDT 24
Peak memory 215764 kb
Host smart-a0f6b9db-c32d-4760-8b69-3733be09fd4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115224258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1115224258
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3014449589
Short name T27
Test name
Test status
Simulation time 68708200 ps
CPU time 1.35 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:41 PM PDT 24
Peak memory 214684 kb
Host smart-e5780626-0d12-4bcd-9c99-3988f68aa56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014449589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3014449589
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2801564596
Short name T282
Test name
Test status
Simulation time 169129646 ps
CPU time 9.56 seconds
Started May 23 03:46:09 PM PDT 24
Finished May 23 03:46:48 PM PDT 24
Peak memory 214384 kb
Host smart-33b62aa8-4b41-42e9-94bf-5e09dc603902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801564596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2801564596
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.835244318
Short name T38
Test name
Test status
Simulation time 859321242 ps
CPU time 12.87 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:46:04 PM PDT 24
Peak memory 220684 kb
Host smart-f2ce9c2b-7c73-4d6d-8ccb-e272be3119f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835244318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.835244318
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3624006456
Short name T18
Test name
Test status
Simulation time 16565637 ps
CPU time 0.92 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:43 PM PDT 24
Peak memory 206008 kb
Host smart-1c7325e1-0b6b-4051-a1c7-5760c3c48a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624006456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3624006456
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2519636668
Short name T74
Test name
Test status
Simulation time 114659272 ps
CPU time 4.44 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 218084 kb
Host smart-a98f713a-13b9-438a-b204-16602c35d5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519636668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2519636668
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.34598613
Short name T31
Test name
Test status
Simulation time 78865145 ps
CPU time 3.01 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 215588 kb
Host smart-848fd48f-f766-4bd1-ab7c-d8cd79e68fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34598613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.34598613
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.84580706
Short name T407
Test name
Test status
Simulation time 236408108 ps
CPU time 12.04 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 214832 kb
Host smart-fb2d1c8c-50ed-4f61-84e9-b5027de61dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84580706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.84580706
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2270216888
Short name T425
Test name
Test status
Simulation time 351553787 ps
CPU time 5.29 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:55 PM PDT 24
Peak memory 214376 kb
Host smart-8dfcd800-3298-4bdf-af8b-d40f23f2a6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270216888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2270216888
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1120145272
Short name T359
Test name
Test status
Simulation time 8111366482 ps
CPU time 111.2 seconds
Started May 23 03:47:01 PM PDT 24
Finished May 23 03:49:20 PM PDT 24
Peak memory 219712 kb
Host smart-dedeab0d-02b4-40b9-b403-d66486928ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120145272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1120145272
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3742172236
Short name T4
Test name
Test status
Simulation time 213100293 ps
CPU time 4.11 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 214360 kb
Host smart-2462ec59-8a65-495d-a837-e80a4cb28270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742172236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3742172236
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.341054783
Short name T246
Test name
Test status
Simulation time 400565058 ps
CPU time 14.52 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 222556 kb
Host smart-f2895c66-2914-4de9-b6b5-f36226d8931a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341054783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.341054783
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3305299122
Short name T100
Test name
Test status
Simulation time 58512847 ps
CPU time 2.05 seconds
Started May 23 03:47:19 PM PDT 24
Finished May 23 03:47:45 PM PDT 24
Peak memory 214368 kb
Host smart-e6496783-aaca-4af3-b0b4-01619ffb5182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305299122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3305299122
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1822106484
Short name T154
Test name
Test status
Simulation time 836943974 ps
CPU time 8.58 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 213968 kb
Host smart-7acddeea-f15d-4093-818f-09c0187cb4e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822106484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1822106484
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1085022762
Short name T233
Test name
Test status
Simulation time 59998338 ps
CPU time 4.23 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 215392 kb
Host smart-97537508-92f8-4e76-844a-9097be4cc46e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085022762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1085022762
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.999946396
Short name T56
Test name
Test status
Simulation time 365744430 ps
CPU time 3.06 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 214292 kb
Host smart-7f26fabb-0ea2-4f15-8ba1-744c650cf0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999946396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.999946396
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1640398999
Short name T129
Test name
Test status
Simulation time 1336290092 ps
CPU time 12.44 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:33 PM PDT 24
Peak memory 214412 kb
Host smart-58537a8b-ac0c-4990-a362-ee6e842e38d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640398999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1640398999
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3190603703
Short name T171
Test name
Test status
Simulation time 838974910 ps
CPU time 7.55 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:42 PM PDT 24
Peak memory 214044 kb
Host smart-7fb1dbf6-36f2-4a18-8e21-330a61f6436f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190603703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3190603703
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.848187529
Short name T77
Test name
Test status
Simulation time 392381117 ps
CPU time 4.76 seconds
Started May 23 03:47:17 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 210832 kb
Host smart-fab5f61a-e973-4f02-a007-ae72e6b594e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848187529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.848187529
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.211638545
Short name T15
Test name
Test status
Simulation time 100105669 ps
CPU time 2.18 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:01 PM PDT 24
Peak memory 209004 kb
Host smart-321eb4bf-2cb4-438e-ac70-97d06beb69e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211638545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.211638545
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2390741668
Short name T67
Test name
Test status
Simulation time 43077466422 ps
CPU time 389.06 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:53:22 PM PDT 24
Peak memory 218720 kb
Host smart-3a63109f-71ce-4fc1-b7e5-21d450f24021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390741668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2390741668
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2099911456
Short name T55
Test name
Test status
Simulation time 525412827 ps
CPU time 21.05 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 222552 kb
Host smart-f7b2d275-8f13-49ee-a874-92d360a244ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099911456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2099911456
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3621216080
Short name T183
Test name
Test status
Simulation time 494008438 ps
CPU time 3.08 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 222732 kb
Host smart-a1b1f182-502d-4c77-9860-06d413d42eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621216080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3621216080
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3971048293
Short name T185
Test name
Test status
Simulation time 139948753 ps
CPU time 5.37 seconds
Started May 23 03:46:32 PM PDT 24
Finished May 23 03:47:05 PM PDT 24
Peak memory 222688 kb
Host smart-0c485bb2-fdf4-4c83-b82d-6690b06fe7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971048293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3971048293
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.4163724608
Short name T201
Test name
Test status
Simulation time 1748163451 ps
CPU time 45.34 seconds
Started May 23 03:45:24 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 217528 kb
Host smart-2af9235e-3485-4d15-86f2-203dfd470880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163724608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4163724608
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.208850823
Short name T140
Test name
Test status
Simulation time 35056498 ps
CPU time 2.71 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 214380 kb
Host smart-03425410-29c3-4d5e-99a5-3958cc7e2c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208850823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.208850823
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2404850462
Short name T239
Test name
Test status
Simulation time 578330503 ps
CPU time 25.02 seconds
Started May 23 03:47:21 PM PDT 24
Finished May 23 03:48:09 PM PDT 24
Peak memory 214880 kb
Host smart-11b7851b-c5c9-4ccc-a8cd-c0d5221c6169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404850462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2404850462
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.722555603
Short name T161
Test name
Test status
Simulation time 338539408 ps
CPU time 4.96 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 205852 kb
Host smart-10fa1145-9a28-4e7a-95ce-70a260fb2081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722555603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.722555603
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3985775155
Short name T35
Test name
Test status
Simulation time 136987440 ps
CPU time 4.35 seconds
Started May 23 03:47:23 PM PDT 24
Finished May 23 03:47:49 PM PDT 24
Peak memory 220284 kb
Host smart-0b3f0f63-c0c7-4a9b-b1d4-2530f6174c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985775155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3985775155
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1616802102
Short name T186
Test name
Test status
Simulation time 104649548 ps
CPU time 4.92 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 216380 kb
Host smart-8eccccb7-8df2-45c5-98a8-ddf8fa864e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616802102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1616802102
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.296573917
Short name T181
Test name
Test status
Simulation time 40152594 ps
CPU time 2.32 seconds
Started May 23 03:47:25 PM PDT 24
Finished May 23 03:47:48 PM PDT 24
Peak memory 217532 kb
Host smart-326c1296-165b-4cee-acb9-3d4055f010bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296573917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.296573917
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4039116792
Short name T310
Test name
Test status
Simulation time 44306675 ps
CPU time 1.93 seconds
Started May 23 03:44:26 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 214328 kb
Host smart-2a678a8e-3146-4622-882c-62a87b67925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039116792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4039116792
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3978271001
Short name T411
Test name
Test status
Simulation time 336786442 ps
CPU time 6.55 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:28 PM PDT 24
Peak memory 214352 kb
Host smart-6a755b90-d4a2-4f5f-abdf-5b41ba6293bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978271001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3978271001
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1539709498
Short name T481
Test name
Test status
Simulation time 307824727 ps
CPU time 3.69 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:44 PM PDT 24
Peak memory 208672 kb
Host smart-5ab4a328-952c-41f2-a722-c7e75eb6a805
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539709498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1539709498
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1142082491
Short name T277
Test name
Test status
Simulation time 2205895180 ps
CPU time 43.31 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:47:32 PM PDT 24
Peak memory 221236 kb
Host smart-b9dd4214-3761-4972-b842-3884b39cbd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142082491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1142082491
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.874089212
Short name T267
Test name
Test status
Simulation time 105144484 ps
CPU time 2.81 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 219576 kb
Host smart-e9fcd427-4119-41ac-9af3-b08c0d3f8c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874089212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.874089212
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.106295271
Short name T184
Test name
Test status
Simulation time 96122933 ps
CPU time 2.77 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 217800 kb
Host smart-2dead8a5-1dc2-4dc0-9c65-d5f6ccb297ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106295271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.106295271
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.915088946
Short name T170
Test name
Test status
Simulation time 269990884 ps
CPU time 2.64 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 210340 kb
Host smart-c54f6572-ffc5-4469-bee2-9c824854044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915088946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.915088946
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1710150171
Short name T167
Test name
Test status
Simulation time 408674676 ps
CPU time 6.41 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 214036 kb
Host smart-a6218430-76f6-4a7d-900b-5cf4477ed1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710150171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1710150171
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2528412850
Short name T285
Test name
Test status
Simulation time 5215484031 ps
CPU time 50.8 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 221548 kb
Host smart-2666e6bb-024a-4f2a-a935-b384ec3ea7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528412850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2528412850
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.122501007
Short name T311
Test name
Test status
Simulation time 37294118 ps
CPU time 2.39 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 214464 kb
Host smart-726f7d4c-c586-4d69-bba2-187ce289bad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122501007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.122501007
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2674215180
Short name T412
Test name
Test status
Simulation time 60288095 ps
CPU time 4.16 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 215276 kb
Host smart-c4c7294e-18da-49b9-a842-5ad2d82d386b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674215180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2674215180
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3950733726
Short name T289
Test name
Test status
Simulation time 4731948327 ps
CPU time 28.33 seconds
Started May 23 03:44:27 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 222744 kb
Host smart-28bb27ec-eff7-4148-9ea7-eb98844d9053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950733726 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3950733726
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3737583827
Short name T106
Test name
Test status
Simulation time 70427660 ps
CPU time 2.63 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:01 PM PDT 24
Peak memory 221340 kb
Host smart-c903a617-fa8b-4b5c-85e8-890919713477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737583827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3737583827
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1687429658
Short name T174
Test name
Test status
Simulation time 112305676 ps
CPU time 3.41 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:41 PM PDT 24
Peak memory 210520 kb
Host smart-05c7f9a5-7cce-4066-9f47-58a193bc98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687429658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1687429658
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.918285258
Short name T187
Test name
Test status
Simulation time 84943144 ps
CPU time 3.11 seconds
Started May 23 03:45:45 PM PDT 24
Finished May 23 03:46:14 PM PDT 24
Peak memory 222712 kb
Host smart-b5cab65c-5628-4d35-8da4-1d3eb0ba00ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918285258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.918285258
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3452946436
Short name T417
Test name
Test status
Simulation time 212611667 ps
CPU time 3.69 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 214320 kb
Host smart-b3a650fe-5c28-4c73-b47a-79e9229be15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452946436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3452946436
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3784683363
Short name T68
Test name
Test status
Simulation time 154240438 ps
CPU time 3.89 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 214424 kb
Host smart-ebb9fea5-0a92-46c6-9a2f-5fa0abe110d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784683363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3784683363
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3513356130
Short name T245
Test name
Test status
Simulation time 66864011 ps
CPU time 4.25 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 222528 kb
Host smart-2349ff2c-c5b7-4355-afba-b133ef6764a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513356130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3513356130
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2294837563
Short name T142
Test name
Test status
Simulation time 116524309 ps
CPU time 2.49 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 214304 kb
Host smart-d448a5fc-9f83-41b3-b6da-e19f4cbd2210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294837563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2294837563
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2938408726
Short name T819
Test name
Test status
Simulation time 398256666 ps
CPU time 3.55 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 209104 kb
Host smart-f3b3f7a1-7efc-44aa-856b-a91fbeaa7545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938408726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2938408726
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4088051501
Short name T301
Test name
Test status
Simulation time 449353550 ps
CPU time 10.87 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:07 PM PDT 24
Peak memory 215372 kb
Host smart-1c281d2c-16f8-49dc-b0af-edc337c7c441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088051501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4088051501
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3104865666
Short name T322
Test name
Test status
Simulation time 7988015144 ps
CPU time 56.07 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:47:50 PM PDT 24
Peak memory 222672 kb
Host smart-ee391868-250c-489a-b74c-f2a0505135b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104865666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3104865666
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1491929875
Short name T265
Test name
Test status
Simulation time 133380619 ps
CPU time 3.77 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 214284 kb
Host smart-9f10a641-8941-4cf0-840c-f4059cacdbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491929875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1491929875
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3908145086
Short name T358
Test name
Test status
Simulation time 74554678 ps
CPU time 2.75 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 222544 kb
Host smart-8b8eba3c-2076-4aa5-b9ee-06d93b9718db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908145086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3908145086
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2099827014
Short name T175
Test name
Test status
Simulation time 219875226 ps
CPU time 3.49 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 214316 kb
Host smart-85986f4a-7614-4fff-892c-ffa1ab01b6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099827014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2099827014
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2664989272
Short name T157
Test name
Test status
Simulation time 163987309 ps
CPU time 3.08 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 205784 kb
Host smart-725da8f1-4e47-4ab6-bcca-e7175577afce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664989272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2664989272
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3305860467
Short name T178
Test name
Test status
Simulation time 542816958 ps
CPU time 5.77 seconds
Started May 23 03:38:54 PM PDT 24
Finished May 23 03:39:03 PM PDT 24
Peak memory 214020 kb
Host smart-f79e9f26-6ebf-421f-b83a-d239273bb494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305860467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3305860467
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1263573715
Short name T165
Test name
Test status
Simulation time 55110243 ps
CPU time 3.05 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 214068 kb
Host smart-8c3464e1-f2e2-47e4-9482-4750b0349d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263573715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1263573715
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1631396056
Short name T159
Test name
Test status
Simulation time 101770726 ps
CPU time 5.45 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 214056 kb
Host smart-d5a0375e-3f8b-46c8-b634-479a49ed0f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631396056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1631396056
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2289949709
Short name T43
Test name
Test status
Simulation time 1470477318 ps
CPU time 10.47 seconds
Started May 23 03:45:56 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 210916 kb
Host smart-f59579cc-187e-42f0-8433-99d8c71033b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289949709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2289949709
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3394782740
Short name T189
Test name
Test status
Simulation time 144306630 ps
CPU time 3.16 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 222724 kb
Host smart-c51a39d7-00dd-44b5-b424-432270e02eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394782740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3394782740
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2407311720
Short name T14
Test name
Test status
Simulation time 413599009 ps
CPU time 6.21 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 237212 kb
Host smart-e0743876-b1f9-482f-b5fa-518b1c077d41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407311720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2407311720
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.351714033
Short name T180
Test name
Test status
Simulation time 1963956011 ps
CPU time 21.18 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:55 PM PDT 24
Peak memory 217932 kb
Host smart-71e16975-8794-4c8e-9bb3-9edfe92ccea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351714033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.351714033
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_smoke.715171216
Short name T16
Test name
Test status
Simulation time 250741548 ps
CPU time 3.38 seconds
Started May 23 03:44:10 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 208608 kb
Host smart-8e27ed13-92a2-4272-968a-bef78d30195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715171216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.715171216
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.982588834
Short name T6
Test name
Test status
Simulation time 91970202 ps
CPU time 3.29 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:41 PM PDT 24
Peak memory 208012 kb
Host smart-360415cc-4f56-47a9-908b-bbec3f438e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982588834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.982588834
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4226013718
Short name T278
Test name
Test status
Simulation time 540461435 ps
CPU time 6.64 seconds
Started May 23 03:45:27 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 210016 kb
Host smart-23c8e6d5-a8a2-4d10-9fd9-6ef7467aeb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226013718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4226013718
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1232215244
Short name T593
Test name
Test status
Simulation time 52293235 ps
CPU time 2.62 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 207536 kb
Host smart-5c368268-83db-4ab2-9cc0-63f20c543177
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232215244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1232215244
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3889671689
Short name T224
Test name
Test status
Simulation time 3346858618 ps
CPU time 9.61 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 222976 kb
Host smart-187b1834-8d26-496b-9598-7d18f8720613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889671689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3889671689
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2253203109
Short name T375
Test name
Test status
Simulation time 89936572 ps
CPU time 3.14 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:17 PM PDT 24
Peak memory 214332 kb
Host smart-58bf2d13-2a33-4c8e-929e-46c8d72c7247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253203109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2253203109
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1037107231
Short name T338
Test name
Test status
Simulation time 42817076 ps
CPU time 2 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 222504 kb
Host smart-230d1d85-5693-4cf9-a9af-d160f2811fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037107231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1037107231
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3472815705
Short name T362
Test name
Test status
Simulation time 3833950275 ps
CPU time 65.42 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 215524 kb
Host smart-04ca9094-916b-4d43-ab04-1c6c3a121c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472815705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3472815705
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1834071804
Short name T308
Test name
Test status
Simulation time 27905454 ps
CPU time 2.08 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:36 PM PDT 24
Peak memory 214300 kb
Host smart-1a1d1db2-3e09-46f1-84cc-f738f798a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834071804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1834071804
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.390275336
Short name T272
Test name
Test status
Simulation time 146765298 ps
CPU time 3.81 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:57 PM PDT 24
Peak memory 214460 kb
Host smart-b55e7796-bd8d-41b0-a76b-b5fc4140b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390275336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.390275336
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2376002099
Short name T334
Test name
Test status
Simulation time 47583265 ps
CPU time 2.1 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 214376 kb
Host smart-89bbb1ae-c3b1-4b55-92ac-a68922744ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376002099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2376002099
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3564210036
Short name T214
Test name
Test status
Simulation time 11400592895 ps
CPU time 135.32 seconds
Started May 23 03:46:38 PM PDT 24
Finished May 23 03:49:22 PM PDT 24
Peak memory 217600 kb
Host smart-2923cb39-029a-44c3-828f-f36aa9429379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564210036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3564210036
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.927608598
Short name T143
Test name
Test status
Simulation time 56166302 ps
CPU time 2.77 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 216820 kb
Host smart-d6955365-98f9-4183-b6d0-a1066ef028a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927608598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.927608598
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3127899238
Short name T298
Test name
Test status
Simulation time 96567828 ps
CPU time 4.21 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 208896 kb
Host smart-b5c54f26-bd79-412e-b8b2-86f8fecc51e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127899238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3127899238
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3810334170
Short name T134
Test name
Test status
Simulation time 219168781 ps
CPU time 9.27 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 220396 kb
Host smart-06ada971-6877-4552-9b66-4c5bffca4de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810334170 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3810334170
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1767790402
Short name T182
Test name
Test status
Simulation time 112361566 ps
CPU time 2.82 seconds
Started May 23 03:46:52 PM PDT 24
Finished May 23 03:47:24 PM PDT 24
Peak memory 222736 kb
Host smart-294d407f-7513-474f-8976-357ff1c0d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767790402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1767790402
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3170864195
Short name T929
Test name
Test status
Simulation time 1505343759 ps
CPU time 14.03 seconds
Started May 23 03:39:05 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205808 kb
Host smart-0a838421-78a3-421c-a0bb-c9ab1efa0001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170864195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
170864195
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1112876548
Short name T997
Test name
Test status
Simulation time 602300374 ps
CPU time 8.43 seconds
Started May 23 03:38:56 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 205872 kb
Host smart-22b34602-5abd-4282-a4be-e0ddeca1cd8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112876548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
112876548
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2164654605
Short name T954
Test name
Test status
Simulation time 69217183 ps
CPU time 1.18 seconds
Started May 23 03:39:06 PM PDT 24
Finished May 23 03:39:12 PM PDT 24
Peak memory 205860 kb
Host smart-cff64a2b-6ea0-428a-a9a7-1e3bde577f96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164654605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
164654605
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4160285021
Short name T196
Test name
Test status
Simulation time 30992154 ps
CPU time 1.56 seconds
Started May 23 03:39:06 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214152 kb
Host smart-0d09c1a4-b5ec-4a02-a5fb-ee438fb5b716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160285021 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4160285021
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2929214664
Short name T145
Test name
Test status
Simulation time 96848837 ps
CPU time 1.04 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 205816 kb
Host smart-7a2b8377-46df-4cc5-90b4-9573273ded73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929214664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2929214664
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2623818593
Short name T1044
Test name
Test status
Simulation time 118004170 ps
CPU time 0.75 seconds
Started May 23 03:39:04 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 205512 kb
Host smart-0b0a1217-9f21-468a-9300-5b44f57acd84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623818593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2623818593
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2712351260
Short name T1002
Test name
Test status
Simulation time 44846458 ps
CPU time 2.22 seconds
Started May 23 03:38:52 PM PDT 24
Finished May 23 03:38:58 PM PDT 24
Peak memory 205820 kb
Host smart-c7b21edc-a1ad-4e2d-81b4-c9519e4ef51a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712351260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2712351260
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.506941888
Short name T957
Test name
Test status
Simulation time 202023359 ps
CPU time 4.91 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:04 PM PDT 24
Peak memory 214328 kb
Host smart-cd022fcb-6692-4157-a65b-734b7a4b0381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506941888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.506941888
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1282120
Short name T1038
Test name
Test status
Simulation time 319395979 ps
CPU time 5.07 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:04 PM PDT 24
Peak memory 214304 kb
Host smart-fb7cdad2-376f-48ea-b30b-38fbcd8021ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_S
EQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.key
mgr_shadow_reg_errors_with_csr_rw.1282120
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1815881296
Short name T990
Test name
Test status
Simulation time 283764945 ps
CPU time 2.92 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 214008 kb
Host smart-a88d3e1e-4548-4c9f-acb0-819e431140ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815881296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1815881296
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3228636990
Short name T925
Test name
Test status
Simulation time 262215869 ps
CPU time 4.16 seconds
Started May 23 03:38:54 PM PDT 24
Finished May 23 03:39:01 PM PDT 24
Peak memory 205844 kb
Host smart-0455edd0-aa59-4f48-9a16-06ac00f217b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228636990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
228636990
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.68253879
Short name T1075
Test name
Test status
Simulation time 469593928 ps
CPU time 7.95 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 205896 kb
Host smart-ede0e867-f827-431b-8446-012c9e54185d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68253879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.68253879
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4150353431
Short name T1000
Test name
Test status
Simulation time 20261376 ps
CPU time 0.94 seconds
Started May 23 03:38:54 PM PDT 24
Finished May 23 03:38:59 PM PDT 24
Peak memory 205708 kb
Host smart-e58faf93-f0bf-4ab0-b88e-8c74a085e86b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150353431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
150353431
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1916445127
Short name T992
Test name
Test status
Simulation time 70151672 ps
CPU time 1.49 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:01 PM PDT 24
Peak memory 214048 kb
Host smart-7dbf61fc-3ecf-41a8-be39-9448dcc31bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916445127 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1916445127
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.642326989
Short name T950
Test name
Test status
Simulation time 22111462 ps
CPU time 1.13 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 205760 kb
Host smart-17cf24d9-13da-499f-982a-6420fd3a8e8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642326989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.642326989
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2678881904
Short name T1079
Test name
Test status
Simulation time 15165312 ps
CPU time 0.77 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:07 PM PDT 24
Peak memory 205572 kb
Host smart-09219d18-68ce-44cb-80a8-f20def4cf89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678881904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2678881904
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.705561544
Short name T973
Test name
Test status
Simulation time 27038816 ps
CPU time 1.53 seconds
Started May 23 03:38:57 PM PDT 24
Finished May 23 03:39:03 PM PDT 24
Peak memory 205820 kb
Host smart-91acda52-a61e-455b-91af-a8db7f2bcdb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705561544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.705561544
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3993438164
Short name T961
Test name
Test status
Simulation time 183384674 ps
CPU time 1.72 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 214320 kb
Host smart-c94b40d1-2b0b-452e-8e72-db3d85abec73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993438164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3993438164
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1340732274
Short name T1032
Test name
Test status
Simulation time 38362552 ps
CPU time 2.21 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:01 PM PDT 24
Peak memory 214180 kb
Host smart-5789f293-0586-4b12-a3d6-8ef2daed1c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340732274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1340732274
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3638229929
Short name T173
Test name
Test status
Simulation time 188983555 ps
CPU time 2.99 seconds
Started May 23 03:38:58 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 205864 kb
Host smart-cac795b6-386c-454d-a2e0-9fdf49896442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638229929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3638229929
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3453510431
Short name T1071
Test name
Test status
Simulation time 41291668 ps
CPU time 1.5 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 214244 kb
Host smart-0a80790d-41c1-4c10-8a3c-cfad867b1c9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453510431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3453510431
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3336429385
Short name T917
Test name
Test status
Simulation time 28476382 ps
CPU time 0.88 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 205648 kb
Host smart-8c9fc163-5453-4460-a459-5cb5b61e30ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336429385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3336429385
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.364236533
Short name T1061
Test name
Test status
Simulation time 18868368 ps
CPU time 0.78 seconds
Started May 23 03:39:04 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 205532 kb
Host smart-7d17bda9-5bf5-43df-adce-b47c07deb19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364236533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.364236533
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1676340408
Short name T1007
Test name
Test status
Simulation time 109313649 ps
CPU time 2.02 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:31 PM PDT 24
Peak memory 205852 kb
Host smart-23889283-bfef-4529-9377-c2031f063f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676340408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1676340408
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4043665065
Short name T939
Test name
Test status
Simulation time 478620980 ps
CPU time 4.15 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 214432 kb
Host smart-8ffce7d2-948d-46b9-9e7f-5e9cf1b8455b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043665065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4043665065
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1258009904
Short name T127
Test name
Test status
Simulation time 158734701 ps
CPU time 4.59 seconds
Started May 23 03:39:04 PM PDT 24
Finished May 23 03:39:14 PM PDT 24
Peak memory 214296 kb
Host smart-82c70376-3b44-42e4-af53-1fbd0cf29f65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258009904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1258009904
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.232623602
Short name T1030
Test name
Test status
Simulation time 94287253 ps
CPU time 2.85 seconds
Started May 23 03:39:05 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214056 kb
Host smart-dda97b09-53ae-465d-89bd-4655b0d3db58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232623602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.232623602
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2728817299
Short name T158
Test name
Test status
Simulation time 120311160 ps
CPU time 3.64 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 205712 kb
Host smart-db4386ed-4944-4c82-abc1-df008b79977e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728817299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2728817299
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2366812481
Short name T190
Test name
Test status
Simulation time 116774939 ps
CPU time 1.51 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:14 PM PDT 24
Peak memory 214076 kb
Host smart-dc0856c8-181f-45d6-a4d8-73eb6a94a23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366812481 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2366812481
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4064186639
Short name T149
Test name
Test status
Simulation time 44214481 ps
CPU time 1.2 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205868 kb
Host smart-1993518f-df81-4fcf-86aa-074599ff4135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064186639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4064186639
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1652857386
Short name T955
Test name
Test status
Simulation time 8152894 ps
CPU time 0.7 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205476 kb
Host smart-39125114-5aa6-4d2f-b9f5-2494e79b50a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652857386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1652857386
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.165832577
Short name T1072
Test name
Test status
Simulation time 81493222 ps
CPU time 2.4 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205800 kb
Host smart-5b53ad14-a7b3-4b31-90c0-281c025cb1cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165832577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.165832577
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4042310800
Short name T927
Test name
Test status
Simulation time 169819074 ps
CPU time 4.67 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 214468 kb
Host smart-bd55b61a-299d-4892-84c4-4284dc453331
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042310800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4042310800
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3624072075
Short name T985
Test name
Test status
Simulation time 325261001 ps
CPU time 6.64 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 214472 kb
Host smart-8b1d9f17-8f89-4632-8942-b95fd3b00f82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624072075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3624072075
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1325885015
Short name T1064
Test name
Test status
Simulation time 137361989 ps
CPU time 2.99 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 216472 kb
Host smart-f7eddef9-fd4b-45c4-8694-5166078ff7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325885015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1325885015
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2640341238
Short name T953
Test name
Test status
Simulation time 98823946 ps
CPU time 1.06 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205800 kb
Host smart-559c3d7f-3a2d-4338-aabc-eda734cd16f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640341238 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2640341238
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.595843976
Short name T951
Test name
Test status
Simulation time 28683047 ps
CPU time 1.41 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 205808 kb
Host smart-f4180791-b34a-41d0-af93-337dea02c3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595843976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.595843976
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3276435899
Short name T1068
Test name
Test status
Simulation time 48031563 ps
CPU time 0.84 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 205584 kb
Host smart-1be9466d-ccdc-43c5-9a62-7ab021187849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276435899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3276435899
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.463368154
Short name T146
Test name
Test status
Simulation time 525618116 ps
CPU time 3.72 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 205868 kb
Host smart-204260f1-f6c9-4a9a-8b86-bda87f3e6982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463368154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.463368154
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1499539526
Short name T1056
Test name
Test status
Simulation time 76350135 ps
CPU time 2.01 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:26 PM PDT 24
Peak memory 214428 kb
Host smart-c404a139-2a13-4d77-abf8-74439de7e084
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499539526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1499539526
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3052432392
Short name T931
Test name
Test status
Simulation time 1141685981 ps
CPU time 7.73 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 214432 kb
Host smart-f7516ea7-0df2-46b5-b5a9-d8580ce0c429
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052432392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3052432392
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3203890010
Short name T1036
Test name
Test status
Simulation time 97164697 ps
CPU time 1.53 seconds
Started May 23 03:39:03 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 214040 kb
Host smart-f574a0d6-33eb-4084-b508-d157b5ac51f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203890010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3203890010
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.860993584
Short name T1058
Test name
Test status
Simulation time 140003338 ps
CPU time 1.22 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 205816 kb
Host smart-0af74cc1-df23-4aa0-a5c4-42e1b04ce08b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860993584 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.860993584
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4202669263
Short name T984
Test name
Test status
Simulation time 40146510 ps
CPU time 1.06 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:20 PM PDT 24
Peak memory 205852 kb
Host smart-fdb6ced1-788d-4317-aca7-ab441f215c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202669263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4202669263
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3927931425
Short name T1054
Test name
Test status
Simulation time 20802351 ps
CPU time 0.71 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205588 kb
Host smart-c149b65c-2d1d-47df-8d89-ee62b81ff471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927931425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3927931425
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.109845682
Short name T937
Test name
Test status
Simulation time 64147756 ps
CPU time 1.84 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 205820 kb
Host smart-cb91d385-a5c4-4b46-aa26-1c87c495d866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109845682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.109845682
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2906492711
Short name T932
Test name
Test status
Simulation time 219495532 ps
CPU time 2.2 seconds
Started May 23 03:39:06 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214464 kb
Host smart-269d95ee-e609-46c8-bfa2-4972ad471116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906492711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2906492711
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1627643718
Short name T1045
Test name
Test status
Simulation time 420578597 ps
CPU time 14.05 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 214272 kb
Host smart-019e148a-6eeb-4831-bdfd-d51a87b9cf33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627643718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1627643718
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3496478784
Short name T977
Test name
Test status
Simulation time 417734524 ps
CPU time 4.1 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 216152 kb
Host smart-9caa9633-67b6-4c52-9b9b-af11d13c23e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496478784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3496478784
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.711095698
Short name T952
Test name
Test status
Simulation time 116327813 ps
CPU time 1.75 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:14 PM PDT 24
Peak memory 214228 kb
Host smart-5f524b9e-bcc5-4489-827c-ccfbf0b826f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711095698 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.711095698
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1453638777
Short name T1065
Test name
Test status
Simulation time 66695223 ps
CPU time 1.16 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 205764 kb
Host smart-53ba8e84-ed0e-4de9-971c-991b0838ffc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453638777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1453638777
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2837569751
Short name T1006
Test name
Test status
Simulation time 10106824 ps
CPU time 0.83 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205576 kb
Host smart-e2a84d62-e7be-482a-84ef-b25e38c742f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837569751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2837569751
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3734535716
Short name T1026
Test name
Test status
Simulation time 138341246 ps
CPU time 3.02 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 205808 kb
Host smart-55c57796-85ab-486d-827d-a203c0860e30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734535716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3734535716
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1083135472
Short name T128
Test name
Test status
Simulation time 68084992 ps
CPU time 1.6 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:20 PM PDT 24
Peak memory 214328 kb
Host smart-0feb62bb-41a2-4102-96e9-bcdeac41cea8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083135472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1083135472
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2157799679
Short name T1050
Test name
Test status
Simulation time 1759988882 ps
CPU time 10.44 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 214412 kb
Host smart-ceae0414-d6e7-451a-95b9-bbc870287297
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157799679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2157799679
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.162128900
Short name T974
Test name
Test status
Simulation time 63747870 ps
CPU time 2.81 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 214068 kb
Host smart-3b9b8b2a-e6bc-4b07-a138-1caa3cfa0e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162128900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.162128900
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2700081704
Short name T1012
Test name
Test status
Simulation time 1019895936 ps
CPU time 4.07 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 213964 kb
Host smart-bf86f07a-f5e9-4ef9-a9ec-118ba88b31f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700081704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2700081704
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3936527074
Short name T922
Test name
Test status
Simulation time 17267803 ps
CPU time 1.04 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 205608 kb
Host smart-c4ff239b-c7aa-4408-9766-ab5cafcf7d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936527074 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3936527074
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.733546264
Short name T1069
Test name
Test status
Simulation time 54964842 ps
CPU time 1.09 seconds
Started May 23 03:39:09 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 205824 kb
Host smart-c2427c7e-8d61-4305-bc10-88b7c2f7aba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733546264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.733546264
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2405720226
Short name T965
Test name
Test status
Simulation time 40586662 ps
CPU time 0.69 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205484 kb
Host smart-1e306770-5349-4ec1-bc86-441809d15bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405720226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2405720226
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.461683764
Short name T1033
Test name
Test status
Simulation time 226258361 ps
CPU time 3.93 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205824 kb
Host smart-19dca149-cd87-410f-af78-a55f9f4fd737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461683764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.461683764
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1496659825
Short name T993
Test name
Test status
Simulation time 252531751 ps
CPU time 2.2 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 214352 kb
Host smart-1006f6ff-717b-464d-8c7c-8f58f10dbe3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496659825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1496659825
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3035387795
Short name T968
Test name
Test status
Simulation time 212529845 ps
CPU time 3.75 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:11 PM PDT 24
Peak memory 214348 kb
Host smart-2c7b5f50-de9a-4dc4-bd0b-7708988143d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035387795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3035387795
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2609756183
Short name T975
Test name
Test status
Simulation time 23522543 ps
CPU time 1.85 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 214740 kb
Host smart-689432bb-dd25-48ba-aa4f-ab11c15e1b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609756183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2609756183
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.152787428
Short name T1028
Test name
Test status
Simulation time 269124299 ps
CPU time 6.66 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 214020 kb
Host smart-c7c98388-1c7b-41d4-baf2-20e2e832eacf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152787428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.152787428
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3640342074
Short name T1046
Test name
Test status
Simulation time 34152590 ps
CPU time 1.97 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 214176 kb
Host smart-5a735112-558f-4545-820d-7f6a92c94ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640342074 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3640342074
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1209454884
Short name T1052
Test name
Test status
Simulation time 28578970 ps
CPU time 1.23 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205972 kb
Host smart-20b8c23b-0866-401d-8e5b-7b33fb48a6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209454884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1209454884
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3352951994
Short name T982
Test name
Test status
Simulation time 35258876 ps
CPU time 0.71 seconds
Started May 23 03:39:20 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205476 kb
Host smart-3b5267af-3839-4679-996e-05686aec955d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352951994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3352951994
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3535694324
Short name T928
Test name
Test status
Simulation time 22432333 ps
CPU time 1.33 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205820 kb
Host smart-f3798963-769a-40fd-9ac2-7c7273d82772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535694324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3535694324
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1133882886
Short name T934
Test name
Test status
Simulation time 46888525 ps
CPU time 1.96 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:28 PM PDT 24
Peak memory 214404 kb
Host smart-2dd1dea3-ae83-4d6c-98f6-918f6255ab38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133882886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1133882886
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3521524517
Short name T126
Test name
Test status
Simulation time 4428527140 ps
CPU time 15.23 seconds
Started May 23 03:39:05 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 214372 kb
Host smart-21cb35bb-cd46-456a-98b2-9343694d4f1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521524517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3521524517
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2223053896
Short name T1059
Test name
Test status
Simulation time 410611836 ps
CPU time 2.45 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 214008 kb
Host smart-33e64904-5519-4114-8a06-da6fe1f7a34e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223053896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2223053896
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1592763705
Short name T941
Test name
Test status
Simulation time 107772285 ps
CPU time 1.57 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:17 PM PDT 24
Peak memory 216792 kb
Host smart-ae9f491e-a3ee-471e-a625-acf387a5ff59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592763705 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1592763705
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1575345528
Short name T148
Test name
Test status
Simulation time 22766435 ps
CPU time 1.08 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 205832 kb
Host smart-add2ab53-9f3b-4c97-92d5-114bfbad62bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575345528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1575345528
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.331099097
Short name T918
Test name
Test status
Simulation time 10743118 ps
CPU time 0.8 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 205592 kb
Host smart-b9535865-5998-4ffd-825f-9766732a9519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331099097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.331099097
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3649467006
Short name T936
Test name
Test status
Simulation time 105757645 ps
CPU time 3.88 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:29 PM PDT 24
Peak memory 205716 kb
Host smart-54d60e53-e36b-4b09-9909-ba97dbf97c73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649467006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3649467006
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1341631653
Short name T1042
Test name
Test status
Simulation time 525812049 ps
CPU time 2.49 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 214440 kb
Host smart-2f4b68ad-f737-41eb-b946-bf93028f3ac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341631653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1341631653
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2364462787
Short name T1018
Test name
Test status
Simulation time 228102127 ps
CPU time 7.7 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 214348 kb
Host smart-e2ff9f8c-de64-4951-a7c8-a5106bacd03c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364462787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2364462787
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3300348134
Short name T1015
Test name
Test status
Simulation time 39360053 ps
CPU time 2.14 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:31 PM PDT 24
Peak memory 217520 kb
Host smart-6ccd015c-5b2b-4ebc-990d-1df687546cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300348134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3300348134
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.671481356
Short name T172
Test name
Test status
Simulation time 690817071 ps
CPU time 2.86 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 214740 kb
Host smart-3c7ce7ed-00af-4b0c-a8e8-a246a09e4277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671481356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.671481356
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3042397003
Short name T996
Test name
Test status
Simulation time 29180034 ps
CPU time 1.51 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:38 PM PDT 24
Peak memory 205820 kb
Host smart-b7053dab-8f36-453b-9e7f-923bde849351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042397003 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3042397003
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1709065752
Short name T926
Test name
Test status
Simulation time 39787916 ps
CPU time 0.88 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205692 kb
Host smart-9ba613bb-b9bf-4330-8dea-9baedb4644bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709065752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1709065752
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3082632356
Short name T1081
Test name
Test status
Simulation time 10491112 ps
CPU time 0.68 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 205512 kb
Host smart-a1a68834-7af3-4e03-a048-f04fd8a10f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082632356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3082632356
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2925067293
Short name T1066
Test name
Test status
Simulation time 82963198 ps
CPU time 1.61 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:38 PM PDT 24
Peak memory 205752 kb
Host smart-f941c658-b0dd-4e4a-8e1d-ccdcf70afc58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925067293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2925067293
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1689236523
Short name T938
Test name
Test status
Simulation time 169827837 ps
CPU time 3.11 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:29 PM PDT 24
Peak memory 214392 kb
Host smart-b25b451f-174a-4ca8-934e-839ce02e00f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689236523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1689236523
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3965712819
Short name T1020
Test name
Test status
Simulation time 213635034 ps
CPU time 6.39 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:36 PM PDT 24
Peak memory 214348 kb
Host smart-968b9a3d-d758-4675-9cb8-2c99883d3e6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965712819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3965712819
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1430122810
Short name T944
Test name
Test status
Simulation time 155800143 ps
CPU time 2.24 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 214060 kb
Host smart-16076b75-6a69-4ec3-90a6-ac5ac5612b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430122810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1430122810
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3067096173
Short name T1063
Test name
Test status
Simulation time 202486408 ps
CPU time 1.87 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 214068 kb
Host smart-802a76b7-ec18-4a0b-92d9-e778230ee7c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067096173 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3067096173
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3072073758
Short name T1014
Test name
Test status
Simulation time 28220697 ps
CPU time 1.11 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205792 kb
Host smart-ba9dde93-23eb-4025-b132-955fabc670fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072073758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3072073758
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2412343475
Short name T991
Test name
Test status
Simulation time 38317612 ps
CPU time 0.78 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205560 kb
Host smart-32051c64-16e7-4b85-a602-5fd4e275d298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412343475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2412343475
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2247197250
Short name T946
Test name
Test status
Simulation time 96147947 ps
CPU time 2.68 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:29 PM PDT 24
Peak memory 214012 kb
Host smart-891e38fc-8069-4e4d-9ac1-839d462645d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247197250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2247197250
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1751667192
Short name T964
Test name
Test status
Simulation time 243981945 ps
CPU time 1.54 seconds
Started May 23 03:39:18 PM PDT 24
Finished May 23 03:39:29 PM PDT 24
Peak memory 214328 kb
Host smart-12f23878-57ac-4ae1-8aba-1643d2bf9d75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751667192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1751667192
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3702394986
Short name T966
Test name
Test status
Simulation time 63759635 ps
CPU time 2.67 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:32 PM PDT 24
Peak memory 214012 kb
Host smart-b26d5842-caff-4d4f-a8d7-b268caece4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702394986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3702394986
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1860418378
Short name T168
Test name
Test status
Simulation time 71647311 ps
CPU time 2.6 seconds
Started May 23 03:39:09 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 205808 kb
Host smart-d3eab8da-de6b-4697-9771-1a1dbcef2ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860418378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1860418378
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3998882841
Short name T1010
Test name
Test status
Simulation time 1832753163 ps
CPU time 12.46 seconds
Started May 23 03:39:09 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 205800 kb
Host smart-e9fa5903-3dc4-4ec6-b7b2-ca98b7df1763
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998882841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
998882841
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.66374352
Short name T987
Test name
Test status
Simulation time 5354036456 ps
CPU time 16.07 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:41 PM PDT 24
Peak memory 205824 kb
Host smart-c69d0861-73fa-4e6d-8a84-7f87f1a35dce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66374352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.66374352
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3270864269
Short name T945
Test name
Test status
Simulation time 153019918 ps
CPU time 1.19 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:36 PM PDT 24
Peak memory 205728 kb
Host smart-95f01387-80ec-4fcc-9939-d9266d0f26af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270864269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
270864269
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1953158142
Short name T980
Test name
Test status
Simulation time 223254646 ps
CPU time 1.65 seconds
Started May 23 03:38:52 PM PDT 24
Finished May 23 03:38:58 PM PDT 24
Peak memory 214036 kb
Host smart-2d712dc5-2ef2-45ee-aba7-8134fc8cfa82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953158142 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1953158142
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2498090310
Short name T144
Test name
Test status
Simulation time 10917917 ps
CPU time 0.89 seconds
Started May 23 03:38:57 PM PDT 24
Finished May 23 03:39:02 PM PDT 24
Peak memory 205552 kb
Host smart-6c7f1e5b-15ef-4651-a0e2-063b973890f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498090310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2498090310
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.835652809
Short name T1022
Test name
Test status
Simulation time 53326993 ps
CPU time 0.68 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:29 PM PDT 24
Peak memory 205544 kb
Host smart-973fb3e7-98b3-4457-af5d-9f1cb84b19ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835652809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.835652809
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1178649670
Short name T998
Test name
Test status
Simulation time 500859470 ps
CPU time 1.69 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 205712 kb
Host smart-91b57577-6acb-4ad8-a9e3-0332823ef0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178649670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1178649670
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4252624226
Short name T940
Test name
Test status
Simulation time 434065622 ps
CPU time 3.83 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:03 PM PDT 24
Peak memory 214328 kb
Host smart-e74a504a-1b85-4e21-92ac-5ad3133a2816
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252624226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4252624226
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3322540492
Short name T1077
Test name
Test status
Simulation time 900155613 ps
CPU time 7.58 seconds
Started May 23 03:38:59 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214272 kb
Host smart-de4b947e-3f9b-4c9f-b9a1-72096b18875f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322540492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3322540492
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3679852370
Short name T921
Test name
Test status
Simulation time 123508219 ps
CPU time 4.65 seconds
Started May 23 03:38:54 PM PDT 24
Finished May 23 03:39:02 PM PDT 24
Peak memory 213972 kb
Host smart-d0dc4064-a07f-4c7a-8f09-b9b1d25ce0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679852370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3679852370
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2153963446
Short name T948
Test name
Test status
Simulation time 9737023 ps
CPU time 0.81 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205508 kb
Host smart-fbd4415a-b81c-4e10-a98b-444484097472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153963446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2153963446
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1433368577
Short name T1062
Test name
Test status
Simulation time 42332932 ps
CPU time 0.81 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 205488 kb
Host smart-da4a1cde-b28d-4d7e-a2fd-5dcb370c37b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433368577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1433368577
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2937583327
Short name T949
Test name
Test status
Simulation time 9288557 ps
CPU time 0.77 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:33 PM PDT 24
Peak memory 205500 kb
Host smart-48c91a79-b5bb-44fa-ae01-be011399d1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937583327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2937583327
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2281505098
Short name T967
Test name
Test status
Simulation time 24350273 ps
CPU time 0.85 seconds
Started May 23 03:39:34 PM PDT 24
Finished May 23 03:39:42 PM PDT 24
Peak memory 205516 kb
Host smart-e4e0e6f3-63c4-4f15-bca6-d84f74023c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281505098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2281505098
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1264559045
Short name T923
Test name
Test status
Simulation time 51655144 ps
CPU time 0.88 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:17 PM PDT 24
Peak memory 205520 kb
Host smart-397e0d5e-2dd9-4d77-a056-127d0edcfdaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264559045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1264559045
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1893922416
Short name T972
Test name
Test status
Simulation time 43190161 ps
CPU time 0.68 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 205568 kb
Host smart-7a414f89-b7be-4d47-8470-b56280656117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893922416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1893922416
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2088282861
Short name T1027
Test name
Test status
Simulation time 12396734 ps
CPU time 0.71 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 205400 kb
Host smart-6eafd7ea-5fd6-4f3f-9511-28029feed9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088282861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2088282861
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1014179931
Short name T969
Test name
Test status
Simulation time 18537511 ps
CPU time 0.77 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205568 kb
Host smart-d0f558aa-4ecc-46f3-8993-10a17ccc3da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014179931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1014179931
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.129794788
Short name T1019
Test name
Test status
Simulation time 17668644 ps
CPU time 0.68 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:32 PM PDT 24
Peak memory 205540 kb
Host smart-e44422b0-55e0-416e-897d-b50d63cafbfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129794788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.129794788
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1467969795
Short name T930
Test name
Test status
Simulation time 13178005 ps
CPU time 0.72 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:20 PM PDT 24
Peak memory 205592 kb
Host smart-535972a1-94b8-410b-bac9-58ec983317c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467969795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1467969795
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3158592698
Short name T947
Test name
Test status
Simulation time 200636269 ps
CPU time 6.66 seconds
Started May 23 03:39:16 PM PDT 24
Finished May 23 03:39:31 PM PDT 24
Peak memory 205804 kb
Host smart-1bf1cade-732b-4282-a5f4-9b493e3e072b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158592698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
158592698
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.724814058
Short name T1073
Test name
Test status
Simulation time 2089519493 ps
CPU time 14.63 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:43 PM PDT 24
Peak memory 205804 kb
Host smart-f50cc836-1adb-442c-99d2-19d98fe20c7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724814058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.724814058
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.6361089
Short name T981
Test name
Test status
Simulation time 44011076 ps
CPU time 1.12 seconds
Started May 23 03:38:58 PM PDT 24
Finished May 23 03:39:04 PM PDT 24
Peak memory 205844 kb
Host smart-83232de9-a01c-4da1-86b4-1c3348e205e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6361089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.6361089
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1629268936
Short name T920
Test name
Test status
Simulation time 41252674 ps
CPU time 1.57 seconds
Started May 23 03:38:59 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 214260 kb
Host smart-3164d1ea-269f-4a2c-8801-808a10d0e07a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629268936 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1629268936
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3361880715
Short name T956
Test name
Test status
Simulation time 11109577 ps
CPU time 0.99 seconds
Started May 23 03:38:58 PM PDT 24
Finished May 23 03:39:04 PM PDT 24
Peak memory 205736 kb
Host smart-dfa4321b-926e-4fbf-9dee-2eb3dde5347a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361880715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3361880715
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.980474023
Short name T989
Test name
Test status
Simulation time 40363059 ps
CPU time 0.74 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 205464 kb
Host smart-3267659c-f582-4b6c-82e1-663dfb7a4609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980474023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.980474023
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3357545384
Short name T1067
Test name
Test status
Simulation time 119045942 ps
CPU time 3.13 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 205560 kb
Host smart-8031da16-32be-4cc9-a1ca-ed79e6160c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357545384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3357545384
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.206629061
Short name T960
Test name
Test status
Simulation time 628475876 ps
CPU time 1.98 seconds
Started May 23 03:38:59 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 214444 kb
Host smart-26ae4ec1-5be3-4625-9d1e-2a1ef1c63bb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206629061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.206629061
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.685690081
Short name T942
Test name
Test status
Simulation time 491690819 ps
CPU time 9.62 seconds
Started May 23 03:38:55 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 214364 kb
Host smart-1e4344fa-108f-44fa-a5af-c70177aba3ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685690081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.685690081
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2094854766
Short name T1047
Test name
Test status
Simulation time 102683704 ps
CPU time 2.41 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 222196 kb
Host smart-5ffe42d0-503e-44b5-80e1-86db63a90596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094854766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2094854766
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2815442173
Short name T162
Test name
Test status
Simulation time 214785496 ps
CPU time 5.98 seconds
Started May 23 03:39:03 PM PDT 24
Finished May 23 03:39:14 PM PDT 24
Peak memory 214024 kb
Host smart-ffc4087b-8d0c-406f-8e45-dd0724fdd94f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815442173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2815442173
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.830113410
Short name T1004
Test name
Test status
Simulation time 12643585 ps
CPU time 0.86 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205580 kb
Host smart-ea7e5bd5-eba4-4b66-9661-40fe926b54cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830113410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.830113410
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2829827937
Short name T1049
Test name
Test status
Simulation time 16291663 ps
CPU time 0.81 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 205588 kb
Host smart-96c5dc97-cf20-43cc-b621-51863ce98afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829827937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2829827937
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3634073512
Short name T1013
Test name
Test status
Simulation time 18222185 ps
CPU time 0.8 seconds
Started May 23 03:39:18 PM PDT 24
Finished May 23 03:39:28 PM PDT 24
Peak memory 205620 kb
Host smart-ce81e1f9-c29d-49e9-99f2-98e65c486f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634073512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3634073512
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.180745006
Short name T976
Test name
Test status
Simulation time 13245407 ps
CPU time 0.72 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205476 kb
Host smart-aedd3d5f-a022-4805-ba98-f7b6a4631e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180745006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.180745006
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2754607603
Short name T943
Test name
Test status
Simulation time 23606208 ps
CPU time 0.9 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205552 kb
Host smart-7d71173d-1d83-4030-9065-bea57b451d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754607603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2754607603
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.663303705
Short name T999
Test name
Test status
Simulation time 10714510 ps
CPU time 0.7 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:33 PM PDT 24
Peak memory 205588 kb
Host smart-9b603544-26ee-4019-b31b-7af43cba9389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663303705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.663303705
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2798546964
Short name T994
Test name
Test status
Simulation time 24020466 ps
CPU time 0.71 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205556 kb
Host smart-af97e0bf-9a7e-4cf7-9a5a-9c2041e2fd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798546964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2798546964
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.831156720
Short name T1078
Test name
Test status
Simulation time 30349699 ps
CPU time 0.69 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:33 PM PDT 24
Peak memory 205564 kb
Host smart-7ce675db-d1fc-467d-9106-62ed681ccefc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831156720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.831156720
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3702812289
Short name T1021
Test name
Test status
Simulation time 12487517 ps
CPU time 0.85 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205552 kb
Host smart-f84f6229-25bb-4460-9b54-3cf4208cef5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702812289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3702812289
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1364625894
Short name T1029
Test name
Test status
Simulation time 8972430 ps
CPU time 0.82 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 205516 kb
Host smart-41a710d7-bd08-4b32-b992-db96a3c151bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364625894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1364625894
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3012637396
Short name T1023
Test name
Test status
Simulation time 854177963 ps
CPU time 4.36 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 205732 kb
Host smart-f07a8ab3-802a-4147-ac53-70332d62b0f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012637396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
012637396
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.860687709
Short name T153
Test name
Test status
Simulation time 265981088 ps
CPU time 11.55 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205848 kb
Host smart-05583843-60a3-4e5e-a042-9bbef55924e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860687709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.860687709
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1959964640
Short name T1011
Test name
Test status
Simulation time 27165081 ps
CPU time 0.93 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 205732 kb
Host smart-612cdade-eade-4ba2-b2ec-c48a966e99de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959964640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
959964640
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3681838179
Short name T1016
Test name
Test status
Simulation time 42819922 ps
CPU time 1.85 seconds
Started May 23 03:38:57 PM PDT 24
Finished May 23 03:39:03 PM PDT 24
Peak memory 213972 kb
Host smart-ce3d200f-1a6a-4237-ab19-6b0a634907cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681838179 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3681838179
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3160111398
Short name T1035
Test name
Test status
Simulation time 35737322 ps
CPU time 0.96 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205648 kb
Host smart-61744344-9e01-4e63-885b-a73adcfbfaa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160111398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3160111398
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2104571072
Short name T1048
Test name
Test status
Simulation time 13813312 ps
CPU time 0.84 seconds
Started May 23 03:38:58 PM PDT 24
Finished May 23 03:39:04 PM PDT 24
Peak memory 205528 kb
Host smart-25fc159f-65de-49ef-8bae-7a24691f1afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104571072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2104571072
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3579973911
Short name T1040
Test name
Test status
Simulation time 85351704 ps
CPU time 1.73 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205744 kb
Host smart-301eb563-f572-4ec0-b453-3d0539b04515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579973911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3579973911
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2133957308
Short name T983
Test name
Test status
Simulation time 75798245 ps
CPU time 1.68 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 214368 kb
Host smart-686fb4e0-cf44-46ce-aca2-3328a7f9b346
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133957308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2133957308
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4059777366
Short name T963
Test name
Test status
Simulation time 350514024 ps
CPU time 13.41 seconds
Started May 23 03:39:09 PM PDT 24
Finished May 23 03:39:28 PM PDT 24
Peak memory 220584 kb
Host smart-341abb41-b4d2-4083-8c6d-41ae96e4ca40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059777366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4059777366
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3500235243
Short name T919
Test name
Test status
Simulation time 69505371 ps
CPU time 1.54 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 215372 kb
Host smart-c253ba7a-f797-4d09-b101-4d88a8f42468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500235243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3500235243
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.832867268
Short name T912
Test name
Test status
Simulation time 36990886 ps
CPU time 0.78 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:33 PM PDT 24
Peak memory 205500 kb
Host smart-edb9fd07-f741-4e65-a8e1-4ff2e5463bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832867268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.832867268
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2341729195
Short name T1001
Test name
Test status
Simulation time 18492712 ps
CPU time 0.82 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:36 PM PDT 24
Peak memory 205580 kb
Host smart-1cb16c2c-c9c5-46a9-8815-013a9a562c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341729195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2341729195
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2969438194
Short name T1008
Test name
Test status
Simulation time 60565211 ps
CPU time 0.9 seconds
Started May 23 03:39:18 PM PDT 24
Finished May 23 03:39:28 PM PDT 24
Peak memory 205736 kb
Host smart-09e5acd1-6e83-4dd8-873c-1017e55c81a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969438194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2969438194
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2655705553
Short name T1070
Test name
Test status
Simulation time 34155910 ps
CPU time 0.82 seconds
Started May 23 03:39:16 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 205564 kb
Host smart-aa0f755d-ed5e-47a7-8268-d1350a43d78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655705553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2655705553
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4204486265
Short name T915
Test name
Test status
Simulation time 18145949 ps
CPU time 0.8 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205548 kb
Host smart-734f6eb5-9033-4ac7-b54e-089419b38c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204486265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4204486265
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1285045374
Short name T1031
Test name
Test status
Simulation time 36569116 ps
CPU time 0.69 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:32 PM PDT 24
Peak memory 205508 kb
Host smart-f04dac09-3153-4fa0-8a0e-8f8c19f610ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285045374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1285045374
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2772228152
Short name T1041
Test name
Test status
Simulation time 10998315 ps
CPU time 0.83 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205584 kb
Host smart-ecc89e78-3014-4c69-9f7d-83d58c3458b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772228152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2772228152
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3156975687
Short name T914
Test name
Test status
Simulation time 127383323 ps
CPU time 0.72 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:35 PM PDT 24
Peak memory 205588 kb
Host smart-c49d71ba-4cb9-45af-8da2-06e96db1bc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156975687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3156975687
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1774288548
Short name T913
Test name
Test status
Simulation time 8388538 ps
CPU time 0.7 seconds
Started May 23 03:39:16 PM PDT 24
Finished May 23 03:39:25 PM PDT 24
Peak memory 205576 kb
Host smart-eec9d77c-6261-4258-b58e-c7684d40186c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774288548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1774288548
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2793862646
Short name T935
Test name
Test status
Simulation time 12905469 ps
CPU time 0.77 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:27 PM PDT 24
Peak memory 205552 kb
Host smart-2b93aad8-9596-4abc-9fea-ef80fdb1e52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793862646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2793862646
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3560922912
Short name T958
Test name
Test status
Simulation time 33677817 ps
CPU time 1.25 seconds
Started May 23 03:38:59 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 214100 kb
Host smart-e5b9a795-6e32-42ac-b9b1-9cb38a414ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560922912 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3560922912
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2031944072
Short name T933
Test name
Test status
Simulation time 25831816 ps
CPU time 1.18 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:28 PM PDT 24
Peak memory 205756 kb
Host smart-03527a3a-a25e-45b7-acd3-1110409ac430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031944072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2031944072
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.415146010
Short name T1057
Test name
Test status
Simulation time 137585649 ps
CPU time 0.85 seconds
Started May 23 03:39:20 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205512 kb
Host smart-5f952c3f-21c8-4117-aff8-fe6ce2704971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415146010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.415146010
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3814478352
Short name T1017
Test name
Test status
Simulation time 325016464 ps
CPU time 2.47 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:20 PM PDT 24
Peak memory 205772 kb
Host smart-7a3ca5f6-0a87-4970-9640-b5a68f57c707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814478352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3814478352
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.528659820
Short name T1024
Test name
Test status
Simulation time 211637984 ps
CPU time 3.6 seconds
Started May 23 03:39:04 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214412 kb
Host smart-00af3d74-4da1-4a55-b8bc-b70da9046823
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528659820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.528659820
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2209892225
Short name T1053
Test name
Test status
Simulation time 94128394 ps
CPU time 4.03 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:10 PM PDT 24
Peak memory 220396 kb
Host smart-43abef79-7b13-4693-a461-e407a8be37d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209892225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2209892225
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2860679162
Short name T924
Test name
Test status
Simulation time 206798424 ps
CPU time 3.66 seconds
Started May 23 03:39:19 PM PDT 24
Finished May 23 03:39:32 PM PDT 24
Peak memory 214064 kb
Host smart-3c5edf94-95fe-4b7c-a2a1-3bb15bec608e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860679162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2860679162
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1119935715
Short name T155
Test name
Test status
Simulation time 114017630 ps
CPU time 5.41 seconds
Started May 23 03:39:05 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 205760 kb
Host smart-f241019e-2582-4925-92f1-78f368a3a8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119935715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1119935715
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.195553281
Short name T1076
Test name
Test status
Simulation time 47519918 ps
CPU time 1.45 seconds
Started May 23 03:38:58 PM PDT 24
Finished May 23 03:39:05 PM PDT 24
Peak memory 214160 kb
Host smart-316481cb-0252-4f32-b11a-d5533c18f0fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195553281 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.195553281
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2448785602
Short name T959
Test name
Test status
Simulation time 15188609 ps
CPU time 1.27 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 205824 kb
Host smart-99afcfb3-2498-4062-8254-6da618115c6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448785602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2448785602
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2576278531
Short name T995
Test name
Test status
Simulation time 37227293 ps
CPU time 0.8 seconds
Started May 23 03:39:20 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 205588 kb
Host smart-2f3ae6b0-efac-48f1-ab56-68e2f82ceadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576278531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2576278531
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1311876357
Short name T1037
Test name
Test status
Simulation time 105170322 ps
CPU time 2.99 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 205828 kb
Host smart-cd597f20-dadf-45b0-846c-119d198f5779
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311876357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1311876357
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4219241161
Short name T130
Test name
Test status
Simulation time 180306285 ps
CPU time 3.39 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:16 PM PDT 24
Peak memory 214372 kb
Host smart-65f0d718-7b97-4866-931d-92f811cb1553
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219241161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4219241161
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3526940134
Short name T123
Test name
Test status
Simulation time 233697772 ps
CPU time 5.81 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:18 PM PDT 24
Peak memory 214504 kb
Host smart-3f3cefc1-f98f-41d1-9d71-40c27a294d8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526940134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3526940134
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4196299108
Short name T970
Test name
Test status
Simulation time 47581203 ps
CPU time 3.18 seconds
Started May 23 03:39:02 PM PDT 24
Finished May 23 03:39:11 PM PDT 24
Peak memory 216280 kb
Host smart-d321f0d4-1ec3-44f0-a5f5-7589f3d67d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196299108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4196299108
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3766774202
Short name T164
Test name
Test status
Simulation time 253149681 ps
CPU time 4.21 seconds
Started May 23 03:38:59 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 215144 kb
Host smart-feaf27c3-f384-44e2-92aa-4fbd933573ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766774202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3766774202
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1799878837
Short name T986
Test name
Test status
Simulation time 75020607 ps
CPU time 2.01 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 217124 kb
Host smart-6db1d04b-b47d-4c4a-b8f8-01eaa2eb18e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799878837 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1799878837
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2721734246
Short name T1034
Test name
Test status
Simulation time 16800792 ps
CPU time 1.02 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:24 PM PDT 24
Peak memory 205840 kb
Host smart-7816d84b-8b85-4a52-bc2b-c8eba32ae748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721734246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2721734246
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1440290335
Short name T971
Test name
Test status
Simulation time 14628612 ps
CPU time 0.71 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 205544 kb
Host smart-a14c1a06-38c5-47e8-98cb-c971d52ce802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440290335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1440290335
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3402790679
Short name T1051
Test name
Test status
Simulation time 432802801 ps
CPU time 2.69 seconds
Started May 23 03:39:00 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 214028 kb
Host smart-16f95e21-cf97-446e-a1ae-958b857a8b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402790679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3402790679
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1234264559
Short name T1060
Test name
Test status
Simulation time 315178224 ps
CPU time 2.13 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:17 PM PDT 24
Peak memory 214236 kb
Host smart-e0e90f2e-6920-43d9-aeea-26bff7cc204d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234264559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1234264559
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2326369276
Short name T1009
Test name
Test status
Simulation time 835911895 ps
CPU time 9.96 seconds
Started May 23 03:38:57 PM PDT 24
Finished May 23 03:39:12 PM PDT 24
Peak memory 214408 kb
Host smart-6a3a03f6-b0ba-469b-8e59-1ec5a76300d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326369276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2326369276
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.27020515
Short name T1055
Test name
Test status
Simulation time 76190044 ps
CPU time 1.82 seconds
Started May 23 03:39:06 PM PDT 24
Finished May 23 03:39:13 PM PDT 24
Peak memory 214904 kb
Host smart-29dd1953-5a9d-4a26-884b-6b36ad3ed2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.27020515
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4244849766
Short name T962
Test name
Test status
Simulation time 133530661 ps
CPU time 2.33 seconds
Started May 23 03:39:09 PM PDT 24
Finished May 23 03:39:17 PM PDT 24
Peak memory 219548 kb
Host smart-38ffa4de-d0ea-4e41-ac51-0791d5337758
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244849766 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4244849766
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2266012994
Short name T1005
Test name
Test status
Simulation time 99453362 ps
CPU time 1.02 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205764 kb
Host smart-1792a607-4cb9-4a7f-bb23-94b1bc7610fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266012994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2266012994
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1697517686
Short name T979
Test name
Test status
Simulation time 17354068 ps
CPU time 0.78 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205636 kb
Host smart-3939fa40-8e04-4017-9602-58e9cef70fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697517686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1697517686
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.845361746
Short name T1080
Test name
Test status
Simulation time 153421960 ps
CPU time 2.01 seconds
Started May 23 03:39:11 PM PDT 24
Finished May 23 03:39:19 PM PDT 24
Peak memory 205756 kb
Host smart-20a8d0c7-90c4-405b-a849-1a97841bc3cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845361746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.845361746
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3104910783
Short name T125
Test name
Test status
Simulation time 129132212 ps
CPU time 4.06 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:26 PM PDT 24
Peak memory 214400 kb
Host smart-01a8783e-bb7f-4a42-92da-ed4591b482d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104910783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3104910783
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4054841458
Short name T1074
Test name
Test status
Simulation time 256783347 ps
CPU time 3.44 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:23 PM PDT 24
Peak memory 214492 kb
Host smart-3c597d37-e66f-4e5a-ade4-da53d3edc589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054841458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4054841458
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4022184879
Short name T916
Test name
Test status
Simulation time 248121407 ps
CPU time 1.81 seconds
Started May 23 03:39:08 PM PDT 24
Finished May 23 03:39:15 PM PDT 24
Peak memory 214028 kb
Host smart-c61418a5-8d81-45e9-ad43-39b2fb05204d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022184879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4022184879
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4164214123
Short name T156
Test name
Test status
Simulation time 483170232 ps
CPU time 6.92 seconds
Started May 23 03:38:57 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 205908 kb
Host smart-65c4560a-559d-41d0-be2e-12e59b392425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164214123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4164214123
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2054237096
Short name T1003
Test name
Test status
Simulation time 613080337 ps
CPU time 1.99 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 214136 kb
Host smart-e6775a7f-6040-499e-a2e7-ba3cfb24c4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054237096 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2054237096
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.411529636
Short name T988
Test name
Test status
Simulation time 84945801 ps
CPU time 0.94 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205672 kb
Host smart-b8fdabe4-9103-43d3-bd10-5679c8a49a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411529636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.411529636
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3466464231
Short name T1043
Test name
Test status
Simulation time 10761389 ps
CPU time 0.69 seconds
Started May 23 03:39:13 PM PDT 24
Finished May 23 03:39:21 PM PDT 24
Peak memory 205604 kb
Host smart-0a4959dd-3c59-46d1-a888-6264fa53c108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466464231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3466464231
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3998788451
Short name T147
Test name
Test status
Simulation time 94100465 ps
CPU time 2.15 seconds
Started May 23 03:39:10 PM PDT 24
Finished May 23 03:39:17 PM PDT 24
Peak memory 205820 kb
Host smart-dad02c4e-6bed-4eb2-83d9-a0f58e4173de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998788451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3998788451
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2924039067
Short name T1039
Test name
Test status
Simulation time 117581027 ps
CPU time 2.95 seconds
Started May 23 03:39:07 PM PDT 24
Finished May 23 03:39:14 PM PDT 24
Peak memory 214372 kb
Host smart-5dc87278-64bc-429d-b2ab-64c6bf35ad81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924039067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2924039067
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2630167341
Short name T1025
Test name
Test status
Simulation time 1279252683 ps
CPU time 12.78 seconds
Started May 23 03:39:04 PM PDT 24
Finished May 23 03:39:22 PM PDT 24
Peak memory 214408 kb
Host smart-a3f1ba50-1d73-4def-9ac4-dfa40c345ba5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630167341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2630167341
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1842257749
Short name T978
Test name
Test status
Simulation time 33728673 ps
CPU time 1.85 seconds
Started May 23 03:39:01 PM PDT 24
Finished May 23 03:39:08 PM PDT 24
Peak memory 213672 kb
Host smart-4cdb6206-4edc-47df-a0ed-7e46e893e9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842257749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1842257749
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4045048371
Short name T163
Test name
Test status
Simulation time 848534765 ps
CPU time 6.44 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:30 PM PDT 24
Peak memory 214032 kb
Host smart-384e771e-425d-4272-a123-5b1c11b87fce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045048371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4045048371
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1621303698
Short name T442
Test name
Test status
Simulation time 15498237 ps
CPU time 0.82 seconds
Started May 23 03:44:28 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 205996 kb
Host smart-add2bccd-c695-4fd7-b7b1-bd44a0440fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621303698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1621303698
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.728861442
Short name T404
Test name
Test status
Simulation time 245607293 ps
CPU time 4.72 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 222448 kb
Host smart-c986991d-7230-4de5-8b99-43e5bf79a41e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728861442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.728861442
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1192352543
Short name T827
Test name
Test status
Simulation time 191904071 ps
CPU time 3.16 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 209308 kb
Host smart-a57b3b1d-d268-4975-86ec-bcb2765e577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192352543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1192352543
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.652323669
Short name T402
Test name
Test status
Simulation time 148434444 ps
CPU time 2.09 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 207508 kb
Host smart-96080333-7a0a-484b-a145-7094f2c221f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652323669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.652323669
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4048315006
Short name T280
Test name
Test status
Simulation time 122329129 ps
CPU time 5.16 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:25 PM PDT 24
Peak memory 222552 kb
Host smart-5afa503e-ab22-4c52-a937-05b27ed36573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048315006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4048315006
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2174766874
Short name T752
Test name
Test status
Simulation time 52922379 ps
CPU time 2.55 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 214320 kb
Host smart-0cf1255d-7808-4b55-b34c-3267be5fe77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174766874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2174766874
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3959877147
Short name T787
Test name
Test status
Simulation time 611343852 ps
CPU time 4.97 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 214376 kb
Host smart-c0786977-1082-45d9-bc29-29719f15c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959877147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3959877147
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3655446560
Short name T775
Test name
Test status
Simulation time 506312165 ps
CPU time 4.13 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 209388 kb
Host smart-b6307eb8-d020-48e0-bd0c-5262d32c4e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655446560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3655446560
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1359281539
Short name T400
Test name
Test status
Simulation time 30546089 ps
CPU time 2.31 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 206900 kb
Host smart-5edd33d0-9690-4bf5-b0b1-412c45533184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359281539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1359281539
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2743086141
Short name T624
Test name
Test status
Simulation time 624391293 ps
CPU time 14.49 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 208008 kb
Host smart-284e9d1b-c48a-4ed8-809d-d3d89bb87d0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743086141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2743086141
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.242946817
Short name T551
Test name
Test status
Simulation time 186963974 ps
CPU time 5.68 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 208580 kb
Host smart-88cac12e-d725-45fb-b4f6-f7ef239d29ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242946817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.242946817
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1943703435
Short name T646
Test name
Test status
Simulation time 205900599 ps
CPU time 2.98 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 208192 kb
Host smart-bd5c24fe-6b49-4f3f-92c0-f50a0ca163d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943703435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1943703435
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1862515991
Short name T251
Test name
Test status
Simulation time 336593302 ps
CPU time 2.87 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:31 PM PDT 24
Peak memory 216092 kb
Host smart-adde7fcb-4384-4c98-99a5-bd6e9b72e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862515991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1862515991
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1644295925
Short name T331
Test name
Test status
Simulation time 418922329 ps
CPU time 20.28 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:48 PM PDT 24
Peak memory 215512 kb
Host smart-92cb6956-bdf5-48b4-acd4-ed8789eafb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644295925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1644295925
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2394333268
Short name T894
Test name
Test status
Simulation time 455587113 ps
CPU time 4.67 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:46 PM PDT 24
Peak memory 208884 kb
Host smart-35603bd6-ae6f-4fd1-93c1-3d67c592240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394333268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2394333268
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.5400124
Short name T766
Test name
Test status
Simulation time 109676774 ps
CPU time 2.5 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 210068 kb
Host smart-78f8182e-bea7-4d8c-a5b0-cbf3ec5488e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5400124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.5400124
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2375202474
Short name T872
Test name
Test status
Simulation time 133827346 ps
CPU time 0.96 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:51 PM PDT 24
Peak memory 206156 kb
Host smart-b87e52ac-21bb-42c4-8bd0-37061191e18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375202474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2375202474
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.888293678
Short name T30
Test name
Test status
Simulation time 627312430 ps
CPU time 1.75 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:52 PM PDT 24
Peak memory 208468 kb
Host smart-a3c4b4ba-0bad-4b51-a128-ddff0b9f60f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888293678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.888293678
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3977744865
Short name T506
Test name
Test status
Simulation time 576075310 ps
CPU time 1.92 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 209436 kb
Host smart-c9d469b7-069b-494c-99e7-12c10c28d3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977744865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3977744865
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3929038637
Short name T108
Test name
Test status
Simulation time 291349264 ps
CPU time 3.7 seconds
Started May 23 03:44:22 PM PDT 24
Finished May 23 03:44:35 PM PDT 24
Peak memory 209036 kb
Host smart-44fcd1b0-b543-40b8-8851-d995344b9957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929038637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3929038637
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3544432368
Short name T548
Test name
Test status
Simulation time 103399059 ps
CPU time 4.58 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 210188 kb
Host smart-aff9de80-9435-46e9-9f84-2213ae66ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544432368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3544432368
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1887678688
Short name T768
Test name
Test status
Simulation time 53263887 ps
CPU time 3.42 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:31 PM PDT 24
Peak memory 207460 kb
Host smart-a907208e-c7ae-45f2-952d-a665f02eec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887678688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1887678688
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3997629257
Short name T44
Test name
Test status
Simulation time 624504820 ps
CPU time 6.5 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 233620 kb
Host smart-b811c715-e093-4484-8558-4d7e463062dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997629257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3997629257
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.240549738
Short name T208
Test name
Test status
Simulation time 2936214891 ps
CPU time 24.39 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:50 PM PDT 24
Peak memory 208564 kb
Host smart-57c7874b-9b49-41db-a568-a654fde52eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240549738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.240549738
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2337586511
Short name T571
Test name
Test status
Simulation time 23464320 ps
CPU time 1.92 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 206868 kb
Host smart-a84e9e3a-f5a9-4749-a2c8-35661b414503
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337586511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2337586511
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1662937119
Short name T745
Test name
Test status
Simulation time 254605610 ps
CPU time 5.21 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:52 PM PDT 24
Peak memory 208800 kb
Host smart-47bb8114-ec0f-4006-b792-b9bd274dbb4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662937119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1662937119
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.16918405
Short name T769
Test name
Test status
Simulation time 220280654 ps
CPU time 3.02 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 208572 kb
Host smart-e396ee67-27d5-4470-b831-5963417a2c45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.16918405
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.971457942
Short name T284
Test name
Test status
Simulation time 30490638 ps
CPU time 2.3 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:45 PM PDT 24
Peak memory 214444 kb
Host smart-8b64eeaa-e819-418b-be21-197ebeabeae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971457942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.971457942
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3507745219
Short name T578
Test name
Test status
Simulation time 50561158 ps
CPU time 2.59 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 208492 kb
Host smart-02e3adaa-6b8d-41f3-99bf-a637d48ef324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507745219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3507745219
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2860793199
Short name T351
Test name
Test status
Simulation time 7007170504 ps
CPU time 39.59 seconds
Started May 23 03:44:20 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 221744 kb
Host smart-673d8ab9-3973-465f-a781-4d43edf127b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860793199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2860793199
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.308307153
Short name T258
Test name
Test status
Simulation time 505090134 ps
CPU time 4.11 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:50 PM PDT 24
Peak memory 209248 kb
Host smart-9e4fb99c-1048-4f9f-9f46-5903f40495c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308307153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.308307153
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4047002949
Short name T869
Test name
Test status
Simulation time 441477894 ps
CPU time 3.43 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 210860 kb
Host smart-8b4188fe-0e98-4305-a1d6-007d5608bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047002949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4047002949
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.570180849
Short name T431
Test name
Test status
Simulation time 16247688 ps
CPU time 0.75 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 205984 kb
Host smart-cadf0a3c-2824-4fd1-b6de-08f36c418b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570180849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.570180849
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3608719009
Short name T420
Test name
Test status
Simulation time 1413018791 ps
CPU time 7.49 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 214364 kb
Host smart-77c625cb-ec3b-49c4-a223-172f5215c287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608719009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3608719009
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2821141467
Short name T20
Test name
Test status
Simulation time 201122834 ps
CPU time 2.22 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 03:45:46 PM PDT 24
Peak memory 216116 kb
Host smart-16e42726-b703-4874-adda-39200f60948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821141467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2821141467
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1834056780
Short name T728
Test name
Test status
Simulation time 32808711 ps
CPU time 2.5 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 214400 kb
Host smart-15e6dc21-3bb9-466a-8625-e1d8dfa0218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834056780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1834056780
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.43171100
Short name T812
Test name
Test status
Simulation time 365148159 ps
CPU time 4.09 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 222476 kb
Host smart-ee88d665-dcd6-428b-9631-59599f191964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43171100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.43171100
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.59288993
Short name T365
Test name
Test status
Simulation time 140048109 ps
CPU time 3.35 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 219192 kb
Host smart-ac3a20c3-8295-4c6d-98cb-136892004a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59288993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.59288993
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3636375706
Short name T729
Test name
Test status
Simulation time 79347318 ps
CPU time 3.57 seconds
Started May 23 03:45:24 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 209052 kb
Host smart-17a9a786-5ece-40e8-8723-4ebb04e98b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636375706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3636375706
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2352967567
Short name T250
Test name
Test status
Simulation time 328827418 ps
CPU time 4.38 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 208988 kb
Host smart-40b62e97-4216-4df6-a56e-9968d8718be9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352967567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2352967567
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4036006078
Short name T748
Test name
Test status
Simulation time 437158294 ps
CPU time 2.34 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:40 PM PDT 24
Peak memory 206844 kb
Host smart-7ba57df7-8efa-4af9-8f6a-91394bfa8d1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036006078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4036006078
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2353587696
Short name T659
Test name
Test status
Simulation time 158075144 ps
CPU time 6.44 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 208960 kb
Host smart-5be87d83-844b-4fb4-afc1-1d3b009f91dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353587696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2353587696
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2122013874
Short name T247
Test name
Test status
Simulation time 23254767 ps
CPU time 1.76 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:51 PM PDT 24
Peak memory 218540 kb
Host smart-85bc9fa8-e985-4a02-8b2e-36c0906590f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122013874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2122013874
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2948803345
Short name T844
Test name
Test status
Simulation time 65885861 ps
CPU time 3.14 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:49 PM PDT 24
Peak memory 207992 kb
Host smart-a04f43e8-4451-4207-8a7e-a929815aa242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948803345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2948803345
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3377533169
Short name T836
Test name
Test status
Simulation time 3941921195 ps
CPU time 41.95 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 222156 kb
Host smart-274c5a1f-02db-464c-8e6f-a5d25e996135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377533169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3377533169
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4229705288
Short name T132
Test name
Test status
Simulation time 233974860 ps
CPU time 1.6 seconds
Started May 23 03:45:17 PM PDT 24
Finished May 23 03:45:38 PM PDT 24
Peak memory 214444 kb
Host smart-f40a712f-7283-4626-8367-edba6dd73a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229705288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4229705288
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.658451021
Short name T655
Test name
Test status
Simulation time 12907337 ps
CPU time 0.77 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 206004 kb
Host smart-4f5cb1a3-dcdf-4af1-bb89-fba9b6449ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658451021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.658451021
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2607194538
Short name T69
Test name
Test status
Simulation time 49018715 ps
CPU time 2.45 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 207408 kb
Host smart-5e551e04-1b77-4778-8610-4ea9b463a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607194538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2607194538
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.71015817
Short name T672
Test name
Test status
Simulation time 164406492 ps
CPU time 3.72 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 214372 kb
Host smart-961d70c8-c2c2-4353-a137-0c9c04c8d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71015817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.71015817
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.575303328
Short name T268
Test name
Test status
Simulation time 90279230 ps
CPU time 1.78 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:51 PM PDT 24
Peak memory 214336 kb
Host smart-6eb27954-a2b5-456d-b43f-7124a2965d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575303328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.575303328
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.657113384
Short name T540
Test name
Test status
Simulation time 122222343 ps
CPU time 2.53 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 214352 kb
Host smart-733d6c23-0910-4e08-a3ab-55cd978b064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657113384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.657113384
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1921884940
Short name T574
Test name
Test status
Simulation time 9703410031 ps
CPU time 38.11 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 208912 kb
Host smart-3e61eb69-c031-4830-ba87-380b2926363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921884940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1921884940
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1643684274
Short name T210
Test name
Test status
Simulation time 35823892 ps
CPU time 2.34 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 206984 kb
Host smart-7b083afe-56bd-4578-82fb-cf5891484f23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643684274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1643684274
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4108621517
Short name T643
Test name
Test status
Simulation time 267249832 ps
CPU time 3.25 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 208904 kb
Host smart-dc63d848-a966-4a54-9c25-c4283f070710
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108621517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4108621517
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.138184807
Short name T211
Test name
Test status
Simulation time 933564701 ps
CPU time 6.89 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:46:02 PM PDT 24
Peak memory 208808 kb
Host smart-2a5af904-1593-427e-9cd5-f5f1af7612d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138184807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.138184807
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1044602041
Short name T741
Test name
Test status
Simulation time 1108124550 ps
CPU time 6.57 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:46:02 PM PDT 24
Peak memory 208452 kb
Host smart-4c9ddf3d-3266-4af7-ab05-b852edb31dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044602041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1044602041
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3715648850
Short name T598
Test name
Test status
Simulation time 160745157 ps
CPU time 2.07 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 206960 kb
Host smart-6c73f3f8-347f-4a57-a8cb-468672e4eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715648850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3715648850
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4188776665
Short name T79
Test name
Test status
Simulation time 5709931181 ps
CPU time 121.32 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:48:05 PM PDT 24
Peak memory 216300 kb
Host smart-656210ad-7046-42ce-9fb6-80befd5363af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188776665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4188776665
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1733570736
Short name T160
Test name
Test status
Simulation time 115728567 ps
CPU time 2.99 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 211060 kb
Host smart-7cd8636b-3e28-4fe0-b981-a29c63ac4515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733570736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1733570736
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.997154167
Short name T494
Test name
Test status
Simulation time 132103966 ps
CPU time 0.72 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:04 PM PDT 24
Peak memory 205992 kb
Host smart-7f196ded-fcc8-42be-b0f5-90589e352970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997154167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.997154167
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.818854820
Short name T78
Test name
Test status
Simulation time 215209004 ps
CPU time 7.04 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:46:01 PM PDT 24
Peak memory 222816 kb
Host smart-01ed1338-9daa-49bb-8d47-79d311ea7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818854820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.818854820
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.69197212
Short name T648
Test name
Test status
Simulation time 732823961 ps
CPU time 3.2 seconds
Started May 23 03:45:46 PM PDT 24
Finished May 23 03:46:16 PM PDT 24
Peak memory 218348 kb
Host smart-3ec4a532-201b-48b4-9a88-b5c434dafe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69197212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.69197212
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2866748172
Short name T546
Test name
Test status
Simulation time 118663658 ps
CPU time 3.95 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 214308 kb
Host smart-4cb91907-e56f-4297-aa12-3ebba4edd44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866748172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2866748172
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3112392367
Short name T217
Test name
Test status
Simulation time 239173731 ps
CPU time 3.28 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 220260 kb
Host smart-32a19cd1-036b-4fdd-a22c-01ced7fe3356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112392367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3112392367
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1527494798
Short name T853
Test name
Test status
Simulation time 9271152138 ps
CPU time 48.62 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 208476 kb
Host smart-5cad7c12-d645-4452-9f71-9658ecf7a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527494798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1527494798
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4049538264
Short name T797
Test name
Test status
Simulation time 398195497 ps
CPU time 3.96 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 208864 kb
Host smart-7d42f848-f367-4a43-999b-3d2e86ecae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049538264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4049538264
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1408930311
Short name T444
Test name
Test status
Simulation time 237983915 ps
CPU time 1.88 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 206936 kb
Host smart-5a7fdb1d-e68b-421d-9c0b-5dfabdfd507d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408930311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1408930311
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1528647196
Short name T589
Test name
Test status
Simulation time 325188597 ps
CPU time 5.39 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 207112 kb
Host smart-29b75c02-f348-4261-941e-57b4c2ba3012
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528647196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1528647196
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3547045946
Short name T441
Test name
Test status
Simulation time 126362953 ps
CPU time 3.09 seconds
Started May 23 03:45:43 PM PDT 24
Finished May 23 03:46:11 PM PDT 24
Peak memory 214360 kb
Host smart-5531319a-3a85-41b7-9b5c-82563f54419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547045946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3547045946
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2448426056
Short name T776
Test name
Test status
Simulation time 36688332 ps
CPU time 2.32 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 206944 kb
Host smart-0aa20a21-4798-49d0-9570-37f2005182ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448426056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2448426056
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3969182834
Short name T384
Test name
Test status
Simulation time 84907217 ps
CPU time 4.08 seconds
Started May 23 03:45:25 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 217564 kb
Host smart-8ad188a2-c42f-4e1a-965f-322579de4763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969182834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3969182834
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.305784395
Short name T452
Test name
Test status
Simulation time 841658846 ps
CPU time 5.83 seconds
Started May 23 03:45:29 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 214372 kb
Host smart-10c3f0a3-cbcf-4cef-9d34-8c6c8089a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305784395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.305784395
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.285686819
Short name T382
Test name
Test status
Simulation time 38100754 ps
CPU time 1.65 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 210036 kb
Host smart-6becd011-30ff-4b88-be5c-7e5a194e50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285686819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.285686819
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.885337512
Short name T736
Test name
Test status
Simulation time 62174268 ps
CPU time 0.72 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 205996 kb
Host smart-b2e32740-92ce-4902-b8d7-f865846ce17e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885337512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.885337512
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1301999686
Short name T663
Test name
Test status
Simulation time 42820433 ps
CPU time 2.77 seconds
Started May 23 03:45:46 PM PDT 24
Finished May 23 03:46:16 PM PDT 24
Peak memory 221992 kb
Host smart-b6eef71b-9072-494c-86bb-32413bab4a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301999686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1301999686
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4275405715
Short name T636
Test name
Test status
Simulation time 495583007 ps
CPU time 3.87 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 214352 kb
Host smart-c0ef9a74-017e-4a4a-b7b6-0ccf34de6124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275405715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4275405715
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1222370621
Short name T355
Test name
Test status
Simulation time 87962731 ps
CPU time 3.05 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 214444 kb
Host smart-e2c9746c-f71b-41b5-ab8d-5b643782cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222370621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1222370621
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1682747957
Short name T649
Test name
Test status
Simulation time 88111498 ps
CPU time 3.09 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 214356 kb
Host smart-7a301403-f1a4-4bf2-8826-309fae1680f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682747957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1682747957
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1432834947
Short name T799
Test name
Test status
Simulation time 903124486 ps
CPU time 7.06 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 214468 kb
Host smart-2b848f2c-439b-46d0-8de4-7fb3953a9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432834947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1432834947
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.559001288
Short name T432
Test name
Test status
Simulation time 112802246 ps
CPU time 4.18 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 206920 kb
Host smart-1f0209c0-a450-4584-b35a-6356b3184060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559001288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.559001288
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3349295968
Short name T576
Test name
Test status
Simulation time 177631976 ps
CPU time 3.9 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 208676 kb
Host smart-fb0165a6-e1ab-48d6-91b6-55406bdef43b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349295968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3349295968
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2680698759
Short name T790
Test name
Test status
Simulation time 5336382039 ps
CPU time 22.38 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 208296 kb
Host smart-a88795a9-c700-4d64-9586-aed8b380cef2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680698759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2680698759
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.173873062
Short name T136
Test name
Test status
Simulation time 155855392 ps
CPU time 3.68 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 210008 kb
Host smart-c2b91c8f-f319-45df-9cc1-8c9047dc2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173873062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.173873062
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1781454834
Short name T544
Test name
Test status
Simulation time 51031755 ps
CPU time 2.3 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 206956 kb
Host smart-15531875-2bf4-4980-9047-5f5f8179f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781454834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1781454834
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2127861969
Short name T360
Test name
Test status
Simulation time 2946597968 ps
CPU time 20.3 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 222652 kb
Host smart-eda45016-ef85-4f2b-a1ba-7ce8f040f8c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127861969 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2127861969
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.593813352
Short name T882
Test name
Test status
Simulation time 259883331 ps
CPU time 3.49 seconds
Started May 23 03:45:32 PM PDT 24
Finished May 23 03:45:58 PM PDT 24
Peak memory 207656 kb
Host smart-5272748c-1d01-429f-95ea-160c71fa77af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593813352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.593813352
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2645992522
Short name T61
Test name
Test status
Simulation time 326915647 ps
CPU time 1.45 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:51 PM PDT 24
Peak memory 209704 kb
Host smart-e421e561-cab3-40b8-b21d-fa3fa22a4665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645992522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2645992522
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.810413858
Short name T462
Test name
Test status
Simulation time 14587755 ps
CPU time 0.94 seconds
Started May 23 03:45:57 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 206160 kb
Host smart-c38dda8b-d17c-47ae-ac96-23f44d8bcb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810413858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.810413858
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2897131357
Short name T29
Test name
Test status
Simulation time 204461539 ps
CPU time 4.2 seconds
Started May 23 03:45:33 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 209956 kb
Host smart-dc54780d-79ca-4964-bd7a-06dbf070b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897131357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2897131357
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3599254802
Short name T369
Test name
Test status
Simulation time 476667972 ps
CPU time 4.62 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 208372 kb
Host smart-078f8a66-507c-4b09-9d5d-673f1e3715cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599254802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3599254802
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1269291080
Short name T105
Test name
Test status
Simulation time 473561618 ps
CPU time 4.42 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 214312 kb
Host smart-fa0aa839-1f2d-4600-be9f-6ab3db5ca1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269291080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1269291080
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.887369375
Short name T244
Test name
Test status
Simulation time 711697904 ps
CPU time 5.09 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 222476 kb
Host smart-32dc143c-9e62-45a1-b13c-ecdf9cffcccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887369375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.887369375
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2304385936
Short name T594
Test name
Test status
Simulation time 291433482 ps
CPU time 3.39 seconds
Started May 23 03:45:31 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 210616 kb
Host smart-8810ba1f-8607-456b-8646-f194c8af454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304385936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2304385936
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1400410072
Short name T682
Test name
Test status
Simulation time 176315848 ps
CPU time 2.48 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 207688 kb
Host smart-f5772783-5b55-49e7-8878-6286b7c37747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400410072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1400410072
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3874811693
Short name T478
Test name
Test status
Simulation time 31106115 ps
CPU time 2.34 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 206168 kb
Host smart-e139e187-e9ba-499a-967b-a5a9d21b71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874811693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3874811693
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.235612616
Short name T809
Test name
Test status
Simulation time 153298818 ps
CPU time 4.48 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 207904 kb
Host smart-582d7ae0-dfce-4e34-abef-5d2857a29bc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235612616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.235612616
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2533107581
Short name T603
Test name
Test status
Simulation time 482330892 ps
CPU time 4.36 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 208636 kb
Host smart-ef68ab90-bb54-4592-b5aa-136818aeb658
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533107581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2533107581
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.203775685
Short name T617
Test name
Test status
Simulation time 1412798220 ps
CPU time 44.69 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 207900 kb
Host smart-6a9eae7d-a0dd-4e41-a062-2130419e448c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203775685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.203775685
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3215700668
Short name T512
Test name
Test status
Simulation time 246011512 ps
CPU time 2.22 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 207420 kb
Host smart-80c7327f-74aa-488b-ab37-f19284ecfcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215700668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3215700668
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.876456945
Short name T533
Test name
Test status
Simulation time 226014859 ps
CPU time 4.34 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 208432 kb
Host smart-11866267-ad9b-4608-a1bc-4436fc5ffa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876456945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.876456945
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1282905330
Short name T389
Test name
Test status
Simulation time 685721823 ps
CPU time 18.22 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 214716 kb
Host smart-eba4f0c8-76c0-43df-9fe6-56d8dc487776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282905330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1282905330
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3346599934
Short name T850
Test name
Test status
Simulation time 1381379032 ps
CPU time 10.27 seconds
Started May 23 03:45:35 PM PDT 24
Finished May 23 03:46:08 PM PDT 24
Peak memory 207700 kb
Host smart-8ca7cd05-4fd7-422a-8ba4-7014fdad7a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346599934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3346599934
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1721652926
Short name T845
Test name
Test status
Simulation time 849205501 ps
CPU time 4.62 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 210032 kb
Host smart-b1047f6a-15f6-4e64-9a15-d8642a5ea03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721652926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1721652926
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3935680517
Short name T635
Test name
Test status
Simulation time 64795460 ps
CPU time 0.91 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 206184 kb
Host smart-99446376-9578-46dc-848f-d99b33a88204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935680517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3935680517
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.863684338
Short name T423
Test name
Test status
Simulation time 61454496 ps
CPU time 2.37 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 214372 kb
Host smart-27a27111-50ee-4541-960f-23a4d61258f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863684338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.863684338
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2902009673
Short name T403
Test name
Test status
Simulation time 236904359 ps
CPU time 5.03 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 210268 kb
Host smart-98d234f5-5d21-4c6c-9900-9da48b1fe216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902009673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2902009673
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2721135099
Short name T80
Test name
Test status
Simulation time 172257130 ps
CPU time 2.42 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:04 PM PDT 24
Peak memory 207400 kb
Host smart-0f571dff-fe04-4785-bed8-8ce8472bf70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721135099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2721135099
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2197094829
Short name T117
Test name
Test status
Simulation time 515555390 ps
CPU time 10.45 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:29 PM PDT 24
Peak memory 214364 kb
Host smart-ccb383f4-f116-4f9f-9261-3f3a4e3012e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197094829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2197094829
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2654514216
Short name T374
Test name
Test status
Simulation time 127200076 ps
CPU time 2.32 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:03 PM PDT 24
Peak memory 214980 kb
Host smart-11ef8201-bb1c-4e59-b60b-c75a3719d1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654514216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2654514216
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1019719846
Short name T7
Test name
Test status
Simulation time 2100422823 ps
CPU time 6.32 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 214312 kb
Host smart-93d83a17-960f-4c44-9677-c87135740278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019719846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1019719846
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1092600308
Short name T477
Test name
Test status
Simulation time 171646866 ps
CPU time 4.5 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 207780 kb
Host smart-1065c9ae-ff78-4a15-95c0-578b3ae581c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092600308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1092600308
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3861611070
Short name T865
Test name
Test status
Simulation time 1867686588 ps
CPU time 4.79 seconds
Started May 23 03:45:43 PM PDT 24
Finished May 23 03:46:12 PM PDT 24
Peak memory 206864 kb
Host smart-15ce8aa6-07ff-4ada-b39e-f50b906dd5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861611070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3861611070
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2795318042
Short name T641
Test name
Test status
Simulation time 581724797 ps
CPU time 6.74 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:12 PM PDT 24
Peak memory 208372 kb
Host smart-b45a4e9c-2fb4-4968-8fb0-41774774fd2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795318042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2795318042
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4162576024
Short name T810
Test name
Test status
Simulation time 37525940 ps
CPU time 2.29 seconds
Started May 23 03:46:00 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 206840 kb
Host smart-02720b53-ed01-4508-bf66-29e281c82a72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162576024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4162576024
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2192142091
Short name T454
Test name
Test status
Simulation time 54272280 ps
CPU time 2.62 seconds
Started May 23 03:45:56 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 208172 kb
Host smart-c9c382ac-eee7-4675-bc48-ea09d0a11428
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192142091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2192142091
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2937643674
Short name T535
Test name
Test status
Simulation time 18719766 ps
CPU time 1.68 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 214444 kb
Host smart-49bd177d-0664-41f4-b74c-5e119967a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937643674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2937643674
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1809696719
Short name T451
Test name
Test status
Simulation time 71297954 ps
CPU time 2.96 seconds
Started May 23 03:45:34 PM PDT 24
Finished May 23 03:46:00 PM PDT 24
Peak memory 208580 kb
Host smart-0b98dd11-350f-4fc3-9d69-ef5b465c1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809696719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1809696719
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.684302227
Short name T304
Test name
Test status
Simulation time 671628060 ps
CPU time 13.61 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:13 PM PDT 24
Peak memory 215168 kb
Host smart-15af5e55-6f52-432d-8914-263949687edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684302227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.684302227
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2710727682
Short name T786
Test name
Test status
Simulation time 2999275871 ps
CPU time 9.89 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:13 PM PDT 24
Peak memory 209524 kb
Host smart-d096a2a2-aeb5-416c-bad7-3f640017b848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710727682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2710727682
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.214029003
Short name T814
Test name
Test status
Simulation time 181580689 ps
CPU time 2.81 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 210280 kb
Host smart-19ec863e-6266-4874-b734-8bdf6c9452d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214029003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.214029003
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2402816822
Short name T111
Test name
Test status
Simulation time 14425898 ps
CPU time 0.75 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 205976 kb
Host smart-6d44c75d-995a-49ec-9a6d-091353fe8ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402816822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2402816822
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.145513309
Short name T302
Test name
Test status
Simulation time 118079835 ps
CPU time 4.16 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 214364 kb
Host smart-bf1bc18d-d8ee-49ea-a032-8db776ad60a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145513309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.145513309
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2588543143
Short name T82
Test name
Test status
Simulation time 68361027 ps
CPU time 2.23 seconds
Started May 23 03:45:38 PM PDT 24
Finished May 23 03:46:06 PM PDT 24
Peak memory 207764 kb
Host smart-6e97e563-5346-490b-b41f-4d4dfe55d7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588543143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2588543143
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1830313716
Short name T104
Test name
Test status
Simulation time 71050810 ps
CPU time 2.4 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 214368 kb
Host smart-2bccf191-5e36-458f-9a93-43a847dd929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830313716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1830313716
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2430217910
Short name T751
Test name
Test status
Simulation time 63171257 ps
CPU time 3.55 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 222084 kb
Host smart-3080b9fe-8b69-4b0a-b647-44a56f26ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430217910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2430217910
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.91707289
Short name T870
Test name
Test status
Simulation time 131699058 ps
CPU time 3.82 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 219700 kb
Host smart-92ad328c-bfb8-4f42-85ef-94e426717bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91707289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.91707289
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2550374975
Short name T808
Test name
Test status
Simulation time 163626358 ps
CPU time 5.33 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 209684 kb
Host smart-c436c4d5-9c8b-4763-82fc-8fb7b8a06185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550374975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2550374975
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.236313247
Short name T605
Test name
Test status
Simulation time 30702130 ps
CPU time 2.16 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 208424 kb
Host smart-7b2322e7-48f1-4e81-9f47-7ae054d7a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236313247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.236313247
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.93476457
Short name T566
Test name
Test status
Simulation time 34583841 ps
CPU time 2.21 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 205436 kb
Host smart-6fcd4ae4-a6e9-467a-85e9-8c9058761f6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93476457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.93476457
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2302697418
Short name T604
Test name
Test status
Simulation time 607761089 ps
CPU time 3.5 seconds
Started May 23 03:45:57 PM PDT 24
Finished May 23 03:46:29 PM PDT 24
Peak memory 208720 kb
Host smart-bb91e6fc-dfcd-414a-85ca-521645dc66df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302697418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2302697418
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3259926556
Short name T645
Test name
Test status
Simulation time 1088143516 ps
CPU time 7.1 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 208312 kb
Host smart-6e1015a4-e2e5-4443-9ef8-8d7fe5acce0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259926556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3259926556
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2778613328
Short name T801
Test name
Test status
Simulation time 413941793 ps
CPU time 9.21 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:28 PM PDT 24
Peak memory 218444 kb
Host smart-653c8c6f-2a48-41bb-8854-9237ea57c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778613328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2778613328
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.927810220
Short name T490
Test name
Test status
Simulation time 205758704 ps
CPU time 2.48 seconds
Started May 23 03:45:46 PM PDT 24
Finished May 23 03:46:16 PM PDT 24
Peak memory 206988 kb
Host smart-bf093428-4918-4f9e-a6f7-54e1ac311ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927810220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.927810220
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2588162224
Short name T76
Test name
Test status
Simulation time 509370600 ps
CPU time 16.04 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:36 PM PDT 24
Peak memory 222520 kb
Host smart-fe8ef38c-4bf3-4919-8a3c-d20d6502bff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588162224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2588162224
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3177754887
Short name T366
Test name
Test status
Simulation time 207142026 ps
CPU time 7.85 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:13 PM PDT 24
Peak memory 222632 kb
Host smart-93f91505-cc22-42a7-b163-a39efdad6b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177754887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3177754887
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1648444836
Short name T591
Test name
Test status
Simulation time 303983157 ps
CPU time 4.47 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 214368 kb
Host smart-24df4f19-e171-417d-90e5-019f1aa24edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648444836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1648444836
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3626404693
Short name T66
Test name
Test status
Simulation time 336108720 ps
CPU time 3.36 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 210460 kb
Host smart-25f68e17-579f-410a-9cbd-81d4d1a33f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626404693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3626404693
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3155634134
Short name T459
Test name
Test status
Simulation time 15508692 ps
CPU time 0.77 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 206004 kb
Host smart-831aae87-104f-4432-b478-12037a6365e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155634134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3155634134
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3835314508
Short name T884
Test name
Test status
Simulation time 138570441 ps
CPU time 2.89 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 214632 kb
Host smart-1df7b09f-0bcb-4510-920e-c45d310d75c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835314508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3835314508
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1798806762
Short name T890
Test name
Test status
Simulation time 77970103 ps
CPU time 3.39 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 207008 kb
Host smart-939ff04b-694c-4330-9cb1-b535f879e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798806762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1798806762
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1726845025
Short name T824
Test name
Test status
Simulation time 73541992 ps
CPU time 2.34 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:16 PM PDT 24
Peak memory 214324 kb
Host smart-ac130b8f-b3aa-4721-bd73-baffd46826b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726845025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1726845025
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4277313264
Short name T699
Test name
Test status
Simulation time 86388910 ps
CPU time 3.2 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 214264 kb
Host smart-195fec45-a965-4f8e-a1f2-edde54491428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277313264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4277313264
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3901932740
Short name T581
Test name
Test status
Simulation time 91954649 ps
CPU time 4.2 seconds
Started May 23 03:45:36 PM PDT 24
Finished May 23 03:46:05 PM PDT 24
Peak memory 208800 kb
Host smart-3535d9a6-5fd5-4dd2-926c-ef63f6f5ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901932740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3901932740
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3981992844
Short name T305
Test name
Test status
Simulation time 172111737 ps
CPU time 6.61 seconds
Started May 23 03:45:39 PM PDT 24
Finished May 23 03:46:11 PM PDT 24
Peak memory 208436 kb
Host smart-9bb744e4-ee4b-47f8-ae46-8a6d69471237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981992844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3981992844
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4090030199
Short name T487
Test name
Test status
Simulation time 123848317 ps
CPU time 2.3 seconds
Started May 23 03:45:46 PM PDT 24
Finished May 23 03:46:15 PM PDT 24
Peak memory 206996 kb
Host smart-ab7246ae-6e2d-46e3-a56e-01d96eca1c47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090030199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4090030199
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.153861826
Short name T873
Test name
Test status
Simulation time 283961893 ps
CPU time 6.35 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 208116 kb
Host smart-3bedc664-5158-49a7-a881-f5308130cf4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153861826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.153861826
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3523870550
Short name T486
Test name
Test status
Simulation time 1606590585 ps
CPU time 48.57 seconds
Started May 23 03:45:37 PM PDT 24
Finished May 23 03:46:52 PM PDT 24
Peak memory 208448 kb
Host smart-59ddf0f1-c5da-4be1-bc41-858448624b61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523870550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3523870550
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2754184113
Short name T719
Test name
Test status
Simulation time 517239704 ps
CPU time 16.81 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 218276 kb
Host smart-cb0c36d2-bf96-42d7-8ddf-8dc23e232b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754184113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2754184113
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2100802264
Short name T857
Test name
Test status
Simulation time 234667046 ps
CPU time 2.67 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 208452 kb
Host smart-c523c96a-5cf7-4ba3-93d5-d299ecc41cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100802264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2100802264
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3993672818
Short name T307
Test name
Test status
Simulation time 9603982215 ps
CPU time 62.14 seconds
Started May 23 03:45:45 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 222676 kb
Host smart-49505bae-da66-4f9b-bc73-5b7064055727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993672818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3993672818
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2526554705
Short name T138
Test name
Test status
Simulation time 2663314244 ps
CPU time 25.53 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:46 PM PDT 24
Peak memory 222712 kb
Host smart-a70519cd-251e-4639-8894-da5362c237ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526554705 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2526554705
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1664957247
Short name T262
Test name
Test status
Simulation time 135059559 ps
CPU time 4.25 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 207548 kb
Host smart-13316389-aafe-46b9-841a-b981074f6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664957247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1664957247
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1681957762
Short name T657
Test name
Test status
Simulation time 54198588 ps
CPU time 1.96 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 209768 kb
Host smart-9de70c9a-6b71-46ed-ab71-4fc08552bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681957762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1681957762
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.456158614
Short name T623
Test name
Test status
Simulation time 159027304 ps
CPU time 0.89 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 205928 kb
Host smart-e31dec82-f2ca-4014-b807-1702de16876d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456158614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.456158614
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1936143735
Short name T287
Test name
Test status
Simulation time 139835532 ps
CPU time 7.68 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 214356 kb
Host smart-b5a07e36-b85e-4cb3-b984-973e759917b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936143735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1936143735
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.521060151
Short name T188
Test name
Test status
Simulation time 255606257 ps
CPU time 4.49 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 218096 kb
Host smart-4a845e16-1e02-49b2-90d5-a8aed7ce8329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521060151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.521060151
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.203356153
Short name T65
Test name
Test status
Simulation time 39237715 ps
CPU time 2.44 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 214456 kb
Host smart-3afeaab7-9e29-49be-884e-1e3e5026d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203356153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.203356153
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4213766163
Short name T899
Test name
Test status
Simulation time 480921408 ps
CPU time 3 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 210576 kb
Host smart-17908afc-7533-46e8-bce0-f09598355d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213766163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4213766163
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2453915126
Short name T668
Test name
Test status
Simulation time 49035578 ps
CPU time 2.08 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 207664 kb
Host smart-6de52359-51c0-4562-b671-89d730e6ff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453915126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2453915126
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1635787211
Short name T906
Test name
Test status
Simulation time 95856140 ps
CPU time 4.08 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 207444 kb
Host smart-e2b9beee-5337-46fa-bc95-c474dc918988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635787211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1635787211
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3343741568
Short name T893
Test name
Test status
Simulation time 434684525 ps
CPU time 3.97 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 209048 kb
Host smart-a8bebdd1-8de4-431d-85a7-8233ae97c1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343741568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3343741568
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1530625807
Short name T475
Test name
Test status
Simulation time 321016166 ps
CPU time 6.08 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 208280 kb
Host smart-f4b55de2-94e7-4105-98c9-83926874719d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530625807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1530625807
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4027218938
Short name T762
Test name
Test status
Simulation time 1934977946 ps
CPU time 50.36 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 208996 kb
Host smart-922ebca7-8619-4406-b6e6-bdf328a155d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027218938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4027218938
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2803462390
Short name T485
Test name
Test status
Simulation time 170268929 ps
CPU time 4.01 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 208916 kb
Host smart-853edd5e-5573-4fdf-8778-db057fc44ffe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803462390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2803462390
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.690459247
Short name T118
Test name
Test status
Simulation time 55788231 ps
CPU time 2.68 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 214368 kb
Host smart-acbe452b-8bdd-43cb-be98-857273e867fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690459247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.690459247
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4020508656
Short name T388
Test name
Test status
Simulation time 131931862 ps
CPU time 2.46 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:17 PM PDT 24
Peak memory 206172 kb
Host smart-e882f35b-647f-4039-ae58-ad22a047ed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020508656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4020508656
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1277145170
Short name T829
Test name
Test status
Simulation time 512285504 ps
CPU time 14.42 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 207584 kb
Host smart-f0b9f8ae-2a7e-4ad3-a138-83c6133ae1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277145170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1277145170
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1553149657
Short name T378
Test name
Test status
Simulation time 129893835 ps
CPU time 4.17 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 210348 kb
Host smart-7b7c72e1-315e-42cf-8395-04fdcc6a02c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553149657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1553149657
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1040250493
Short name T433
Test name
Test status
Simulation time 34287886 ps
CPU time 0.76 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:16 PM PDT 24
Peak memory 206024 kb
Host smart-efe1df56-5929-43c0-84e8-c182abe403e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040250493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1040250493
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3460250700
Short name T418
Test name
Test status
Simulation time 165629122 ps
CPU time 3.8 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 214424 kb
Host smart-f34b8d8d-73ef-4238-a31b-939429b123d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460250700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3460250700
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2320950388
Short name T815
Test name
Test status
Simulation time 109850756 ps
CPU time 4.65 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 218428 kb
Host smart-ac8821ea-2a6f-4246-9064-e2f6197ff99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320950388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2320950388
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1057060486
Short name T792
Test name
Test status
Simulation time 167289704 ps
CPU time 4.26 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 206704 kb
Host smart-8b87e63e-8cd7-447a-bc7e-ea795b205eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057060486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1057060486
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4201959053
Short name T62
Test name
Test status
Simulation time 320421802 ps
CPU time 2.75 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 219464 kb
Host smart-359a6f6a-87cf-474d-a911-aeaf397ff786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201959053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4201959053
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3441016442
Short name T325
Test name
Test status
Simulation time 940475511 ps
CPU time 6.94 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 208828 kb
Host smart-474c4e1d-b7b5-4590-9bdb-a986e74d302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441016442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3441016442
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1716472764
Short name T398
Test name
Test status
Simulation time 50967878 ps
CPU time 2.61 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 206856 kb
Host smart-e4670156-f3ae-4111-bf00-1f0cd29ac859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716472764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1716472764
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2962901528
Short name T393
Test name
Test status
Simulation time 29095492 ps
CPU time 2.22 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 206960 kb
Host smart-c9ceb129-750c-4276-9046-71bda9a801ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962901528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2962901528
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1793653092
Short name T620
Test name
Test status
Simulation time 1019225242 ps
CPU time 24.11 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:43 PM PDT 24
Peak memory 208924 kb
Host smart-459a2d80-9b9e-40fb-9a9b-503cee7f8a4a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793653092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1793653092
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.967720900
Short name T392
Test name
Test status
Simulation time 33231682 ps
CPU time 2.13 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 206880 kb
Host smart-8b7be2c0-bb64-45fa-bdb3-4513afd74e20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967720900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.967720900
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4293486234
Short name T582
Test name
Test status
Simulation time 127405785 ps
CPU time 3.38 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 209464 kb
Host smart-2f357c54-a069-4963-8e70-21fc5844b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293486234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4293486234
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3469219760
Short name T661
Test name
Test status
Simulation time 196722849 ps
CPU time 2.66 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 206960 kb
Host smart-049cb73d-aede-4097-8926-08b41d808831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469219760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3469219760
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2652170061
Short name T740
Test name
Test status
Simulation time 13865587728 ps
CPU time 151.29 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:48:47 PM PDT 24
Peak memory 220704 kb
Host smart-fbb3a8cd-91b8-4432-85bc-ec594f43ffb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652170061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2652170061
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3157593004
Short name T601
Test name
Test status
Simulation time 294350752 ps
CPU time 9.65 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 220208 kb
Host smart-5ba7c13d-efc2-4d0a-9178-67856c56d645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157593004 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3157593004
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1950731010
Short name T835
Test name
Test status
Simulation time 91929321 ps
CPU time 2 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 208076 kb
Host smart-626524ff-bda1-4d21-84cc-94f46672922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950731010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1950731010
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4055011786
Short name T735
Test name
Test status
Simulation time 40472001 ps
CPU time 0.72 seconds
Started May 23 03:44:39 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 206004 kb
Host smart-d238d280-2286-4a8f-82df-99b1dec43857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055011786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4055011786
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1099487203
Short name T328
Test name
Test status
Simulation time 59484785 ps
CPU time 4.41 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 214372 kb
Host smart-7c4d6b12-6c4d-49fa-b67b-4c7310dec189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099487203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1099487203
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1136839661
Short name T508
Test name
Test status
Simulation time 468855536 ps
CPU time 11.73 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 214336 kb
Host smart-cabd9331-10ad-4f0d-93fa-03a60862dd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136839661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1136839661
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1991699441
Short name T107
Test name
Test status
Simulation time 193248474 ps
CPU time 4.61 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 222504 kb
Host smart-c3fe4e54-407b-428b-97c1-8b834bccde58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991699441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1991699441
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1994360988
Short name T606
Test name
Test status
Simulation time 399253260 ps
CPU time 3.2 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 219908 kb
Host smart-dcdb810e-b1e2-408a-b578-f952bf1c7c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994360988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1994360988
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1852110459
Short name T780
Test name
Test status
Simulation time 335633905 ps
CPU time 8.15 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 214364 kb
Host smart-8c0d6ce2-0b3a-4267-a73d-768c03e8d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852110459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1852110459
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2584528869
Short name T13
Test name
Test status
Simulation time 2355117279 ps
CPU time 9.91 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 233948 kb
Host smart-5f685ddc-58d6-4f56-acc5-bfd34359a0b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584528869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2584528869
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2134495728
Short name T715
Test name
Test status
Simulation time 493564836 ps
CPU time 12.15 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:51 PM PDT 24
Peak memory 208048 kb
Host smart-671b8531-0303-4cd1-a056-add4998f4139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134495728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2134495728
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4138882265
Short name T457
Test name
Test status
Simulation time 943043268 ps
CPU time 5.85 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 207944 kb
Host smart-d0ce46c0-affb-437d-8a76-2650cd39d507
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138882265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4138882265
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.696885965
Short name T445
Test name
Test status
Simulation time 528132444 ps
CPU time 4.08 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:44:52 PM PDT 24
Peak memory 208744 kb
Host smart-d4836a92-164e-48af-bdee-62eb472c28a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696885965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.696885965
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1000169294
Short name T580
Test name
Test status
Simulation time 33181605 ps
CPU time 2.37 seconds
Started May 23 03:44:28 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 206832 kb
Host smart-a31db1b1-2334-4284-9b80-be1064202b0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000169294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1000169294
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3125897660
Short name T531
Test name
Test status
Simulation time 1622811591 ps
CPU time 7.13 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 218204 kb
Host smart-c4864833-ef8b-42ed-9a56-7e1bdaaf5a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125897660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3125897660
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.938780803
Short name T755
Test name
Test status
Simulation time 38938949 ps
CPU time 1.7 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:44:58 PM PDT 24
Peak memory 206644 kb
Host smart-3957d4d5-46c2-4b26-90a4-8285b1eb95b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938780803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.938780803
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4253795053
Short name T194
Test name
Test status
Simulation time 687812619 ps
CPU time 12.64 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 218396 kb
Host smart-3b980606-b8d6-448b-9bba-76e65034a131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253795053 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4253795053
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1045388123
Short name T625
Test name
Test status
Simulation time 229411505 ps
CPU time 5.68 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 209252 kb
Host smart-042af8ff-b136-4954-82fa-af95f68f7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045388123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1045388123
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3088808180
Short name T513
Test name
Test status
Simulation time 481725523 ps
CPU time 2.97 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 210568 kb
Host smart-c89ae3d3-77df-418b-a10d-ada9b4a0beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088808180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3088808180
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1409289401
Short name T902
Test name
Test status
Simulation time 13120379 ps
CPU time 0.88 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 205992 kb
Host smart-af52d28c-cc12-4f77-96d4-d049b221bbc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409289401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1409289401
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.415761046
Short name T419
Test name
Test status
Simulation time 36957061 ps
CPU time 3 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 214380 kb
Host smart-8484b92e-6b60-4b93-878d-dfeb0b5c13d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415761046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.415761046
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.916082422
Short name T771
Test name
Test status
Simulation time 1018748690 ps
CPU time 2.28 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 207612 kb
Host smart-db300dac-a34c-43ea-a267-b5d734fe498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916082422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.916082422
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3501171241
Short name T337
Test name
Test status
Simulation time 66512272 ps
CPU time 3.4 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 214380 kb
Host smart-11fc981e-eaee-4894-818d-9a66f04d7017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501171241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3501171241
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3693352671
Short name T229
Test name
Test status
Simulation time 1400788083 ps
CPU time 11.4 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 220120 kb
Host smart-655ee69d-ff4a-4a74-90a2-1d24d4c32e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693352671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3693352671
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.404230046
Short name T677
Test name
Test status
Simulation time 51969571 ps
CPU time 3.25 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 215316 kb
Host smart-8c7f326c-2f83-47d3-ac07-086368f2a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404230046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.404230046
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.988412231
Short name T866
Test name
Test status
Simulation time 144757391 ps
CPU time 3.28 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 209116 kb
Host smart-ceb17e00-794f-48e7-a3f8-559995a0c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988412231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.988412231
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1560487596
Short name T370
Test name
Test status
Simulation time 318761914 ps
CPU time 3.26 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:19 PM PDT 24
Peak memory 214356 kb
Host smart-538a3e40-ce1f-434b-9a78-88887abf8275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560487596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1560487596
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1470078269
Short name T397
Test name
Test status
Simulation time 49145570 ps
CPU time 2.23 seconds
Started May 23 03:45:46 PM PDT 24
Finished May 23 03:46:15 PM PDT 24
Peak memory 206968 kb
Host smart-c303c10e-f5a6-4bb4-b79c-e13490e18b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470078269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1470078269
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2862212230
Short name T807
Test name
Test status
Simulation time 268611758 ps
CPU time 4.3 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:20 PM PDT 24
Peak memory 208632 kb
Host smart-a03a0e7b-a00f-455e-aaa2-bea90f79287e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862212230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2862212230
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.567661210
Short name T527
Test name
Test status
Simulation time 65464563 ps
CPU time 3.46 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 208660 kb
Host smart-2f3141bb-e2b1-4ac8-a80d-d370e56c8fc1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567661210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.567661210
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2249618956
Short name T767
Test name
Test status
Simulation time 2809039366 ps
CPU time 33.94 seconds
Started May 23 03:45:48 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 208120 kb
Host smart-ee76e3a7-db2d-4806-9fb0-e078fca28789
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249618956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2249618956
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1877644733
Short name T761
Test name
Test status
Simulation time 390586668 ps
CPU time 2.25 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:22 PM PDT 24
Peak memory 207716 kb
Host smart-55478046-ae30-4cba-9388-68bdd4242ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877644733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1877644733
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.589217504
Short name T892
Test name
Test status
Simulation time 39209088 ps
CPU time 1.71 seconds
Started May 23 03:45:55 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 206856 kb
Host smart-6e94687c-589d-49ea-9759-3d047b3232d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589217504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.589217504
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2486221364
Short name T216
Test name
Test status
Simulation time 19370493916 ps
CPU time 193.23 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:49:33 PM PDT 24
Peak memory 218752 kb
Host smart-8eeafde7-b069-41c8-ad99-5f3e409fa34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486221364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2486221364
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.189501914
Short name T84
Test name
Test status
Simulation time 2298439067 ps
CPU time 20.23 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 222700 kb
Host smart-dfcff264-67d1-49d3-be37-fe6a44564e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189501914 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.189501914
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3638410534
Short name T443
Test name
Test status
Simulation time 210030572 ps
CPU time 4.86 seconds
Started May 23 03:45:51 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 206992 kb
Host smart-4e986597-d0de-445b-8ff7-ea11142ea119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638410534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3638410534
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1250954659
Short name T383
Test name
Test status
Simulation time 485991787 ps
CPU time 2.9 seconds
Started May 23 03:45:57 PM PDT 24
Finished May 23 03:46:29 PM PDT 24
Peak memory 210096 kb
Host smart-4100960b-3be8-40a2-8b65-638911e62ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250954659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1250954659
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.791404504
Short name T509
Test name
Test status
Simulation time 46108224 ps
CPU time 0.88 seconds
Started May 23 03:45:56 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 205952 kb
Host smart-adf65938-df76-4095-bf1f-7d3ec95b5e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791404504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.791404504
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2263224306
Short name T406
Test name
Test status
Simulation time 157277343 ps
CPU time 3.09 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 215416 kb
Host smart-34c85937-49f6-47ce-bc6f-f6b309448767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263224306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2263224306
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2452493629
Short name T11
Test name
Test status
Simulation time 242456174 ps
CPU time 2.59 seconds
Started May 23 03:45:58 PM PDT 24
Finished May 23 03:46:29 PM PDT 24
Peak memory 217596 kb
Host smart-0ab78ca5-bd04-423f-ac4c-3db87da2a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452493629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2452493629
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1337073145
Short name T241
Test name
Test status
Simulation time 1193841649 ps
CPU time 21.04 seconds
Started May 23 03:45:54 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 208232 kb
Host smart-b1051468-f8ef-4e31-890d-97038ae332b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337073145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1337073145
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.808473469
Short name T109
Test name
Test status
Simulation time 949191825 ps
CPU time 28.59 seconds
Started May 23 03:45:55 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 219332 kb
Host smart-5dc34533-4523-4250-bb38-620c1db854b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808473469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.808473469
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4048509774
Short name T830
Test name
Test status
Simulation time 1008764400 ps
CPU time 4.54 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 222456 kb
Host smart-9b92adad-5b46-47e5-9c6e-209fa7769f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048509774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4048509774
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2335028674
Short name T553
Test name
Test status
Simulation time 81085837 ps
CPU time 2.95 seconds
Started May 23 03:45:49 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 214496 kb
Host smart-6a578d63-1606-4468-a876-bb92020003fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335028674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2335028674
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3392681013
Short name T324
Test name
Test status
Simulation time 104708880 ps
CPU time 4.6 seconds
Started May 23 03:45:55 PM PDT 24
Finished May 23 03:46:28 PM PDT 24
Peak memory 207432 kb
Host smart-85546676-6ef1-4d16-9e89-aa04e86cb0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392681013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3392681013
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3597714677
Short name T248
Test name
Test status
Simulation time 6505366077 ps
CPU time 25.48 seconds
Started May 23 03:46:01 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 208620 kb
Host smart-8edf7663-82c5-4247-84c9-85e56579732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597714677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3597714677
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.689333698
Short name T467
Test name
Test status
Simulation time 221176223 ps
CPU time 2.94 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:21 PM PDT 24
Peak memory 208628 kb
Host smart-d29ffde1-5b64-45b2-9887-bd3b06c5b1e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689333698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.689333698
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3125946794
Short name T333
Test name
Test status
Simulation time 230592545 ps
CPU time 4.89 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 208072 kb
Host smart-245cf13d-53b9-4177-9297-929b65eec8b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125946794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3125946794
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1441819879
Short name T249
Test name
Test status
Simulation time 138405424 ps
CPU time 2.6 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 207340 kb
Host smart-628200b0-aba6-49fb-9bf6-9f09f565a9ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441819879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1441819879
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2483438931
Short name T465
Test name
Test status
Simulation time 179016521 ps
CPU time 5.38 seconds
Started May 23 03:46:01 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 209716 kb
Host smart-a444b34a-cef4-4a70-b678-22a956d2d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483438931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2483438931
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.566959087
Short name T871
Test name
Test status
Simulation time 652035012 ps
CPU time 5.61 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 208816 kb
Host smart-15381f96-d689-463d-a137-44abc4ef1b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566959087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.566959087
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2612051962
Short name T626
Test name
Test status
Simulation time 319702688 ps
CPU time 8.53 seconds
Started May 23 03:45:56 PM PDT 24
Finished May 23 03:46:33 PM PDT 24
Peak memory 215112 kb
Host smart-5ad2c616-063f-456b-97d8-97698d67be5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612051962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2612051962
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1487536814
Short name T363
Test name
Test status
Simulation time 73047513 ps
CPU time 2.58 seconds
Started May 23 03:45:47 PM PDT 24
Finished May 23 03:46:18 PM PDT 24
Peak memory 219840 kb
Host smart-823c3e3b-648c-470e-908c-3531af664f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487536814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1487536814
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1760630234
Short name T558
Test name
Test status
Simulation time 81039479 ps
CPU time 2.82 seconds
Started May 23 03:45:55 PM PDT 24
Finished May 23 03:46:27 PM PDT 24
Peak memory 210224 kb
Host smart-2f198fed-62ec-4e57-9f44-36d5a26a04a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760630234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1760630234
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1608742625
Short name T447
Test name
Test status
Simulation time 83342614 ps
CPU time 0.94 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:33 PM PDT 24
Peak memory 205996 kb
Host smart-16df7a72-b254-4e11-87ba-fddcb515a90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608742625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1608742625
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2372960917
Short name T33
Test name
Test status
Simulation time 553688589 ps
CPU time 2.99 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 208220 kb
Host smart-b623386e-341b-45a7-b3d3-290465ba2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372960917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2372960917
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2817126624
Short name T749
Test name
Test status
Simulation time 256332365 ps
CPU time 3.28 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 208228 kb
Host smart-8162cae2-e6a6-458b-8276-cc0e2aa08614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817126624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2817126624
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3776433584
Short name T102
Test name
Test status
Simulation time 304141456 ps
CPU time 3.52 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:43 PM PDT 24
Peak memory 208284 kb
Host smart-f9c70e2b-4a7f-4a7b-b7d5-7963d02bc27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776433584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3776433584
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2797370480
Short name T372
Test name
Test status
Simulation time 266467232 ps
CPU time 3.27 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 214328 kb
Host smart-51067a86-4db9-4230-be6c-f8c5b146a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797370480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2797370480
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.991141888
Short name T817
Test name
Test status
Simulation time 37996736 ps
CPU time 2.64 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:23 PM PDT 24
Peak memory 220396 kb
Host smart-76196aaa-f528-4090-b1a4-251af3693a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991141888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.991141888
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2421637835
Short name T320
Test name
Test status
Simulation time 472479892 ps
CPU time 5.75 seconds
Started May 23 03:45:58 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 210464 kb
Host smart-bece3305-d725-49a4-bfe7-82fe464bb428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421637835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2421637835
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1715110354
Short name T621
Test name
Test status
Simulation time 38776448 ps
CPU time 2.27 seconds
Started May 23 03:45:53 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 207012 kb
Host smart-826ac557-4c77-4275-80a0-8a4ed36a39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715110354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1715110354
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1321088
Short name T495
Test name
Test status
Simulation time 464387487 ps
CPU time 5.61 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:26 PM PDT 24
Peak memory 208660 kb
Host smart-86398c50-d648-46bb-abfd-af45fa8d983d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1321088
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1327475636
Short name T296
Test name
Test status
Simulation time 149493095 ps
CPU time 3.35 seconds
Started May 23 03:45:56 PM PDT 24
Finished May 23 03:46:28 PM PDT 24
Peak memory 208936 kb
Host smart-686b6449-e260-4b2b-9f7e-a147bb118b7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327475636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1327475636
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1044942138
Short name T94
Test name
Test status
Simulation time 188451851 ps
CPU time 2.61 seconds
Started May 23 03:45:52 PM PDT 24
Finished May 23 03:46:24 PM PDT 24
Peak memory 206984 kb
Host smart-3e7d4488-f4cd-4835-8887-f59dea8148b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044942138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1044942138
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.677633452
Short name T837
Test name
Test status
Simulation time 73101562 ps
CPU time 3.4 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:33 PM PDT 24
Peak memory 207620 kb
Host smart-f22b652a-8254-4091-8d07-cba16f9c5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677633452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.677633452
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.147020234
Short name T484
Test name
Test status
Simulation time 261171660 ps
CPU time 5.73 seconds
Started May 23 03:45:50 PM PDT 24
Finished May 23 03:46:25 PM PDT 24
Peak memory 208620 kb
Host smart-b0acfc8e-de8c-4629-ad1d-9d8fb0920a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147020234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.147020234
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2721327215
Short name T896
Test name
Test status
Simulation time 9552310277 ps
CPU time 96.51 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:48:13 PM PDT 24
Peak memory 216828 kb
Host smart-355dc764-ee57-43ef-9008-1c5305b29411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721327215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2721327215
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3201909342
Short name T861
Test name
Test status
Simulation time 89674872 ps
CPU time 3.57 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 206996 kb
Host smart-db802dc4-696c-43fd-b03f-079f5d0fafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201909342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3201909342
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4029587040
Short name T177
Test name
Test status
Simulation time 39509901 ps
CPU time 1.92 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:31 PM PDT 24
Peak memory 210044 kb
Host smart-a199edcf-b80e-46bd-ab47-9fe7c63659cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029587040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4029587040
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2580383180
Short name T446
Test name
Test status
Simulation time 16558108 ps
CPU time 0.78 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 205988 kb
Host smart-7a371cc2-7ddf-4537-9249-aad6cb905d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580383180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2580383180
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.408390920
Short name T97
Test name
Test status
Simulation time 56050621 ps
CPU time 2.86 seconds
Started May 23 03:46:01 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 215488 kb
Host smart-f8ebbc3a-3260-4105-9ab7-986ef2857a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408390920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.408390920
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1095977492
Short name T684
Test name
Test status
Simulation time 2202464943 ps
CPU time 5.83 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 221896 kb
Host smart-bd21274d-3815-4ff5-a482-608a9f4eed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095977492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1095977492
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1077928963
Short name T70
Test name
Test status
Simulation time 189833701 ps
CPU time 4.31 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 218480 kb
Host smart-4df2a1cb-f95d-49ac-9ae0-8ab9763844a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077928963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1077928963
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3113953791
Short name T340
Test name
Test status
Simulation time 145648955 ps
CPU time 3.64 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 214352 kb
Host smart-43fee85d-72ff-4640-b61d-f45e7130092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113953791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3113953791
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.618525035
Short name T64
Test name
Test status
Simulation time 287399306 ps
CPU time 3.33 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:33 PM PDT 24
Peak memory 209952 kb
Host smart-c3c79092-b5da-48e7-845a-c767130897b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618525035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.618525035
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2281282816
Short name T253
Test name
Test status
Simulation time 207821670 ps
CPU time 5.83 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 209024 kb
Host smart-fbbe3567-da2b-43c2-bb86-bad1b148dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281282816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2281282816
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3279932794
Short name T674
Test name
Test status
Simulation time 120551107 ps
CPU time 3.8 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 208756 kb
Host smart-6c7f867a-64aa-4afe-984a-59b8c5222bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279932794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3279932794
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1909410352
Short name T3
Test name
Test status
Simulation time 1095397764 ps
CPU time 13.47 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 208496 kb
Host smart-566f2f8e-105a-483f-aada-7effd7cc11e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909410352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1909410352
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2570309167
Short name T823
Test name
Test status
Simulation time 873389789 ps
CPU time 30.23 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:47:04 PM PDT 24
Peak memory 208904 kb
Host smart-002781df-98d9-47f4-9f4c-6be21901ef8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570309167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2570309167
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2388144855
Short name T610
Test name
Test status
Simulation time 662605562 ps
CPU time 7.38 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 206984 kb
Host smart-73d7b733-104d-4e76-b822-515eec254767
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388144855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2388144855
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2298815673
Short name T209
Test name
Test status
Simulation time 267809984 ps
CPU time 3.09 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:43 PM PDT 24
Peak memory 209700 kb
Host smart-438f9aff-b7f0-4f29-8dfe-946d7508b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298815673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2298815673
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2097742355
Short name T391
Test name
Test status
Simulation time 125250497 ps
CPU time 3.36 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:33 PM PDT 24
Peak memory 208796 kb
Host smart-32c8e93d-3ce9-449b-b937-a9fd76695639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097742355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2097742355
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2726308961
Short name T385
Test name
Test status
Simulation time 27428005 ps
CPU time 0.8 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 205968 kb
Host smart-9bd94280-8e1d-424e-85bd-836c1a4ca282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726308961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2726308961
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1027169791
Short name T760
Test name
Test status
Simulation time 263809798 ps
CPU time 10.78 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 222680 kb
Host smart-bc3a6c33-5653-49ee-85ed-e8726f05a488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027169791 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1027169791
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.935535414
Short name T488
Test name
Test status
Simulation time 563026342 ps
CPU time 4.51 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 209100 kb
Host smart-c8f35583-14f5-451e-80fb-2852e5d64d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935535414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.935535414
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.130723830
Short name T720
Test name
Test status
Simulation time 39353770 ps
CPU time 2.13 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 209700 kb
Host smart-8271e3f2-ca64-4a2c-8d15-767d78901033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130723830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.130723830
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3689378664
Short name T511
Test name
Test status
Simulation time 12761037 ps
CPU time 0.78 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:30 PM PDT 24
Peak memory 205976 kb
Host smart-148ac761-285a-465d-bd71-5201257ad316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689378664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3689378664
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3295702416
Short name T480
Test name
Test status
Simulation time 169698924 ps
CPU time 2.95 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 209824 kb
Host smart-ca266c7b-59ca-40ca-8b07-619b8b9214e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295702416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3295702416
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2447161564
Short name T732
Test name
Test status
Simulation time 384429870 ps
CPU time 3.43 seconds
Started May 23 03:46:01 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 214612 kb
Host smart-e9366d7c-0199-47cc-ab35-77b612ad0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447161564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2447161564
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3516438199
Short name T294
Test name
Test status
Simulation time 123677872 ps
CPU time 2.38 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:37 PM PDT 24
Peak memory 214312 kb
Host smart-b57979f6-553e-496a-af05-62914ef8226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516438199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3516438199
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.3521289891
Short name T880
Test name
Test status
Simulation time 105792071 ps
CPU time 4.24 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 208880 kb
Host smart-8143990d-6d18-4a53-8c9f-66706a62d997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521289891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3521289891
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.783427204
Short name T716
Test name
Test status
Simulation time 7551493706 ps
CPU time 85.72 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:48:03 PM PDT 24
Peak memory 209096 kb
Host smart-24b3933f-ed9e-4bf1-a7a4-04a3c91bc210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783427204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.783427204
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2222070555
Short name T300
Test name
Test status
Simulation time 52407422 ps
CPU time 2.93 seconds
Started May 23 03:46:02 PM PDT 24
Finished May 23 03:46:32 PM PDT 24
Peak memory 207008 kb
Host smart-3b7b84ed-6d43-422d-b968-e23fb09edf4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222070555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2222070555
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4030557614
Short name T602
Test name
Test status
Simulation time 46959943 ps
CPU time 2.5 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 206904 kb
Host smart-e95c277a-443d-4dc0-8247-0adfe070bd06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030557614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4030557614
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3876952337
Short name T757
Test name
Test status
Simulation time 301785835 ps
CPU time 2.79 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 208664 kb
Host smart-4800bf11-b4c4-4e85-88e4-4da868116ef4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876952337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3876952337
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3537342361
Short name T802
Test name
Test status
Simulation time 658286554 ps
CPU time 3.47 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 218212 kb
Host smart-3c9f4cdd-576f-4a32-a679-f9cfc6842149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537342361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3537342361
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2020332837
Short name T612
Test name
Test status
Simulation time 111995440 ps
CPU time 3.16 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 206896 kb
Host smart-d492c79d-48cb-4419-a476-98c084ac63a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020332837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2020332837
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3857735061
Short name T777
Test name
Test status
Simulation time 19531793487 ps
CPU time 321.49 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:51:52 PM PDT 24
Peak memory 218348 kb
Host smart-4de8fe07-c001-4066-90c3-f36c584449ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857735061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3857735061
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1979987888
Short name T274
Test name
Test status
Simulation time 535198503 ps
CPU time 11.28 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:48 PM PDT 24
Peak memory 222756 kb
Host smart-561ef2d8-3f70-4417-a478-5b6f2a58e5ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979987888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1979987888
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2718712966
Short name T619
Test name
Test status
Simulation time 54792607 ps
CPU time 3.28 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 207720 kb
Host smart-2f4e4356-14d7-46b6-9bf3-77c9848e5960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718712966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2718712966
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1800860403
Short name T826
Test name
Test status
Simulation time 387120098 ps
CPU time 1.93 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 209864 kb
Host smart-26fd2feb-d8ac-433b-818a-d48f138662dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800860403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1800860403
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3559988027
Short name T537
Test name
Test status
Simulation time 13170139 ps
CPU time 0.83 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:37 PM PDT 24
Peak memory 205956 kb
Host smart-23a34ed9-27f3-40fe-b7fb-f61088f8026e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559988027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3559988027
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1787552246
Short name T887
Test name
Test status
Simulation time 737515397 ps
CPU time 40.33 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 214520 kb
Host smart-bca4a2f4-46cc-4cd0-96a7-bc345e5f6fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787552246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1787552246
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.208717871
Short name T800
Test name
Test status
Simulation time 120499968 ps
CPU time 3.01 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 209108 kb
Host smart-bbb481f9-5d4b-4389-ac1a-cd450ff32d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208717871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.208717871
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1377720517
Short name T297
Test name
Test status
Simulation time 81086731 ps
CPU time 3.72 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:44 PM PDT 24
Peak memory 214360 kb
Host smart-83f50967-0613-4105-99b0-298254b40a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377720517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1377720517
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3789956716
Short name T339
Test name
Test status
Simulation time 214173263 ps
CPU time 3.76 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:43 PM PDT 24
Peak memory 205980 kb
Host smart-6a91a196-797c-42e3-8390-5773540c023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789956716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3789956716
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.218551350
Short name T710
Test name
Test status
Simulation time 218307125 ps
CPU time 6.1 seconds
Started May 23 03:46:09 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 210084 kb
Host smart-5244495e-9678-471a-9432-0835597e783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218551350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.218551350
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1729948784
Short name T514
Test name
Test status
Simulation time 224102415 ps
CPU time 2.64 seconds
Started May 23 03:46:03 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 206940 kb
Host smart-4b70c3d2-a451-435f-9724-578e1a0985d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729948784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1729948784
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3607160378
Short name T96
Test name
Test status
Simulation time 306718291 ps
CPU time 2.94 seconds
Started May 23 03:46:07 PM PDT 24
Finished May 23 03:46:40 PM PDT 24
Peak memory 206968 kb
Host smart-d6f42eb5-91d4-4de8-9812-fac17eedfe7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607160378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3607160378
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1574725809
Short name T493
Test name
Test status
Simulation time 12742769263 ps
CPU time 64.53 seconds
Started May 23 03:46:04 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 208492 kb
Host smart-642e7b44-2d0a-4e4b-ab07-9c8c39100b98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574725809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1574725809
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1069542918
Short name T905
Test name
Test status
Simulation time 64168841 ps
CPU time 3.11 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:35 PM PDT 24
Peak memory 208792 kb
Host smart-e49a159a-f537-4087-8626-991d01b44e07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069542918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1069542918
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2735537058
Short name T364
Test name
Test status
Simulation time 295424219 ps
CPU time 3.46 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:36 PM PDT 24
Peak memory 218300 kb
Host smart-91616e84-735f-4be9-b312-fb0a26e48e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735537058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2735537058
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.303791348
Short name T592
Test name
Test status
Simulation time 141505194 ps
CPU time 2.61 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:37 PM PDT 24
Peak memory 206836 kb
Host smart-98987f4c-4144-48cf-9fa8-61a4c77e0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303791348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.303791348
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3004615812
Short name T336
Test name
Test status
Simulation time 118878417 ps
CPU time 5.56 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 209392 kb
Host smart-0dac7ec8-3f6a-45f0-9b94-293bcd8cf9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004615812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3004615812
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2476927018
Short name T1
Test name
Test status
Simulation time 614052680 ps
CPU time 4.75 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 208152 kb
Host smart-46f25662-39ea-4c59-8ef3-7ef703f48a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476927018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2476927018
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.621362007
Short name T779
Test name
Test status
Simulation time 39065757 ps
CPU time 0.77 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:39 PM PDT 24
Peak memory 206008 kb
Host smart-d8723f4e-d337-43f1-9733-ec62c272faae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621362007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.621362007
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1630491632
Short name T28
Test name
Test status
Simulation time 151403417 ps
CPU time 2.31 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 208592 kb
Host smart-ca61e6ab-aa1c-4a45-a4a4-a82be7a3fd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630491632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1630491632
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2372708473
Short name T843
Test name
Test status
Simulation time 140285500 ps
CPU time 2.95 seconds
Started May 23 03:46:12 PM PDT 24
Finished May 23 03:46:44 PM PDT 24
Peak memory 209404 kb
Host smart-c29ae8d7-1a3a-426a-bb7e-7481b14e0e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372708473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2372708473
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2547227662
Short name T662
Test name
Test status
Simulation time 27592734 ps
CPU time 1.88 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 214380 kb
Host smart-960378c1-8f82-4c3f-946a-1f69c517e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547227662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2547227662
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2952732081
Short name T341
Test name
Test status
Simulation time 104053998 ps
CPU time 3.7 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:42 PM PDT 24
Peak memory 214320 kb
Host smart-1e1e2873-f9e2-431f-92cc-41e12580ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952732081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2952732081
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3026418809
Short name T491
Test name
Test status
Simulation time 33146037 ps
CPU time 2.58 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:41 PM PDT 24
Peak memory 207972 kb
Host smart-ca09c476-b453-48cc-8dcd-d8c737f1de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026418809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3026418809
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1279573327
Short name T347
Test name
Test status
Simulation time 246174333 ps
CPU time 5.74 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 214408 kb
Host smart-b1661976-d676-4754-99c1-753428c07edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279573327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1279573327
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3417669615
Short name T874
Test name
Test status
Simulation time 148121070 ps
CPU time 5.34 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 208396 kb
Host smart-249a8b3f-dcf6-44b9-b370-7f08e113fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417669615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3417669615
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2958440765
Short name T878
Test name
Test status
Simulation time 71428591 ps
CPU time 1.76 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 206868 kb
Host smart-99ef3f27-fc29-411e-aa4f-4150e395282f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958440765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2958440765
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2518561182
Short name T121
Test name
Test status
Simulation time 214913560 ps
CPU time 2.91 seconds
Started May 23 03:46:05 PM PDT 24
Finished May 23 03:46:36 PM PDT 24
Peak memory 206980 kb
Host smart-c33493da-124b-400c-80f8-b1a1865fc244
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518561182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2518561182
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.478525369
Short name T597
Test name
Test status
Simulation time 362878153 ps
CPU time 4 seconds
Started May 23 03:46:17 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 210048 kb
Host smart-4fc0ed73-63f1-4757-956c-ad9cb609401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478525369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.478525369
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.759676883
Short name T822
Test name
Test status
Simulation time 656761667 ps
CPU time 4.05 seconds
Started May 23 03:46:18 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 207312 kb
Host smart-ef2406ef-8151-4e45-9941-c60328f8cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759676883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.759676883
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2493961183
Short name T299
Test name
Test status
Simulation time 5940559699 ps
CPU time 19.09 seconds
Started May 23 03:46:06 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 216796 kb
Host smart-5469d8a6-ce9e-4f56-981d-c2c6c925e81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493961183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2493961183
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.274544968
Short name T371
Test name
Test status
Simulation time 1424419915 ps
CPU time 15.08 seconds
Started May 23 03:46:09 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 222672 kb
Host smart-ef1c0a6a-a6ae-4f14-88b8-d4041a7ea0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274544968 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.274544968
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3564002433
Short name T323
Test name
Test status
Simulation time 3724282613 ps
CPU time 45.91 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 214480 kb
Host smart-eba957c7-581b-45e7-b493-d92942f9b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564002433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3564002433
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3025682509
Short name T37
Test name
Test status
Simulation time 413403020 ps
CPU time 2.72 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:51 PM PDT 24
Peak memory 210424 kb
Host smart-b8685958-2204-4f63-b4e7-ad2e3ee34688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025682509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3025682509
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1777322177
Short name T742
Test name
Test status
Simulation time 44952635 ps
CPU time 0.74 seconds
Started May 23 03:46:16 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 205984 kb
Host smart-9259b96b-1520-495a-83c6-e31dc08b1e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777322177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1777322177
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3924807628
Short name T590
Test name
Test status
Simulation time 135669321 ps
CPU time 3.43 seconds
Started May 23 03:46:19 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 222936 kb
Host smart-92a94072-7bda-4087-ad40-758b4ee048e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924807628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3924807628
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1140383913
Short name T856
Test name
Test status
Simulation time 270108232 ps
CPU time 3.37 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 222528 kb
Host smart-597d8881-8983-4720-9fad-459ceab2f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140383913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1140383913
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1600845451
Short name T725
Test name
Test status
Simulation time 473173589 ps
CPU time 5.77 seconds
Started May 23 03:46:20 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 214388 kb
Host smart-ca9a848b-8f74-4e94-9cc8-f9c7b56b6470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600845451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1600845451
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1291729595
Short name T57
Test name
Test status
Simulation time 122539665 ps
CPU time 2.1 seconds
Started May 23 03:46:19 PM PDT 24
Finished May 23 03:46:48 PM PDT 24
Peak memory 220368 kb
Host smart-18809937-395e-477f-b422-86af74090963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291729595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1291729595
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2508022389
Short name T215
Test name
Test status
Simulation time 273984985 ps
CPU time 5.9 seconds
Started May 23 03:46:18 PM PDT 24
Finished May 23 03:46:51 PM PDT 24
Peak memory 209600 kb
Host smart-5b77bd6f-5cc2-41d5-8cd5-18bf63745214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508022389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2508022389
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4120352457
Short name T413
Test name
Test status
Simulation time 217631646 ps
CPU time 6.63 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 207632 kb
Host smart-684551b2-686b-47fd-8b2c-2ade7fd48d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120352457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4120352457
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3467537175
Short name T207
Test name
Test status
Simulation time 56255159 ps
CPU time 2.84 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:43 PM PDT 24
Peak memory 207072 kb
Host smart-ff2e148b-7b67-4d51-95f8-18b20677fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467537175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3467537175
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.658743602
Short name T833
Test name
Test status
Simulation time 46510514 ps
CPU time 2.1 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 209004 kb
Host smart-02bd6675-02ff-4d63-b3f3-937a7b34bf8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658743602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.658743602
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.900433550
Short name T758
Test name
Test status
Simulation time 802588853 ps
CPU time 4.21 seconds
Started May 23 03:46:10 PM PDT 24
Finished May 23 03:46:45 PM PDT 24
Peak memory 207004 kb
Host smart-c19dff51-542b-4fd2-92c5-54827583d791
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900433550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.900433550
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.119203610
Short name T472
Test name
Test status
Simulation time 762863611 ps
CPU time 11.44 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:47:05 PM PDT 24
Peak memory 208008 kb
Host smart-d1672bbc-1264-40d4-847e-4f06b1762e5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119203610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.119203610
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1310556592
Short name T885
Test name
Test status
Simulation time 207905470 ps
CPU time 2.8 seconds
Started May 23 03:46:18 PM PDT 24
Finished May 23 03:46:48 PM PDT 24
Peak memory 215608 kb
Host smart-d5e3a64d-0289-4b94-98f9-e58c57eb517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310556592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1310556592
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3887061078
Short name T536
Test name
Test status
Simulation time 52165682 ps
CPU time 2.52 seconds
Started May 23 03:46:08 PM PDT 24
Finished May 23 03:46:41 PM PDT 24
Peak memory 207044 kb
Host smart-473a408a-91c2-4937-b484-c3478acdd359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887061078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3887061078
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3388051528
Short name T569
Test name
Test status
Simulation time 10561645749 ps
CPU time 23.47 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:47:11 PM PDT 24
Peak memory 208696 kb
Host smart-69ff5eb8-83ba-4601-93c5-64ffb176e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388051528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3388051528
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1716226079
Short name T379
Test name
Test status
Simulation time 54025075 ps
CPU time 2 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:46:51 PM PDT 24
Peak memory 210140 kb
Host smart-fad24603-f4dc-4a1c-9be2-b99ac430903d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716226079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1716226079
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2772443785
Short name T683
Test name
Test status
Simulation time 28999950 ps
CPU time 0.77 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 206004 kb
Host smart-bf52d5a3-ef84-470c-8ffc-ed5dc7294b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772443785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2772443785
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1361287356
Short name T421
Test name
Test status
Simulation time 76437572 ps
CPU time 3.02 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 215412 kb
Host smart-78b909da-8219-45dd-bcec-d8690fced25b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361287356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1361287356
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3486979042
Short name T21
Test name
Test status
Simulation time 115011443 ps
CPU time 4.43 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 214756 kb
Host smart-5d7e0cd7-e67e-47d9-ba8e-719ec2966495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486979042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3486979042
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2412802176
Short name T731
Test name
Test status
Simulation time 291940521 ps
CPU time 2.15 seconds
Started May 23 03:46:20 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 209580 kb
Host smart-86ff5f36-6018-4983-a6f6-f71a799d16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412802176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2412802176
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4079455161
Short name T26
Test name
Test status
Simulation time 1757342319 ps
CPU time 42.76 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 221768 kb
Host smart-d787ac17-110a-40c7-a549-6ced00efc088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079455161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4079455161
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3418613156
Short name T312
Test name
Test status
Simulation time 87075213 ps
CPU time 3.35 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 214312 kb
Host smart-92ba6a02-69a7-45c9-97b7-49711c0c8827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418613156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3418613156
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1725462094
Short name T860
Test name
Test status
Simulation time 522217356 ps
CPU time 2.96 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:52 PM PDT 24
Peak memory 209068 kb
Host smart-1bf85b59-c67a-4fa9-a236-e3010f796720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725462094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1725462094
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2751117191
Short name T448
Test name
Test status
Simulation time 477510086 ps
CPU time 3.48 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:51 PM PDT 24
Peak memory 207932 kb
Host smart-1781d245-a4ff-4017-8359-7e3054ca4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751117191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2751117191
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2409699994
Short name T883
Test name
Test status
Simulation time 508213977 ps
CPU time 4.52 seconds
Started May 23 03:46:16 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 206900 kb
Host smart-21d3956c-6ec5-4c3b-afb3-3e5ecc2a2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409699994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2409699994
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1241786840
Short name T326
Test name
Test status
Simulation time 115045260 ps
CPU time 4.75 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 206992 kb
Host smart-2858d26a-ec26-4cfa-9a41-fcfd1cc69f52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241786840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1241786840
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2496068455
Short name T295
Test name
Test status
Simulation time 236215129 ps
CPU time 2.26 seconds
Started May 23 03:46:16 PM PDT 24
Finished May 23 03:46:46 PM PDT 24
Peak memory 208684 kb
Host smart-0ee5f061-183f-43fe-87b3-691eaabdd5fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496068455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2496068455
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1710390524
Short name T327
Test name
Test status
Simulation time 39379611 ps
CPU time 2.44 seconds
Started May 23 03:46:17 PM PDT 24
Finished May 23 03:46:47 PM PDT 24
Peak memory 207432 kb
Host smart-c2ceb9c5-5e0f-4ff0-9bc2-b7dbf2d5324e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710390524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1710390524
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1095289581
Short name T679
Test name
Test status
Simulation time 148380552 ps
CPU time 2.9 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 207860 kb
Host smart-edca975b-1875-4c5e-8a7d-0310bfbfa4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095289581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1095289581
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1034390310
Short name T687
Test name
Test status
Simulation time 338178914 ps
CPU time 4.07 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 208788 kb
Host smart-ee46fafc-a75f-48e3-b520-5f43ba8736d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034390310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1034390310
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2821435422
Short name T381
Test name
Test status
Simulation time 75059756 ps
CPU time 2.07 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 209872 kb
Host smart-6c95f073-abb9-42b4-85db-388596da2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821435422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2821435422
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3605525651
Short name T464
Test name
Test status
Simulation time 119749256 ps
CPU time 0.75 seconds
Started May 23 03:46:20 PM PDT 24
Finished May 23 03:46:48 PM PDT 24
Peak memory 205996 kb
Host smart-7a2e922f-9781-4dae-8486-264ff13c7b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605525651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3605525651
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1329139153
Short name T88
Test name
Test status
Simulation time 69299488 ps
CPU time 3.55 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 209588 kb
Host smart-26474024-2167-4759-8d2e-9e29d647def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329139153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1329139153
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4138718024
Short name T279
Test name
Test status
Simulation time 69728016 ps
CPU time 2.77 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 214204 kb
Host smart-116a8434-85e3-40f3-89ac-c9927f2e369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138718024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4138718024
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.760111515
Short name T690
Test name
Test status
Simulation time 88078236 ps
CPU time 3 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 221068 kb
Host smart-4a20c66a-a0c6-4faf-b5cd-f955f9c877a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760111515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.760111515
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.906826734
Short name T218
Test name
Test status
Simulation time 89395177 ps
CPU time 4.36 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 209704 kb
Host smart-92a89499-1676-4eba-9fd4-c532cec0d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906826734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.906826734
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3672484371
Short name T747
Test name
Test status
Simulation time 59219013 ps
CPU time 3.74 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 214328 kb
Host smart-81f09b24-88ec-48f2-83ba-c9cf6710c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672484371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3672484371
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1520466310
Short name T396
Test name
Test status
Simulation time 78046437 ps
CPU time 3.2 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:55 PM PDT 24
Peak memory 206880 kb
Host smart-f60cca8e-9e0b-4223-82ca-6757f4c7ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520466310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1520466310
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.445342825
Short name T781
Test name
Test status
Simulation time 297491987 ps
CPU time 3.58 seconds
Started May 23 03:46:22 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 207444 kb
Host smart-1e4d884c-b344-4959-9be2-2c7226737c99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445342825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.445342825
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3369693628
Short name T463
Test name
Test status
Simulation time 312348531 ps
CPU time 3.28 seconds
Started May 23 03:46:15 PM PDT 24
Finished May 23 03:46:46 PM PDT 24
Peak memory 206772 kb
Host smart-e3c85595-3f4b-40c9-b638-4fa4a5cfb11b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369693628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3369693628
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1835721269
Short name T257
Test name
Test status
Simulation time 45701942 ps
CPU time 2.45 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 208236 kb
Host smart-bf94ac8d-f509-41d0-922a-65b60b377c66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835721269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1835721269
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4140614133
Short name T587
Test name
Test status
Simulation time 34430756 ps
CPU time 2.07 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:52 PM PDT 24
Peak memory 209104 kb
Host smart-9fb3f8e6-3580-4412-9e8b-28f972f8c4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140614133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4140614133
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.74982698
Short name T430
Test name
Test status
Simulation time 269922702 ps
CPU time 3 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 208620 kb
Host smart-c339c518-729a-450c-a691-0886bfe15105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74982698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.74982698
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1510632924
Short name T759
Test name
Test status
Simulation time 1124007073 ps
CPU time 8.36 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 219212 kb
Host smart-943cb44c-8e56-4074-a06d-5149d6049807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510632924 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1510632924
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2747594363
Short name T19
Test name
Test status
Simulation time 5611413231 ps
CPU time 69.53 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:48:05 PM PDT 24
Peak memory 209796 kb
Host smart-984379d7-5017-4785-8f2f-1ef800fb6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747594363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2747594363
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1506752848
Short name T434
Test name
Test status
Simulation time 15273301 ps
CPU time 0.79 seconds
Started May 23 03:44:49 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 205992 kb
Host smart-e19e0749-461f-4c66-af60-e27501c76bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506752848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1506752848
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3299959598
Short name T256
Test name
Test status
Simulation time 63518634 ps
CPU time 2.74 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 214376 kb
Host smart-2a540e1f-8645-4b51-aebd-3f6255bbdb31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299959598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3299959598
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3589749882
Short name T32
Test name
Test status
Simulation time 60286986 ps
CPU time 2.19 seconds
Started May 23 03:44:50 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 208428 kb
Host smart-a40a264b-b920-4969-a121-0e52dad793e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589749882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3589749882
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.905075096
Short name T564
Test name
Test status
Simulation time 219098968 ps
CPU time 3.18 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 207800 kb
Host smart-cac72118-28a3-414a-b4b1-0d994d465576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905075096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.905075096
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1459947609
Short name T103
Test name
Test status
Simulation time 83448100 ps
CPU time 2.95 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 214452 kb
Host smart-e64ecf68-ffc7-435c-86ee-b380bff23d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459947609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1459947609
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.422607676
Short name T292
Test name
Test status
Simulation time 934771364 ps
CPU time 3.12 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 214320 kb
Host smart-40fa9a12-9a84-4d15-98bc-a108ad6353d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422607676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.422607676
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3381108218
Short name T222
Test name
Test status
Simulation time 353417367 ps
CPU time 4.3 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 208796 kb
Host smart-aaeafe3b-b7e4-420c-bd3e-983b93b071de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381108218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3381108218
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3489107991
Short name T707
Test name
Test status
Simulation time 17240972153 ps
CPU time 23.53 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 208904 kb
Host smart-2a72595d-c142-4386-99f1-6c4b848b2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489107991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3489107991
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4020080619
Short name T93
Test name
Test status
Simulation time 384513539 ps
CPU time 7.21 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:58 PM PDT 24
Peak memory 207976 kb
Host smart-80fe5ab4-3297-485e-a790-8ec380f1cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020080619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4020080619
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.504564895
Short name T673
Test name
Test status
Simulation time 157285921 ps
CPU time 3.17 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 207064 kb
Host smart-24cbe208-c218-43c8-bea7-0308210b3801
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504564895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.504564895
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.432118910
Short name T778
Test name
Test status
Simulation time 1745113940 ps
CPU time 7.48 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 208052 kb
Host smart-988e451d-568a-4f75-9c46-a10a07103c83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432118910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.432118910
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1935364257
Short name T670
Test name
Test status
Simulation time 61257919 ps
CPU time 3.05 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 208744 kb
Host smart-ff0258ac-663e-4211-b3b6-444fc65fde8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935364257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1935364257
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3047075036
Short name T692
Test name
Test status
Simulation time 91198701 ps
CPU time 1.89 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 207248 kb
Host smart-8c6f7c04-171d-4874-a93b-0dd085030626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047075036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3047075036
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3308458924
Short name T449
Test name
Test status
Simulation time 32204840 ps
CPU time 2.05 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:45 PM PDT 24
Peak memory 206192 kb
Host smart-9e7cf960-7f34-4a11-8385-8650e2af08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308458924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3308458924
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3002780788
Short name T193
Test name
Test status
Simulation time 1136602630 ps
CPU time 12.3 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 222600 kb
Host smart-1f30b951-0806-42d5-b812-b0945277b6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002780788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3002780788
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3439222421
Short name T515
Test name
Test status
Simulation time 112753374 ps
CPU time 2.95 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 207560 kb
Host smart-2cf88e95-ca22-4f86-9ef7-d1382cd1802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439222421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3439222421
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1481308779
Short name T554
Test name
Test status
Simulation time 337456067 ps
CPU time 3.38 seconds
Started May 23 03:44:49 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 210636 kb
Host smart-0fb7536c-c57c-4dda-ae35-8d1da466eba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481308779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1481308779
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3406335562
Short name T904
Test name
Test status
Simulation time 46247389 ps
CPU time 0.75 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 205992 kb
Host smart-4685dee2-7a18-4cd0-a5a4-8742f667a826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406335562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3406335562
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1152677086
Short name T352
Test name
Test status
Simulation time 36572200 ps
CPU time 2.76 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:57 PM PDT 24
Peak memory 214396 kb
Host smart-0b7e4af6-8108-4b83-ae52-020200ffb0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152677086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1152677086
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.948334442
Short name T552
Test name
Test status
Simulation time 52249900 ps
CPU time 2.33 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 208856 kb
Host smart-97435506-56b5-4559-8eca-e6acf2ebfcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948334442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.948334442
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3056569695
Short name T559
Test name
Test status
Simulation time 50449420 ps
CPU time 2.57 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 218372 kb
Host smart-05a53672-8736-4655-bca3-3456cdac1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056569695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3056569695
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2531670508
Short name T230
Test name
Test status
Simulation time 272452833 ps
CPU time 3.49 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:52 PM PDT 24
Peak memory 209436 kb
Host smart-5f371275-110b-45bc-b49b-7186c3efd979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531670508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2531670508
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4291956840
Short name T51
Test name
Test status
Simulation time 58515963 ps
CPU time 1.96 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 214320 kb
Host smart-d53bea5b-814f-4d70-988b-d756c53f33e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291956840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4291956840
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1676425222
Short name T8
Test name
Test status
Simulation time 117911564 ps
CPU time 4.02 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 222600 kb
Host smart-eff2ac45-1b1a-44fe-b591-8ea7e54a7791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676425222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1676425222
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4038410232
Short name T840
Test name
Test status
Simulation time 962503949 ps
CPU time 25.86 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 209192 kb
Host smart-b3c36139-53e9-4007-8803-9902f0d3ce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038410232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4038410232
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2043353806
Short name T542
Test name
Test status
Simulation time 22511441 ps
CPU time 1.91 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 207396 kb
Host smart-0bfd3455-3133-4dcd-9bf1-9dee8e0f4631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043353806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2043353806
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3963008207
Short name T348
Test name
Test status
Simulation time 135980610 ps
CPU time 3.52 seconds
Started May 23 03:46:18 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 208236 kb
Host smart-df769e86-4f46-436d-af0c-ed8706878063
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963008207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3963008207
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1105829129
Short name T460
Test name
Test status
Simulation time 2069245444 ps
CPU time 31.74 seconds
Started May 23 03:46:17 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 208764 kb
Host smart-f5eabe88-d523-4d50-b844-d35790890614
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105829129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1105829129
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1369990582
Short name T2
Test name
Test status
Simulation time 368373840 ps
CPU time 3.67 seconds
Started May 23 03:46:21 PM PDT 24
Finished May 23 03:46:52 PM PDT 24
Peak memory 208776 kb
Host smart-6c3468b4-84ec-4ada-afac-50e16553adf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369990582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1369990582
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3741640179
Short name T550
Test name
Test status
Simulation time 806987194 ps
CPU time 3.57 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 207500 kb
Host smart-542adb40-bc33-4629-bb21-f2730bbbfd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741640179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3741640179
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2698505711
Short name T428
Test name
Test status
Simulation time 4493168654 ps
CPU time 40.48 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 208912 kb
Host smart-4a845e45-344c-4473-b545-2dcfaf3e5125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698505711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2698505711
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.244813656
Short name T538
Test name
Test status
Simulation time 224272760 ps
CPU time 7.64 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:47:04 PM PDT 24
Peak memory 208620 kb
Host smart-e19d7666-062c-46dd-aa48-446b3be71977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244813656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.244813656
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1466230081
Short name T380
Test name
Test status
Simulation time 159972932 ps
CPU time 1.44 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 209656 kb
Host smart-612ef634-692e-4e44-b838-1910938e5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466230081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1466230081
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.792794075
Short name T588
Test name
Test status
Simulation time 27099634 ps
CPU time 0.88 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 205980 kb
Host smart-4fc823d3-f6d2-43c1-88dd-352d105538f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792794075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.792794075
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3741768069
Short name T349
Test name
Test status
Simulation time 199447340 ps
CPU time 3.61 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 214396 kb
Host smart-87a6eeeb-4589-40c9-b10d-197b8f4a562f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741768069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3741768069
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1698738291
Short name T595
Test name
Test status
Simulation time 954536313 ps
CPU time 2.97 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 216620 kb
Host smart-b8215b3a-cbce-481b-b18e-d5b5abe74c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698738291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1698738291
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1216083231
Short name T881
Test name
Test status
Simulation time 28310808 ps
CPU time 2.06 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 214464 kb
Host smart-f470526c-a9be-4946-af65-4df72a1a2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216083231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1216083231
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.548808012
Short name T231
Test name
Test status
Simulation time 232499806 ps
CPU time 3.68 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 222472 kb
Host smart-5cac528e-2d68-4c2f-a322-43c8ecaf6de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548808012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.548808012
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1249496354
Short name T223
Test name
Test status
Simulation time 126612392 ps
CPU time 6.2 seconds
Started May 23 03:46:23 PM PDT 24
Finished May 23 03:46:57 PM PDT 24
Peak memory 214456 kb
Host smart-2d75ce00-2750-4292-8179-84b2364faf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249496354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1249496354
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4022735955
Short name T529
Test name
Test status
Simulation time 92778148 ps
CPU time 4.2 seconds
Started May 23 03:46:18 PM PDT 24
Finished May 23 03:46:50 PM PDT 24
Peak memory 218284 kb
Host smart-ad3e2ed0-bc19-4218-b717-94ad0d0ab559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022735955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4022735955
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2491473447
Short name T900
Test name
Test status
Simulation time 91570832 ps
CPU time 4.07 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 209044 kb
Host smart-c8004924-d991-4e29-8841-583d9b15d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491473447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2491473447
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2351057071
Short name T273
Test name
Test status
Simulation time 718750528 ps
CPU time 7.51 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:06 PM PDT 24
Peak memory 208964 kb
Host smart-8f48cb0c-ed48-42d4-bb33-ce0d6999656c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351057071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2351057071
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3535565854
Short name T367
Test name
Test status
Simulation time 99972639 ps
CPU time 2.73 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 207044 kb
Host smart-6d00798b-29ca-4e08-a138-e95d8b35f864
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535565854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3535565854
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1763209067
Short name T458
Test name
Test status
Simulation time 125372578 ps
CPU time 2.62 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 208900 kb
Host smart-29c6f6d6-996e-4f31-904e-da81e7d9d156
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763209067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1763209067
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2665007328
Short name T415
Test name
Test status
Simulation time 18297035 ps
CPU time 1.62 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 207048 kb
Host smart-e3b59ad1-81e7-4af3-9407-9aae3aac9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665007328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2665007328
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2143758532
Short name T658
Test name
Test status
Simulation time 82554562 ps
CPU time 2.27 seconds
Started May 23 03:46:20 PM PDT 24
Finished May 23 03:46:49 PM PDT 24
Peak memory 208192 kb
Host smart-b9773902-2b44-4141-9186-6d87cbd2f5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143758532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2143758532
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.973377872
Short name T260
Test name
Test status
Simulation time 260087859 ps
CPU time 4.5 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 209808 kb
Host smart-cf36047d-6905-4770-a730-fe6a3802237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973377872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.973377872
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.89462224
Short name T36
Test name
Test status
Simulation time 193822255 ps
CPU time 4.06 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 210644 kb
Host smart-b7d39d93-77b7-465e-8a7d-7928ff2ca5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89462224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.89462224
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.768643868
Short name T479
Test name
Test status
Simulation time 50695047 ps
CPU time 0.87 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:54 PM PDT 24
Peak memory 205996 kb
Host smart-2e7bce75-2b7a-43c7-ada4-b6bf9f7da2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768643868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.768643868
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2786261166
Short name T409
Test name
Test status
Simulation time 53224316 ps
CPU time 3.87 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:02 PM PDT 24
Peak memory 214344 kb
Host smart-bfc7ca31-a304-41eb-93f8-a2be5ce593e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786261166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2786261166
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.830821272
Short name T911
Test name
Test status
Simulation time 171540218 ps
CPU time 4.25 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:03 PM PDT 24
Peak memory 209772 kb
Host smart-291c4d50-ffba-43cd-9855-f046cf6c09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830821272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.830821272
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3398287966
Short name T350
Test name
Test status
Simulation time 119579151 ps
CPU time 5.15 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:47:04 PM PDT 24
Peak memory 208488 kb
Host smart-fe26ffa4-c5bd-4c17-8c48-0a80b70add41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398287966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3398287966
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.907785853
Short name T469
Test name
Test status
Simulation time 1108364389 ps
CPU time 8.98 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:47:03 PM PDT 24
Peak memory 222396 kb
Host smart-f3fc8d9c-b344-4e46-b6dc-3be0cd29398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907785853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.907785853
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3855086532
Short name T561
Test name
Test status
Simulation time 135697353 ps
CPU time 2.57 seconds
Started May 23 03:46:47 PM PDT 24
Finished May 23 03:47:20 PM PDT 24
Peak memory 220576 kb
Host smart-36f5180d-1a6e-421e-a56a-61b9f1192f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855086532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3855086532
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2332266355
Short name T847
Test name
Test status
Simulation time 937304033 ps
CPU time 21.27 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 210140 kb
Host smart-b419b380-ca9c-4fa6-90b9-a2e2b84ce02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332266355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2332266355
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.782077760
Short name T476
Test name
Test status
Simulation time 3659573722 ps
CPU time 37.36 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 209000 kb
Host smart-c4c1ccf6-a6cf-4a41-a8ab-54233f4a81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782077760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.782077760
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.836238905
Short name T703
Test name
Test status
Simulation time 60513847 ps
CPU time 3.02 seconds
Started May 23 03:46:25 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 206996 kb
Host smart-95ff6cae-5243-4b2e-b763-b489d142a0ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836238905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.836238905
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2655581626
Short name T560
Test name
Test status
Simulation time 78996895 ps
CPU time 3.08 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:02 PM PDT 24
Peak memory 206948 kb
Host smart-58531ba9-e445-4ce9-a067-4bfc4bfc5bb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655581626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2655581626
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3186913896
Short name T483
Test name
Test status
Simulation time 207324940 ps
CPU time 2.71 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 206964 kb
Host smart-8a0ed718-95b1-4c26-8dcb-677dd15b416d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186913896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3186913896
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2698457079
Short name T737
Test name
Test status
Simulation time 47943501 ps
CPU time 2.25 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 207160 kb
Host smart-0ab67ead-9375-46bb-98d4-796aa8c7cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698457079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2698457079
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3253428503
Short name T630
Test name
Test status
Simulation time 65761748 ps
CPU time 2.97 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 207552 kb
Host smart-b7b370d5-64e4-48ee-9f8b-1f66d37d10a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253428503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3253428503
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2909914832
Short name T306
Test name
Test status
Simulation time 746652832 ps
CPU time 28.78 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:47:24 PM PDT 24
Peak memory 216016 kb
Host smart-7a6311ed-2e2d-44ee-9a61-f4b83e647474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909914832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2909914832
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.191176743
Short name T401
Test name
Test status
Simulation time 1423080056 ps
CPU time 7.8 seconds
Started May 23 03:46:30 PM PDT 24
Finished May 23 03:47:06 PM PDT 24
Peak memory 209952 kb
Host smart-0415d15d-ffd2-42b0-a1d1-d768b46d8a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191176743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.191176743
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2341037826
Short name T179
Test name
Test status
Simulation time 176680863 ps
CPU time 1.86 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 214452 kb
Host smart-69e4e793-5a9b-4843-b70f-eb4ccb87a2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341037826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2341037826
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1971148317
Short name T910
Test name
Test status
Simulation time 22776155 ps
CPU time 1.05 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:46:57 PM PDT 24
Peak memory 206252 kb
Host smart-50f004a3-71af-4288-9c24-32c183fd5dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971148317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1971148317
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2016280602
Short name T879
Test name
Test status
Simulation time 44885653 ps
CPU time 3.21 seconds
Started May 23 03:46:36 PM PDT 24
Finished May 23 03:47:08 PM PDT 24
Peak memory 215392 kb
Host smart-95dd9e64-edb2-4002-9ad5-d2418be543fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016280602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2016280602
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3677357688
Short name T34
Test name
Test status
Simulation time 459644788 ps
CPU time 8.73 seconds
Started May 23 03:46:30 PM PDT 24
Finished May 23 03:47:07 PM PDT 24
Peak memory 210436 kb
Host smart-3c1e8e2f-3bcc-41d5-b9b5-a01ca6f69819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677357688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3677357688
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3961495794
Short name T291
Test name
Test status
Simulation time 132132136 ps
CPU time 5.33 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 214404 kb
Host smart-cc40a8e0-59f2-40f9-a8cd-a0b7c5ee2a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961495794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3961495794
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.82075223
Short name T376
Test name
Test status
Simulation time 69180511 ps
CPU time 3.34 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 214384 kb
Host smart-76633677-99c6-4031-ac21-a8c2ea9d844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82075223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.82075223
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.671236716
Short name T342
Test name
Test status
Simulation time 355327080 ps
CPU time 5.63 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 214384 kb
Host smart-db6f8379-4179-4069-bd73-b4e0a385a3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671236716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.671236716
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.2250061499
Short name T651
Test name
Test status
Simulation time 514599238 ps
CPU time 4.96 seconds
Started May 23 03:46:37 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 214444 kb
Host smart-28e18f1f-3b46-47c4-a159-d4ef0091a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250061499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2250061499
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.747078828
Short name T642
Test name
Test status
Simulation time 255686372 ps
CPU time 7.27 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:20 PM PDT 24
Peak memory 208076 kb
Host smart-7cc845f8-35ef-4f2a-8f8f-c8e28b82e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747078828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.747078828
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3197490652
Short name T753
Test name
Test status
Simulation time 7668567919 ps
CPU time 78.16 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:48:17 PM PDT 24
Peak memory 208404 kb
Host smart-aa18a238-42ac-4a19-a1d1-cc0ba704f347
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197490652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3197490652
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2607163888
Short name T570
Test name
Test status
Simulation time 68804915 ps
CPU time 2.59 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 208740 kb
Host smart-f857c4c6-c2dd-4bde-87a2-7114046e713e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607163888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2607163888
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3109047085
Short name T521
Test name
Test status
Simulation time 419650856 ps
CPU time 3.47 seconds
Started May 23 03:46:36 PM PDT 24
Finished May 23 03:47:08 PM PDT 24
Peak memory 207284 kb
Host smart-cd97545e-edfa-4c10-b6be-d1cc32e2457d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109047085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3109047085
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.650326282
Short name T704
Test name
Test status
Simulation time 204132221 ps
CPU time 3.73 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:47:03 PM PDT 24
Peak memory 209460 kb
Host smart-e3317c56-e7ae-450c-9999-c0868d641918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650326282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.650326282
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.721218204
Short name T563
Test name
Test status
Simulation time 155515730 ps
CPU time 3.67 seconds
Started May 23 03:46:24 PM PDT 24
Finished May 23 03:46:56 PM PDT 24
Peak memory 208476 kb
Host smart-448f0bb1-b6a3-4809-b121-a75073c255e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721218204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.721218204
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3900025922
Short name T627
Test name
Test status
Simulation time 85474948 ps
CPU time 4.34 seconds
Started May 23 03:46:35 PM PDT 24
Finished May 23 03:47:07 PM PDT 24
Peak memory 209228 kb
Host smart-54030d56-881a-4677-860f-9aec2cdfd09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900025922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3900025922
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.741400739
Short name T805
Test name
Test status
Simulation time 51894996 ps
CPU time 1.51 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 210484 kb
Host smart-d56332fb-2e42-4a32-9a73-b7be12a8acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741400739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.741400739
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3583632345
Short name T473
Test name
Test status
Simulation time 17479801 ps
CPU time 0.85 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:46:58 PM PDT 24
Peak memory 205992 kb
Host smart-4e30a22d-e418-4e44-a2ee-438b47364a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583632345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3583632345
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3234024082
Short name T405
Test name
Test status
Simulation time 152536707 ps
CPU time 3.56 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:46:59 PM PDT 24
Peak memory 214328 kb
Host smart-e0af9dfa-dc29-426b-81d4-25e569d71bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234024082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3234024082
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1505324453
Short name T634
Test name
Test status
Simulation time 252977377 ps
CPU time 4.23 seconds
Started May 23 03:46:37 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 221256 kb
Host smart-95be187c-9938-473c-aa78-2f0ef6de24cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505324453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1505324453
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.704332024
Short name T789
Test name
Test status
Simulation time 887193515 ps
CPU time 20.81 seconds
Started May 23 03:46:36 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 209196 kb
Host smart-c93835ad-ba47-4b28-b625-e817f8b8fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704332024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.704332024
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2077207372
Short name T357
Test name
Test status
Simulation time 63599296 ps
CPU time 2.65 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 214400 kb
Host smart-acfed18c-e164-4454-95af-0325e0a12345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077207372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2077207372
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3168192577
Short name T356
Test name
Test status
Simulation time 98422017 ps
CPU time 2.27 seconds
Started May 23 03:46:35 PM PDT 24
Finished May 23 03:47:06 PM PDT 24
Peak memory 220540 kb
Host smart-a536a7d6-41cb-40e7-978a-d4da83b22eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168192577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3168192577
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3829799097
Short name T219
Test name
Test status
Simulation time 190350853 ps
CPU time 3.42 seconds
Started May 23 03:46:35 PM PDT 24
Finished May 23 03:47:07 PM PDT 24
Peak memory 207840 kb
Host smart-dd3ae98b-bdce-464d-92ad-1ac6da7b9d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829799097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3829799097
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2770404635
Short name T864
Test name
Test status
Simulation time 1562223872 ps
CPU time 5.82 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 209744 kb
Host smart-1f52d6f4-2abe-49c7-b197-c8bcdf1953d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770404635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2770404635
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3980437020
Short name T816
Test name
Test status
Simulation time 240877202 ps
CPU time 4.43 seconds
Started May 23 03:46:34 PM PDT 24
Finished May 23 03:47:06 PM PDT 24
Peak memory 208316 kb
Host smart-b448257f-f9c4-4e48-b60f-f0332346bd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980437020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3980437020
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3192535643
Short name T726
Test name
Test status
Simulation time 984292759 ps
CPU time 26.19 seconds
Started May 23 03:46:36 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 208948 kb
Host smart-61c2e8d0-4a72-4253-b822-f74ca0138173
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192535643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3192535643
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1686536827
Short name T694
Test name
Test status
Simulation time 895131907 ps
CPU time 8.26 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:05 PM PDT 24
Peak memory 208260 kb
Host smart-f615a63d-7b9f-4c4e-8d71-9e2a8e1c4495
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686536827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1686536827
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.249381674
Short name T332
Test name
Test status
Simulation time 214210163 ps
CPU time 5.77 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:47:05 PM PDT 24
Peak memory 208636 kb
Host smart-16942242-438c-4fbf-90fd-3d4bc46d5892
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249381674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.249381674
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1682801657
Short name T608
Test name
Test status
Simulation time 99630528 ps
CPU time 3.36 seconds
Started May 23 03:46:38 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 214336 kb
Host smart-dadfc028-361d-4ac3-8779-7601e888590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682801657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1682801657
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3700385232
Short name T438
Test name
Test status
Simulation time 72183554 ps
CPU time 1.74 seconds
Started May 23 03:46:32 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 206824 kb
Host smart-8fc0188a-9e28-4f36-8301-1c152a3c4b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700385232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3700385232
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2489404262
Short name T71
Test name
Test status
Simulation time 573119707 ps
CPU time 18.5 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 222380 kb
Host smart-1f794319-9efb-4f4c-8585-361e7448acfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489404262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2489404262
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4096586826
Short name T303
Test name
Test status
Simulation time 120565161 ps
CPU time 5.88 seconds
Started May 23 03:46:26 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 209112 kb
Host smart-34fa1a74-bf32-4ebc-b4b2-d0f6418cd188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096586826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4096586826
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1136513505
Short name T738
Test name
Test status
Simulation time 45129731 ps
CPU time 1.83 seconds
Started May 23 03:46:37 PM PDT 24
Finished May 23 03:47:07 PM PDT 24
Peak memory 209868 kb
Host smart-064beffb-2392-4df1-9036-f489fb09bf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136513505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1136513505
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1424745981
Short name T437
Test name
Test status
Simulation time 22865908 ps
CPU time 0.81 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:09 PM PDT 24
Peak memory 205988 kb
Host smart-3c27c261-fb33-4a3b-8705-d70434bb6c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424745981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1424745981
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3149442980
Short name T416
Test name
Test status
Simulation time 644906869 ps
CPU time 3.58 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 214356 kb
Host smart-e969270d-93d7-4052-b778-3cec4e474851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149442980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3149442980
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.363315900
Short name T794
Test name
Test status
Simulation time 255749686 ps
CPU time 3.59 seconds
Started May 23 03:46:30 PM PDT 24
Finished May 23 03:47:02 PM PDT 24
Peak memory 208264 kb
Host smart-5087153b-d41e-4c40-847e-80d8d3e9f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363315900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.363315900
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.792340036
Short name T263
Test name
Test status
Simulation time 68826313 ps
CPU time 3.16 seconds
Started May 23 03:46:28 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 214380 kb
Host smart-859cb0dc-e802-47b1-950f-9f1bcdcaa6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792340036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.792340036
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3111411739
Short name T596
Test name
Test status
Simulation time 517931937 ps
CPU time 3.28 seconds
Started May 23 03:46:36 PM PDT 24
Finished May 23 03:47:08 PM PDT 24
Peak memory 206180 kb
Host smart-7e0c2104-f5fb-4d73-97ec-c6488fc78998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111411739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3111411739
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.3872497883
Short name T353
Test name
Test status
Simulation time 208947142 ps
CPU time 6.62 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:47:03 PM PDT 24
Peak memory 208336 kb
Host smart-0a71ea7c-cb85-4660-a287-041b08ffcb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872497883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3872497883
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2718746583
Short name T387
Test name
Test status
Simulation time 74189546 ps
CPU time 1.79 seconds
Started May 23 03:46:38 PM PDT 24
Finished May 23 03:47:08 PM PDT 24
Peak memory 206888 kb
Host smart-b0a546d9-80e9-4b0d-9bb9-4c33381fa323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718746583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2718746583
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4012314586
Short name T750
Test name
Test status
Simulation time 369066296 ps
CPU time 2.97 seconds
Started May 23 03:46:30 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 208708 kb
Host smart-5881f852-e256-455e-8d1e-42cd8efdc754
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012314586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4012314586
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2581086056
Short name T567
Test name
Test status
Simulation time 335885400 ps
CPU time 3.71 seconds
Started May 23 03:46:27 PM PDT 24
Finished May 23 03:47:00 PM PDT 24
Peak memory 206844 kb
Host smart-ed95ff92-ac51-495b-b7ac-0d87d1796e34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581086056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2581086056
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3342969639
Short name T577
Test name
Test status
Simulation time 168161404 ps
CPU time 4.13 seconds
Started May 23 03:46:31 PM PDT 24
Finished May 23 03:47:03 PM PDT 24
Peak memory 208872 kb
Host smart-90a3d8eb-dcd4-4446-a6c7-d0aee7ddea61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342969639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3342969639
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3132231875
Short name T335
Test name
Test status
Simulation time 222412463 ps
CPU time 3.06 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 215892 kb
Host smart-dfff0022-4ac7-400a-9a2e-3699eb2613f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132231875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3132231875
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1896728172
Short name T204
Test name
Test status
Simulation time 106458976 ps
CPU time 3.29 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 206956 kb
Host smart-96b7ef0e-a4ac-49fb-b74b-c0e95d67a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896728172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1896728172
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3064044293
Short name T259
Test name
Test status
Simulation time 231679092 ps
CPU time 5.97 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:20 PM PDT 24
Peak memory 216356 kb
Host smart-c5c52e52-99cf-4db2-81b0-6b360bc17aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064044293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3064044293
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4108657163
Short name T195
Test name
Test status
Simulation time 1580768572 ps
CPU time 25.09 seconds
Started May 23 03:46:45 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 223052 kb
Host smart-703a0505-3dd0-4b93-bd15-2148318d9de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108657163 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4108657163
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4292030169
Short name T377
Test name
Test status
Simulation time 1010877659 ps
CPU time 3.84 seconds
Started May 23 03:46:29 PM PDT 24
Finished May 23 03:47:01 PM PDT 24
Peak memory 218572 kb
Host smart-976ba112-83bd-48da-b66f-2b9e0d1b24bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292030169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4292030169
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3286441657
Short name T137
Test name
Test status
Simulation time 291934089 ps
CPU time 5.02 seconds
Started May 23 03:46:46 PM PDT 24
Finished May 23 03:47:21 PM PDT 24
Peak memory 210096 kb
Host smart-7d412443-ee96-41dd-b426-e9cfc7a1443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286441657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3286441657
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2644518048
Short name T783
Test name
Test status
Simulation time 57693505 ps
CPU time 0.9 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 205996 kb
Host smart-52def4dc-d622-4a46-9581-f434cd98b788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644518048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2644518048
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.617292889
Short name T426
Test name
Test status
Simulation time 62356501 ps
CPU time 4.3 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:19 PM PDT 24
Peak memory 215068 kb
Host smart-2f5ba23f-2353-4e99-a095-8bc73959de14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617292889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.617292889
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.934317499
Short name T660
Test name
Test status
Simulation time 80307156 ps
CPU time 5.32 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 210328 kb
Host smart-834c4571-ed34-4736-900c-090dbb43b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934317499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.934317499
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2476553461
Short name T290
Test name
Test status
Simulation time 72998499 ps
CPU time 1.4 seconds
Started May 23 03:46:47 PM PDT 24
Finished May 23 03:47:19 PM PDT 24
Peak memory 207616 kb
Host smart-ffb28914-3d1c-4f1d-87c9-4851e8905a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476553461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2476553461
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3930712116
Short name T99
Test name
Test status
Simulation time 299316938 ps
CPU time 4.19 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 214400 kb
Host smart-7c555a19-49b6-45aa-8dfd-5fc5dd554daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930712116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3930712116
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1614398277
Short name T497
Test name
Test status
Simulation time 146879433 ps
CPU time 5.83 seconds
Started May 23 03:46:45 PM PDT 24
Finished May 23 03:47:22 PM PDT 24
Peak memory 214396 kb
Host smart-c2a97220-5d0d-41f6-a47e-df8ec18d9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614398277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1614398277
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1680295165
Short name T234
Test name
Test status
Simulation time 263373728 ps
CPU time 2.97 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 207188 kb
Host smart-273347b9-a2b7-4687-8ec8-fa9fe56b9ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680295165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1680295165
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1456389375
Short name T689
Test name
Test status
Simulation time 123914081 ps
CPU time 3.7 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 206692 kb
Host smart-30377fe2-4216-4253-adea-8e808fd70f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456389375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1456389375
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1745238917
Short name T618
Test name
Test status
Simulation time 1538625160 ps
CPU time 5.12 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 208868 kb
Host smart-f77dad7b-7506-41f9-bad7-38b6e0fd07f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745238917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1745238917
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3939281005
Short name T470
Test name
Test status
Simulation time 64683697 ps
CPU time 3.16 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 208728 kb
Host smart-19504973-a012-400b-9aac-442f12f7e8bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939281005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3939281005
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4095369625
Short name T820
Test name
Test status
Simulation time 3013255381 ps
CPU time 19.72 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 208652 kb
Host smart-8e92a360-0035-4e66-b211-1aeb45f1956b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095369625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4095369625
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2935055755
Short name T782
Test name
Test status
Simulation time 260965854 ps
CPU time 3.33 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 209756 kb
Host smart-4c9c64d4-17a3-4713-ae33-fee770d37897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935055755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2935055755
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1185956211
Short name T572
Test name
Test status
Simulation time 54835805 ps
CPU time 2.56 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 207920 kb
Host smart-d30bc931-c8b1-4a5d-8f2d-3469b939818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185956211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1185956211
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1569032635
Short name T517
Test name
Test status
Simulation time 412076091 ps
CPU time 7.92 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 208708 kb
Host smart-79c7e529-b48a-4cff-9cd5-f86234bcc199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569032635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1569032635
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2762874704
Short name T584
Test name
Test status
Simulation time 160470389 ps
CPU time 2.21 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 210316 kb
Host smart-a4598940-429a-494b-97e0-667a7a2bcbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762874704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2762874704
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3170579722
Short name T852
Test name
Test status
Simulation time 19745200 ps
CPU time 0.85 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 205988 kb
Host smart-712bedc1-246e-45aa-80fb-9f885b316d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170579722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3170579722
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1575504053
Short name T283
Test name
Test status
Simulation time 220544969 ps
CPU time 4.69 seconds
Started May 23 03:46:50 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 215380 kb
Host smart-f6c5812c-ecd6-4ba1-8eee-5ed4b3e9fd72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575504053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1575504053
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1529929199
Short name T10
Test name
Test status
Simulation time 260906811 ps
CPU time 2.78 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 210724 kb
Host smart-1c6e36b3-43a2-4403-a8af-64fd8b3870cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529929199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1529929199
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2729091940
Short name T49
Test name
Test status
Simulation time 64669936 ps
CPU time 3.2 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 208792 kb
Host smart-050fae5e-191a-4e39-a8fd-a6824efad33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729091940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2729091940
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.100409173
Short name T909
Test name
Test status
Simulation time 500207229 ps
CPU time 7.8 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:20 PM PDT 24
Peak memory 214400 kb
Host smart-fa43edc5-253a-446b-a003-5ae906fe4a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100409173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.100409173
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.616774749
Short name T547
Test name
Test status
Simulation time 194509445 ps
CPU time 3.64 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 221772 kb
Host smart-b02f49dc-97d1-4693-88d6-a52e65cb18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616774749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.616774749
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.627566761
Short name T525
Test name
Test status
Simulation time 465965172 ps
CPU time 3.41 seconds
Started May 23 03:46:40 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 214396 kb
Host smart-fa22a4c7-fe83-4041-95f4-9559d60d9990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627566761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.627566761
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3003016569
Short name T711
Test name
Test status
Simulation time 281434058 ps
CPU time 3.89 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 209820 kb
Host smart-5a8974bb-8829-4b5b-908d-0e98f290cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003016569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3003016569
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2857691438
Short name T611
Test name
Test status
Simulation time 64447534 ps
CPU time 3.21 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 208808 kb
Host smart-3b7ddf59-3f13-4cd6-85f2-183a6b542b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857691438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2857691438
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2527012264
Short name T520
Test name
Test status
Simulation time 41509199 ps
CPU time 2.34 seconds
Started May 23 03:46:45 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 207084 kb
Host smart-9a154153-5b9b-4845-9974-cc4907dd9cfe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527012264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2527012264
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.674852695
Short name T875
Test name
Test status
Simulation time 122219579 ps
CPU time 2.03 seconds
Started May 23 03:46:38 PM PDT 24
Finished May 23 03:47:09 PM PDT 24
Peak memory 208912 kb
Host smart-6f074953-8158-451c-8890-53f14ce836cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674852695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.674852695
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3327839333
Short name T702
Test name
Test status
Simulation time 118160062 ps
CPU time 2.72 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 206848 kb
Host smart-8400e2c6-538a-46e3-966e-d8b230e5eb2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327839333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3327839333
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.435048567
Short name T316
Test name
Test status
Simulation time 53568075 ps
CPU time 2.16 seconds
Started May 23 03:46:45 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 214388 kb
Host smart-8cf76bbc-d69c-4191-aaa4-4277168bc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435048567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.435048567
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2027666674
Short name T568
Test name
Test status
Simulation time 1626697232 ps
CPU time 5.29 seconds
Started May 23 03:46:52 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 208616 kb
Host smart-23061361-c182-4090-88c0-476ef1be7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027666674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2027666674
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.764132909
Short name T545
Test name
Test status
Simulation time 2785031009 ps
CPU time 67.17 seconds
Started May 23 03:46:52 PM PDT 24
Finished May 23 03:48:29 PM PDT 24
Peak memory 216776 kb
Host smart-afaf7ec8-a132-45dd-bca0-52842a027fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764132909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.764132909
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.414855902
Short name T86
Test name
Test status
Simulation time 732042593 ps
CPU time 12.76 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:24 PM PDT 24
Peak memory 222732 kb
Host smart-ad0ee0ea-4a2c-4e56-9325-382b7161b605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414855902 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.414855902
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3235703121
Short name T523
Test name
Test status
Simulation time 103086158 ps
CPU time 2.3 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:10 PM PDT 24
Peak memory 208160 kb
Host smart-1a4f4584-7764-4295-8cda-4cd914327a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235703121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3235703121
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3984263936
Short name T653
Test name
Test status
Simulation time 73498696 ps
CPU time 2.38 seconds
Started May 23 03:46:38 PM PDT 24
Finished May 23 03:47:09 PM PDT 24
Peak memory 209856 kb
Host smart-e93f9938-4ba0-4381-8f3f-02915f8bfedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984263936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3984263936
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1800476401
Short name T796
Test name
Test status
Simulation time 84041858 ps
CPU time 0.8 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:12 PM PDT 24
Peak memory 205944 kb
Host smart-b460efb6-fb61-4a03-8aa3-9d306848667b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800476401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1800476401
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.340863675
Short name T821
Test name
Test status
Simulation time 70246995 ps
CPU time 1.97 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 209884 kb
Host smart-8d424cb8-ca66-4ee3-adc1-69ba943d6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340863675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.340863675
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.58588061
Short name T616
Test name
Test status
Simulation time 285282689 ps
CPU time 3.52 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 214436 kb
Host smart-26dada0e-2b4f-4e04-8e28-7dfd735806de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58588061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.58588061
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_random.2453069447
Short name T891
Test name
Test status
Simulation time 63112229 ps
CPU time 3.43 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 218504 kb
Host smart-f2c68480-b207-488c-b63d-a026098ccf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453069447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2453069447
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3038795911
Short name T825
Test name
Test status
Simulation time 17421668399 ps
CPU time 48.97 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:48:02 PM PDT 24
Peak memory 207960 kb
Host smart-27084b97-a1bf-402f-b88f-31bcff24e03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038795911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3038795911
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3527704166
Short name T696
Test name
Test status
Simulation time 123321284 ps
CPU time 2.39 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 206856 kb
Host smart-4c9ab2ee-cb16-4bd8-b2e3-d8a426fa5d0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527704166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3527704166
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.745628545
Short name T504
Test name
Test status
Simulation time 141779351 ps
CPU time 2.85 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 206960 kb
Host smart-8ed95ed1-8f38-44a8-94cc-560016cabafa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745628545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.745628545
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2088622003
Short name T519
Test name
Test status
Simulation time 102432101 ps
CPU time 4.24 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 208220 kb
Host smart-49de35aa-e396-4e9d-9bf4-11ca6945e39a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088622003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2088622003
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4143300540
Short name T846
Test name
Test status
Simulation time 253835017 ps
CPU time 2.94 seconds
Started May 23 03:46:50 PM PDT 24
Finished May 23 03:47:23 PM PDT 24
Peak memory 218364 kb
Host smart-7c724659-e016-423e-befa-c75490ea9166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143300540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4143300540
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.876910047
Short name T640
Test name
Test status
Simulation time 1754971246 ps
CPU time 26.48 seconds
Started May 23 03:46:44 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 208884 kb
Host smart-a04cb15f-66b9-47cb-8861-016fd2c267c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876910047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.876910047
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.574336584
Short name T199
Test name
Test status
Simulation time 2439424477 ps
CPU time 57.1 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:48:08 PM PDT 24
Peak memory 222604 kb
Host smart-6200112b-5a6a-4391-b3a1-15b7313063e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574336584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.574336584
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1223565556
Short name T664
Test name
Test status
Simulation time 301660456 ps
CPU time 10.83 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:22 PM PDT 24
Peak memory 222648 kb
Host smart-766d32d4-23e6-40a7-af19-b80d2d50e470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223565556 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1223565556
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.996388716
Short name T607
Test name
Test status
Simulation time 145692585 ps
CPU time 4.84 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 218352 kb
Host smart-b1b8700a-59b8-4c51-82ae-4b1f8ed9edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996388716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.996388716
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3184120966
Short name T851
Test name
Test status
Simulation time 35388900 ps
CPU time 1.67 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:13 PM PDT 24
Peak memory 210392 kb
Host smart-9ee02624-a525-4a13-800f-028c0bc6edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184120966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3184120966
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.108111857
Short name T112
Test name
Test status
Simulation time 16492207 ps
CPU time 0.9 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 206152 kb
Host smart-263fd346-54da-45b7-802a-d553fff816be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108111857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.108111857
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3893351840
Short name T139
Test name
Test status
Simulation time 984024568 ps
CPU time 14.33 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 215380 kb
Host smart-f86a50cb-d1e4-4726-9044-416b57d84203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893351840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3893351840
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2723988777
Short name T555
Test name
Test status
Simulation time 207513231 ps
CPU time 3.06 seconds
Started May 23 03:46:39 PM PDT 24
Finished May 23 03:47:11 PM PDT 24
Peak memory 207736 kb
Host smart-f3b90b1c-7793-433a-8928-9ab634ca85f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723988777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2723988777
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2343901222
Short name T53
Test name
Test status
Simulation time 120748266 ps
CPU time 2.13 seconds
Started May 23 03:46:46 PM PDT 24
Finished May 23 03:47:18 PM PDT 24
Peak memory 215608 kb
Host smart-2cb755e2-683c-4c63-889f-17a82296ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343901222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2343901222
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1131967371
Short name T701
Test name
Test status
Simulation time 750521537 ps
CPU time 3.93 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 221856 kb
Host smart-d1a90b5f-b4d7-4161-b45a-26c802c405b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131967371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1131967371
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1816806523
Short name T709
Test name
Test status
Simulation time 190048818 ps
CPU time 2.54 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 218420 kb
Host smart-383e6670-069e-4f95-b5c7-cbc9d294d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816806523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1816806523
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2692508629
Short name T708
Test name
Test status
Simulation time 450369634 ps
CPU time 5.56 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 207124 kb
Host smart-29808ecc-a756-444b-98c5-884c64f98ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692508629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2692508629
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3220917202
Short name T675
Test name
Test status
Simulation time 221395134 ps
CPU time 8.78 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:20 PM PDT 24
Peak memory 208660 kb
Host smart-3da266aa-e665-43ed-ae2c-2228b4f4ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220917202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3220917202
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3051668657
Short name T116
Test name
Test status
Simulation time 196888529 ps
CPU time 3.03 seconds
Started May 23 03:46:43 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 207052 kb
Host smart-f8e5725c-9cf9-4501-9cf1-43d20f222660
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051668657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3051668657
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.4128155810
Short name T721
Test name
Test status
Simulation time 678604306 ps
CPU time 3.6 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:16 PM PDT 24
Peak memory 207252 kb
Host smart-bceb07c3-c5a8-4d8f-abb5-e99e4d482380
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128155810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.4128155810
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4143802512
Short name T399
Test name
Test status
Simulation time 603295909 ps
CPU time 16.36 seconds
Started May 23 03:46:46 PM PDT 24
Finished May 23 03:47:32 PM PDT 24
Peak memory 209056 kb
Host smart-e8c4a639-083d-4d5b-af27-3f0cef4c79d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143802512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4143802512
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4201214273
Short name T330
Test name
Test status
Simulation time 138504685 ps
CPU time 1.74 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 207740 kb
Host smart-197c5248-b5fd-484a-a1a1-224bdb13b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201214273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4201214273
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.18304137
Short name T806
Test name
Test status
Simulation time 195703371 ps
CPU time 2.7 seconds
Started May 23 03:46:42 PM PDT 24
Finished May 23 03:47:15 PM PDT 24
Peak memory 208512 kb
Host smart-f7a4e546-727d-4789-a3c3-0b6d0ee1daaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18304137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.18304137
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.840725494
Short name T197
Test name
Test status
Simulation time 1706142396 ps
CPU time 28.79 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:51 PM PDT 24
Peak memory 221172 kb
Host smart-90a736e3-de59-440f-a341-8eda01e727d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840725494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.840725494
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4290801098
Short name T368
Test name
Test status
Simulation time 227796006 ps
CPU time 5.81 seconds
Started May 23 03:46:41 PM PDT 24
Finished May 23 03:47:17 PM PDT 24
Peak memory 214432 kb
Host smart-39f95471-3596-4bc6-ab64-3beb901f900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290801098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4290801098
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.336159130
Short name T614
Test name
Test status
Simulation time 12910337 ps
CPU time 0.89 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 206196 kb
Host smart-06f7b1e5-4c0b-4396-85ae-ef8bf9dded73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336159130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.336159130
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3519211928
Short name T424
Test name
Test status
Simulation time 65439694 ps
CPU time 2.87 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 214336 kb
Host smart-3f250a9d-089a-40fa-9a81-043e6d977ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519211928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3519211928
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1265726490
Short name T754
Test name
Test status
Simulation time 380575093 ps
CPU time 6.14 seconds
Started May 23 03:44:49 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 209468 kb
Host smart-07a5d26e-0705-4ccd-8ec3-884a0aeacb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265726490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1265726490
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2897405848
Short name T73
Test name
Test status
Simulation time 81583359 ps
CPU time 2.25 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 209288 kb
Host smart-e0c5e764-c671-4895-8c30-eff2c6a41097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897405848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2897405848
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2202310353
Short name T281
Test name
Test status
Simulation time 464230334 ps
CPU time 3.71 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 222528 kb
Host smart-8ee1f876-1c8a-48e7-a6b2-27720ce4021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202310353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2202310353
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1170482650
Short name T455
Test name
Test status
Simulation time 33195151 ps
CPU time 2.31 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 214968 kb
Host smart-625e093c-5eb1-4527-a056-908da3bf8bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170482650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1170482650
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.451251346
Short name T818
Test name
Test status
Simulation time 36124761 ps
CPU time 2.79 seconds
Started May 23 03:44:56 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 207436 kb
Host smart-0dd7b994-4ec3-4501-b542-274a18572022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451251346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.451251346
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.456688188
Short name T115
Test name
Test status
Simulation time 1102229713 ps
CPU time 21.12 seconds
Started May 23 03:44:54 PM PDT 24
Finished May 23 03:45:33 PM PDT 24
Peak memory 230464 kb
Host smart-ec3f28fc-c440-4eda-9b18-f563cb481b9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456688188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.456688188
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2717589434
Short name T501
Test name
Test status
Simulation time 58577426 ps
CPU time 3.18 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 206936 kb
Host smart-7cdaab72-2b45-4a1d-b187-b229340756de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717589434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2717589434
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2856440385
Short name T698
Test name
Test status
Simulation time 46350493 ps
CPU time 2.57 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 207100 kb
Host smart-96e609a1-51e2-4c56-b424-dda0ccfc5b4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856440385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2856440385
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.769795045
Short name T678
Test name
Test status
Simulation time 4626193605 ps
CPU time 38.86 seconds
Started May 23 03:44:49 PM PDT 24
Finished May 23 03:45:46 PM PDT 24
Peak memory 209128 kb
Host smart-e95b83f4-dc1e-4ab3-bed0-2c5a6eb4d433
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769795045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.769795045
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2872535244
Short name T394
Test name
Test status
Simulation time 220399271 ps
CPU time 3.11 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 208640 kb
Host smart-f0108dc5-a59c-4221-8c31-59a2ad4bfd17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872535244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2872535244
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1068544975
Short name T238
Test name
Test status
Simulation time 181561903 ps
CPU time 2.4 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 215764 kb
Host smart-427bb03a-a6c6-442c-88ff-528d4ec3e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068544975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1068544975
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1923853979
Short name T543
Test name
Test status
Simulation time 1500883555 ps
CPU time 3.23 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 208404 kb
Host smart-043fa901-c33a-4d34-91c0-c8016ab63abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923853979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1923853979
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1676071070
Short name T114
Test name
Test status
Simulation time 4681849118 ps
CPU time 28.11 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:45 PM PDT 24
Peak memory 216384 kb
Host smart-c77e22c7-7b76-4249-8481-92153ca2b4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676071070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1676071070
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2840946516
Short name T135
Test name
Test status
Simulation time 689289904 ps
CPU time 18.26 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 222600 kb
Host smart-9ad72e12-dfe6-48ac-bbde-ab02dce20573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840946516 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2840946516
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1852305845
Short name T746
Test name
Test status
Simulation time 348890798 ps
CPU time 7.78 seconds
Started May 23 03:45:00 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 207920 kb
Host smart-b4478a25-5234-429a-870b-0f82a87fde07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852305845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1852305845
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1201136183
Short name T169
Test name
Test status
Simulation time 57704912 ps
CPU time 2.56 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 210184 kb
Host smart-b9c1fce2-5114-4ca0-bbf8-09b1fe3d205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201136183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1201136183
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3770095860
Short name T722
Test name
Test status
Simulation time 13275641 ps
CPU time 0.86 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 205980 kb
Host smart-cb6abc28-eea4-4890-8618-2ed2fd2de122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770095860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3770095860
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4005929486
Short name T410
Test name
Test status
Simulation time 168221959 ps
CPU time 9.45 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:34 PM PDT 24
Peak memory 214284 kb
Host smart-772c6748-af62-4416-a9eb-1c1c9b511cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005929486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4005929486
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3283573132
Short name T666
Test name
Test status
Simulation time 687974878 ps
CPU time 3.31 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 210176 kb
Host smart-8c871cf3-8eab-4539-b2e7-621751e61989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283573132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3283573132
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2713284050
Short name T858
Test name
Test status
Simulation time 138582098 ps
CPU time 2.27 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:26 PM PDT 24
Peak memory 218348 kb
Host smart-45c480e4-4908-496b-b5ab-f1d63ba05f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713284050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2713284050
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2074477455
Short name T313
Test name
Test status
Simulation time 505125604 ps
CPU time 2.8 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:26 PM PDT 24
Peak memory 214472 kb
Host smart-7e8e1848-e5ce-480e-92d9-187a47bfb11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074477455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2074477455
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2228436964
Short name T309
Test name
Test status
Simulation time 212642048 ps
CPU time 4.71 seconds
Started May 23 03:46:51 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 214328 kb
Host smart-fa5baf4c-4f08-4baa-a64a-28e5b4d7bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228436964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2228436964
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.595203899
Short name T565
Test name
Test status
Simulation time 411504393 ps
CPU time 2.69 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 209588 kb
Host smart-ff9117d3-d845-4a73-8dd9-60f49d0de655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595203899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.595203899
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2278695495
Short name T723
Test name
Test status
Simulation time 70905715 ps
CPU time 3.7 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 207616 kb
Host smart-ad325699-4a08-410b-a620-847d19bd1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278695495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2278695495
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2400253609
Short name T562
Test name
Test status
Simulation time 2480647182 ps
CPU time 6.34 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 207064 kb
Host smart-dfc73fb4-47fd-4d00-81f4-9aa9a286060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400253609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2400253609
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.403012899
Short name T489
Test name
Test status
Simulation time 504244936 ps
CPU time 5.72 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 207160 kb
Host smart-94c135a2-95f2-4f88-875b-10d034fa8568
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403012899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.403012899
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1295781625
Short name T390
Test name
Test status
Simulation time 294583376 ps
CPU time 4.98 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:34 PM PDT 24
Peak memory 208704 kb
Host smart-6deeca49-5d10-448e-96d8-a393baddcc55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295781625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1295781625
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2998904813
Short name T318
Test name
Test status
Simulation time 1544356872 ps
CPU time 8.07 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 208424 kb
Host smart-3f181247-af19-4f63-91ce-f86a0b0e1d58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998904813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2998904813
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.750444941
Short name T482
Test name
Test status
Simulation time 2845580458 ps
CPU time 16.78 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 214080 kb
Host smart-233d5dcc-a809-4f32-81e8-63fdecd25c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750444941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.750444941
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.840526243
Short name T700
Test name
Test status
Simulation time 271019924 ps
CPU time 3.15 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 208760 kb
Host smart-7d5b291b-197b-4096-b541-5f2e4dd8a648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840526243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.840526243
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3773335502
Short name T286
Test name
Test status
Simulation time 6708940415 ps
CPU time 35.64 seconds
Started May 23 03:46:52 PM PDT 24
Finished May 23 03:47:57 PM PDT 24
Peak memory 220640 kb
Host smart-05d7e105-4f59-42e4-ba9d-78162bf86bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773335502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3773335502
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3382153481
Short name T784
Test name
Test status
Simulation time 205351790 ps
CPU time 13.09 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 222652 kb
Host smart-f9967183-5006-42b3-be0e-849dea141284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382153481 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3382153481
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3916846140
Short name T622
Test name
Test status
Simulation time 262732576 ps
CPU time 2.45 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 208024 kb
Host smart-8f8fd3c6-5a76-477d-b67c-503d85950966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916846140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3916846140
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2338589039
Short name T788
Test name
Test status
Simulation time 1277451047 ps
CPU time 29.02 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:52 PM PDT 24
Peak memory 211016 kb
Host smart-97fa8202-2066-437c-b897-7df749d9919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338589039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2338589039
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2984532442
Short name T435
Test name
Test status
Simulation time 15112519 ps
CPU time 0.91 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:25 PM PDT 24
Peak memory 206160 kb
Host smart-11a9bb1b-8fa7-4d2e-afa2-fbf443bddb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984532442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2984532442
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.406404532
Short name T40
Test name
Test status
Simulation time 267317501 ps
CPU time 3.33 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 209004 kb
Host smart-e74b98e1-3747-4ef7-9832-ba200490a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406404532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.406404532
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.989732908
Short name T734
Test name
Test status
Simulation time 88978200 ps
CPU time 1.85 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 208340 kb
Host smart-33d70776-0ffc-4cad-942b-fd21f2851cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989732908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.989732908
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2786459705
Short name T804
Test name
Test status
Simulation time 474743501 ps
CPU time 3.94 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 219564 kb
Host smart-f222e7ea-bedf-4128-85b8-c78ec40fb97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786459705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2786459705
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.810413669
Short name T575
Test name
Test status
Simulation time 81003640 ps
CPU time 3.85 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 220404 kb
Host smart-7f7114e5-be81-487e-bddd-b9713f77794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810413669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.810413669
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4160029555
Short name T633
Test name
Test status
Simulation time 119662195 ps
CPU time 4.84 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:31 PM PDT 24
Peak memory 209996 kb
Host smart-64fe1b4b-ad8b-47ed-aee1-56ad281512d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160029555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4160029555
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.60311972
Short name T791
Test name
Test status
Simulation time 55216274 ps
CPU time 3.19 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 208856 kb
Host smart-0704ff33-2213-451c-98ba-7ad55f726850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60311972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.60311972
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2829475913
Short name T456
Test name
Test status
Simulation time 36101632 ps
CPU time 2.66 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:26 PM PDT 24
Peak memory 207640 kb
Host smart-6488df72-2484-437c-84b1-3d1164ed4ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829475913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2829475913
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.781661513
Short name T665
Test name
Test status
Simulation time 3578561193 ps
CPU time 36.89 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:48:01 PM PDT 24
Peak memory 208696 kb
Host smart-75220116-fbf6-4bc4-b631-ebf8d5b660ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781661513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.781661513
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2284585839
Short name T474
Test name
Test status
Simulation time 5907717311 ps
CPU time 28.77 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:53 PM PDT 24
Peak memory 208376 kb
Host smart-43adc69d-d941-4a1b-b5b5-ac1e123ceb07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284585839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2284585839
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1094882604
Short name T319
Test name
Test status
Simulation time 74175113 ps
CPU time 3.55 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 208700 kb
Host smart-7509f12f-b32e-4539-be9f-21690fb07775
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094882604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1094882604
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1005347396
Short name T522
Test name
Test status
Simulation time 26010468 ps
CPU time 1.62 seconds
Started May 23 03:46:53 PM PDT 24
Finished May 23 03:47:24 PM PDT 24
Peak memory 207968 kb
Host smart-4eff48f4-4d7e-4773-aec9-331bd9c773c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005347396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1005347396
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1033679446
Short name T119
Test name
Test status
Simulation time 50343908 ps
CPU time 2.52 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 206888 kb
Host smart-b5f6d39f-63bb-425e-afea-d617269faf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033679446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1033679446
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.305621739
Short name T90
Test name
Test status
Simulation time 40818592615 ps
CPU time 219.74 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:51:03 PM PDT 24
Peak memory 217552 kb
Host smart-fe6ab909-c453-4879-9d34-db2a98f3661f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305621739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.305621739
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2242586915
Short name T499
Test name
Test status
Simulation time 893611636 ps
CPU time 8.89 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 222636 kb
Host smart-42257c55-9c8c-4f2b-ab76-190960a62d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242586915 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2242586915
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1525364839
Short name T276
Test name
Test status
Simulation time 505926074 ps
CPU time 3.21 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 210104 kb
Host smart-11e65a81-317e-4cac-9596-c4e5a04f9f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525364839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1525364839
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1190666236
Short name T811
Test name
Test status
Simulation time 134335625 ps
CPU time 3.09 seconds
Started May 23 03:47:01 PM PDT 24
Finished May 23 03:47:32 PM PDT 24
Peak memory 210180 kb
Host smart-0412ebca-2efb-448c-b356-52d4d855690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190666236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1190666236
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1896191853
Short name T680
Test name
Test status
Simulation time 96740241 ps
CPU time 0.92 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:24 PM PDT 24
Peak memory 206144 kb
Host smart-8f0868d8-04c2-484b-ab85-7f707782a2e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896191853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1896191853
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3491462402
Short name T408
Test name
Test status
Simulation time 60191211 ps
CPU time 4.23 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 214320 kb
Host smart-978e9dc2-f1a2-467a-b8b8-f94104b58b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491462402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3491462402
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3953232151
Short name T81
Test name
Test status
Simulation time 63861218 ps
CPU time 2.72 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 209136 kb
Host smart-d70440fc-dc15-498f-80c0-db0aea3b74e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953232151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3953232151
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2054893766
Short name T23
Test name
Test status
Simulation time 349574954 ps
CPU time 4.17 seconds
Started May 23 03:47:06 PM PDT 24
Finished May 23 03:47:36 PM PDT 24
Peak memory 221424 kb
Host smart-fedca093-1aa4-4968-b1fb-5f61f2ed9c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054893766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2054893766
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2802850273
Short name T243
Test name
Test status
Simulation time 114908907 ps
CPU time 1.98 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:26 PM PDT 24
Peak memory 214400 kb
Host smart-a53271e0-192b-4051-8b16-2915ab5dee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802850273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2802850273
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1659857237
Short name T48
Test name
Test status
Simulation time 175601965 ps
CPU time 3.6 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 220560 kb
Host smart-6ef783a9-53d4-4a4d-9761-29db85ed3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659857237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1659857237
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2548586812
Short name T585
Test name
Test status
Simulation time 390098729 ps
CPU time 5.52 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 207432 kb
Host smart-06ca30ee-3ca0-4ff6-be70-e6a8c7e201e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548586812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2548586812
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3741137124
Short name T638
Test name
Test status
Simulation time 32463961 ps
CPU time 2.45 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 207604 kb
Host smart-1f058312-50f4-4724-87da-fde9d4c666cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741137124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3741137124
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3431149292
Short name T583
Test name
Test status
Simulation time 97538758 ps
CPU time 3.87 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 207500 kb
Host smart-08b4da83-0055-4bb2-b017-6fc178858dee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431149292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3431149292
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2062861262
Short name T688
Test name
Test status
Simulation time 54687387 ps
CPU time 2.84 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:31 PM PDT 24
Peak memory 208860 kb
Host smart-b975e31d-4dc6-4098-a7d3-0860f9fd3613
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062861262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2062861262
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3087981633
Short name T888
Test name
Test status
Simulation time 1268435593 ps
CPU time 31.51 seconds
Started May 23 03:47:01 PM PDT 24
Finished May 23 03:48:00 PM PDT 24
Peak memory 209236 kb
Host smart-3dcc0a20-b8c9-4695-ad99-cf761ad34590
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087981633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3087981633
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2146891840
Short name T45
Test name
Test status
Simulation time 101889893 ps
CPU time 4.18 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 214332 kb
Host smart-3bebefef-a283-4ef7-8719-c7880382a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146891840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2146891840
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3206775670
Short name T676
Test name
Test status
Simulation time 438279188 ps
CPU time 4.93 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 208248 kb
Host smart-79373fa6-2d3d-43e5-a832-626a2dc1ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206775670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3206775670
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2884890015
Short name T221
Test name
Test status
Simulation time 1281543369 ps
CPU time 41.43 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:48:06 PM PDT 24
Peak memory 215676 kb
Host smart-81b53f76-8998-43d9-b129-53691c8a9026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884890015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2884890015
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.282928324
Short name T192
Test name
Test status
Simulation time 2317303984 ps
CPU time 21.8 seconds
Started May 23 03:47:01 PM PDT 24
Finished May 23 03:47:50 PM PDT 24
Peak memory 222060 kb
Host smart-2171459e-86a3-47af-bac3-0bbb78540094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282928324 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.282928324
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2781625438
Short name T502
Test name
Test status
Simulation time 826886651 ps
CPU time 8.57 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 209128 kb
Host smart-3dd3653f-99a5-4f15-85d6-1441a9c6e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781625438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2781625438
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3416887087
Short name T693
Test name
Test status
Simulation time 66172570 ps
CPU time 3.05 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 210172 kb
Host smart-4596781f-0aae-41a6-8dd3-6a2d751bafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416887087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3416887087
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3240740458
Short name T838
Test name
Test status
Simulation time 15074436 ps
CPU time 0.77 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 206000 kb
Host smart-87d29554-1284-4ebd-911c-59edcf16c772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240740458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3240740458
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.93833842
Short name T152
Test name
Test status
Simulation time 212970867 ps
CPU time 3.86 seconds
Started May 23 03:47:02 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 214432 kb
Host smart-ffc2e1fe-09b4-49ec-b4f2-0c24937f9d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93833842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.93833842
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2071869864
Short name T220
Test name
Test status
Simulation time 536514525 ps
CPU time 5.29 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:32 PM PDT 24
Peak memory 214424 kb
Host smart-69733c36-eb44-4244-bf1b-1eb3d83b9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071869864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2071869864
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3707874278
Short name T50
Test name
Test status
Simulation time 290435354 ps
CPU time 2.25 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:31 PM PDT 24
Peak memory 209704 kb
Host smart-60e7b495-d6fa-40b8-bf14-6b0c79cef8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707874278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3707874278
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3435490531
Short name T901
Test name
Test status
Simulation time 108451711 ps
CPU time 4.3 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 214380 kb
Host smart-619750ce-19e1-4f19-ba7a-aed80b84bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435490531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3435490531
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1415870553
Short name T373
Test name
Test status
Simulation time 128754201 ps
CPU time 2.51 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 222404 kb
Host smart-c26266db-b377-4f0f-bbe9-e2a6fe12151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415870553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1415870553
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3135724774
Short name T466
Test name
Test status
Simulation time 73779821 ps
CPU time 3.31 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:31 PM PDT 24
Peak memory 209708 kb
Host smart-ec91381e-1d29-4598-952b-b9844bcac18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135724774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3135724774
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.336576805
Short name T240
Test name
Test status
Simulation time 65224066 ps
CPU time 3.71 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 210124 kb
Host smart-bea75466-0bd2-43db-b89d-7c8ad6e0929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336576805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.336576805
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.355833645
Short name T235
Test name
Test status
Simulation time 353413286 ps
CPU time 4.36 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 206980 kb
Host smart-95d00a7a-05ea-4f81-a61d-fcd069d705a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355833645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.355833645
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3135806458
Short name T557
Test name
Test status
Simulation time 6486697581 ps
CPU time 17.06 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:51 PM PDT 24
Peak memory 207964 kb
Host smart-99b3b683-a7fe-466b-92c2-f3b82fafb0ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135806458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3135806458
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1155151625
Short name T862
Test name
Test status
Simulation time 38935214 ps
CPU time 2.27 seconds
Started May 23 03:47:00 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 206980 kb
Host smart-87529f93-2713-49af-a6ec-9c03c2061640
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155151625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1155151625
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1689652993
Short name T739
Test name
Test status
Simulation time 1247567346 ps
CPU time 5.01 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 208704 kb
Host smart-9ec9039a-1a5b-46c7-9140-2fd05ffa1afe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689652993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1689652993
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4017910857
Short name T344
Test name
Test status
Simulation time 325921508 ps
CPU time 2.92 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:27 PM PDT 24
Peak memory 210152 kb
Host smart-8979582d-2cd4-4231-8f1c-98073dbe815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017910857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4017910857
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3464495220
Short name T849
Test name
Test status
Simulation time 884159381 ps
CPU time 5.28 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 208292 kb
Host smart-7d457812-d1c2-4bd3-9db4-0d1b14a8f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464495220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3464495220
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1599105497
Short name T226
Test name
Test status
Simulation time 1839083732 ps
CPU time 36.07 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:48:02 PM PDT 24
Peak memory 217348 kb
Host smart-15b90dbc-3d09-4c19-a2df-352b9211aa3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599105497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1599105497
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.322333867
Short name T72
Test name
Test status
Simulation time 1170808562 ps
CPU time 17.8 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:42 PM PDT 24
Peak memory 222648 kb
Host smart-df467d63-a5b1-4383-8bff-405992515a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322333867 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.322333867
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.386508771
Short name T724
Test name
Test status
Simulation time 124420411 ps
CPU time 5.23 seconds
Started May 23 03:46:54 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 218536 kb
Host smart-db186202-1188-4bb6-9aa0-30cb508e27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386508771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.386508771
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.458123337
Short name T713
Test name
Test status
Simulation time 1265446634 ps
CPU time 8.02 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 211044 kb
Host smart-205f40db-9e21-4cdf-8a45-a1f005e31d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458123337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.458123337
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1180723889
Short name T839
Test name
Test status
Simulation time 11669585 ps
CPU time 0.76 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 205976 kb
Host smart-bfe907aa-ce0b-4690-ae65-5d17841539b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180723889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1180723889
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1828453210
Short name T414
Test name
Test status
Simulation time 106101809 ps
CPU time 1.83 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 209396 kb
Host smart-be3f8587-9724-4750-9294-8d13adaa6983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828453210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1828453210
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1612026513
Short name T293
Test name
Test status
Simulation time 271518153 ps
CPU time 2.8 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 222388 kb
Host smart-6e442cf0-4f83-4429-b08f-565d764d69f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612026513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1612026513
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1586957003
Short name T654
Test name
Test status
Simulation time 98930339 ps
CPU time 2.54 seconds
Started May 23 03:46:58 PM PDT 24
Finished May 23 03:47:29 PM PDT 24
Peak memory 216168 kb
Host smart-56b0d619-dab3-4984-bde6-768cd8eb5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586957003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1586957003
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1611852884
Short name T329
Test name
Test status
Simulation time 325821715 ps
CPU time 9 seconds
Started May 23 03:46:55 PM PDT 24
Finished May 23 03:47:33 PM PDT 24
Peak memory 208136 kb
Host smart-6950fb9f-bafb-43b6-b83c-4a6d520686a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611852884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1611852884
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.436157561
Short name T471
Test name
Test status
Simulation time 411668956 ps
CPU time 8.09 seconds
Started May 23 03:46:59 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 208324 kb
Host smart-12fed2fc-f8cd-4944-a1e7-f3f295393dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436157561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.436157561
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2555019596
Short name T647
Test name
Test status
Simulation time 934076760 ps
CPU time 2.9 seconds
Started May 23 03:46:59 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 206848 kb
Host smart-3ce5d417-3a92-44ba-a5cc-0ad23e04f366
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555019596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2555019596
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1522980251
Short name T652
Test name
Test status
Simulation time 81288560 ps
CPU time 2.64 seconds
Started May 23 03:46:57 PM PDT 24
Finished May 23 03:47:28 PM PDT 24
Peak memory 207080 kb
Host smart-b26f38c9-0b78-4978-826c-e3bda1e70596
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522980251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1522980251
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4218066987
Short name T252
Test name
Test status
Simulation time 3073393152 ps
CPU time 30.81 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:48:04 PM PDT 24
Peak memory 208756 kb
Host smart-041d5004-6116-4732-9dd0-dfce9c9337e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218066987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4218066987
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.484204546
Short name T712
Test name
Test status
Simulation time 229923551 ps
CPU time 3.1 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 215740 kb
Host smart-70856f57-5214-4236-bf61-4b1244f2144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484204546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.484204546
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3678268591
Short name T492
Test name
Test status
Simulation time 59118296 ps
CPU time 2.42 seconds
Started May 23 03:46:59 PM PDT 24
Finished May 23 03:47:30 PM PDT 24
Peak memory 206732 kb
Host smart-deaece78-90f3-40cc-974d-a95b43e4c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678268591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3678268591
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2214175535
Short name T644
Test name
Test status
Simulation time 1389884398 ps
CPU time 42.14 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:48:17 PM PDT 24
Peak memory 215772 kb
Host smart-2b675394-4dad-44a8-977b-ad0fe01d37a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214175535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2214175535
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3602430394
Short name T254
Test name
Test status
Simulation time 278675515 ps
CPU time 6.21 seconds
Started May 23 03:46:56 PM PDT 24
Finished May 23 03:47:31 PM PDT 24
Peak memory 209632 kb
Host smart-cdba9f7c-7ac9-4487-a43b-c879a65cacc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602430394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3602430394
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2738108446
Short name T176
Test name
Test status
Simulation time 95218276 ps
CPU time 2.19 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 210080 kb
Host smart-13371b20-3d1a-4913-91a8-3a691f629044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738108446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2738108446
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3479445380
Short name T496
Test name
Test status
Simulation time 12680520 ps
CPU time 0.75 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 205972 kb
Host smart-be2a9d8f-d462-4088-9c53-b020e52b092f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479445380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3479445380
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4271049050
Short name T386
Test name
Test status
Simulation time 48854729 ps
CPU time 3.33 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 214392 kb
Host smart-1f98fc40-3ea9-4ca3-b758-1975b6f3d621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271049050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4271049050
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3745290631
Short name T83
Test name
Test status
Simulation time 320819242 ps
CPU time 3.74 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 208828 kb
Host smart-7a83ce9a-752b-4166-bbac-3d22418c4343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745290631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3745290631
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4240966829
Short name T264
Test name
Test status
Simulation time 302564061 ps
CPU time 2.86 seconds
Started May 23 03:47:13 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 214468 kb
Host smart-68aac1ca-1c8d-47d2-ae96-e81754bf4773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240966829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4240966829
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2357212400
Short name T242
Test name
Test status
Simulation time 1576518327 ps
CPU time 4.53 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 214688 kb
Host smart-7c40ccfa-ef5f-4362-b27c-d570d7436f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357212400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2357212400
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3777075719
Short name T718
Test name
Test status
Simulation time 84402440 ps
CPU time 2.41 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 218664 kb
Host smart-697f28a8-4c80-4222-b346-ca9c77a3c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777075719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3777075719
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.494564119
Short name T785
Test name
Test status
Simulation time 399338102 ps
CPU time 4.98 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:40 PM PDT 24
Peak memory 208900 kb
Host smart-45633f6a-c4f7-48ee-8401-1c204070b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494564119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.494564119
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2855747618
Short name T261
Test name
Test status
Simulation time 61636059 ps
CPU time 2.48 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 206884 kb
Host smart-2a8be7b0-c29e-4354-97e1-44e90b5080a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855747618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2855747618
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.276185284
Short name T730
Test name
Test status
Simulation time 67466610 ps
CPU time 3.54 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 208824 kb
Host smart-99f11877-9bca-4b32-8a3b-888e8bbed92f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276185284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.276185284
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2053709071
Short name T770
Test name
Test status
Simulation time 24133595 ps
CPU time 1.79 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:36 PM PDT 24
Peak memory 208800 kb
Host smart-9af7e442-1703-446e-aadd-7b74c0b0dd1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053709071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2053709071
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1086953378
Short name T773
Test name
Test status
Simulation time 28573080 ps
CPU time 1.55 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 207700 kb
Host smart-04dbf6c7-ab5e-42b8-a73a-e7a334e387b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086953378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1086953378
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3993196340
Short name T631
Test name
Test status
Simulation time 935826777 ps
CPU time 18.62 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:54 PM PDT 24
Peak memory 208716 kb
Host smart-9bda458e-db90-49df-a6e1-003f6ef0deb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993196340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3993196340
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3444704325
Short name T834
Test name
Test status
Simulation time 7220413090 ps
CPU time 219.98 seconds
Started May 23 03:47:11 PM PDT 24
Finished May 23 03:51:16 PM PDT 24
Peak memory 222536 kb
Host smart-363af0e1-e088-4b67-af4d-4bbf6103d3c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444704325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3444704325
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2100768050
Short name T886
Test name
Test status
Simulation time 3588520651 ps
CPU time 37.85 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:48:12 PM PDT 24
Peak memory 208372 kb
Host smart-b27c3d67-d991-4fb3-a049-60cdefffeef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100768050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2100768050
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2064523853
Short name T500
Test name
Test status
Simulation time 53792517 ps
CPU time 0.82 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 205944 kb
Host smart-33aad77d-446f-4dad-b434-2e5964a4cfb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064523853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2064523853
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.579815493
Short name T686
Test name
Test status
Simulation time 330139503 ps
CPU time 8.76 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 218428 kb
Host smart-982339a4-4b90-4e2f-90c1-691aa1c65b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579815493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.579815493
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.790027391
Short name T832
Test name
Test status
Simulation time 24599602 ps
CPU time 1.24 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 207476 kb
Host smart-06f043ef-d593-499e-ba4d-ef154991496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790027391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.790027391
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3488660675
Short name T343
Test name
Test status
Simulation time 109170069 ps
CPU time 1.96 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 214384 kb
Host smart-df5c262c-3979-4598-9795-7f8caa1a600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488660675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3488660675
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2914408892
Short name T639
Test name
Test status
Simulation time 91997707 ps
CPU time 2.28 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 220192 kb
Host smart-e17cd14a-89b6-4494-9aee-7920958ea6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914408892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2914408892
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.502232059
Short name T271
Test name
Test status
Simulation time 848459445 ps
CPU time 7.22 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 218464 kb
Host smart-e0234bfd-b34a-45cc-8eb4-eac8875cff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502232059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.502232059
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2890876281
Short name T798
Test name
Test status
Simulation time 110637752 ps
CPU time 4.6 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 208632 kb
Host smart-20d71b3b-3351-4a7e-8e6b-aa01b3063930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890876281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2890876281
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1610191386
Short name T895
Test name
Test status
Simulation time 912519880 ps
CPU time 8.45 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:42 PM PDT 24
Peak memory 208848 kb
Host smart-1a99f4a2-886b-43f6-97a2-bbe97bae3ef2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610191386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1610191386
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.677433200
Short name T669
Test name
Test status
Simulation time 3385967386 ps
CPU time 62.88 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:48:38 PM PDT 24
Peak memory 208492 kb
Host smart-d0a7220f-ef92-4f71-8d4b-111b471274aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677433200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.677433200
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1404092163
Short name T650
Test name
Test status
Simulation time 726928160 ps
CPU time 7.27 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 206876 kb
Host smart-02dde18f-bc0f-4be1-978a-547d6f89760a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404092163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1404092163
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.489318019
Short name T579
Test name
Test status
Simulation time 349940460 ps
CPU time 3.67 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 208788 kb
Host smart-26c022be-8389-4d4b-b2e6-02e283765212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489318019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.489318019
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3671081059
Short name T695
Test name
Test status
Simulation time 250469004 ps
CPU time 4.91 seconds
Started May 23 03:47:13 PM PDT 24
Finished May 23 03:47:43 PM PDT 24
Peak memory 208088 kb
Host smart-954dd906-5228-46de-9100-3c63f2b0b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671081059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3671081059
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2631187455
Short name T288
Test name
Test status
Simulation time 3197294186 ps
CPU time 30.69 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:48:05 PM PDT 24
Peak memory 216440 kb
Host smart-0a43c8fc-fda3-474a-b536-727ec2daad42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631187455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2631187455
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2805173800
Short name T321
Test name
Test status
Simulation time 357599803 ps
CPU time 9.42 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:45 PM PDT 24
Peak memory 209900 kb
Host smart-a635bf0b-d673-44d9-8919-290d1180d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805173800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2805173800
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3853145117
Short name T586
Test name
Test status
Simulation time 248152265 ps
CPU time 2.69 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 210136 kb
Host smart-dca57f24-ea3b-4a05-a9bf-278eba465448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853145117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3853145117
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1286324361
Short name T855
Test name
Test status
Simulation time 9354698 ps
CPU time 0.89 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 206016 kb
Host smart-d0e69279-f22c-4990-b438-15fe0a77c34a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286324361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1286324361
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3708437864
Short name T841
Test name
Test status
Simulation time 400074422 ps
CPU time 3.43 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 214360 kb
Host smart-278bcee8-a3c4-4f46-9799-74082120779a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708437864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3708437864
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3431322096
Short name T39
Test name
Test status
Simulation time 263481774 ps
CPU time 3.76 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 222496 kb
Host smart-9675ceb5-2c45-4129-9dab-68741fbf3a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431322096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3431322096
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1177571351
Short name T763
Test name
Test status
Simulation time 60240188 ps
CPU time 2.35 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 219852 kb
Host smart-0afac542-98a4-4350-bd9a-addf190e4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177571351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1177571351
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.835978108
Short name T772
Test name
Test status
Simulation time 601956296 ps
CPU time 4.06 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 215168 kb
Host smart-50d991ac-e8e3-48f3-93ad-6895bb172756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835978108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.835978108
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4051489219
Short name T314
Test name
Test status
Simulation time 85958757 ps
CPU time 3.79 seconds
Started May 23 03:47:07 PM PDT 24
Finished May 23 03:47:37 PM PDT 24
Peak memory 214360 kb
Host smart-532c8ae5-c5d3-4d61-9a82-972fa32d6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051489219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4051489219
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1927018043
Short name T516
Test name
Test status
Simulation time 110227500 ps
CPU time 2.83 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 220336 kb
Host smart-5cd78f2d-5896-417c-8c08-deaec727fc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927018043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1927018043
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2835383763
Short name T395
Test name
Test status
Simulation time 124314042 ps
CPU time 5.09 seconds
Started May 23 03:47:11 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 208960 kb
Host smart-58464a86-541d-40a1-ac3d-b188e7695efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835383763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2835383763
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.714398547
Short name T453
Test name
Test status
Simulation time 4244906354 ps
CPU time 19.24 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:54 PM PDT 24
Peak memory 208308 kb
Host smart-7641ec99-0d48-4973-b156-0670810a82c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714398547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.714398547
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.279155833
Short name T848
Test name
Test status
Simulation time 142179220 ps
CPU time 2.98 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 207384 kb
Host smart-49d4b296-5835-4337-b777-07a5013f3413
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279155833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.279155833
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.658416738
Short name T212
Test name
Test status
Simulation time 59432732 ps
CPU time 3 seconds
Started May 23 03:47:11 PM PDT 24
Finished May 23 03:47:39 PM PDT 24
Peak memory 207116 kb
Host smart-0ae3eb7d-3320-4d50-af05-b2cfd60ffa5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658416738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.658416738
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3476393181
Short name T764
Test name
Test status
Simulation time 3001401456 ps
CPU time 9.61 seconds
Started May 23 03:47:10 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 208580 kb
Host smart-d3ec1826-75ff-4ac9-8550-8e8729b6762c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476393181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3476393181
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3837873833
Short name T468
Test name
Test status
Simulation time 98099180 ps
CPU time 3.34 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 209772 kb
Host smart-0897a65e-a825-42c7-9563-a918e4c292bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837873833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3837873833
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3923757268
Short name T440
Test name
Test status
Simulation time 131395364 ps
CPU time 2.24 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:47:38 PM PDT 24
Peak memory 206144 kb
Host smart-225c281f-afdf-4452-af38-95052e9f7ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923757268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3923757268
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4083675717
Short name T198
Test name
Test status
Simulation time 14582490416 ps
CPU time 33.68 seconds
Started May 23 03:47:09 PM PDT 24
Finished May 23 03:48:09 PM PDT 24
Peak memory 222592 kb
Host smart-90e7b0a8-b5c8-4229-8e84-85dc9168f2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083675717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4083675717
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4003443493
Short name T270
Test name
Test status
Simulation time 343262595 ps
CPU time 6.8 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 214352 kb
Host smart-c43511be-76fb-40b7-a825-90f438443ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003443493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4003443493
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.321948241
Short name T877
Test name
Test status
Simulation time 130072937 ps
CPU time 3.43 seconds
Started May 23 03:47:12 PM PDT 24
Finished May 23 03:47:41 PM PDT 24
Peak memory 219408 kb
Host smart-d17f36b5-ccfc-43b3-a699-f4d30d3a6184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321948241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.321948241
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1011115242
Short name T150
Test name
Test status
Simulation time 236333856 ps
CPU time 3.28 seconds
Started May 23 03:47:20 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 215772 kb
Host smart-1a437578-0381-44a0-ba05-3643f955cb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011115242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1011115242
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.484768071
Short name T85
Test name
Test status
Simulation time 144096566 ps
CPU time 2.14 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 208456 kb
Host smart-9e6c9fa4-2bbe-4ae2-8ce4-eec7dd292936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484768071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.484768071
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2181406600
Short name T269
Test name
Test status
Simulation time 290451689 ps
CPU time 2.79 seconds
Started May 23 03:47:20 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 214348 kb
Host smart-ae2734df-8aab-402f-a5dd-51d5816906dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181406600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2181406600
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2422735139
Short name T714
Test name
Test status
Simulation time 354413431 ps
CPU time 3.93 seconds
Started May 23 03:47:16 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 208708 kb
Host smart-ce85a892-896a-4bb1-94c5-28cd20e033fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422735139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2422735139
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3581220288
Short name T503
Test name
Test status
Simulation time 330435355 ps
CPU time 4.35 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 208056 kb
Host smart-047f78b5-423f-49ef-869c-7e5340cada09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581220288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3581220288
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1942166810
Short name T439
Test name
Test status
Simulation time 143835467 ps
CPU time 2.73 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 208548 kb
Host smart-f21230bb-4ffe-427b-822f-83ce6083b479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942166810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1942166810
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3397731059
Short name T876
Test name
Test status
Simulation time 1096523786 ps
CPU time 27.64 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:48:10 PM PDT 24
Peak memory 208196 kb
Host smart-914a25d6-994a-4852-92c0-9adda355d246
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397731059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3397731059
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.392567808
Short name T898
Test name
Test status
Simulation time 76852485 ps
CPU time 2.73 seconds
Started May 23 03:47:22 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 208952 kb
Host smart-74ef96d8-cc2b-4173-b903-940769939209
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392567808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.392567808
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4253424265
Short name T556
Test name
Test status
Simulation time 366660723 ps
CPU time 4.51 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:50 PM PDT 24
Peak memory 208692 kb
Host smart-2b73c80a-ad67-40e0-a0a5-f5a0013b8f86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253424265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4253424265
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.167647462
Short name T461
Test name
Test status
Simulation time 71650239 ps
CPU time 3.03 seconds
Started May 23 03:47:19 PM PDT 24
Finished May 23 03:47:45 PM PDT 24
Peak memory 214388 kb
Host smart-3e71be6c-3335-4c70-a8ad-5328bc91f68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167647462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.167647462
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.16334053
Short name T667
Test name
Test status
Simulation time 1261822234 ps
CPU time 2.51 seconds
Started May 23 03:47:08 PM PDT 24
Finished May 23 03:47:36 PM PDT 24
Peak memory 207316 kb
Host smart-5722404d-5478-4131-b05b-741c37d48196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16334053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.16334053
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4183787855
Short name T361
Test name
Test status
Simulation time 1857436205 ps
CPU time 18.75 seconds
Started May 23 03:47:17 PM PDT 24
Finished May 23 03:48:00 PM PDT 24
Peak memory 216104 kb
Host smart-7014a33c-1aa4-4a96-a4bc-fa1395d61e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183787855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4183787855
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1843198766
Short name T191
Test name
Test status
Simulation time 606387633 ps
CPU time 15.48 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:57 PM PDT 24
Peak memory 222680 kb
Host smart-858be071-eea5-4457-9754-5a92c21b28f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843198766 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1843198766
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1350845943
Short name T236
Test name
Test status
Simulation time 58057648 ps
CPU time 2.89 seconds
Started May 23 03:47:20 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 208168 kb
Host smart-bfb5422e-09b9-41b2-b613-04629c723e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350845943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1350845943
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.363835947
Short name T203
Test name
Test status
Simulation time 424704030 ps
CPU time 4.2 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 210120 kb
Host smart-a5d0e538-6434-45f9-a104-970bd75af697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363835947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.363835947
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2281009097
Short name T429
Test name
Test status
Simulation time 31679942 ps
CPU time 0.78 seconds
Started May 23 03:47:20 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 205988 kb
Host smart-ed6aff2a-14df-45f9-a7f6-8238ea141962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281009097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2281009097
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1345094712
Short name T60
Test name
Test status
Simulation time 31532478 ps
CPU time 1.71 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 207800 kb
Host smart-a969a76e-6a82-4cf0-a6cd-4c2ff58c9676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345094712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1345094712
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1205833170
Short name T868
Test name
Test status
Simulation time 135107604 ps
CPU time 2.4 seconds
Started May 23 03:47:17 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 209932 kb
Host smart-0d45793d-b6cf-4124-87e8-90e1fda41370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205833170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1205833170
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3120397844
Short name T54
Test name
Test status
Simulation time 32221566 ps
CPU time 1.89 seconds
Started May 23 03:47:19 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 206176 kb
Host smart-31eb96ee-deab-47b4-aedb-44841b73d430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120397844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3120397844
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3412374192
Short name T91
Test name
Test status
Simulation time 166792114 ps
CPU time 4.15 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:49 PM PDT 24
Peak memory 218228 kb
Host smart-50a802d4-93c7-437e-8ef1-4a57bea3ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412374192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3412374192
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2644746627
Short name T903
Test name
Test status
Simulation time 21811565 ps
CPU time 1.8 seconds
Started May 23 03:47:19 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 206852 kb
Host smart-620c5a5a-4abc-4df5-be3b-1408d889fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644746627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2644746627
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4262165404
Short name T705
Test name
Test status
Simulation time 37480280 ps
CPU time 2.49 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:44 PM PDT 24
Peak memory 206916 kb
Host smart-272e191d-008c-4438-8c2c-8fd6edb6bf45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262165404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4262165404
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.566986920
Short name T539
Test name
Test status
Simulation time 174539126 ps
CPU time 3.94 seconds
Started May 23 03:47:18 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 208564 kb
Host smart-df1fc064-b8f7-40ee-ba42-b56bb586006c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566986920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.566986920
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1779790045
Short name T854
Test name
Test status
Simulation time 541653364 ps
CPU time 7.01 seconds
Started May 23 03:47:21 PM PDT 24
Finished May 23 03:47:51 PM PDT 24
Peak memory 208832 kb
Host smart-5e87501c-5a2a-4a2c-afbb-15f24978de9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779790045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1779790045
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1093373388
Short name T691
Test name
Test status
Simulation time 106302092 ps
CPU time 1.5 seconds
Started May 23 03:47:22 PM PDT 24
Finished May 23 03:47:45 PM PDT 24
Peak memory 207900 kb
Host smart-b3c7ddce-e404-4d1d-9d96-f629318a9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093373388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1093373388
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.17882684
Short name T505
Test name
Test status
Simulation time 73067218 ps
CPU time 2.7 seconds
Started May 23 03:47:20 PM PDT 24
Finished May 23 03:47:46 PM PDT 24
Peak memory 208368 kb
Host smart-55a1430c-db6f-4da8-bc63-91597192b271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17882684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.17882684
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.486867326
Short name T629
Test name
Test status
Simulation time 3934137767 ps
CPU time 42.44 seconds
Started May 23 03:47:22 PM PDT 24
Finished May 23 03:48:27 PM PDT 24
Peak memory 214604 kb
Host smart-046f118d-a1ae-4924-ba73-0a9fb30eded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486867326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.486867326
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2884313411
Short name T131
Test name
Test status
Simulation time 43245337 ps
CPU time 1.52 seconds
Started May 23 03:47:24 PM PDT 24
Finished May 23 03:47:47 PM PDT 24
Peak memory 209920 kb
Host smart-e2e32f20-c6f5-4266-84d5-dfe5b1a85eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884313411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2884313411
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3155001912
Short name T436
Test name
Test status
Simulation time 102573375 ps
CPU time 0.74 seconds
Started May 23 03:44:57 PM PDT 24
Finished May 23 03:45:17 PM PDT 24
Peak memory 205960 kb
Host smart-34d144c2-24d1-463c-929c-892c1b10352b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155001912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3155001912
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.644283077
Short name T628
Test name
Test status
Simulation time 114899379 ps
CPU time 1.66 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 209704 kb
Host smart-8dd78251-a166-42e4-abcc-7c9254c6759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644283077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.644283077
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.661101147
Short name T87
Test name
Test status
Simulation time 154931729 ps
CPU time 2.63 seconds
Started May 23 03:45:15 PM PDT 24
Finished May 23 03:45:36 PM PDT 24
Peak memory 210272 kb
Host smart-4f6056cc-e303-4881-a68d-518ed610ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661101147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.661101147
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4143036644
Short name T609
Test name
Test status
Simulation time 278572648 ps
CPU time 3.64 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 214720 kb
Host smart-0661cbea-cabc-4a87-9798-41875dbd7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143036644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4143036644
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1994245127
Short name T744
Test name
Test status
Simulation time 349230822 ps
CPU time 3.83 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 208888 kb
Host smart-108958b3-4458-489a-9db8-775d10ad5fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994245127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1994245127
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.56073025
Short name T354
Test name
Test status
Simulation time 434840402 ps
CPU time 5.72 seconds
Started May 23 03:44:50 PM PDT 24
Finished May 23 03:45:13 PM PDT 24
Peak memory 207140 kb
Host smart-b72b866e-7210-4d39-98f3-58e945667628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56073025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.56073025
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3684963962
Short name T897
Test name
Test status
Simulation time 209431952 ps
CPU time 2.78 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 208276 kb
Host smart-42d58007-9d32-4228-b560-5f8f73d28510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684963962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3684963962
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1145216170
Short name T518
Test name
Test status
Simulation time 41612347 ps
CPU time 1.84 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:15 PM PDT 24
Peak memory 206924 kb
Host smart-da52b92e-efc1-4367-8fa2-63697fc53608
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145216170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1145216170
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2092842136
Short name T317
Test name
Test status
Simulation time 245071675 ps
CPU time 2.06 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 208752 kb
Host smart-21f3424b-2618-4b7a-bc21-e66462b1dadd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092842136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2092842136
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2727725818
Short name T831
Test name
Test status
Simulation time 623025584 ps
CPU time 4.54 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:21 PM PDT 24
Peak memory 207940 kb
Host smart-6c133a36-5525-4fcf-90b0-28887030ac14
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727725818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2727725818
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1057206030
Short name T573
Test name
Test status
Simulation time 396924243 ps
CPU time 10.15 seconds
Started May 23 03:45:06 PM PDT 24
Finished May 23 03:45:33 PM PDT 24
Peak memory 214492 kb
Host smart-4c800ebf-c7a4-4080-a5ea-4e698348686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057206030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1057206030
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3970857266
Short name T863
Test name
Test status
Simulation time 38771690 ps
CPU time 2.35 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:15 PM PDT 24
Peak memory 208396 kb
Host smart-982e23a9-bc98-4adb-b226-e2f7355c2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970857266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3970857266
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1669604602
Short name T133
Test name
Test status
Simulation time 288262300 ps
CPU time 11.85 seconds
Started May 23 03:45:00 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 220116 kb
Host smart-49172158-2496-47f6-8e94-50621d7b9a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669604602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1669604602
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1092674080
Short name T889
Test name
Test status
Simulation time 118291500 ps
CPU time 4.84 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 214376 kb
Host smart-6e108ddd-b61b-46c3-8c62-b910331cf181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092674080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1092674080
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.211493375
Short name T202
Test name
Test status
Simulation time 248819706 ps
CPU time 1.95 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 210432 kb
Host smart-fd8c6466-652b-4e61-9103-1c54f03929bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211493375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.211493375
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2139451220
Short name T600
Test name
Test status
Simulation time 52018722 ps
CPU time 0.75 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:23 PM PDT 24
Peak memory 205992 kb
Host smart-031f7fe2-6012-4ceb-bcea-89b58e80f1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139451220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2139451220
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2303865031
Short name T275
Test name
Test status
Simulation time 327798210 ps
CPU time 4.74 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 214764 kb
Host smart-64985eae-dc9a-4c21-9b3c-1233a3c081f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303865031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2303865031
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3692941123
Short name T671
Test name
Test status
Simulation time 613377551 ps
CPU time 14.33 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:45:35 PM PDT 24
Peak memory 208756 kb
Host smart-bcd591f6-56a5-4f45-b919-2834d5bec4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692941123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3692941123
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.598861761
Short name T613
Test name
Test status
Simulation time 160013598 ps
CPU time 5.58 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 209848 kb
Host smart-7ed7ba1e-6970-45c9-8fbd-50f9ef3b279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598861761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.598861761
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3580550138
Short name T101
Test name
Test status
Simulation time 56124879 ps
CPU time 1.9 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 214296 kb
Host smart-88f01f59-49d5-4395-9c47-26196cf3c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580550138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3580550138
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3770683502
Short name T615
Test name
Test status
Simulation time 33413687 ps
CPU time 2.12 seconds
Started May 23 03:44:55 PM PDT 24
Finished May 23 03:45:16 PM PDT 24
Peak memory 214388 kb
Host smart-fd65ca1e-67d8-4f75-a5fb-47392e80db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770683502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3770683502
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1351137016
Short name T534
Test name
Test status
Simulation time 170863242 ps
CPU time 4.56 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:21 PM PDT 24
Peak memory 207328 kb
Host smart-82564d50-c728-4cf4-9f35-af935ce79376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351137016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1351137016
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4129922324
Short name T345
Test name
Test status
Simulation time 1434312769 ps
CPU time 15.95 seconds
Started May 23 03:45:00 PM PDT 24
Finished May 23 03:45:39 PM PDT 24
Peak memory 208344 kb
Host smart-c7151947-aadb-4857-9a60-fe1575b3925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129922324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4129922324
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2831961684
Short name T697
Test name
Test status
Simulation time 176024081 ps
CPU time 2.68 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 206984 kb
Host smart-1dd5edab-cbd9-4293-9c34-8fd6206fef17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831961684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2831961684
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2459223586
Short name T795
Test name
Test status
Simulation time 970978564 ps
CPU time 7.2 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 208660 kb
Host smart-8413304a-2803-4f51-8afa-28e456fc17fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459223586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2459223586
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2851930703
Short name T756
Test name
Test status
Simulation time 4127318629 ps
CPU time 27.36 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 207912 kb
Host smart-40cfbaec-78fd-4e84-a803-a5fc55f20cc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851930703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2851930703
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2668827102
Short name T346
Test name
Test status
Simulation time 97430091 ps
CPU time 1.66 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 207952 kb
Host smart-660b46b7-f9f0-4f4e-91a7-73b05081b12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668827102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2668827102
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3344621345
Short name T122
Test name
Test status
Simulation time 216094647 ps
CPU time 6.29 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 208588 kb
Host smart-65e6c6a9-e96f-4ea8-80db-29e6bb858172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344621345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3344621345
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.390412677
Short name T206
Test name
Test status
Simulation time 91161738 ps
CPU time 4.19 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 209168 kb
Host smart-93eff519-e9f5-4726-8e8a-f3484a7fd2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390412677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.390412677
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.767231910
Short name T166
Test name
Test status
Simulation time 82716737 ps
CPU time 2.34 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 210400 kb
Host smart-1741e46c-8113-40d6-82de-411db5ba06c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767231910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.767231910
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1343793666
Short name T681
Test name
Test status
Simulation time 19189938 ps
CPU time 0.82 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:23 PM PDT 24
Peak memory 206012 kb
Host smart-c19948e1-363e-45ac-8839-5bd6981d1a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343793666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1343793666
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2169988050
Short name T232
Test name
Test status
Simulation time 40095937 ps
CPU time 2.94 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 214384 kb
Host smart-fda4c177-dc05-493e-9c1e-2731d050bd37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169988050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2169988050
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2401774146
Short name T225
Test name
Test status
Simulation time 125030431 ps
CPU time 5.11 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:35 PM PDT 24
Peak memory 218512 kb
Host smart-50de76fc-54a2-472d-80fa-16d97dd19273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401774146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2401774146
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2306308590
Short name T793
Test name
Test status
Simulation time 47091698 ps
CPU time 1.56 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 207476 kb
Host smart-8ea74937-08b7-457d-9600-2c2144d8d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306308590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2306308590
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1124681568
Short name T813
Test name
Test status
Simulation time 391865957 ps
CPU time 5.97 seconds
Started May 23 03:45:06 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 209568 kb
Host smart-d5948799-797d-4d18-b343-6ef1f44e18e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124681568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1124681568
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3959074409
Short name T266
Test name
Test status
Simulation time 79198712 ps
CPU time 2.72 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 214232 kb
Host smart-42e3603d-6b79-4d5a-aaec-fb2f768a7485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959074409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3959074409
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.32584326
Short name T907
Test name
Test status
Simulation time 92997311 ps
CPU time 3.34 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 209704 kb
Host smart-03f6c2e7-677d-4267-b014-b1069f37a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32584326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.32584326
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1356574252
Short name T549
Test name
Test status
Simulation time 150271377 ps
CPU time 2.94 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 207024 kb
Host smart-53fcd95b-504f-4f15-8f54-cb5d6e29868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356574252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1356574252
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1534377258
Short name T743
Test name
Test status
Simulation time 157738053 ps
CPU time 5.04 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 208624 kb
Host smart-dda993d7-454c-4299-aca8-fb2c78f25537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534377258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1534377258
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.523228758
Short name T828
Test name
Test status
Simulation time 850416634 ps
CPU time 11.23 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:43 PM PDT 24
Peak memory 208692 kb
Host smart-942bb9f5-c356-415e-a24a-ea2d36fb476e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523228758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.523228758
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.327772677
Short name T530
Test name
Test status
Simulation time 75187444 ps
CPU time 2.31 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 207076 kb
Host smart-f8964e0a-f644-48c0-b1ed-63e05de0745d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327772677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.327772677
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.104396215
Short name T685
Test name
Test status
Simulation time 284617639 ps
CPU time 3.29 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 206976 kb
Host smart-ead6d050-c3fd-48c4-a2c2-8869033ed2c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104396215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.104396215
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4216896007
Short name T120
Test name
Test status
Simulation time 92087810 ps
CPU time 2.07 seconds
Started May 23 03:45:07 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 208000 kb
Host smart-2c0207a4-5b98-47de-ba7c-83ca16a2bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216896007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4216896007
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3842942716
Short name T450
Test name
Test status
Simulation time 88971792 ps
CPU time 2.56 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 208496 kb
Host smart-cdea0741-9555-4b98-b576-9f80c935ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842942716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3842942716
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4138470809
Short name T859
Test name
Test status
Simulation time 48291527 ps
CPU time 3.07 seconds
Started May 23 03:44:58 PM PDT 24
Finished May 23 03:45:20 PM PDT 24
Peak memory 207036 kb
Host smart-a5a6c4b9-d7ce-4e0d-b43d-b0ba0ea92834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138470809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4138470809
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1327999509
Short name T227
Test name
Test status
Simulation time 258008251 ps
CPU time 16.51 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 222664 kb
Host smart-ca27d494-7df2-41be-ac5d-97f4e2985fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327999509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1327999509
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2963348115
Short name T842
Test name
Test status
Simulation time 829955567 ps
CPU time 5.12 seconds
Started May 23 03:45:08 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 207920 kb
Host smart-da01e939-0c28-405e-8d52-64a74a46a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963348115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2963348115
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4055694930
Short name T92
Test name
Test status
Simulation time 256843082 ps
CPU time 2.06 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:31 PM PDT 24
Peak memory 210204 kb
Host smart-a326555b-50f3-47ac-b2a4-f8c3a85cc420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055694930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4055694930
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3009792823
Short name T524
Test name
Test status
Simulation time 87034836 ps
CPU time 0.94 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:45:22 PM PDT 24
Peak memory 205952 kb
Host smart-f03f3acd-ef95-409e-8160-d064127dd244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009792823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3009792823
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2210309885
Short name T22
Test name
Test status
Simulation time 28677993 ps
CPU time 1.48 seconds
Started May 23 03:45:09 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 214696 kb
Host smart-cf281c65-1490-4f2e-be74-aafb2f4bc01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210309885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2210309885
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2510676382
Short name T908
Test name
Test status
Simulation time 95236262 ps
CPU time 1.63 seconds
Started May 23 03:45:06 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 207048 kb
Host smart-77855559-ee16-4c3c-956e-7f47c4d0bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510676382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2510676382
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.897774183
Short name T599
Test name
Test status
Simulation time 50802589 ps
CPU time 2.05 seconds
Started May 23 03:45:23 PM PDT 24
Finished May 23 03:45:46 PM PDT 24
Peak memory 214364 kb
Host smart-7282ddce-281e-447a-931f-b0786cb35db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897774183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.897774183
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1225009792
Short name T315
Test name
Test status
Simulation time 132695738 ps
CPU time 3.54 seconds
Started May 23 03:45:21 PM PDT 24
Finished May 23 03:45:45 PM PDT 24
Peak memory 214324 kb
Host smart-80122b5d-512a-4acf-88d4-81923daeb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225009792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1225009792
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1339125666
Short name T58
Test name
Test status
Simulation time 875977087 ps
CPU time 4.62 seconds
Started May 23 03:45:19 PM PDT 24
Finished May 23 03:45:44 PM PDT 24
Peak memory 214380 kb
Host smart-fadb378c-703a-4ca4-8eaa-bd5447749392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339125666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1339125666
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.122762335
Short name T510
Test name
Test status
Simulation time 1567991994 ps
CPU time 29.02 seconds
Started May 23 03:45:21 PM PDT 24
Finished May 23 03:46:10 PM PDT 24
Peak memory 208848 kb
Host smart-14ad4f95-4611-4f87-b714-c894b2598f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122762335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.122762335
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1173947851
Short name T867
Test name
Test status
Simulation time 740247829 ps
CPU time 11.69 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 208444 kb
Host smart-652d826d-7d20-4ad3-908b-65a2ed60a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173947851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1173947851
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.328479181
Short name T255
Test name
Test status
Simulation time 176373709 ps
CPU time 2.58 seconds
Started May 23 03:45:11 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 208772 kb
Host smart-2395b0f6-473b-4523-9c5b-577f69619262
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328479181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.328479181
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2375831212
Short name T774
Test name
Test status
Simulation time 67949609 ps
CPU time 3.16 seconds
Started May 23 03:45:05 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 206872 kb
Host smart-b65b8f6f-4d90-4386-8122-59e9ff831c12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375831212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2375831212
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.305842181
Short name T765
Test name
Test status
Simulation time 27502285 ps
CPU time 2.12 seconds
Started May 23 03:45:12 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 208488 kb
Host smart-d790d537-8be8-407d-927e-6c67dc811e82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305842181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.305842181
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1640102072
Short name T205
Test name
Test status
Simulation time 74377168 ps
CPU time 3.63 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:45:44 PM PDT 24
Peak memory 214368 kb
Host smart-0ce1ac43-635d-49be-a057-35ef29423081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640102072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1640102072
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4203053304
Short name T498
Test name
Test status
Simulation time 108134252 ps
CPU time 2.51 seconds
Started May 23 03:45:02 PM PDT 24
Finished May 23 03:45:22 PM PDT 24
Peak memory 206988 kb
Host smart-fa5882f5-e680-4cfa-86df-1f5ccd7f97b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203053304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4203053304
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.961800904
Short name T803
Test name
Test status
Simulation time 691586588 ps
CPU time 12.25 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:31 PM PDT 24
Peak memory 208804 kb
Host smart-1b1796a2-487d-4788-8e26-200eeeae65a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961800904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.961800904
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2213701576
Short name T41
Test name
Test status
Simulation time 68989989 ps
CPU time 2.7 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:30 PM PDT 24
Peak memory 210108 kb
Host smart-f3b0bbc4-750c-498c-b30e-0a1f16ce1d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213701576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2213701576
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.214568920
Short name T733
Test name
Test status
Simulation time 35956104 ps
CPU time 0.78 seconds
Started May 23 03:45:23 PM PDT 24
Finished May 23 03:45:44 PM PDT 24
Peak memory 205948 kb
Host smart-5f706ce1-d236-48ae-84c1-96b47a2739e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214568920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.214568920
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1946180240
Short name T427
Test name
Test status
Simulation time 1328288532 ps
CPU time 8.19 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:36 PM PDT 24
Peak memory 214724 kb
Host smart-d3c2bfb2-e3cf-48fb-b88e-e977401fcf70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946180240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1946180240
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3749126838
Short name T727
Test name
Test status
Simulation time 151192294 ps
CPU time 4.45 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 219632 kb
Host smart-acf11b9a-ea5a-4f5c-a980-7b9c5b324c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749126838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3749126838
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3448162664
Short name T541
Test name
Test status
Simulation time 737053146 ps
CPU time 4.97 seconds
Started May 23 03:45:16 PM PDT 24
Finished May 23 03:45:39 PM PDT 24
Peak memory 209316 kb
Host smart-f6fb54fa-dd0b-4b47-a07c-d5b67f216843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448162664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3448162664
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.989323089
Short name T656
Test name
Test status
Simulation time 741593757 ps
CPU time 5.64 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:57 PM PDT 24
Peak memory 222464 kb
Host smart-c10cae9c-6686-4c29-adab-e95b2c09ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989323089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.989323089
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1045281717
Short name T632
Test name
Test status
Simulation time 115204900 ps
CPU time 2.45 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:52 PM PDT 24
Peak memory 222456 kb
Host smart-ff5eddb1-4861-4acd-a5d7-e95d66b66e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045281717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1045281717
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3977898073
Short name T526
Test name
Test status
Simulation time 891577633 ps
CPU time 7.93 seconds
Started May 23 03:45:22 PM PDT 24
Finished May 23 03:45:50 PM PDT 24
Peak memory 220188 kb
Host smart-b63b33d5-94c0-4f7c-ab42-50130bbd33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977898073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3977898073
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2015766209
Short name T717
Test name
Test status
Simulation time 338820242 ps
CPU time 7.49 seconds
Started May 23 03:45:08 PM PDT 24
Finished May 23 03:45:33 PM PDT 24
Peak memory 209252 kb
Host smart-64d88794-a6b2-4bd1-8ca9-5b18d96c88a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015766209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2015766209
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4179432487
Short name T532
Test name
Test status
Simulation time 36187938 ps
CPU time 2.47 seconds
Started May 23 03:45:18 PM PDT 24
Finished May 23 03:45:40 PM PDT 24
Peak memory 206664 kb
Host smart-dd56758e-cc2a-4aa8-81e9-3fe964e84109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179432487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4179432487
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1547741688
Short name T507
Test name
Test status
Simulation time 140335608 ps
CPU time 3.9 seconds
Started May 23 03:45:17 PM PDT 24
Finished May 23 03:45:41 PM PDT 24
Peak memory 207012 kb
Host smart-53f47abd-2dec-4ddb-a9d7-5c128bc34fb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547741688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1547741688
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2624472788
Short name T637
Test name
Test status
Simulation time 449137659 ps
CPU time 9.67 seconds
Started May 23 03:45:14 PM PDT 24
Finished May 23 03:45:42 PM PDT 24
Peak memory 208224 kb
Host smart-9d8809ca-4689-4dd5-b33f-496cc5c66eee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624472788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2624472788
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2379395123
Short name T706
Test name
Test status
Simulation time 43082374 ps
CPU time 2.72 seconds
Started May 23 03:45:08 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 208760 kb
Host smart-fcec5334-a830-4c92-89ef-7e6bf1072328
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379395123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2379395123
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3662170143
Short name T528
Test name
Test status
Simulation time 276204710 ps
CPU time 3.82 seconds
Started May 23 03:45:30 PM PDT 24
Finished May 23 03:45:55 PM PDT 24
Peak memory 214372 kb
Host smart-5a522f9e-fc9b-406b-a1f3-fd02284c0c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662170143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3662170143
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1663572979
Short name T98
Test name
Test status
Simulation time 455303987 ps
CPU time 5.23 seconds
Started May 23 03:45:10 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 206848 kb
Host smart-09283c72-9ec0-4c37-9b16-fc87801a18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663572979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1663572979
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.860929127
Short name T200
Test name
Test status
Simulation time 3135979908 ps
CPU time 22.06 seconds
Started May 23 03:45:26 PM PDT 24
Finished May 23 03:46:09 PM PDT 24
Peak memory 216488 kb
Host smart-92b51d8b-34d9-42d1-ad21-df1561203b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860929127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.860929127
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2585212618
Short name T228
Test name
Test status
Simulation time 211635418 ps
CPU time 13.77 seconds
Started May 23 03:45:20 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 222744 kb
Host smart-d9615586-642a-4449-b1c4-6ed5e4a865a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585212618 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2585212618
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3325604135
Short name T237
Test name
Test status
Simulation time 146224691 ps
CPU time 4.69 seconds
Started May 23 03:45:28 PM PDT 24
Finished May 23 03:45:54 PM PDT 24
Peak memory 210256 kb
Host smart-5c405068-8da4-45c9-8815-dbfa16e55094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325604135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3325604135
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2666506787
Short name T42
Test name
Test status
Simulation time 135651768 ps
CPU time 1.62 seconds
Started May 23 03:45:21 PM PDT 24
Finished May 23 03:45:43 PM PDT 24
Peak memory 208664 kb
Host smart-94cc5fe2-799d-41d2-87ca-f26a84916ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666506787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2666506787
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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