Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4853

1

T1

2

T2

14

T11

8

auto[1]

543

1

T1

1

T16

5

T43

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4853

1

T1

2

T2

14

T11

8

auto[1]

543

1

T1

1

T16

5

T43

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4872

1

T1

2

T2

10

T11

8

auto[1]

524

1

T1

1

T2

4

T14

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4872

1

T1

2

T2

10

T11

8

auto[1]

524

1

T1

1

T2

4

T14

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T1	1		T2	3		T13	4
auto[OpGenId]	1180	1			T1	1		T2	1		T12	3
auto[OpGenSwOut]	1169	1			T1	1		T2	6		T12	3
auto[OpGenHwOut]	2543	1			T2	4		T11	8		T13	2
auto[OpDisable]	72	1			T48	1		T50	1		T67	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T1	1		T2	3		T13	4
auto[OpGenId]	1180	1			T1	1		T2	1		T12	3
auto[OpGenSwOut]	1169	1			T1	1		T2	6		T12	3
auto[OpGenHwOut]	2543	1			T2	4		T11	8		T13	2
auto[OpDisable]	72	1			T48	1		T50	1		T67	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4833

1

T1

1

T2

12

T11

3

auto[1]

563

1

T1

2

T2

2

T11

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4833

1

T1

1

T2

12

T11

3

auto[1]

563

1

T1

2

T2

2

T11

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5117

1

T1

3

T2

14

T11

8

auto[1]

279

1

T13

3

T120

13

T136

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1847	1			T1	1		T2	6		T11	3
auto[1]	671	1			T2	1		T11	3		T13	1
auto[2]	732	1			T1	1		T2	1		T12	1
auto[3]	672	1			T2	5		T11	1		T12	3
auto[4]	416	1			T11	1		T15	1		T16	1
auto[5]	383	1			T1	1		T2	1		T13	5
auto[6]	332	1			T33	1		T43	2		T203	2
auto[7]	343	1			T17	2		T43	2		T199	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1474	1			T1	1		T2	1		T11	1
clear_one[1]	671	1			T2	1		T11	3		T13	1
clear_one[2]	732	1			T1	1		T2	1		T12	1
clear_one[3]	672	1			T2	5		T11	1		T12	3
clear_none	1847	1			T1	1		T2	6		T11	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1000	1			T2	4		T12	1		T13	3
auto[StInit]	655	1			T2	1		T11	1		T12	1
auto[StCreatorRootKey]	563	1			T2	2		T11	1		T12	1
auto[StOwnerIntKey]	503	1			T1	1		T2	2		T11	1
auto[StOwnerKey]	481	1			T1	1		T2	2		T11	1
auto[StDisabled]	1896	1			T1	1		T2	3		T11	4
auto[StInvalid]	298	1			T33	2		T35	2		T51	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1000	1			T2	4		T12	1		T13	3
auto[StInit]	655	1			T2	1		T11	1		T12	1
auto[StCreatorRootKey]	563	1			T2	2		T11	1		T12	1
auto[StOwnerIntKey]	503	1			T1	1		T2	2		T11	1
auto[StOwnerKey]	481	1			T1	1		T2	2		T11	1
auto[StDisabled]	1896	1			T1	1		T2	3		T11	4
auto[StInvalid]	298	1			T33	2		T35	2		T51	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[0] - auto[1]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[0] - auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpGenId]	178	1			T12	1		T18	1		T199	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	151	1			T2	2		T13	1		T33	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	250	1			T2	1		T13	1		T15	1
auto[0]	auto[StInit]	auto[OpAdvance]	31	1			T149	1		T22	1		T223	1
auto[0]	auto[StInit]	auto[OpGenId]	97	1			T116	1		T60	1		T130	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	102	1			T60	2		T44	2		T149	4
auto[0]	auto[StInit]	auto[OpGenHwOut]	190	1			T11	1		T19	1		T201	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T130	1		T63	1		T82	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	54	1			T105	1		T45	1		T46	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	44	1			T137	1		T45	3		T21	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	74	1			T43	1		T49	1		T133	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T44	1		T78	1		T224	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T136	2		T46	1		T127	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T1	1		T2	1		T136	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T68	1		T57	1		T225	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T14	1		T57	1		T44	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	16	1			T196	1		T44	1		T138	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T12	1		T134	1		T44	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T2	1		T11	1		T43	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T195	1		T44	1		T138	1
auto[0]	auto[StDisabled]	auto[OpGenId]	58	1			T26	1		T195	1		T105	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T26	1		T60	1		T44	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	178	1			T2	1		T11	1		T16	1
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T67	1		T44	1		T45	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T88	1		T226	1		T227	1
auto[0]	auto[StInvalid]	auto[OpGenId]	30	1			T35	1		T66	1		T89	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	30	1			T228	1		T88	1		T106	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T51	1		T52	1		T83	1
auto[1]	auto[StReset]	auto[OpGenId]	15	1			T135	1		T4	1		T229	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T199	1		T120	1		T56	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T202	1		T230	2		T4	2
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T26	1		T231	1		T232	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T4	1		T138	1		T233	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T44	1		T47	1		T234	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T235	1		T236	1		T73	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T120	1		T109	1		T114	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T15	1		T120	1		T237	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T2	1		T13	1		T46	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T16	1		T17	1		T60	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T238	2		T239	1		T240	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T135	1		T137	1		T47	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T26	1		T120	1		T241	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T11	1		T203	1		T201	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T139	2		T242	1		T243	2
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T126	1		T77	1		T244	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T85	3		T46	1		T138	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T203	1		T60	1		T136	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	33	1			T136	1		T63	1		T139	1
auto[1]	auto[StDisabled]	auto[OpGenId]	52	1			T48	1		T60	2		T196	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T15	1		T60	1		T136	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T11	2		T17	1		T120	2
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T57	1		T126	1		T6	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T51	1		T83	1		T245	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T227	1		T246	1		T247	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T52	1		T83	1		T106	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T52	1		T92	1		T87	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T248	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T48	1		T196	1		T187	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T48	1		T45	1		T46	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	37	1			T43	1		T202	1		T120	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T249	1		T101	1		T250	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T196	1		T44	1		T4	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T138	1		T251	1		T141	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T17	1		T202	1		T133	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T141	1		T252	1		T253	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T30	1		T46	1		T4	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T44	1		T138	1		T248	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T84	1		T126	1		T254	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T128	1		T217	1		T255	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T82	1		T46	1		T138	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T93	1		T96	1		T256	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T16	1		T17	1		T116	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T2	1		T23	1		T59	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T60	1		T44	1		T45	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T44	2		T127	1		T257	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T17	1		T201	1		T44	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	28	1			T1	1		T120	1		T23	1
auto[2]	auto[StDisabled]	auto[OpGenId]	68	1			T49	1		T60	2		T44	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T12	1		T120	1		T105	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	174	1			T13	1		T16	2		T17	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T48	1		T50	1		T45	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	10	1			T258	1		T89	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T92	1		T245	1		T227	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T33	1		T90	1		T260	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T259	1		T261	1		T113	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T262	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T18	1		T60	1		T47	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T2	1		T20	1		T249	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T199	1		T202	1		T44	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T57	1		T190	1		T263	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T12	1		T50	1		T138	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T2	1		T264	1		T77	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T203	1		T60	1		T44	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T105	1		T257	1		T93	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T2	1		T12	1		T265	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T59	1		T6	1		T77	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T11	1		T202	1		T132	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T2	1		T138	1		T266	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T4	1		T141	1		T267	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T12	1		T195	1		T257	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T44	1		T81	1		T235	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T138	1		T59	1		T114	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T195	1		T80	1		T257	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T4	1		T257	1		T6	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T16	1		T230	1		T236	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	13	1			T85	1		T4	1		T268	1
auto[3]	auto[StDisabled]	auto[OpGenId]	62	1			T13	1		T67	1		T60	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T15	1		T134	1		T63	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T2	1		T203	1		T202	2
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T46	1		T127	1		T73	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T269	1		T270	1		T271	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T52	1		T88	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T258	1		T89	1		T226	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T92	1		T272	1		T273	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T15	1		T33	1		T48	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T274	1		T77	1		T53	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	29	1			T16	1		T29	1		T258	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T197	1		T180	1		T275	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	10	1			T93	1		T239	1		T276	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	16	1			T199	1		T230	1		T277	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T217	1		T94	1		T278	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T57	1		T74	1		T279	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T20	1		T280	1		T211	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T201	1		T44	1		T235	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T57	1		T281	1		T282	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T141	1		T283	1		T284	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T63	1		T257	1		T78	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T44	1		T241	1		T285	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T281	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T4	1		T281	2		T77	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T281	2		T6	1		T190	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T132	1		T225	1		T286	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T44	2		T287	1		T241	1
auto[4]	auto[StDisabled]	auto[OpGenId]	41	1			T195	1		T44	1		T138	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T136	1		T128	1		T141	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T11	1		T17	1		T132	2
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T77	1		T78	1		T288	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T289	1		T270	1		T290	1
auto[4]	auto[StInvalid]	auto[OpGenId]	11	1			T51	1		T245	1		T291	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T89	1		T292	1		T246	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T86	1		T293	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T13	1		T44	1		T249	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	20	1			T45	1		T47	1		T257	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	27	1			T203	1		T202	1		T44	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T294	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T48	1		T20	1		T45	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	10	1			T120	5		T4	2		T239	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T16	1		T43	1		T120	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T295	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T44	1		T45	1		T127	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T195	1		T296	1		T234	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T203	1		T297	1		T298	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T13	1		T248	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T85	1		T53	1		T299	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T23	1		T45	1		T4	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T141	1		T77	1		T300	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T120	2		T141	1		T301	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T1	1		T135	1		T268	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T57	1		T20	1		T79	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T133	1		T235	1		T302	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	24	1			T2	1		T13	3		T44	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T120	1		T60	1		T241	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T85	2		T4	1		T141	3
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T16	1		T57	1		T44	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T141	1		T303	1		T304	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T113	1		T269	1		T305	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T83	1		T306	1		T307	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T33	1		T86	1		T289	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T308	1		T272	1		T273	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T141	1		T266	1		T191	2
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T92	1		T53	1		T309	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T33	1		T43	1		T45	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T266	1		T310	1		T311	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T45	1		T312	1		T313	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T46	1		T59	1		T314	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T60	1		T315	1		T316	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T151	1		T310	1		T239	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T317	1		T255	1		T318	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T63	1		T47	1		T242	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T135	1		T319	1		T315	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T137	1		T45	1		T53	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T44	1		T191	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T44	1		T59	1		T75	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T133	1		T84	1		T286	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T320	1		T242	1		T321	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T105	1		T111	1		T211	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T60	1		T191	1		T322	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T60	2		T323	1		T324	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	17	1			T85	1		T137	2		T45	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T44	1		T257	1		T325	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T199	1		T60	1		T85	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T43	1		T203	2		T201	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T190	1		T239	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	6	1			T35	1		T306	2		T227	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T228	1		T66	1		T258	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T83	1		T326	1		T270	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T52	1		T269	1		T327	1
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T4	2		T138	1		T328	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T46	1		T248	1		T77	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T17	2		T235	2		T45	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T266	1		T329	1		T330	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T46	1		T141	1		T78	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T331	1		T53	1		T332	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T24	1		T333	1		T334	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T190	1		T309	2		T335	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T213	1		T336	1		T266	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T249	1		T53	1		T238	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T44	1		T141	1		T337	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T45	1		T75	1		T338	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T105	1		T44	1		T45	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T60	1		T138	1		T139	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T43	1		T47	1		T138	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T60	1		T136	1		T339	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	11	1			T199	1		T45	1		T46	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T279	1		T340	2		T341	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T84	1		T47	1		T127	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T105	1		T310	1		T341	4
auto[7]	auto[StDisabled]	auto[OpGenId]	20	1			T199	1		T342	1		T343	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T136	1		T225	1		T45	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T43	1		T202	1		T44	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T344	1		T74	1		T180	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	6	1			T326	1		T345	1		T346	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T226	1		T347	1		T308	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T348	1		T245	1		T349	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T88	1		T87	1		T327	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1474

1

T1

1

T2

1

T11

1

clear_one[1]

auto[0]

auto[0]

auto[0]

409

1

T2

1

T13

1

T15

2

clear_one[1]

auto[0]

auto[0]

auto[1]

107

1

T11

3

T203

2

T133

1

clear_one[1]

auto[0]

auto[1]

auto[0]

109

1

T17

2

T201

1

T60

2

clear_one[1]

auto[0]

auto[1]

auto[1]

46

1

T136

2

T44

2

T138

1

clear_one[2]

auto[0]

auto[0]

auto[0]

420

1

T12

1

T17

4

T33

1

clear_one[2]

auto[0]

auto[0]

auto[1]

145

1

T1

1

T2

1

T13

1

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T16

3

T43

2

T60

1

clear_one[2]

auto[1]

auto[0]

auto[1]

44

1

T127

1

T138

4

T257

2

clear_one[3]

auto[0]

auto[0]

auto[0]

395

1

T2

4

T11

1

T12

3

clear_one[3]

auto[0]

auto[1]

auto[0]

110

1

T2

1

T202

3

T57

2

clear_one[3]

auto[1]

auto[0]

auto[0]

137

1

T16

1

T67

1

T120

1

clear_one[3]

auto[1]

auto[1]

auto[0]

30

1

T134

1

T135

1

T57

1

clear_none

auto[0]

auto[0]

auto[0]

1334

1

T2

3

T11

1

T12

2

clear_none

auto[0]

auto[0]

auto[1]

135

1

T11

2

T133

3

T81

1

clear_none

auto[0]

auto[1]

auto[0]

138

1

T2

2

T14

1

T17

1

clear_none

auto[0]

auto[1]

auto[1]

31

1

T2

1

T26

1

T44

1

clear_none

auto[1]

auto[0]

auto[0]

120

1

T16

1

T43

2

T68

1

clear_none

auto[1]

auto[0]

auto[1]

29

1

T105

1

T149

2

T45

2

clear_none

auto[1]

auto[1]

auto[0]

34

1

T60

1

T134

1

T57

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T1

1

T4

1

T138

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1357	1			T1	1		T2	1		T11	1
clear_all	auto[1]	117	1			T13	3		T120	7		T136	1
clear_one[1]	auto[0]	622	1			T2	1		T11	3		T13	1
clear_one[1]	auto[1]	49	1			T120	3		T136	3		T85	2
clear_one[2]	auto[0]	689	1			T1	1		T2	1		T12	1
clear_one[2]	auto[1]	43	1			T120	3		T136	1		T248	2
clear_one[3]	auto[0]	647	1			T2	5		T11	1		T12	3
clear_one[3]	auto[1]	25	1			T85	1		T350	1		T266	6
clear_none	auto[0]	1802	1			T1	1		T2	6		T11	3
clear_none	auto[1]	45	1			T136	2		T149	12		T350	2