Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11341

1

T1

10

T2

51

T3

3

auto[Attestation]

7729

1

T1

14

T2

34

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2718	1			T1	5		T2	9		T12	3
auto[Aes]	3422	1			T1	3		T2	13		T3	2
auto[Kmac]	3425	1			T1	3		T2	13		T3	1
auto[Otbn]	3404	1			T1	4		T2	15		T11	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7825	1			T1	8		T2	45		T3	1
auto[OpGenId]	6101	1			T1	9		T2	35		T3	1
auto[OpGenSwOut]	5969	1			T1	7		T2	34		T3	1
auto[OpGenHwOut]	7000	1			T1	8		T2	16		T3	2
auto[OpDisable]	143	1			T48	1		T49	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10879

1

T1

17

T2

51

T3

1

auto[OpDoneFail]

16159

1

T1

15

T2

79

T3

4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6455	1			T1	1		T2	32		T3	1
auto[StInit]	3943	1			T1	6		T2	21		T3	4
auto[StCreatorRootKey]	3280	1			T1	4		T2	18		T11	2
auto[StOwnerIntKey]	2915	1			T1	6		T2	12		T11	2
auto[StOwnerKey]	2412	1			T1	5		T2	9		T11	2
auto[StDisabled]	8033	1			T1	10		T2	38		T11	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	337	1			T2	2		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T60	3		T57	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	102	1			T67	1		T26	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	84	1			T2	1		T14	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T1	1		T2	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	232	1			T2	1		T60	3		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	347	1			T2	3		T12	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	99	1			T2	1		T18	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	103	1			T67	1		T195	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T2	1		T196	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T195	1		T60	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	197	1			T2	4		T14	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	329	1			T12	1		T34	1		T197	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T2	1		T3	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T105	1		T57	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T68	1		T120	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T105	1		T57	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	202	1			T2	2		T26	2		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	327	1			T2	5		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T12	1		T105	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T2	1		T13	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T2	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T134	1		T57	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	218	1			T26	1		T195	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T60	1		T44	9		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T2	1		T34	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T1	1		T60	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T12	1		T15	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T44	1		T138	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	213	1			T1	2		T12	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	79	1			T60	3		T44	4		T46	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T2	1		T67	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T2	1		T13	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T2	1		T195	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	51	1			T44	1		T63	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	210	1			T67	1		T26	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T60	1		T44	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	93	1			T2	1		T130	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T2	1		T12	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T1	1		T195	1		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T1	1		T44	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	221	1			T2	2		T60	2		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T60	1		T44	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	124	1			T1	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T2	1		T199	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T13	1		T14	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T15	1		T67	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	228	1			T2	1		T12	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	259	1			T2	1		T15	2		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T2	1		T19	1		T60	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	62	1			T197	1		T60	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T60	1		T44	3		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T60	1		T135	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T1	1		T2	1		T199	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	467	1			T13	4		T16	3		T43	6
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T1	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	103	1			T197	1		T26	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T1	1		T16	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T132	1		T57	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	284	1			T16	3		T43	3		T60	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	489	1			T12	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	137	1			T2	1		T17	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T49	1		T197	2		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T1	1		T50	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T17	1		T116	2		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	305	1			T2	1		T12	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	440	1			T2	1		T15	1		T203	8
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	141	1			T2	1		T11	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T197	3		T60	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	111	1			T1	2		T116	2		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T203	1		T133	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	270	1			T1	1		T11	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T44	2		T45	1		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T19	1		T135	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T13	1		T116	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T116	1		T120	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T68	1		T60	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	164	1			T50	1		T60	1		T105	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T2	1		T60	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T3	1		T15	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	126	1			T1	1		T16	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T132	1		T135	1		T204	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	105	1			T16	1		T43	1		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	289	1			T16	1		T43	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T2	1		T60	1		T63	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	111	1			T13	1		T14	1		T34	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T17	1		T202	1		T60	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	107	1			T2	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	72	1			T2	1		T201	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	292	1			T2	1		T13	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	51	1			T60	1		T44	2		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	114	1			T60	2		T57	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	123	1			T2	3		T11	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T11	1		T105	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	82	1			T11	1		T105	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	279	1			T2	1		T11	3		T203	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	237	1			T1	1		T2	2		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	691	1			T2	3		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	210	1			T2	1		T67	1		T195	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	664	1			T2	8		T12	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T68	1		T120	1		T105	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	674	1			T2	3		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T2	2		T13	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	668	1			T2	5		T12	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T1	1		T12	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	395	1			T1	2		T2	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	181	1			T2	2		T13	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	420	1			T2	1		T67	2		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T1	2		T2	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	390	1			T2	3		T60	3		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T13	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	434	1			T1	1		T2	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T197	1		T60	3		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	549	1			T1	1		T2	3		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	254	1			T1	1		T16	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	892	1			T1	1		T3	1		T13	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T1	1		T17	1		T116	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	943	1			T2	2		T12	2		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	290	1			T1	2		T116	2		T203	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	864	1			T1	1		T2	2		T11	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	178	1			T13	1		T116	2		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	315	1			T19	1		T50	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	318	1			T1	1		T16	2		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	483	1			T2	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	269	1			T2	2		T14	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	465	1			T2	2		T13	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	287	1			T2	2		T11	3		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	458	1			T2	2		T11	3		T203	1