Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33200

1

T1

36

T2

159

T3

5

auto[1]

251

1

T13

4

T120

7

T136

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33210	1			T1	36		T2	159		T3	5
auto[134217728:268435455]	8	1			T139	1		T266	1		T335	1
auto[268435456:402653183]	7	1			T85	1		T137	1		T266	1
auto[402653184:536870911]	12	1			T266	2		T310	2		T240	1
auto[536870912:671088639]	3	1			T266	1		T368	1		T309	1
auto[671088640:805306367]	6	1			T85	1		T268	1		T369	1
auto[805306368:939524095]	6	1			T120	1		T266	1		T248	1
auto[939524096:1073741823]	7	1			T248	2		T242	1		T310	1
auto[1073741824:1207959551]	5	1			T85	1		T139	1		T295	1
auto[1207959552:1342177279]	8	1			T248	1		T310	1		T359	1
auto[1342177280:1476395007]	5	1			T13	1		T149	1		T341	1
auto[1476395008:1610612735]	4	1			T369	1		T310	1		T240	1
auto[1610612736:1744830463]	9	1			T13	2		T137	1		T368	1
auto[1744830464:1879048191]	11	1			T85	1		T139	1		T281	1
auto[1879048192:2013265919]	8	1			T281	2		T369	1		T310	1
auto[2013265920:2147483647]	11	1			T139	1		T268	1		T340	1
auto[2147483648:2281701375]	2	1			T370	1		T371	1		-	-
auto[2281701376:2415919103]	7	1			T266	1		T309	1		T240	1
auto[2415919104:2550136831]	15	1			T120	1		T85	1		T137	1
auto[2550136832:2684354559]	6	1			T149	1		T369	1		T372	1
auto[2684354560:2818572287]	9	1			T13	1		T268	1		T281	1
auto[2818572288:2952790015]	9	1			T120	1		T149	1		T268	1
auto[2952790016:3087007743]	5	1			T120	1		T368	1		T310	1
auto[3087007744:3221225471]	4	1			T372	1		T335	1		T240	1
auto[3221225472:3355443199]	8	1			T248	1		T372	1		T253	1
auto[3355443200:3489660927]	10	1			T136	1		T85	1		T325	1
auto[3489660928:3623878655]	7	1			T120	1		T268	1		T281	1
auto[3623878656:3758096383]	7	1			T149	1		T268	1		T341	2
auto[3758096384:3892314111]	12	1			T120	1		T137	1		T149	1
auto[3892314112:4026531839]	9	1			T85	1		T149	1		T360	1
auto[4026531840:4160749567]	5	1			T136	1		T369	1		T243	1
auto[4160749568:4294967295]	16	1			T242	1		T369	1		T360	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33200	1			T1	36		T2	159		T3	5
auto[0:134217727]	auto[1]	10	1			T120	1		T136	1		T137	1
auto[134217728:268435455]	auto[1]	8	1			T139	1		T266	1		T335	1
auto[268435456:402653183]	auto[1]	7	1			T85	1		T137	1		T266	1
auto[402653184:536870911]	auto[1]	12	1			T266	2		T310	2		T240	1
auto[536870912:671088639]	auto[1]	3	1			T266	1		T368	1		T309	1
auto[671088640:805306367]	auto[1]	6	1			T85	1		T268	1		T369	1
auto[805306368:939524095]	auto[1]	6	1			T120	1		T266	1		T248	1
auto[939524096:1073741823]	auto[1]	7	1			T248	2		T242	1		T310	1
auto[1073741824:1207959551]	auto[1]	5	1			T85	1		T139	1		T295	1
auto[1207959552:1342177279]	auto[1]	8	1			T248	1		T310	1		T359	1
auto[1342177280:1476395007]	auto[1]	5	1			T13	1		T149	1		T341	1
auto[1476395008:1610612735]	auto[1]	4	1			T369	1		T310	1		T240	1
auto[1610612736:1744830463]	auto[1]	9	1			T13	2		T137	1		T368	1
auto[1744830464:1879048191]	auto[1]	11	1			T85	1		T139	1		T281	1
auto[1879048192:2013265919]	auto[1]	8	1			T281	2		T369	1		T310	1
auto[2013265920:2147483647]	auto[1]	11	1			T139	1		T268	1		T340	1
auto[2147483648:2281701375]	auto[1]	2	1			T370	1		T371	1		-	-
auto[2281701376:2415919103]	auto[1]	7	1			T266	1		T309	1		T240	1
auto[2415919104:2550136831]	auto[1]	15	1			T120	1		T85	1		T137	1
auto[2550136832:2684354559]	auto[1]	6	1			T149	1		T369	1		T372	1
auto[2684354560:2818572287]	auto[1]	9	1			T13	1		T268	1		T281	1
auto[2818572288:2952790015]	auto[1]	9	1			T120	1		T149	1		T268	1
auto[2952790016:3087007743]	auto[1]	5	1			T120	1		T368	1		T310	1
auto[3087007744:3221225471]	auto[1]	4	1			T372	1		T335	1		T240	1
auto[3221225472:3355443199]	auto[1]	8	1			T248	1		T372	1		T253	1
auto[3355443200:3489660927]	auto[1]	10	1			T136	1		T85	1		T325	1
auto[3489660928:3623878655]	auto[1]	7	1			T120	1		T268	1		T281	1
auto[3623878656:3758096383]	auto[1]	7	1			T149	1		T268	1		T341	2
auto[3758096384:3892314111]	auto[1]	12	1			T120	1		T137	1		T149	1
auto[3892314112:4026531839]	auto[1]	9	1			T85	1		T149	1		T360	1
auto[4026531840:4160749567]	auto[1]	5	1			T136	1		T369	1		T243	1
auto[4160749568:4294967295]	auto[1]	16	1			T242	1		T369	1		T360	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1613

1

T1

1

T2

1

T12

4

auto[1]

1840

1

T1

2

T2

10

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	126	1			T14	1		T48	1		T50	1
auto[134217728:268435455]	86	1			T2	1		T19	1		T120	1
auto[268435456:402653183]	105	1			T2	2		T68	1		T67	1
auto[402653184:536870911]	109	1			T35	1		T51	1		T56	1
auto[536870912:671088639]	101	1			T50	1		T68	1		T44	1
auto[671088640:805306367]	102	1			T14	1		T51	1		T56	1
auto[805306368:939524095]	88	1			T12	1		T13	1		T116	1
auto[939524096:1073741823]	132	1			T2	1		T197	1		T26	1
auto[1073741824:1207959551]	102	1			T120	1		T57	3		T52	1
auto[1207959552:1342177279]	112	1			T116	1		T35	1		T56	1
auto[1342177280:1476395007]	125	1			T13	1		T33	2		T51	2
auto[1476395008:1610612735]	106	1			T1	1		T14	1		T33	1
auto[1610612736:1744830463]	102	1			T1	1		T2	2		T33	1
auto[1744830464:1879048191]	104	1			T67	1		T52	1		T44	1
auto[1879048192:2013265919]	104	1			T116	1		T197	1		T67	1
auto[2013265920:2147483647]	101	1			T12	1		T33	1		T51	1
auto[2147483648:2281701375]	106	1			T12	1		T33	1		T68	2
auto[2281701376:2415919103]	99	1			T120	1		T60	1		T52	1
auto[2415919104:2550136831]	116	1			T1	1		T13	1		T48	1
auto[2550136832:2684354559]	123	1			T13	1		T57	1		T44	1
auto[2684354560:2818572287]	115	1			T26	2		T120	1		T57	1
auto[2818572288:2952790015]	116	1			T2	1		T12	1		T13	1
auto[2952790016:3087007743]	107	1			T2	1		T105	1		T44	3
auto[3087007744:3221225471]	98	1			T67	1		T135	1		T57	1
auto[3221225472:3355443199]	90	1			T12	1		T13	1		T68	1
auto[3355443200:3489660927]	121	1			T2	1		T33	1		T48	1
auto[3489660928:3623878655]	111	1			T19	1		T35	2		T51	1
auto[3623878656:3758096383]	111	1			T2	1		T50	1		T67	1
auto[3758096384:3892314111]	104	1			T18	1		T35	1		T195	1
auto[3892314112:4026531839]	103	1			T2	1		T197	1		T57	1
auto[4026531840:4160749567]	118	1			T195	2		T60	2		T23	1
auto[4160749568:4294967295]	110	1			T35	1		T60	2		T57	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T48	1		T51	1		T56	1
auto[0:134217727]	auto[1]	66	1			T14	1		T50	1		T57	1
auto[134217728:268435455]	auto[0]	46	1			T120	1		T60	1		T29	1
auto[134217728:268435455]	auto[1]	40	1			T2	1		T19	1		T44	1
auto[268435456:402653183]	auto[0]	55	1			T67	1		T44	1		T373	1
auto[268435456:402653183]	auto[1]	50	1			T2	2		T68	1		T26	1
auto[402653184:536870911]	auto[0]	59	1			T35	1		T51	1		T56	1
auto[402653184:536870911]	auto[1]	50	1			T136	1		T44	1		T85	2
auto[536870912:671088639]	auto[0]	49	1			T4	2		T214	1		T249	1
auto[536870912:671088639]	auto[1]	52	1			T50	1		T68	1		T44	1
auto[671088640:805306367]	auto[0]	41	1			T51	1		T138	1		T141	1
auto[671088640:805306367]	auto[1]	61	1			T14	1		T56	1		T257	1
auto[805306368:939524095]	auto[0]	42	1			T12	1		T13	1		T116	1
auto[805306368:939524095]	auto[1]	46	1			T204	1		T44	1		T45	2
auto[939524096:1073741823]	auto[0]	63	1			T26	1		T51	1		T120	1
auto[939524096:1073741823]	auto[1]	69	1			T2	1		T197	1		T60	1
auto[1073741824:1207959551]	auto[0]	42	1			T120	1		T57	2		T128	1
auto[1073741824:1207959551]	auto[1]	60	1			T57	1		T52	1		T44	2
auto[1207959552:1342177279]	auto[0]	54	1			T35	1		T56	1		T52	1
auto[1207959552:1342177279]	auto[1]	58	1			T116	1		T130	1		T44	2
auto[1342177280:1476395007]	auto[0]	59	1			T13	1		T33	2		T51	2
auto[1342177280:1476395007]	auto[1]	66	1			T56	1		T57	1		T200	1
auto[1476395008:1610612735]	auto[0]	40	1			T33	1		T50	1		T56	1
auto[1476395008:1610612735]	auto[1]	66	1			T1	1		T14	1		T135	1
auto[1610612736:1744830463]	auto[0]	55	1			T1	1		T33	1		T57	1
auto[1610612736:1744830463]	auto[1]	47	1			T2	2		T60	1		T83	1
auto[1744830464:1879048191]	auto[0]	41	1			T44	1		T258	1		T214	1
auto[1744830464:1879048191]	auto[1]	63	1			T67	1		T52	1		T64	2
auto[1879048192:2013265919]	auto[0]	39	1			T116	1		T67	1		T258	1
auto[1879048192:2013265919]	auto[1]	65	1			T197	1		T57	2		T44	1
auto[2013265920:2147483647]	auto[0]	47	1			T12	1		T33	1		T149	1
auto[2013265920:2147483647]	auto[1]	54	1			T51	1		T57	1		T44	1
auto[2147483648:2281701375]	auto[0]	49	1			T33	1		T68	1		T105	1
auto[2147483648:2281701375]	auto[1]	57	1			T12	1		T68	1		T57	1
auto[2281701376:2415919103]	auto[0]	39	1			T138	1		T213	1		T249	1
auto[2281701376:2415919103]	auto[1]	60	1			T120	1		T60	1		T52	1
auto[2415919104:2550136831]	auto[0]	51	1			T51	1		T57	1		T83	1
auto[2415919104:2550136831]	auto[1]	65	1			T1	1		T13	1		T48	1
auto[2550136832:2684354559]	auto[0]	56	1			T63	1		T365	1		T138	1
auto[2550136832:2684354559]	auto[1]	67	1			T13	1		T57	1		T44	1
auto[2684354560:2818572287]	auto[0]	56	1			T26	1		T120	1		T63	1
auto[2684354560:2818572287]	auto[1]	59	1			T26	1		T57	1		T44	1
auto[2818572288:2952790015]	auto[0]	53	1			T12	1		T63	1		T89	1
auto[2818572288:2952790015]	auto[1]	63	1			T2	1		T13	1		T135	1
auto[2952790016:3087007743]	auto[0]	48	1			T105	1		T257	1		T141	1
auto[2952790016:3087007743]	auto[1]	59	1			T2	1		T44	3		T66	1
auto[3087007744:3221225471]	auto[0]	51	1			T67	1		T57	1		T52	1
auto[3087007744:3221225471]	auto[1]	47	1			T135	1		T149	1		T45	1
auto[3221225472:3355443199]	auto[0]	37	1			T12	1		T51	1		T64	1
auto[3221225472:3355443199]	auto[1]	53	1			T13	1		T68	1		T197	1
auto[3355443200:3489660927]	auto[0]	63	1			T33	1		T48	1		T57	1
auto[3355443200:3489660927]	auto[1]	58	1			T2	1		T18	1		T120	1
auto[3489660928:3623878655]	auto[0]	61	1			T35	2		T51	1		T57	1
auto[3489660928:3623878655]	auto[1]	50	1			T19	1		T56	1		T105	1
auto[3623878656:3758096383]	auto[0]	52	1			T67	1		T120	1		T105	1
auto[3623878656:3758096383]	auto[1]	59	1			T2	1		T50	1		T134	1
auto[3758096384:3892314111]	auto[0]	48	1			T18	1		T60	1		T105	1
auto[3758096384:3892314111]	auto[1]	56	1			T35	1		T195	1		T120	1
auto[3892314112:4026531839]	auto[0]	47	1			T2	1		T45	2		T374	1
auto[3892314112:4026531839]	auto[1]	56	1			T197	1		T57	1		T44	2
auto[4026531840:4160749567]	auto[0]	65	1			T195	1		T60	1		T63	1
auto[4026531840:4160749567]	auto[1]	53	1			T195	1		T60	1		T23	1
auto[4160749568:4294967295]	auto[0]	45	1			T60	1		T44	2		T82	1
auto[4160749568:4294967295]	auto[1]	65	1			T35	1		T60	1		T57	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1626

1

T1

2

T2

4

T12

3

auto[1]

1827

1

T1

1

T2

7

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T12	1		T33	1		T35	1
auto[134217728:268435455]	122	1			T1	1		T13	1		T33	1
auto[268435456:402653183]	104	1			T197	2		T67	1		T195	1
auto[402653184:536870911]	111	1			T35	1		T67	1		T60	2
auto[536870912:671088639]	115	1			T13	1		T48	1		T50	1
auto[671088640:805306367]	129	1			T33	1		T50	2		T23	1
auto[805306368:939524095]	93	1			T2	1		T33	1		T26	1
auto[939524096:1073741823]	112	1			T51	1		T105	1		T135	1
auto[1073741824:1207959551]	116	1			T2	2		T116	1		T204	1
auto[1207959552:1342177279]	123	1			T50	1		T35	1		T67	1
auto[1342177280:1476395007]	109	1			T2	1		T12	1		T19	1
auto[1476395008:1610612735]	101	1			T60	2		T52	2		T44	2
auto[1610612736:1744830463]	94	1			T1	1		T2	2		T68	1
auto[1744830464:1879048191]	93	1			T19	1		T120	1		T134	1
auto[1879048192:2013265919]	117	1			T14	1		T68	1		T52	1
auto[2013265920:2147483647]	111	1			T56	2		T44	2		T63	1
auto[2147483648:2281701375]	105	1			T48	1		T68	1		T60	1
auto[2281701376:2415919103]	103	1			T2	1		T18	1		T120	2
auto[2415919104:2550136831]	106	1			T13	2		T60	1		T23	1
auto[2550136832:2684354559]	99	1			T2	1		T33	1		T60	1
auto[2684354560:2818572287]	123	1			T1	1		T35	1		T51	1
auto[2818572288:2952790015]	96	1			T35	1		T105	1		T52	1
auto[2952790016:3087007743]	102	1			T33	1		T116	1		T197	2
auto[3087007744:3221225471]	96	1			T26	1		T60	1		T135	1
auto[3221225472:3355443199]	101	1			T51	1		T120	1		T56	1
auto[3355443200:3489660927]	109	1			T14	1		T33	1		T52	1
auto[3489660928:3623878655]	108	1			T2	1		T13	1		T35	1
auto[3623878656:3758096383]	117	1			T13	1		T68	2		T67	1
auto[3758096384:3892314111]	102	1			T12	1		T51	2		T120	2
auto[3892314112:4026531839]	118	1			T2	1		T67	1		T56	1
auto[4026531840:4160749567]	108	1			T2	1		T12	1		T14	1
auto[4160749568:4294967295]	97	1			T12	1		T57	3		T44	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T33	1		T35	1		T4	2
auto[0:134217727]	auto[1]	53	1			T12	1		T63	1		T45	1
auto[134217728:268435455]	auto[0]	61	1			T1	1		T33	1		T51	1
auto[134217728:268435455]	auto[1]	61	1			T13	1		T48	1		T18	1
auto[268435456:402653183]	auto[0]	50	1			T195	1		T45	1		T258	1
auto[268435456:402653183]	auto[1]	54	1			T197	2		T67	1		T57	1
auto[402653184:536870911]	auto[0]	47	1			T35	1		T67	1		T60	1
auto[402653184:536870911]	auto[1]	64	1			T60	1		T57	1		T44	2
auto[536870912:671088639]	auto[0]	50	1			T48	1		T50	1		T105	1
auto[536870912:671088639]	auto[1]	65	1			T13	1		T44	2		T85	1
auto[671088640:805306367]	auto[0]	57	1			T33	1		T50	1		T44	1
auto[671088640:805306367]	auto[1]	72	1			T50	1		T23	1		T57	1
auto[805306368:939524095]	auto[0]	47	1			T33	1		T137	1		T373	1
auto[805306368:939524095]	auto[1]	46	1			T2	1		T26	1		T45	1
auto[939524096:1073741823]	auto[0]	53	1			T51	1		T105	1		T57	2
auto[939524096:1073741823]	auto[1]	59	1			T135	1		T44	2		T47	1
auto[1073741824:1207959551]	auto[0]	54	1			T2	2		T213	1		T139	1
auto[1073741824:1207959551]	auto[1]	62	1			T116	1		T204	1		T82	1
auto[1207959552:1342177279]	auto[0]	63	1			T35	1		T67	1		T26	1
auto[1207959552:1342177279]	auto[1]	60	1			T50	1		T120	1		T135	1
auto[1342177280:1476395007]	auto[0]	51	1			T2	1		T120	1		T45	1
auto[1342177280:1476395007]	auto[1]	58	1			T12	1		T19	1		T130	1
auto[1476395008:1610612735]	auto[0]	47	1			T60	2		T52	1		T20	1
auto[1476395008:1610612735]	auto[1]	54	1			T52	1		T44	2		T63	1
auto[1610612736:1744830463]	auto[0]	42	1			T2	1		T60	1		T57	1
auto[1610612736:1744830463]	auto[1]	52	1			T1	1		T2	1		T68	1
auto[1744830464:1879048191]	auto[0]	46	1			T45	2		T374	1		T92	1
auto[1744830464:1879048191]	auto[1]	47	1			T19	1		T120	1		T134	1
auto[1879048192:2013265919]	auto[0]	56	1			T14	1		T88	1		T47	1
auto[1879048192:2013265919]	auto[1]	61	1			T68	1		T52	1		T44	1
auto[2013265920:2147483647]	auto[0]	47	1			T44	1		T63	1		T45	2
auto[2013265920:2147483647]	auto[1]	64	1			T56	2		T44	1		T46	3
auto[2147483648:2281701375]	auto[0]	51	1			T48	1		T60	1		T57	1
auto[2147483648:2281701375]	auto[1]	54	1			T68	1		T57	1		T204	1
auto[2281701376:2415919103]	auto[0]	47	1			T18	1		T120	2		T57	1
auto[2281701376:2415919103]	auto[1]	56	1			T2	1		T44	1		T58	1
auto[2415919104:2550136831]	auto[0]	50	1			T13	1		T60	1		T23	1
auto[2415919104:2550136831]	auto[1]	56	1			T13	1		T57	1		T200	1
auto[2550136832:2684354559]	auto[0]	57	1			T33	1		T60	1		T66	1
auto[2550136832:2684354559]	auto[1]	42	1			T2	1		T105	1		T57	1
auto[2684354560:2818572287]	auto[0]	52	1			T1	1		T51	1		T195	1
auto[2684354560:2818572287]	auto[1]	71	1			T35	1		T136	1		T57	2
auto[2818572288:2952790015]	auto[0]	50	1			T35	1		T105	1		T64	1
auto[2818572288:2952790015]	auto[1]	46	1			T52	1		T83	1		T45	1
auto[2952790016:3087007743]	auto[0]	48	1			T33	1		T83	1		T127	1
auto[2952790016:3087007743]	auto[1]	54	1			T116	1		T197	2		T204	1
auto[3087007744:3221225471]	auto[0]	43	1			T63	1		T106	1		T257	1
auto[3087007744:3221225471]	auto[1]	53	1			T26	1		T60	1		T135	1
auto[3221225472:3355443199]	auto[0]	50	1			T51	1		T120	1		T56	1
auto[3221225472:3355443199]	auto[1]	51	1			T60	1		T44	1		T137	1
auto[3355443200:3489660927]	auto[0]	51	1			T33	1		T52	1		T44	1
auto[3355443200:3489660927]	auto[1]	58	1			T14	1		T44	3		T64	1
auto[3489660928:3623878655]	auto[0]	52	1			T35	1		T51	1		T60	1
auto[3489660928:3623878655]	auto[1]	56	1			T2	1		T13	1		T195	1
auto[3623878656:3758096383]	auto[0]	59	1			T13	1		T68	1		T67	1
auto[3623878656:3758096383]	auto[1]	58	1			T68	1		T136	1		T44	1
auto[3758096384:3892314111]	auto[0]	47	1			T12	1		T51	2		T120	2
auto[3758096384:3892314111]	auto[1]	55	1			T57	1		T44	1		T83	1
auto[3892314112:4026531839]	auto[0]	52	1			T67	1		T56	1		T45	2
auto[3892314112:4026531839]	auto[1]	66	1			T2	1		T23	1		T57	1
auto[4026531840:4160749567]	auto[0]	47	1			T12	1		T51	1		T60	1
auto[4026531840:4160749567]	auto[1]	61	1			T2	1		T14	1		T116	1
auto[4160749568:4294967295]	auto[0]	39	1			T12	1		T44	2		T137	1
auto[4160749568:4294967295]	auto[1]	58	1			T57	3		T44	1		T82	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T1

1

T2

2

T12

3

auto[1]

1838

1

T1

2

T2

9

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T12	2		T116	1		T50	1
auto[134217728:268435455]	104	1			T195	1		T60	1		T130	1
auto[268435456:402653183]	92	1			T197	1		T51	1		T63	1
auto[402653184:536870911]	109	1			T13	1		T116	1		T68	1
auto[536870912:671088639]	98	1			T2	1		T197	1		T26	1
auto[671088640:805306367]	102	1			T26	1		T51	1		T120	1
auto[805306368:939524095]	93	1			T2	1		T195	1		T105	1
auto[939524096:1073741823]	107	1			T2	1		T14	1		T33	2
auto[1073741824:1207959551]	93	1			T2	1		T33	1		T120	1
auto[1207959552:1342177279]	96	1			T51	1		T56	2		T52	1
auto[1342177280:1476395007]	89	1			T1	1		T18	1		T51	1
auto[1476395008:1610612735]	100	1			T2	1		T67	1		T134	1
auto[1610612736:1744830463]	86	1			T1	1		T2	1		T12	1
auto[1744830464:1879048191]	120	1			T13	1		T14	1		T33	1
auto[1879048192:2013265919]	115	1			T2	1		T13	1		T135	1
auto[2013265920:2147483647]	101	1			T68	1		T60	1		T105	1
auto[2147483648:2281701375]	116	1			T2	1		T14	1		T50	1
auto[2281701376:2415919103]	129	1			T116	1		T48	1		T68	1
auto[2415919104:2550136831]	119	1			T51	2		T60	1		T204	1
auto[2550136832:2684354559]	117	1			T1	1		T19	1		T50	1
auto[2684354560:2818572287]	129	1			T2	1		T13	2		T33	3
auto[2818572288:2952790015]	128	1			T56	1		T44	1		T137	1
auto[2952790016:3087007743]	118	1			T35	1		T204	1		T52	2
auto[3087007744:3221225471]	128	1			T12	1		T135	1		T57	2
auto[3221225472:3355443199]	106	1			T35	1		T26	1		T120	2
auto[3355443200:3489660927]	111	1			T2	1		T48	1		T57	3
auto[3489660928:3623878655]	100	1			T18	1		T35	1		T67	1
auto[3623878656:3758096383]	112	1			T12	1		T197	1		T56	2
auto[3758096384:3892314111]	111	1			T13	1		T67	1		T51	1
auto[3892314112:4026531839]	106	1			T50	1		T51	1		T60	3
auto[4026531840:4160749567]	119	1			T2	1		T120	2		T60	2
auto[4160749568:4294967295]	108	1			T19	1		T60	1		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T12	2		T68	1		T23	1
auto[0:134217727]	auto[1]	50	1			T116	1		T50	1		T44	1
auto[134217728:268435455]	auto[0]	49	1			T195	1		T60	1		T105	1
auto[134217728:268435455]	auto[1]	55	1			T130	1		T82	1		T58	1
auto[268435456:402653183]	auto[0]	34	1			T51	1		T63	1		T45	1
auto[268435456:402653183]	auto[1]	58	1			T197	1		T45	2		T138	1
auto[402653184:536870911]	auto[0]	44	1			T116	1		T68	1		T57	2
auto[402653184:536870911]	auto[1]	65	1			T13	1		T44	1		T137	2
auto[536870912:671088639]	auto[0]	50	1			T26	1		T105	1		T228	1
auto[536870912:671088639]	auto[1]	48	1			T2	1		T197	1		T105	1
auto[671088640:805306367]	auto[0]	52	1			T51	1		T120	1		T83	1
auto[671088640:805306367]	auto[1]	50	1			T26	1		T134	1		T45	1
auto[805306368:939524095]	auto[0]	35	1			T2	1		T137	1		T45	1
auto[805306368:939524095]	auto[1]	58	1			T195	1		T105	1		T57	1
auto[939524096:1073741823]	auto[0]	50	1			T33	2		T56	1		T45	2
auto[939524096:1073741823]	auto[1]	57	1			T2	1		T14	1		T35	1
auto[1073741824:1207959551]	auto[0]	48	1			T33	1		T57	1		T20	1
auto[1073741824:1207959551]	auto[1]	45	1			T2	1		T120	1		T57	2
auto[1207959552:1342177279]	auto[0]	51	1			T51	1		T56	1		T44	1
auto[1207959552:1342177279]	auto[1]	45	1			T56	1		T52	1		T44	2
auto[1342177280:1476395007]	auto[0]	42	1			T51	1		T60	1		T45	3
auto[1342177280:1476395007]	auto[1]	47	1			T1	1		T18	1		T57	1
auto[1476395008:1610612735]	auto[0]	49	1			T67	1		T134	1		T105	1
auto[1476395008:1610612735]	auto[1]	51	1			T2	1		T44	2		T45	1
auto[1610612736:1744830463]	auto[0]	35	1			T1	1		T57	1		T204	1
auto[1610612736:1744830463]	auto[1]	51	1			T2	1		T12	1		T134	1
auto[1744830464:1879048191]	auto[0]	49	1			T13	1		T33	1		T67	1
auto[1744830464:1879048191]	auto[1]	71	1			T14	1		T26	1		T51	1
auto[1879048192:2013265919]	auto[0]	52	1			T44	1		T45	2		T127	1
auto[1879048192:2013265919]	auto[1]	63	1			T2	1		T13	1		T135	1
auto[2013265920:2147483647]	auto[0]	54	1			T60	1		T105	1		T44	1
auto[2013265920:2147483647]	auto[1]	47	1			T68	1		T44	1		T265	1
auto[2147483648:2281701375]	auto[0]	46	1			T14	1		T50	1		T35	1
auto[2147483648:2281701375]	auto[1]	70	1			T2	1		T68	1		T197	1
auto[2281701376:2415919103]	auto[0]	64	1			T48	1		T35	1		T67	1
auto[2281701376:2415919103]	auto[1]	65	1			T116	1		T68	1		T57	1
auto[2415919104:2550136831]	auto[0]	55	1			T51	2		T60	1		T44	1
auto[2415919104:2550136831]	auto[1]	64	1			T204	1		T44	3		T20	1
auto[2550136832:2684354559]	auto[0]	51	1			T63	1		T83	1		T45	1
auto[2550136832:2684354559]	auto[1]	66	1			T1	1		T19	1		T50	1
auto[2684354560:2818572287]	auto[0]	63	1			T2	1		T13	1		T33	3
auto[2684354560:2818572287]	auto[1]	66	1			T13	1		T48	1		T60	1
auto[2818572288:2952790015]	auto[0]	58	1			T56	1		T137	1		T45	1
auto[2818572288:2952790015]	auto[1]	70	1			T44	1		T46	1		T89	1
auto[2952790016:3087007743]	auto[0]	58	1			T35	1		T52	1		T88	1
auto[2952790016:3087007743]	auto[1]	60	1			T204	1		T52	1		T44	2
auto[3087007744:3221225471]	auto[0]	66	1			T52	1		T44	1		T58	1
auto[3087007744:3221225471]	auto[1]	62	1			T12	1		T135	1		T57	2
auto[3221225472:3355443199]	auto[0]	52	1			T35	1		T120	2		T56	1
auto[3221225472:3355443199]	auto[1]	54	1			T26	1		T204	1		T44	1
auto[3355443200:3489660927]	auto[0]	54	1			T57	1		T45	1		T88	1
auto[3355443200:3489660927]	auto[1]	57	1			T2	1		T48	1		T57	2
auto[3489660928:3623878655]	auto[0]	42	1			T18	1		T35	1		T60	1
auto[3489660928:3623878655]	auto[1]	58	1			T67	1		T135	1		T57	1
auto[3623878656:3758096383]	auto[0]	54	1			T12	1		T23	1		T136	1
auto[3623878656:3758096383]	auto[1]	58	1			T197	1		T56	2		T60	1
auto[3758096384:3892314111]	auto[0]	60	1			T67	1		T51	1		T195	1
auto[3758096384:3892314111]	auto[1]	51	1			T13	1		T44	1		T64	1
auto[3892314112:4026531839]	auto[0]	49	1			T51	1		T60	1		T57	1
auto[3892314112:4026531839]	auto[1]	57	1			T50	1		T60	2		T57	1
auto[4026531840:4160749567]	auto[0]	52	1			T120	2		T60	1		T63	1
auto[4026531840:4160749567]	auto[1]	67	1			T2	1		T60	1		T136	1
auto[4160749568:4294967295]	auto[0]	56	1			T57	1		T20	1		T46	1
auto[4160749568:4294967295]	auto[1]	52	1			T19	1		T60	1		T66	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1630

1

T1

2

T2

3

T12

4

auto[1]

1824

1

T1

1

T2

8

T12

1