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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.15 98.37 100.00 99.02 98.41 91.17


Total test records in report: 1090
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T1007 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1440776141 May 26 02:38:14 PM PDT 24 May 26 02:38:16 PM PDT 24 10700122 ps
T1008 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1222918744 May 26 02:38:52 PM PDT 24 May 26 02:38:57 PM PDT 24 193291170 ps
T1009 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1723996722 May 26 02:38:49 PM PDT 24 May 26 02:38:52 PM PDT 24 61690202 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3456642675 May 26 02:38:36 PM PDT 24 May 26 02:38:42 PM PDT 24 290274499 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3525062616 May 26 02:38:46 PM PDT 24 May 26 02:38:54 PM PDT 24 336863166 ps
T1012 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.832270189 May 26 02:38:34 PM PDT 24 May 26 02:38:36 PM PDT 24 26628246 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.702851726 May 26 02:38:44 PM PDT 24 May 26 02:38:52 PM PDT 24 1149714711 ps
T171 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3262187461 May 26 02:38:42 PM PDT 24 May 26 02:38:47 PM PDT 24 413728241 ps
T1014 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3945576808 May 26 02:38:48 PM PDT 24 May 26 02:38:51 PM PDT 24 24329635 ps
T1015 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.669197285 May 26 02:38:49 PM PDT 24 May 26 02:38:51 PM PDT 24 11529571 ps
T1016 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.935479363 May 26 02:38:15 PM PDT 24 May 26 02:38:18 PM PDT 24 48486614 ps
T1017 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3300969221 May 26 02:38:49 PM PDT 24 May 26 02:38:51 PM PDT 24 36076936 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1395939673 May 26 02:38:42 PM PDT 24 May 26 02:38:45 PM PDT 24 91883962 ps
T1019 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2652648223 May 26 02:38:06 PM PDT 24 May 26 02:38:09 PM PDT 24 37222209 ps
T1020 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3188851116 May 26 02:38:07 PM PDT 24 May 26 02:38:09 PM PDT 24 21879391 ps
T1021 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1492013492 May 26 02:38:57 PM PDT 24 May 26 02:38:59 PM PDT 24 15920510 ps
T1022 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1622420822 May 26 02:38:50 PM PDT 24 May 26 02:38:54 PM PDT 24 253538739 ps
T1023 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2792827611 May 26 02:38:44 PM PDT 24 May 26 02:38:47 PM PDT 24 21287387 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3756969356 May 26 02:38:43 PM PDT 24 May 26 02:38:46 PM PDT 24 90571851 ps
T1025 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1592181210 May 26 02:38:42 PM PDT 24 May 26 02:38:44 PM PDT 24 24918775 ps
T174 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.224705437 May 26 02:38:23 PM PDT 24 May 26 02:38:30 PM PDT 24 154451946 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1240158713 May 26 02:38:17 PM PDT 24 May 26 02:38:18 PM PDT 24 14061098 ps
T1027 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3174790252 May 26 02:38:42 PM PDT 24 May 26 02:38:44 PM PDT 24 21056967 ps
T1028 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1454037842 May 26 02:38:28 PM PDT 24 May 26 02:38:33 PM PDT 24 200725791 ps
T1029 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2802664804 May 26 02:38:15 PM PDT 24 May 26 02:38:19 PM PDT 24 75305142 ps
T1030 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.131039047 May 26 02:38:46 PM PDT 24 May 26 02:38:49 PM PDT 24 26223844 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1107117739 May 26 02:38:43 PM PDT 24 May 26 02:38:46 PM PDT 24 114519234 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2415082891 May 26 02:38:37 PM PDT 24 May 26 02:38:45 PM PDT 24 240709715 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1400645936 May 26 02:38:41 PM PDT 24 May 26 02:38:43 PM PDT 24 16835574 ps
T172 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1764757767 May 26 02:38:48 PM PDT 24 May 26 02:39:01 PM PDT 24 750954709 ps
T1034 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3253410339 May 26 02:38:33 PM PDT 24 May 26 02:38:35 PM PDT 24 64069125 ps
T1035 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2975970487 May 26 02:38:44 PM PDT 24 May 26 02:38:46 PM PDT 24 30375677 ps
T1036 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3633340846 May 26 02:38:06 PM PDT 24 May 26 02:38:08 PM PDT 24 50674600 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1000534560 May 26 02:38:47 PM PDT 24 May 26 02:38:49 PM PDT 24 26168793 ps
T1038 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3147172014 May 26 02:39:00 PM PDT 24 May 26 02:39:02 PM PDT 24 14192568 ps
T1039 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1277434380 May 26 02:38:22 PM PDT 24 May 26 02:38:26 PM PDT 24 673682464 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4086765056 May 26 02:38:45 PM PDT 24 May 26 02:38:49 PM PDT 24 130004714 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2299878105 May 26 02:38:11 PM PDT 24 May 26 02:38:15 PM PDT 24 90050067 ps
T1042 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2745806010 May 26 02:39:00 PM PDT 24 May 26 02:39:01 PM PDT 24 13062555 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.519757580 May 26 02:38:06 PM PDT 24 May 26 02:38:14 PM PDT 24 383313742 ps
T1044 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1576579410 May 26 02:38:44 PM PDT 24 May 26 02:38:49 PM PDT 24 694207283 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.79789149 May 26 02:38:21 PM PDT 24 May 26 02:38:24 PM PDT 24 62489347 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1479902437 May 26 02:38:42 PM PDT 24 May 26 02:38:47 PM PDT 24 181703572 ps
T1047 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3943689003 May 26 02:38:45 PM PDT 24 May 26 02:38:47 PM PDT 24 13537511 ps
T1048 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.979222879 May 26 02:38:45 PM PDT 24 May 26 02:38:50 PM PDT 24 88488993 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3790307261 May 26 02:38:35 PM PDT 24 May 26 02:38:37 PM PDT 24 21699247 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.869659150 May 26 02:38:23 PM PDT 24 May 26 02:38:31 PM PDT 24 254808514 ps
T170 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4028687422 May 26 02:38:42 PM PDT 24 May 26 02:38:48 PM PDT 24 100513050 ps
T1051 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3077596403 May 26 02:38:47 PM PDT 24 May 26 02:38:51 PM PDT 24 439545565 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3624117915 May 26 02:38:46 PM PDT 24 May 26 02:38:50 PM PDT 24 263466902 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.277648097 May 26 02:38:14 PM PDT 24 May 26 02:38:29 PM PDT 24 371990880 ps
T1054 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3887768471 May 26 02:38:23 PM PDT 24 May 26 02:38:29 PM PDT 24 414119780 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3380565815 May 26 02:38:35 PM PDT 24 May 26 02:38:38 PM PDT 24 115486397 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1853245433 May 26 02:38:43 PM PDT 24 May 26 02:38:46 PM PDT 24 108411360 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.373175440 May 26 02:38:17 PM PDT 24 May 26 02:38:18 PM PDT 24 14398317 ps
T1058 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1764895625 May 26 02:38:36 PM PDT 24 May 26 02:38:48 PM PDT 24 976724861 ps
T1059 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.413104338 May 26 02:38:43 PM PDT 24 May 26 02:38:51 PM PDT 24 667529201 ps
T1060 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1084287380 May 26 02:38:46 PM PDT 24 May 26 02:38:52 PM PDT 24 1260496240 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3808356668 May 26 02:38:15 PM PDT 24 May 26 02:38:17 PM PDT 24 202591992 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1440037705 May 26 02:38:26 PM PDT 24 May 26 02:38:41 PM PDT 24 1574302477 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1786206698 May 26 02:38:23 PM PDT 24 May 26 02:38:29 PM PDT 24 122187948 ps
T1064 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3482279884 May 26 02:38:36 PM PDT 24 May 26 02:38:40 PM PDT 24 105059002 ps
T1065 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2282403779 May 26 02:38:50 PM PDT 24 May 26 02:38:53 PM PDT 24 10771092 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2144770404 May 26 02:38:23 PM PDT 24 May 26 02:38:27 PM PDT 24 31165552 ps
T159 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2475228276 May 26 02:38:36 PM PDT 24 May 26 02:38:49 PM PDT 24 1163791995 ps
T1067 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.434547669 May 26 02:38:54 PM PDT 24 May 26 02:38:56 PM PDT 24 21185350 ps
T1068 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2362118658 May 26 02:38:30 PM PDT 24 May 26 02:38:32 PM PDT 24 32378880 ps
T1069 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1972296740 May 26 02:38:47 PM PDT 24 May 26 02:38:50 PM PDT 24 32973992 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1711849344 May 26 02:38:36 PM PDT 24 May 26 02:38:41 PM PDT 24 834275354 ps
T1071 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3499221255 May 26 02:38:41 PM PDT 24 May 26 02:38:44 PM PDT 24 168213247 ps
T1072 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3656240849 May 26 02:38:22 PM PDT 24 May 26 02:38:28 PM PDT 24 781886796 ps
T1073 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1541741347 May 26 02:38:47 PM PDT 24 May 26 02:38:49 PM PDT 24 385021536 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1596089482 May 26 02:38:47 PM PDT 24 May 26 02:38:53 PM PDT 24 210096984 ps
T1075 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1821482827 May 26 02:38:34 PM PDT 24 May 26 02:38:38 PM PDT 24 145902677 ps
T1076 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2952676783 May 26 02:38:48 PM PDT 24 May 26 02:38:50 PM PDT 24 10251641 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3459156179 May 26 02:38:22 PM PDT 24 May 26 02:38:26 PM PDT 24 79117535 ps
T1078 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3928206392 May 26 02:38:54 PM PDT 24 May 26 02:38:56 PM PDT 24 21703974 ps
T1079 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1554378250 May 26 02:38:27 PM PDT 24 May 26 02:38:31 PM PDT 24 653735511 ps
T1080 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1795006784 May 26 02:38:44 PM PDT 24 May 26 02:38:55 PM PDT 24 209457163 ps
T1081 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3419325289 May 26 02:38:24 PM PDT 24 May 26 02:38:28 PM PDT 24 295872349 ps
T1082 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2195841161 May 26 02:38:50 PM PDT 24 May 26 02:38:58 PM PDT 24 338487951 ps
T1083 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3896494172 May 26 02:38:45 PM PDT 24 May 26 02:38:49 PM PDT 24 147282893 ps
T1084 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3534158046 May 26 02:38:50 PM PDT 24 May 26 02:38:52 PM PDT 24 11939011 ps
T169 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.120338585 May 26 02:38:33 PM PDT 24 May 26 02:38:39 PM PDT 24 179863118 ps
T1085 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1678391363 May 26 02:38:44 PM PDT 24 May 26 02:38:47 PM PDT 24 290153002 ps
T1086 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4154311989 May 26 02:38:51 PM PDT 24 May 26 02:38:53 PM PDT 24 40876238 ps
T1087 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1446064440 May 26 02:38:52 PM PDT 24 May 26 02:38:55 PM PDT 24 35737383 ps
T1088 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.913793135 May 26 02:38:43 PM PDT 24 May 26 02:38:45 PM PDT 24 10341011 ps
T1089 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1764864364 May 26 02:38:53 PM PDT 24 May 26 02:38:56 PM PDT 24 88022723 ps
T1090 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3241638283 May 26 02:38:53 PM PDT 24 May 26 02:38:57 PM PDT 24 144174920 ps

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2257728835
Short name T2
Test name
Test status
Simulation time 1257503712 ps
CPU time 17.45 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:22 PM PDT 24
Peak memory 219708 kb
Host smart-6fe6a5d7-2e3e-4d43-bdcc-f3d503395c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257728835 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2257728835
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2208943287
Short name T45
Test name
Test status
Simulation time 6225031807 ps
CPU time 77.33 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:51:48 PM PDT 24
Peak memory 222620 kb
Host smart-7ec32223-60e8-42d0-9559-3febb6cec8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208943287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2208943287
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1035694824
Short name T51
Test name
Test status
Simulation time 50284411 ps
CPU time 2.85 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:36 PM PDT 24
Peak memory 215560 kb
Host smart-43f1f0ca-34b4-4799-83eb-6d698b93e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035694824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1035694824
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1040039645
Short name T44
Test name
Test status
Simulation time 3503058834 ps
CPU time 35.87 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 222624 kb
Host smart-1eeb25e3-f151-4f1d-b595-0a3428351def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040039645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1040039645
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3504022058
Short name T42
Test name
Test status
Simulation time 1595478164 ps
CPU time 19.04 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:28 PM PDT 24
Peak memory 231500 kb
Host smart-dfbfd0f5-e12f-4b75-a639-f4307b702dcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504022058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3504022058
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1841313140
Short name T60
Test name
Test status
Simulation time 4318057885 ps
CPU time 26.05 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 221972 kb
Host smart-123f806b-d2e0-4c58-945e-7f6172a29dfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841313140 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1841313140
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1961325622
Short name T127
Test name
Test status
Simulation time 592028800 ps
CPU time 11.97 seconds
Started May 26 02:50:02 PM PDT 24
Finished May 26 02:50:15 PM PDT 24
Peak memory 222696 kb
Host smart-125873f3-19f5-4ee5-8479-9d6124a142f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961325622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1961325622
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3230740590
Short name T4
Test name
Test status
Simulation time 1304983246 ps
CPU time 35.69 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:49 PM PDT 24
Peak memory 216344 kb
Host smart-6e248144-8141-45d5-8783-1202138017e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230740590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3230740590
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.354430032
Short name T138
Test name
Test status
Simulation time 8152547435 ps
CPU time 243.48 seconds
Started May 26 02:50:27 PM PDT 24
Finished May 26 02:54:32 PM PDT 24
Peak memory 222636 kb
Host smart-faef989a-d43d-4fb3-bc0c-5eb6598c2f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354430032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.354430032
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2234478446
Short name T117
Test name
Test status
Simulation time 1059705135 ps
CPU time 6.52 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 214404 kb
Host smart-cf5a49dc-4de2-4630-a20b-fa1662d66309
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234478446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2234478446
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2231695326
Short name T149
Test name
Test status
Simulation time 893143165 ps
CPU time 41.57 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 214408 kb
Host smart-fbe5b1a6-be08-4296-8239-d78269fb152d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231695326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2231695326
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.158252219
Short name T3
Test name
Test status
Simulation time 841809460 ps
CPU time 10.06 seconds
Started May 26 02:49:48 PM PDT 24
Finished May 26 02:49:59 PM PDT 24
Peak memory 210080 kb
Host smart-8cb378ff-46be-4e43-8a37-636c929b1df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158252219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.158252219
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.78105651
Short name T7
Test name
Test status
Simulation time 80303918 ps
CPU time 3.57 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 218944 kb
Host smart-f4a38a2f-227e-4ab0-88a9-f90529d5c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78105651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.78105651
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3146461819
Short name T310
Test name
Test status
Simulation time 824006247 ps
CPU time 11.51 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:32 PM PDT 24
Peak memory 214420 kb
Host smart-a15bf5d4-ddaf-4742-9731-a459472b09dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146461819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3146461819
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3721201029
Short name T266
Test name
Test status
Simulation time 1616121353 ps
CPU time 39.15 seconds
Started May 26 02:49:06 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 215796 kb
Host smart-eb64e408-6dfd-4056-ba75-885780923523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721201029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3721201029
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3675818509
Short name T177
Test name
Test status
Simulation time 315613855 ps
CPU time 2.18 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:21 PM PDT 24
Peak memory 216708 kb
Host smart-3a2b1a60-d3b8-486b-aad7-69c7a401c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675818509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3675818509
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1658488231
Short name T24
Test name
Test status
Simulation time 177514427 ps
CPU time 4.43 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:13 PM PDT 24
Peak memory 214384 kb
Host smart-21865e8d-a445-4b97-9bf1-f98e7a880484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658488231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1658488231
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1556817541
Short name T46
Test name
Test status
Simulation time 4582744890 ps
CPU time 20.63 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 221040 kb
Host smart-19b10a92-ac5b-491c-976f-ad4a30866b1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556817541 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1556817541
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2866173809
Short name T380
Test name
Test status
Simulation time 1107519267 ps
CPU time 15.59 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 214364 kb
Host smart-42e3e58a-6509-462a-9a03-9649bb77b8f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866173809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2866173809
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3612070558
Short name T335
Test name
Test status
Simulation time 8800938297 ps
CPU time 53.35 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:51:34 PM PDT 24
Peak memory 215524 kb
Host smart-f985e2db-8cb2-47cf-93b0-b5a32f145377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612070558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3612070558
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3052829784
Short name T141
Test name
Test status
Simulation time 1801366903 ps
CPU time 31.03 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 216288 kb
Host smart-afee7e21-18b7-4b92-85e8-902b3535d7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052829784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3052829784
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3067781713
Short name T151
Test name
Test status
Simulation time 973716229 ps
CPU time 4 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 218340 kb
Host smart-54dd037f-fecd-42d0-95bc-3f6ed67f01d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067781713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3067781713
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.809590450
Short name T37
Test name
Test status
Simulation time 41383929 ps
CPU time 1.59 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 209784 kb
Host smart-93e30193-35aa-4ec0-b859-836eab4980a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809590450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.809590450
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1773082488
Short name T341
Test name
Test status
Simulation time 123784901 ps
CPU time 6.97 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 215284 kb
Host smart-48f9928c-f3b1-4994-b3e3-671b9e839d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773082488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1773082488
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1970699986
Short name T29
Test name
Test status
Simulation time 314721222 ps
CPU time 5.19 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 218920 kb
Host smart-198c8f8e-b120-4da4-8ab5-242006ac3d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970699986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1970699986
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4165106011
Short name T53
Test name
Test status
Simulation time 4091611155 ps
CPU time 37.01 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 221856 kb
Host smart-badf5e0d-da6d-4c8e-9086-b01979f10d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165106011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4165106011
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2998798423
Short name T57
Test name
Test status
Simulation time 535447616 ps
CPU time 22.52 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:50:14 PM PDT 24
Peak memory 216700 kb
Host smart-0ce9c27c-9366-4c32-8070-1015f6397037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998798423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2998798423
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2344950858
Short name T121
Test name
Test status
Simulation time 586267654 ps
CPU time 3.83 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 214416 kb
Host smart-1a9c3df0-bbae-4a33-a450-8392e6efdc16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344950858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2344950858
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.787370379
Short name T262
Test name
Test status
Simulation time 912220462 ps
CPU time 9.69 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 215852 kb
Host smart-8727e5f6-e2ef-4697-b9ce-cd9da42dd635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787370379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.787370379
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1086603474
Short name T160
Test name
Test status
Simulation time 853542733 ps
CPU time 6.1 seconds
Started May 26 02:38:16 PM PDT 24
Finished May 26 02:38:23 PM PDT 24
Peak memory 205860 kb
Host smart-e0883d34-aaeb-46b4-9ef8-e9c28df51169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086603474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1086603474
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1107050063
Short name T375
Test name
Test status
Simulation time 2311934244 ps
CPU time 26.57 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:51:22 PM PDT 24
Peak memory 215512 kb
Host smart-c9f77b9d-be07-4d91-a245-d897e7e69dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107050063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1107050063
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.205236088
Short name T120
Test name
Test status
Simulation time 7431084519 ps
CPU time 74.03 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 218984 kb
Host smart-0daad963-24c8-4310-b665-a227e5207610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205236088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.205236088
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2992048399
Short name T102
Test name
Test status
Simulation time 53164787 ps
CPU time 0.96 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 206160 kb
Host smart-19f29c4e-0018-48d2-a820-0a9a250e0f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992048399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2992048399
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.808886917
Short name T97
Test name
Test status
Simulation time 203899915 ps
CPU time 5.52 seconds
Started May 26 02:50:27 PM PDT 24
Finished May 26 02:50:34 PM PDT 24
Peak memory 214368 kb
Host smart-ad0f3da1-52fa-49cb-b7fe-401d63b27600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808886917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.808886917
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.158826076
Short name T69
Test name
Test status
Simulation time 44626258 ps
CPU time 3.1 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 221708 kb
Host smart-3cbc61c3-76c6-4aed-8d10-7193ab859374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158826076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.158826076
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1783999008
Short name T6
Test name
Test status
Simulation time 3239324555 ps
CPU time 44.45 seconds
Started May 26 02:49:52 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 222552 kb
Host smart-c34332fc-0b10-42ea-a321-e03fd300abb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783999008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1783999008
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3179725922
Short name T150
Test name
Test status
Simulation time 214018889 ps
CPU time 4.09 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 222756 kb
Host smart-53d28f14-794b-44fd-8355-c4fc53fabb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179725922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3179725922
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4228752132
Short name T33
Test name
Test status
Simulation time 126259316 ps
CPU time 2.27 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 214468 kb
Host smart-58004302-d8f7-4318-8d69-f875a79006c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228752132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4228752132
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4224459585
Short name T217
Test name
Test status
Simulation time 4809855625 ps
CPU time 48.83 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:50:25 PM PDT 24
Peak memory 215660 kb
Host smart-8ec03eb1-d4e6-4a3d-8a46-3719ddb1a36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224459585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4224459585
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3993513996
Short name T137
Test name
Test status
Simulation time 57617327 ps
CPU time 4.37 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 214456 kb
Host smart-63fdbfce-f37d-4b20-97ed-f5670479550f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993513996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3993513996
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4000784493
Short name T168
Test name
Test status
Simulation time 307164081 ps
CPU time 5.03 seconds
Started May 26 02:38:08 PM PDT 24
Finished May 26 02:38:14 PM PDT 24
Peak memory 213984 kb
Host smart-41989852-1a41-4820-bec6-820d2573b508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000784493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4000784493
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1633336537
Short name T164
Test name
Test status
Simulation time 4824309961 ps
CPU time 7.69 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 215956 kb
Host smart-5b68089e-f116-4721-9301-02d54c158eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633336537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1633336537
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2512304234
Short name T89
Test name
Test status
Simulation time 249987021 ps
CPU time 4.57 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 222508 kb
Host smart-934bbc8b-dd47-433d-aeea-a6e313a9c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512304234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2512304234
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.896250715
Short name T272
Test name
Test status
Simulation time 357789642 ps
CPU time 2.91 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 220544 kb
Host smart-bc171fc5-c780-482b-baf8-125c4dd63f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896250715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.896250715
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1915819448
Short name T227
Test name
Test status
Simulation time 87945227 ps
CPU time 2.04 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 214352 kb
Host smart-096a0fea-2a4e-44fe-b5df-3fdd17ab6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915819448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1915819448
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1232790425
Short name T242
Test name
Test status
Simulation time 1118356129 ps
CPU time 61.39 seconds
Started May 26 02:48:56 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 215828 kb
Host smart-4e08399f-983b-4562-be2b-83ba829c6875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232790425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1232790425
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2475228276
Short name T159
Test name
Test status
Simulation time 1163791995 ps
CPU time 10.41 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 214128 kb
Host smart-b115f788-9a9d-4fe1-956c-d53c7af64369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475228276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2475228276
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.290099650
Short name T153
Test name
Test status
Simulation time 96172040 ps
CPU time 4.62 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:22 PM PDT 24
Peak memory 218372 kb
Host smart-277019cb-0eed-4203-983a-0692aa937b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290099650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.290099650
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2034806884
Short name T61
Test name
Test status
Simulation time 44647999 ps
CPU time 2.35 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 209972 kb
Host smart-55986389-878b-4013-913a-58b393b88d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034806884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2034806884
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4218365989
Short name T270
Test name
Test status
Simulation time 89260726 ps
CPU time 2.07 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 214396 kb
Host smart-e6103471-c9ff-445b-839e-3e0e63f6385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218365989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4218365989
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2589761609
Short name T180
Test name
Test status
Simulation time 2288244546 ps
CPU time 22.61 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 222728 kb
Host smart-d9aecdb0-550c-4342-88ec-70ca0878fbad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589761609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2589761609
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2595553450
Short name T20
Test name
Test status
Simulation time 350181108 ps
CPU time 5.34 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:33 PM PDT 24
Peak memory 222872 kb
Host smart-2d11534e-bdea-45c1-ac12-2a63b083495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595553450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2595553450
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2260548872
Short name T162
Test name
Test status
Simulation time 177176489 ps
CPU time 4.73 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 214048 kb
Host smart-f48b6fdb-6ce6-47f0-87ca-d76fb9150e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260548872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2260548872
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2098903407
Short name T345
Test name
Test status
Simulation time 504709232 ps
CPU time 2.78 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 214304 kb
Host smart-0a8e133d-e9fc-4cbc-a615-5786c32706ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098903407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2098903407
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3252646511
Short name T240
Test name
Test status
Simulation time 26954300026 ps
CPU time 123.72 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:50:41 PM PDT 24
Peak memory 218028 kb
Host smart-b05702ec-198a-4700-82a8-a13288328dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252646511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3252646511
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1736513966
Short name T371
Test name
Test status
Simulation time 252871264 ps
CPU time 12.93 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 214380 kb
Host smart-6d75ffa7-15d9-44d9-b169-fee6c9036779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736513966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1736513966
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2096421909
Short name T228
Test name
Test status
Simulation time 53475995 ps
CPU time 2.85 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 214288 kb
Host smart-559bf577-9f65-4b73-b2a3-0ed65fce94a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096421909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2096421909
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3986972893
Short name T101
Test name
Test status
Simulation time 437608647 ps
CPU time 3.75 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 214452 kb
Host smart-f24638ea-bd2c-49e5-a3c5-58cf72dddfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986972893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3986972893
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1464170911
Short name T78
Test name
Test status
Simulation time 1146599142 ps
CPU time 42.14 seconds
Started May 26 02:51:13 PM PDT 24
Finished May 26 02:51:57 PM PDT 24
Peak memory 215000 kb
Host smart-9ae2cd78-2f16-41a0-9b64-867e7821dd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464170911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1464170911
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2953728484
Short name T99
Test name
Test status
Simulation time 223633709 ps
CPU time 5.67 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 214320 kb
Host smart-3a9c2a6d-8e27-4d80-8050-3255a210410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953728484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2953728484
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2253422547
Short name T93
Test name
Test status
Simulation time 231086063 ps
CPU time 5.36 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 220728 kb
Host smart-286ddfc4-388e-4cc7-bbe8-027bbe0b019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253422547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2253422547
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.415951312
Short name T152
Test name
Test status
Simulation time 646360119 ps
CPU time 4.47 seconds
Started May 26 02:48:37 PM PDT 24
Finished May 26 02:48:42 PM PDT 24
Peak memory 217744 kb
Host smart-2887637a-8f9a-438e-875e-48f7f896ced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415951312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.415951312
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2549442259
Short name T154
Test name
Test status
Simulation time 366584390 ps
CPU time 3.62 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 222716 kb
Host smart-e554ecf0-748d-44ce-8053-b818fe14e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549442259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2549442259
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3722324985
Short name T221
Test name
Test status
Simulation time 2056419212 ps
CPU time 21.56 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 220768 kb
Host smart-77a20c5d-7aa4-4d1d-8126-23339fb91c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722324985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3722324985
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3552818726
Short name T87
Test name
Test status
Simulation time 56754045 ps
CPU time 2.51 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 214380 kb
Host smart-7e5a3bc1-5a6d-4c25-ab29-a6d7034ae09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552818726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3552818726
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.4233279520
Short name T295
Test name
Test status
Simulation time 381464949 ps
CPU time 21.46 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:15 PM PDT 24
Peak memory 215616 kb
Host smart-78f24943-482b-46ff-a37a-dcc04b8f8590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233279520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4233279520
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1960861131
Short name T248
Test name
Test status
Simulation time 868206109 ps
CPU time 47.72 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:53 PM PDT 24
Peak memory 215564 kb
Host smart-6571b255-4a2b-4c33-966d-1e88ba54046b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960861131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1960861131
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3215680968
Short name T190
Test name
Test status
Simulation time 5994188538 ps
CPU time 36.2 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:49:28 PM PDT 24
Peak memory 222608 kb
Host smart-ba4059c5-37b5-4ff3-bc49-8456fd12f7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215680968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3215680968
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.120338585
Short name T169
Test name
Test status
Simulation time 179863118 ps
CPU time 4.99 seconds
Started May 26 02:38:33 PM PDT 24
Finished May 26 02:38:39 PM PDT 24
Peak memory 205852 kb
Host smart-a3b89add-3bbb-425f-8869-1e2bfa9f8597
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120338585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
120338585
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3789687257
Short name T157
Test name
Test status
Simulation time 178726765 ps
CPU time 1.68 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 210016 kb
Host smart-253d2357-ca01-4d87-bfb8-1eaadf557479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789687257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3789687257
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3533784499
Short name T155
Test name
Test status
Simulation time 187271464 ps
CPU time 3.45 seconds
Started May 26 02:49:00 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 222776 kb
Host smart-a54f4ec4-b6af-43cb-805c-1ccb6bd2aedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533784499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3533784499
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.585096680
Short name T411
Test name
Test status
Simulation time 383507135 ps
CPU time 3.64 seconds
Started May 26 02:48:29 PM PDT 24
Finished May 26 02:48:33 PM PDT 24
Peak memory 206836 kb
Host smart-c268355f-540a-4be0-b4b4-bc811831cb63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585096680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.585096680
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4009878073
Short name T232
Test name
Test status
Simulation time 1381678602 ps
CPU time 27.13 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 209580 kb
Host smart-8a0a9d58-6943-49d3-b52b-48cc4a2571ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009878073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4009878073
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2677573098
Short name T47
Test name
Test status
Simulation time 423044083 ps
CPU time 9.27 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:19 PM PDT 24
Peak memory 219664 kb
Host smart-8578da55-78d9-4e3f-8b6b-09c75f81203a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677573098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2677573098
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3519177122
Short name T306
Test name
Test status
Simulation time 128996144 ps
CPU time 5.17 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 214428 kb
Host smart-dee97d75-930a-4f73-b2a4-c41f1585eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519177122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3519177122
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1665885320
Short name T73
Test name
Test status
Simulation time 2881584546 ps
CPU time 11.17 seconds
Started May 26 02:49:17 PM PDT 24
Finished May 26 02:49:29 PM PDT 24
Peak memory 210572 kb
Host smart-11b263db-669d-416b-b49a-d1cb64394615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665885320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1665885320
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.439968317
Short name T194
Test name
Test status
Simulation time 705279073 ps
CPU time 8.67 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 222656 kb
Host smart-b2b426e5-d587-4c9b-93f0-f382128bf6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439968317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.439968317
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2697871776
Short name T268
Test name
Test status
Simulation time 15665493884 ps
CPU time 58.65 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:50:36 PM PDT 24
Peak memory 214332 kb
Host smart-90774c60-0f90-408c-91d3-6f2906d25ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697871776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2697871776
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4226451629
Short name T72
Test name
Test status
Simulation time 120456761 ps
CPU time 2.77 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 210892 kb
Host smart-f5134747-6a29-4a56-ac51-e783f9e5fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226451629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4226451629
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3420775475
Short name T305
Test name
Test status
Simulation time 66815602 ps
CPU time 2.37 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 214324 kb
Host smart-ab7af476-7938-4375-96f8-6be0bc414c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420775475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3420775475
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2104783938
Short name T255
Test name
Test status
Simulation time 2984940393 ps
CPU time 53.52 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:50:38 PM PDT 24
Peak memory 222600 kb
Host smart-a20b289c-3969-4cec-b640-6ef2c64ebac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104783938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2104783938
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3223454794
Short name T126
Test name
Test status
Simulation time 227451482 ps
CPU time 8.9 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 222696 kb
Host smart-c2380528-a722-447f-b859-83a84f89fe2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223454794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3223454794
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.681154325
Short name T181
Test name
Test status
Simulation time 990358290 ps
CPU time 20.23 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 220340 kb
Host smart-12b065f1-0614-402b-b45d-8815779da5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681154325 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.681154325
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1921200948
Short name T294
Test name
Test status
Simulation time 346908204 ps
CPU time 4.16 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 220220 kb
Host smart-4fca1a64-742a-4e95-baf6-131bad95de2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921200948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1921200948
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1132824418
Short name T222
Test name
Test status
Simulation time 1490590534 ps
CPU time 20.47 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:34 PM PDT 24
Peak memory 222524 kb
Host smart-81cccfb5-103c-4473-9ddc-51bce04db811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132824418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1132824418
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1306348469
Short name T86
Test name
Test status
Simulation time 572211821 ps
CPU time 3.56 seconds
Started May 26 02:51:17 PM PDT 24
Finished May 26 02:51:24 PM PDT 24
Peak memory 214336 kb
Host smart-90410dfb-b556-4634-b22d-5d37dba67a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306348469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1306348469
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1921342
Short name T281
Test name
Test status
Simulation time 234399241 ps
CPU time 11.14 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:49:02 PM PDT 24
Peak memory 214392 kb
Host smart-0a116fbd-a083-428e-8fea-fda67bcd877f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1921342
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.519757580
Short name T1043
Test name
Test status
Simulation time 383313742 ps
CPU time 7.21 seconds
Started May 26 02:38:06 PM PDT 24
Finished May 26 02:38:14 PM PDT 24
Peak memory 205752 kb
Host smart-7b841384-38ba-4551-9458-5a41368df8ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519757580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.519757580
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1711293198
Short name T924
Test name
Test status
Simulation time 137188416 ps
CPU time 6.08 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:13 PM PDT 24
Peak memory 205900 kb
Host smart-d125562c-0ae9-451a-8285-fd7d0a01c8c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711293198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
711293198
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3633340846
Short name T1036
Test name
Test status
Simulation time 50674600 ps
CPU time 1 seconds
Started May 26 02:38:06 PM PDT 24
Finished May 26 02:38:08 PM PDT 24
Peak memory 205832 kb
Host smart-fd5c2673-090b-42ff-88e6-3a78f3ec9ccd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633340846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
633340846
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3188851116
Short name T1020
Test name
Test status
Simulation time 21879391 ps
CPU time 1.6 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:09 PM PDT 24
Peak memory 214064 kb
Host smart-1b65229f-789a-4366-92d5-b1180f900a69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188851116 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3188851116
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3740944937
Short name T146
Test name
Test status
Simulation time 10411277 ps
CPU time 1.05 seconds
Started May 26 02:38:11 PM PDT 24
Finished May 26 02:38:14 PM PDT 24
Peak memory 205996 kb
Host smart-dcd338bd-85c9-4f9c-a04f-4e81608ab269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740944937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3740944937
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.871467094
Short name T1003
Test name
Test status
Simulation time 53730950 ps
CPU time 0.85 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:09 PM PDT 24
Peak memory 205584 kb
Host smart-1d50916f-1e3f-4ff1-b469-ea9d34dd34a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871467094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.871467094
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1122160160
Short name T953
Test name
Test status
Simulation time 76391534 ps
CPU time 1.98 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:10 PM PDT 24
Peak memory 205768 kb
Host smart-cafe5bdd-4450-47ff-b246-a70753a9ccfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122160160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1122160160
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2299878105
Short name T1041
Test name
Test status
Simulation time 90050067 ps
CPU time 1.78 seconds
Started May 26 02:38:11 PM PDT 24
Finished May 26 02:38:15 PM PDT 24
Peak memory 214364 kb
Host smart-b2221f15-0490-40fd-964d-d1e8fd57a98d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299878105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2299878105
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3464683630
Short name T967
Test name
Test status
Simulation time 343738092 ps
CPU time 8.49 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 214404 kb
Host smart-c7e03a14-fb2e-4fd7-bd28-451d8fb27ec0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464683630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3464683630
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.431393290
Short name T973
Test name
Test status
Simulation time 465441508 ps
CPU time 4.14 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:12 PM PDT 24
Peak memory 216816 kb
Host smart-4d74c685-c063-4676-82d4-96647bba334c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431393290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.431393290
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3308961043
Short name T161
Test name
Test status
Simulation time 998377001 ps
CPU time 8.81 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:17 PM PDT 24
Peak memory 214004 kb
Host smart-c2732de0-5a4c-4c2f-9bc8-f54846ff8f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308961043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3308961043
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2802664804
Short name T1029
Test name
Test status
Simulation time 75305142 ps
CPU time 3.64 seconds
Started May 26 02:38:15 PM PDT 24
Finished May 26 02:38:19 PM PDT 24
Peak memory 205912 kb
Host smart-2d824ace-b8a9-41d3-9abc-04aa0a3790cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802664804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
802664804
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1549100836
Short name T985
Test name
Test status
Simulation time 1273271200 ps
CPU time 15.54 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:31 PM PDT 24
Peak memory 205804 kb
Host smart-cf4fdefc-d7da-408f-a406-14b3fec6a25d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549100836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
549100836
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3247449295
Short name T936
Test name
Test status
Simulation time 100847502 ps
CPU time 1.04 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 205848 kb
Host smart-203f3350-a3ae-4664-86b3-171ffef1a572
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247449295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
247449295
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2144770404
Short name T1066
Test name
Test status
Simulation time 31165552 ps
CPU time 1.96 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 214100 kb
Host smart-52423e4f-06a9-4114-9df5-37d9bd03c194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144770404 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2144770404
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4065963912
Short name T980
Test name
Test status
Simulation time 28348187 ps
CPU time 1.58 seconds
Started May 26 02:38:27 PM PDT 24
Finished May 26 02:38:30 PM PDT 24
Peak memory 205824 kb
Host smart-62d3e93a-2d3c-46a1-b874-78eaedc4f900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065963912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4065963912
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.373175440
Short name T1057
Test name
Test status
Simulation time 14398317 ps
CPU time 0.72 seconds
Started May 26 02:38:17 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 205504 kb
Host smart-516da4d5-d13a-4e67-bf99-b12778dc0e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373175440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.373175440
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2948485060
Short name T147
Test name
Test status
Simulation time 31598084 ps
CPU time 1.95 seconds
Started May 26 02:38:15 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 205864 kb
Host smart-1a2a4543-79c4-4c09-a2ad-0246c2f820ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948485060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2948485060
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1883880755
Short name T966
Test name
Test status
Simulation time 151792385 ps
CPU time 4.65 seconds
Started May 26 02:38:07 PM PDT 24
Finished May 26 02:38:13 PM PDT 24
Peak memory 214416 kb
Host smart-e03ce9ae-0d69-4b9b-9f22-a7526266d650
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883880755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1883880755
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3521249754
Short name T950
Test name
Test status
Simulation time 113281094 ps
CPU time 3.94 seconds
Started May 26 02:38:05 PM PDT 24
Finished May 26 02:38:10 PM PDT 24
Peak memory 214388 kb
Host smart-2d3e941c-9f60-4169-aaf4-b29c661de080
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521249754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3521249754
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2652648223
Short name T1019
Test name
Test status
Simulation time 37222209 ps
CPU time 2.16 seconds
Started May 26 02:38:06 PM PDT 24
Finished May 26 02:38:09 PM PDT 24
Peak memory 216248 kb
Host smart-d216c649-73fe-41b3-b97e-82739865f79a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652648223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2652648223
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1031909210
Short name T941
Test name
Test status
Simulation time 79018154 ps
CPU time 2.4 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:46 PM PDT 24
Peak memory 214100 kb
Host smart-74a61e09-879b-4188-8f9a-8a771d06b8ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031909210 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1031909210
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.832270189
Short name T1012
Test name
Test status
Simulation time 26628246 ps
CPU time 1.49 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:36 PM PDT 24
Peak memory 205768 kb
Host smart-6d326f06-3aed-4f7e-9d60-6fd77d471fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832270189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.832270189
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4253382178
Short name T926
Test name
Test status
Simulation time 17421102 ps
CPU time 0.72 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:39 PM PDT 24
Peak memory 205592 kb
Host smart-4d6ebc9f-e7cb-4fd3-98f2-35448a9dde3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253382178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4253382178
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2708669670
Short name T1006
Test name
Test status
Simulation time 344569450 ps
CPU time 2.31 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:37 PM PDT 24
Peak memory 205888 kb
Host smart-3c23dc5e-9dfd-4285-9b71-50bfc8336e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708669670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2708669670
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1711849344
Short name T1070
Test name
Test status
Simulation time 834275354 ps
CPU time 3.75 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:41 PM PDT 24
Peak memory 214364 kb
Host smart-38edc0ae-de65-40b3-8105-d17804a33466
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711849344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1711849344
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3737890290
Short name T940
Test name
Test status
Simulation time 144289467 ps
CPU time 1.88 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:38 PM PDT 24
Peak memory 214072 kb
Host smart-c277dfa0-9808-46ba-b1a5-b4b10bb500f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737890290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3737890290
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3146138486
Short name T972
Test name
Test status
Simulation time 79351711 ps
CPU time 1.46 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 214100 kb
Host smart-c0b169ec-71a6-46f3-9a6e-44d9ad447ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146138486 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3146138486
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1541741347
Short name T1073
Test name
Test status
Simulation time 385021536 ps
CPU time 1.27 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205832 kb
Host smart-04d90a38-7e3a-475d-a5ea-766f53c0eee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541741347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1541741347
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3943689003
Short name T1047
Test name
Test status
Simulation time 13537511 ps
CPU time 0.74 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 205596 kb
Host smart-7ccb5e1a-9c60-41e3-9775-c7f934fb17a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943689003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3943689003
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3652623951
Short name T943
Test name
Test status
Simulation time 134498369 ps
CPU time 2.05 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205892 kb
Host smart-e5cd77b0-53f9-418a-8911-15b569729a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652623951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3652623951
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1576579410
Short name T1044
Test name
Test status
Simulation time 694207283 ps
CPU time 4.14 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 214380 kb
Host smart-4ba3a709-bc28-41cb-a035-68f77b83248f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576579410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1576579410
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1795006784
Short name T1080
Test name
Test status
Simulation time 209457163 ps
CPU time 8.8 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 221396 kb
Host smart-50a8032e-56ea-4d3a-8947-8ae1e7a0c590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795006784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1795006784
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1668738762
Short name T932
Test name
Test status
Simulation time 57334477 ps
CPU time 2.35 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 215632 kb
Host smart-956baafd-f8f7-49e0-a4b3-a88d38eab89b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668738762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1668738762
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1764757767
Short name T172
Test name
Test status
Simulation time 750954709 ps
CPU time 11.74 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 205796 kb
Host smart-1feb4759-3123-4bca-9bae-f5cd9eedd944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764757767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1764757767
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1395939673
Short name T1018
Test name
Test status
Simulation time 91883962 ps
CPU time 1.94 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 214084 kb
Host smart-9af5dab1-785b-4f29-ba72-16f8fc725510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395939673 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1395939673
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1400645936
Short name T1033
Test name
Test status
Simulation time 16835574 ps
CPU time 1.06 seconds
Started May 26 02:38:41 PM PDT 24
Finished May 26 02:38:43 PM PDT 24
Peak memory 205676 kb
Host smart-9f9a64b2-ea09-4d90-b8e5-197bed5d0d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400645936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1400645936
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3756969356
Short name T1024
Test name
Test status
Simulation time 90571851 ps
CPU time 0.69 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:46 PM PDT 24
Peak memory 205588 kb
Host smart-38652f91-7090-4967-a713-3670e52fd6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756969356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3756969356
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1717748725
Short name T143
Test name
Test status
Simulation time 114599561 ps
CPU time 2.7 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205908 kb
Host smart-12e69532-3192-4556-9608-c31f2b656640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717748725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1717748725
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.645924763
Short name T964
Test name
Test status
Simulation time 138291117 ps
CPU time 2.01 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 214336 kb
Host smart-7cb1a5b9-76e8-4f9b-8050-bc177590ed7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645924763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.645924763
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2452909642
Short name T122
Test name
Test status
Simulation time 3515083919 ps
CPU time 10.9 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 214500 kb
Host smart-f9f9d3aa-2437-4e13-a106-a32e3aea492a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452909642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2452909642
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.979222879
Short name T1048
Test name
Test status
Simulation time 88488993 ps
CPU time 3.36 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 214196 kb
Host smart-bcf9dd0a-2082-482e-8ecc-1a1e9c9b451f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979222879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.979222879
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4028687422
Short name T170
Test name
Test status
Simulation time 100513050 ps
CPU time 4.29 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:48 PM PDT 24
Peak memory 213992 kb
Host smart-b19f2b79-767a-45c4-ac27-4b3155b1e97b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028687422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4028687422
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3663110597
Short name T920
Test name
Test status
Simulation time 91564060 ps
CPU time 1.06 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 205900 kb
Host smart-c6bd0235-6c7d-4f62-8451-c4e825268965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663110597 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3663110597
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1972296740
Short name T1069
Test name
Test status
Simulation time 32973992 ps
CPU time 1.58 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 205836 kb
Host smart-198c10e5-a846-4873-b947-a805d3a97a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972296740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1972296740
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2687962962
Short name T965
Test name
Test status
Simulation time 9154876 ps
CPU time 0.76 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205496 kb
Host smart-8d01504a-57e9-4f29-a5da-ba967cf580ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687962962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2687962962
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3499221255
Short name T1071
Test name
Test status
Simulation time 168213247 ps
CPU time 2.28 seconds
Started May 26 02:38:41 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 205920 kb
Host smart-5196089d-034c-4e72-abb2-c186c8119742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499221255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3499221255
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1479902437
Short name T1046
Test name
Test status
Simulation time 181703572 ps
CPU time 4.2 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 214376 kb
Host smart-beb99b73-430e-43a8-9189-2abf8d78684f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479902437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1479902437
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1596089482
Short name T1074
Test name
Test status
Simulation time 210096984 ps
CPU time 5.09 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 214388 kb
Host smart-a38f4591-28c7-4bac-b5f8-a46e57ea13ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596089482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1596089482
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.131039047
Short name T1030
Test name
Test status
Simulation time 26223844 ps
CPU time 1.66 seconds
Started May 26 02:38:46 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 213984 kb
Host smart-7c160449-40d7-4f92-95cf-211b44b829d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131039047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.131039047
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3262187461
Short name T171
Test name
Test status
Simulation time 413728241 ps
CPU time 3.3 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 213952 kb
Host smart-f32b0e1d-dc23-4283-b265-794414b224a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262187461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3262187461
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1723996722
Short name T1009
Test name
Test status
Simulation time 61690202 ps
CPU time 1.12 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 205900 kb
Host smart-ea72fff3-dd36-4bbd-bc8d-88c218f9eca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723996722 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1723996722
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2128893496
Short name T957
Test name
Test status
Simulation time 86579755 ps
CPU time 1.49 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 205852 kb
Host smart-a658d1ed-3f1a-4af4-9048-ab10848f5dec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128893496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2128893496
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2264377588
Short name T921
Test name
Test status
Simulation time 49092368 ps
CPU time 0.88 seconds
Started May 26 02:38:52 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 205544 kb
Host smart-3fbfb5af-68b7-4c28-aaa6-ca32c46108ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264377588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2264377588
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.822662406
Short name T988
Test name
Test status
Simulation time 321474147 ps
CPU time 1.95 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205940 kb
Host smart-fc675d42-8800-422a-b824-78243c97bde1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822662406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.822662406
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3896494172
Short name T1083
Test name
Test status
Simulation time 147282893 ps
CPU time 2.61 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 214436 kb
Host smart-7a810821-7cab-4322-a8dc-cf60a91488c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896494172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3896494172
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1084287380
Short name T1060
Test name
Test status
Simulation time 1260496240 ps
CPU time 4.79 seconds
Started May 26 02:38:46 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 220232 kb
Host smart-be982dd3-4f82-4dd2-ac15-0fc361aed29c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084287380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1084287380
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3077596403
Short name T1051
Test name
Test status
Simulation time 439545565 ps
CPU time 2.69 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 214204 kb
Host smart-6673663a-4a2c-4665-bcbf-803c672830f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077596403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3077596403
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.7880951
Short name T922
Test name
Test status
Simulation time 156462123 ps
CPU time 1.66 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 206040 kb
Host smart-2edf8e16-86f3-49e8-a5b4-c9ea2d519497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7880951 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.7880951
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1000534560
Short name T1037
Test name
Test status
Simulation time 26168793 ps
CPU time 0.85 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205684 kb
Host smart-48c1f0dc-da31-42f6-bd0f-20da32cff0ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000534560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1000534560
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3174790252
Short name T1027
Test name
Test status
Simulation time 21056967 ps
CPU time 0.8 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 205580 kb
Host smart-1b126b77-3cdd-4b75-9cd3-483fbad5cc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174790252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3174790252
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2792827611
Short name T1023
Test name
Test status
Simulation time 21287387 ps
CPU time 1.67 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 205860 kb
Host smart-6e5c8375-3c16-405e-b90b-092d1ea92de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792827611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2792827611
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3624117915
Short name T1052
Test name
Test status
Simulation time 263466902 ps
CPU time 2.31 seconds
Started May 26 02:38:46 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 214512 kb
Host smart-b7b788dd-ed6c-40b9-bc33-91d9bb5fd698
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624117915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3624117915
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1107117739
Short name T1031
Test name
Test status
Simulation time 114519234 ps
CPU time 2.3 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:46 PM PDT 24
Peak memory 213892 kb
Host smart-cfd52249-5022-4795-a3bc-38e1870e622c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107117739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1107117739
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.702851726
Short name T1013
Test name
Test status
Simulation time 1149714711 ps
CPU time 6.16 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 214144 kb
Host smart-43ec26dc-c9a4-4a33-a05a-700effca2972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702851726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.702851726
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1592181210
Short name T1025
Test name
Test status
Simulation time 24918775 ps
CPU time 1.07 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 205892 kb
Host smart-5a507147-7823-414e-b541-5c69a0cc94fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592181210 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1592181210
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1111979144
Short name T1004
Test name
Test status
Simulation time 22877299 ps
CPU time 1.13 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 205872 kb
Host smart-d1d4f20b-c012-40f3-9e3f-3b61f6a2cf89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111979144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1111979144
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2975970487
Short name T1035
Test name
Test status
Simulation time 30375677 ps
CPU time 0.78 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:46 PM PDT 24
Peak memory 205508 kb
Host smart-d38895a1-309b-4aaa-888c-081f729c1417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975970487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2975970487
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1446064440
Short name T1087
Test name
Test status
Simulation time 35737383 ps
CPU time 1.48 seconds
Started May 26 02:38:52 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205812 kb
Host smart-abe1f88f-5cf8-4089-9279-d69e61554ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446064440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1446064440
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1222918744
Short name T1008
Test name
Test status
Simulation time 193291170 ps
CPU time 3.68 seconds
Started May 26 02:38:52 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 214388 kb
Host smart-62e69bcb-75bf-4cc1-8fc2-12309c0f42d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222918744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1222918744
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3473823301
Short name T119
Test name
Test status
Simulation time 351207294 ps
CPU time 8.14 seconds
Started May 26 02:38:42 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 214352 kb
Host smart-93ee4640-be04-4f27-b63c-ff348830d147
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473823301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3473823301
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4086765056
Short name T1040
Test name
Test status
Simulation time 130004714 ps
CPU time 3.26 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 214280 kb
Host smart-c1a32cf9-551b-4d79-9d2e-cf4f56ce0aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086765056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4086765056
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3589095204
Short name T166
Test name
Test status
Simulation time 220556087 ps
CPU time 8.43 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 213944 kb
Host smart-be9cdae4-d429-4137-8db0-9bc56895b099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589095204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3589095204
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4163486158
Short name T923
Test name
Test status
Simulation time 56140236 ps
CPU time 2.06 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:48 PM PDT 24
Peak memory 205904 kb
Host smart-b3f6598c-c91c-4bd5-9579-b9fdb2b06642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163486158 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4163486158
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1853245433
Short name T1056
Test name
Test status
Simulation time 108411360 ps
CPU time 1.52 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:46 PM PDT 24
Peak memory 205740 kb
Host smart-cde3958f-1d8b-4116-a490-a8f93240014c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853245433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1853245433
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.783005817
Short name T995
Test name
Test status
Simulation time 10099200 ps
CPU time 0.81 seconds
Started May 26 02:38:52 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 205472 kb
Host smart-2fe838d3-ce71-4d2c-9d08-4d7b31370b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783005817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.783005817
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1725034061
Short name T959
Test name
Test status
Simulation time 249718558 ps
CPU time 1.72 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:48 PM PDT 24
Peak memory 205836 kb
Host smart-9a7e5193-2eba-4e96-a276-e1dfaef99b44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725034061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1725034061
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.283977638
Short name T993
Test name
Test status
Simulation time 268909468 ps
CPU time 4.15 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 214332 kb
Host smart-e3deec82-20f5-409b-9c64-8522f0daef11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283977638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.283977638
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.413104338
Short name T1059
Test name
Test status
Simulation time 667529201 ps
CPU time 6.26 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 214556 kb
Host smart-55a7251a-d6bc-4325-bd67-cd27b0dac2ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413104338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.413104338
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1237235105
Short name T981
Test name
Test status
Simulation time 435331737 ps
CPU time 2.51 seconds
Started May 26 02:38:45 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 217352 kb
Host smart-b14d8cb3-0774-48c7-a8df-c4e8ce1575d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237235105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1237235105
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2348676607
Short name T158
Test name
Test status
Simulation time 340078781 ps
CPU time 6.61 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 214044 kb
Host smart-81c3ccb0-ae2c-4b5c-a44a-d0354ea33e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348676607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2348676607
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.130541725
Short name T1000
Test name
Test status
Simulation time 54794045 ps
CPU time 1.2 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 205800 kb
Host smart-c3b39493-293a-4844-b19d-9e3649afb1b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130541725 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.130541725
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2101587174
Short name T145
Test name
Test status
Simulation time 93745256 ps
CPU time 1.12 seconds
Started May 26 02:38:46 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205776 kb
Host smart-f43de4ac-be59-457c-8e6c-4cb746933c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101587174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2101587174
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3981274717
Short name T929
Test name
Test status
Simulation time 11253136 ps
CPU time 0.7 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 205576 kb
Host smart-c477a11c-0c51-434b-970b-34df27e82810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981274717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3981274717
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3404658757
Short name T979
Test name
Test status
Simulation time 185802061 ps
CPU time 2.22 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 205836 kb
Host smart-33c354ff-5131-4265-9a28-f51a6f129412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404658757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3404658757
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1678391363
Short name T1085
Test name
Test status
Simulation time 290153002 ps
CPU time 1.89 seconds
Started May 26 02:38:44 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 214404 kb
Host smart-bd475ffe-0d42-47dc-8cdf-b6d1c849cf6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678391363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1678391363
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3525062616
Short name T1011
Test name
Test status
Simulation time 336863166 ps
CPU time 6.42 seconds
Started May 26 02:38:46 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 214400 kb
Host smart-b8c2ece9-afce-40b1-91c9-1355a6e9f0d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525062616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3525062616
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2505426845
Short name T948
Test name
Test status
Simulation time 50226894 ps
CPU time 2.16 seconds
Started May 26 02:38:47 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 215024 kb
Host smart-56cf2d3a-4aa8-44e2-b1a4-12efecbdd44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505426845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2505426845
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2209014847
Short name T176
Test name
Test status
Simulation time 656671070 ps
CPU time 6.93 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:58 PM PDT 24
Peak memory 214064 kb
Host smart-8baa8af6-69f1-4a67-94b6-6ca75a8f896f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209014847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2209014847
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1764864364
Short name T1089
Test name
Test status
Simulation time 88022723 ps
CPU time 1.08 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 205784 kb
Host smart-823f01e8-e0c6-4a84-97e2-083e71dd5815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764864364 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1764864364
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1622420822
Short name T1022
Test name
Test status
Simulation time 253538739 ps
CPU time 1.53 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 205872 kb
Host smart-33848772-88ce-49a7-a410-f641937f6fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622420822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1622420822
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2677278964
Short name T971
Test name
Test status
Simulation time 63205894 ps
CPU time 0.82 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205548 kb
Host smart-a1d25ceb-53f0-4ef2-bf46-71feeba5271a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677278964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2677278964
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2681000043
Short name T144
Test name
Test status
Simulation time 34517445 ps
CPU time 2.49 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 205804 kb
Host smart-94a12e55-d32d-4126-9c43-f4275b53277b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681000043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2681000043
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2969748765
Short name T1002
Test name
Test status
Simulation time 85231180 ps
CPU time 1.64 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 214444 kb
Host smart-2c3f7816-5b9d-4f62-8121-9625c442bdeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969748765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2969748765
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2195841161
Short name T1082
Test name
Test status
Simulation time 338487951 ps
CPU time 6.14 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:58 PM PDT 24
Peak memory 214340 kb
Host smart-6edd3419-1567-48d1-8431-8c5b1653bf55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195841161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2195841161
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3241638283
Short name T1090
Test name
Test status
Simulation time 144174920 ps
CPU time 2.21 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 213948 kb
Host smart-4f9cd07e-47ed-437a-8914-10f514dc0fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241638283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3241638283
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2074986981
Short name T947
Test name
Test status
Simulation time 144792337 ps
CPU time 3.72 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 215308 kb
Host smart-8230d96e-01e4-41f8-b020-a97dc4a7d439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074986981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2074986981
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.277648097
Short name T1053
Test name
Test status
Simulation time 371990880 ps
CPU time 13.86 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:29 PM PDT 24
Peak memory 205764 kb
Host smart-3cfc5e4b-226a-4b50-8dea-c3c0fe1aceaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277648097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.277648097
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3715413831
Short name T1001
Test name
Test status
Simulation time 1396011178 ps
CPU time 14.75 seconds
Started May 26 02:38:17 PM PDT 24
Finished May 26 02:38:32 PM PDT 24
Peak memory 205848 kb
Host smart-16e7510c-7a44-4451-a4d7-eab438079332
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715413831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
715413831
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2165430292
Short name T955
Test name
Test status
Simulation time 80520720 ps
CPU time 1.11 seconds
Started May 26 02:38:15 PM PDT 24
Finished May 26 02:38:17 PM PDT 24
Peak memory 205768 kb
Host smart-79f26dd0-880a-48c2-a942-1a3c6b232c2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165430292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
165430292
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2795903302
Short name T925
Test name
Test status
Simulation time 352914736 ps
CPU time 2.07 seconds
Started May 26 02:38:17 PM PDT 24
Finished May 26 02:38:20 PM PDT 24
Peak memory 214316 kb
Host smart-a8e2b3ed-081d-4831-89c9-eee3729c2ea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795903302 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2795903302
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1440776141
Short name T1007
Test name
Test status
Simulation time 10700122 ps
CPU time 0.9 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 205764 kb
Host smart-1455c3e6-864e-4ee5-92f4-01c511eb4dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440776141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1440776141
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1240158713
Short name T1026
Test name
Test status
Simulation time 14061098 ps
CPU time 0.7 seconds
Started May 26 02:38:17 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 205588 kb
Host smart-bb19ed3e-6f86-42a5-bfb4-012d884854b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240158713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1240158713
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.935479363
Short name T1016
Test name
Test status
Simulation time 48486614 ps
CPU time 1.61 seconds
Started May 26 02:38:15 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 205848 kb
Host smart-1ef7377a-af60-40d1-b631-1b87751d6598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935479363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.935479363
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1554378250
Short name T1079
Test name
Test status
Simulation time 653735511 ps
CPU time 2.83 seconds
Started May 26 02:38:27 PM PDT 24
Finished May 26 02:38:31 PM PDT 24
Peak memory 214332 kb
Host smart-208f1a40-9f54-4766-94eb-8815bd0acf53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554378250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1554378250
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.806715490
Short name T125
Test name
Test status
Simulation time 750533343 ps
CPU time 8.73 seconds
Started May 26 02:38:24 PM PDT 24
Finished May 26 02:38:34 PM PDT 24
Peak memory 214328 kb
Host smart-7763c8c8-7ded-4898-9d8a-78541e6b833b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806715490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.806715490
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1867037617
Short name T917
Test name
Test status
Simulation time 76527700 ps
CPU time 2.86 seconds
Started May 26 02:38:30 PM PDT 24
Finished May 26 02:38:33 PM PDT 24
Peak memory 217456 kb
Host smart-a7a95b74-c2b2-4208-8edb-0f656f49b38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867037617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1867037617
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.54272825
Short name T156
Test name
Test status
Simulation time 231973367 ps
CPU time 4.89 seconds
Started May 26 02:38:13 PM PDT 24
Finished May 26 02:38:19 PM PDT 24
Peak memory 213932 kb
Host smart-adf9d345-d8ff-462c-8b28-8dfded7da661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54272825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.54272825
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4154311989
Short name T1086
Test name
Test status
Simulation time 40876238 ps
CPU time 0.75 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205596 kb
Host smart-51141e63-0f01-4ea6-8b4d-61c91ab009b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154311989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4154311989
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3534158046
Short name T1084
Test name
Test status
Simulation time 11939011 ps
CPU time 0.73 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 205596 kb
Host smart-035c2179-abe4-4c1b-be53-914ebd4ee1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534158046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3534158046
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1474369273
Short name T976
Test name
Test status
Simulation time 42043844 ps
CPU time 0.74 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205604 kb
Host smart-764f09b3-ec41-4b98-af1d-dbf4973b116e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474369273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1474369273
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3300969221
Short name T1017
Test name
Test status
Simulation time 36076936 ps
CPU time 0.73 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205552 kb
Host smart-f3b39528-c3aa-4ec8-85d1-c4ca95214677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300969221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3300969221
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.649541220
Short name T918
Test name
Test status
Simulation time 12622303 ps
CPU time 0.73 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205524 kb
Host smart-696a219b-21d4-4d01-98fe-4c6d76cff80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649541220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.649541220
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3928206392
Short name T1078
Test name
Test status
Simulation time 21703974 ps
CPU time 0.84 seconds
Started May 26 02:38:54 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 205584 kb
Host smart-0a663bca-a540-4735-9697-a5fc255894cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928206392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3928206392
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1012846458
Short name T990
Test name
Test status
Simulation time 35147956 ps
CPU time 0.72 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 205736 kb
Host smart-9c36e7e7-806b-4c71-9932-ff5d1f84530d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012846458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1012846458
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1397826836
Short name T939
Test name
Test status
Simulation time 11735816 ps
CPU time 0.82 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205576 kb
Host smart-9c7ae0d6-42bb-4f1b-9401-cd1b641118ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397826836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1397826836
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2282403779
Short name T1065
Test name
Test status
Simulation time 10771092 ps
CPU time 0.73 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205516 kb
Host smart-ff6bd865-320e-4728-9ab7-6b99f8bdeadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282403779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2282403779
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.669197285
Short name T1015
Test name
Test status
Simulation time 11529571 ps
CPU time 0.74 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205576 kb
Host smart-e2763191-8f53-4a6e-a8c5-e074359db04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669197285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.669197285
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4175530877
Short name T987
Test name
Test status
Simulation time 1387527771 ps
CPU time 14.97 seconds
Started May 26 02:38:24 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 205700 kb
Host smart-ed1ddb02-e40f-4f88-a94e-0b95d83e0ad1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175530877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
175530877
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3294980652
Short name T996
Test name
Test status
Simulation time 435742451 ps
CPU time 12.46 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 205892 kb
Host smart-6a173cf9-efcf-4786-af5f-2b4b9b137d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294980652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
294980652
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3808356668
Short name T1061
Test name
Test status
Simulation time 202591992 ps
CPU time 0.92 seconds
Started May 26 02:38:15 PM PDT 24
Finished May 26 02:38:17 PM PDT 24
Peak memory 205580 kb
Host smart-d9c53311-2760-43b4-b0c0-99b339af2781
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808356668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
808356668
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4038980076
Short name T968
Test name
Test status
Simulation time 52476358 ps
CPU time 2.06 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 214200 kb
Host smart-0e2755b2-a50d-4e09-9467-53221559d353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038980076 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4038980076
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2595327477
Short name T958
Test name
Test status
Simulation time 33039868 ps
CPU time 1.63 seconds
Started May 26 02:38:13 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 205840 kb
Host smart-db04c8ea-f888-4222-814b-7bb341e50702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595327477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2595327477
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2205003498
Short name T942
Test name
Test status
Simulation time 35321138 ps
CPU time 0.82 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:15 PM PDT 24
Peak memory 205524 kb
Host smart-905cebc5-113f-440a-93be-d3bfdcdf35a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205003498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2205003498
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1786206698
Short name T1063
Test name
Test status
Simulation time 122187948 ps
CPU time 4.43 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:29 PM PDT 24
Peak memory 205840 kb
Host smart-21605dcc-8ad7-4bdb-947c-05afcf5ebb60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786206698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1786206698
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3419325289
Short name T1081
Test name
Test status
Simulation time 295872349 ps
CPU time 2.55 seconds
Started May 26 02:38:24 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 214360 kb
Host smart-a99ea22d-4fd3-4e32-871c-9127e0655941
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419325289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3419325289
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1992773170
Short name T1005
Test name
Test status
Simulation time 81802562 ps
CPU time 4.64 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:20 PM PDT 24
Peak memory 214396 kb
Host smart-2586399d-2e97-48c1-a3f5-141f2d50b07d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992773170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1992773170
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3829336479
Short name T974
Test name
Test status
Simulation time 182967710 ps
CPU time 2.44 seconds
Started May 26 02:38:14 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 217276 kb
Host smart-12f6a8e4-4f25-40a3-83ee-0d56239a1267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829336479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3829336479
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1176514262
Short name T970
Test name
Test status
Simulation time 20500285 ps
CPU time 0.8 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205552 kb
Host smart-661311e8-dad1-4c83-b6cd-550df7ad3c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176514262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1176514262
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2294588099
Short name T982
Test name
Test status
Simulation time 24973705 ps
CPU time 0.73 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205564 kb
Host smart-6b03feaa-ceca-4757-a34a-a04e749e14fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294588099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2294588099
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3144888297
Short name T927
Test name
Test status
Simulation time 40324780 ps
CPU time 0.73 seconds
Started May 26 02:38:49 PM PDT 24
Finished May 26 02:38:52 PM PDT 24
Peak memory 205588 kb
Host smart-e7cec8fc-2815-4d52-8482-764fb71f90db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144888297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3144888297
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1482531321
Short name T952
Test name
Test status
Simulation time 43677324 ps
CPU time 0.74 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205520 kb
Host smart-200598af-6e70-40a6-8675-79a00de7ceea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482531321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1482531321
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4227234919
Short name T945
Test name
Test status
Simulation time 10007506 ps
CPU time 0.73 seconds
Started May 26 02:38:50 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205756 kb
Host smart-b1c6b0fc-ec21-425e-9b82-cc8f8657e671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227234919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4227234919
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.320268884
Short name T998
Test name
Test status
Simulation time 76373847 ps
CPU time 0.71 seconds
Started May 26 02:38:51 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 205524 kb
Host smart-5f6960c8-0801-4e2a-9bcf-757aa2dcd215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320268884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.320268884
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3945576808
Short name T1014
Test name
Test status
Simulation time 24329635 ps
CPU time 0.78 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 205596 kb
Host smart-f4182e35-4616-42de-ad5b-c0951b93dd7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945576808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3945576808
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.788659622
Short name T933
Test name
Test status
Simulation time 14173173 ps
CPU time 0.87 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205592 kb
Host smart-f181b74f-209e-46fb-a640-ae36b355d2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788659622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.788659622
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.255886864
Short name T938
Test name
Test status
Simulation time 41215314 ps
CPU time 0.7 seconds
Started May 26 02:38:54 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 205592 kb
Host smart-f97a7ef0-9296-4a61-8c2f-2edf17221a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255886864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.255886864
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3301065418
Short name T928
Test name
Test status
Simulation time 49247837 ps
CPU time 0.7 seconds
Started May 26 02:38:53 PM PDT 24
Finished May 26 02:38:55 PM PDT 24
Peak memory 205588 kb
Host smart-426bc9f5-c41c-41d1-8cf1-9c619049863c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301065418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3301065418
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2366814566
Short name T142
Test name
Test status
Simulation time 524299936 ps
CPU time 8.61 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:32 PM PDT 24
Peak memory 205764 kb
Host smart-85652a40-6b2b-4305-a504-1f803fd79020
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366814566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
366814566
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.198537142
Short name T969
Test name
Test status
Simulation time 504247144 ps
CPU time 14.59 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:39 PM PDT 24
Peak memory 205940 kb
Host smart-1a53babc-6af4-43e4-8743-3754064888d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198537142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.198537142
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.502569715
Short name T983
Test name
Test status
Simulation time 32235406 ps
CPU time 1.12 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 205804 kb
Host smart-71049324-b2ce-4ea6-ba99-a8e3e47952fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502569715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.502569715
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1527959790
Short name T944
Test name
Test status
Simulation time 90072623 ps
CPU time 1.53 seconds
Started May 26 02:38:21 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 214028 kb
Host smart-355e5d6e-0505-47da-8150-69c4e649b48a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527959790 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1527959790
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4135171307
Short name T999
Test name
Test status
Simulation time 30361345 ps
CPU time 1.19 seconds
Started May 26 02:38:21 PM PDT 24
Finished May 26 02:38:23 PM PDT 24
Peak memory 205772 kb
Host smart-d38f5804-88bb-4f45-87ae-f048a1a21c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135171307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4135171307
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3902274547
Short name T930
Test name
Test status
Simulation time 93705903 ps
CPU time 0.74 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 205588 kb
Host smart-5431f117-6fca-4e30-8792-3df6d1a21d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902274547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3902274547
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.503723587
Short name T949
Test name
Test status
Simulation time 84193396 ps
CPU time 2.87 seconds
Started May 26 02:38:26 PM PDT 24
Finished May 26 02:38:30 PM PDT 24
Peak memory 205988 kb
Host smart-cfb6f2b3-8de1-465d-9407-82690cb24470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503723587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.503723587
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.773778650
Short name T989
Test name
Test status
Simulation time 199477041 ps
CPU time 3.18 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 214440 kb
Host smart-841eacf4-092a-4b89-a65f-fe45fa363bb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773778650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.773778650
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.869659150
Short name T1050
Test name
Test status
Simulation time 254808514 ps
CPU time 6.18 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:31 PM PDT 24
Peak memory 214392 kb
Host smart-aa085f2e-5f8d-4613-ae45-6bb175cb8145
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869659150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.869659150
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3459156179
Short name T1077
Test name
Test status
Simulation time 79117535 ps
CPU time 2.19 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 205840 kb
Host smart-aa6d3ea4-a3d3-4323-9c84-6656ad657c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459156179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3459156179
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3887768471
Short name T1054
Test name
Test status
Simulation time 414119780 ps
CPU time 4.61 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:29 PM PDT 24
Peak memory 213964 kb
Host smart-0dd72c78-8095-40bf-8318-d8c64ed2f38b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887768471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3887768471
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2952676783
Short name T1076
Test name
Test status
Simulation time 10251641 ps
CPU time 0.66 seconds
Started May 26 02:38:48 PM PDT 24
Finished May 26 02:38:50 PM PDT 24
Peak memory 205520 kb
Host smart-153540a9-2803-4a53-a6b4-c198d1787d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952676783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2952676783
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.434547669
Short name T1067
Test name
Test status
Simulation time 21185350 ps
CPU time 0.84 seconds
Started May 26 02:38:54 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 205592 kb
Host smart-594f1535-75f6-48ec-b8d1-cc64e60ce16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434547669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.434547669
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3272021397
Short name T960
Test name
Test status
Simulation time 129018764 ps
CPU time 0.84 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:38:58 PM PDT 24
Peak memory 205480 kb
Host smart-84b2a527-ed3d-434f-a9e9-c7aa6fa3e0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272021397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3272021397
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1270406772
Short name T984
Test name
Test status
Simulation time 19623253 ps
CPU time 0.8 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 205588 kb
Host smart-62f4f9d4-d02c-4f36-a300-b76e1e044d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270406772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1270406772
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1929997803
Short name T934
Test name
Test status
Simulation time 36828946 ps
CPU time 0.7 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:39:00 PM PDT 24
Peak memory 205592 kb
Host smart-50b3f1ea-59c0-407c-be66-23035f93c859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929997803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1929997803
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3147172014
Short name T1038
Test name
Test status
Simulation time 14192568 ps
CPU time 0.74 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 205476 kb
Host smart-cfb3aa20-e945-4546-b5b9-9488b3296fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147172014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3147172014
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2745806010
Short name T1042
Test name
Test status
Simulation time 13062555 ps
CPU time 0.71 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 205508 kb
Host smart-8768a408-d5e1-4a1a-b481-6b8ab9c76fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745806010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2745806010
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2177748526
Short name T919
Test name
Test status
Simulation time 13144412 ps
CPU time 0.76 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:00 PM PDT 24
Peak memory 205564 kb
Host smart-9072579d-9af5-4cf5-9127-e8e48652e791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177748526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2177748526
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1492013492
Short name T1021
Test name
Test status
Simulation time 15920510 ps
CPU time 0.7 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:38:59 PM PDT 24
Peak memory 205488 kb
Host smart-be7b875f-7330-49b3-9087-55415c8d48b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492013492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1492013492
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.129163147
Short name T935
Test name
Test status
Simulation time 14040156 ps
CPU time 0.87 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:00 PM PDT 24
Peak memory 205720 kb
Host smart-ea5d8723-cb6e-4d03-b303-4e9a68d1f6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129163147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.129163147
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1382691955
Short name T962
Test name
Test status
Simulation time 87139076 ps
CPU time 1.76 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 214064 kb
Host smart-a2b94a00-e871-4f22-9627-d52cf542644b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382691955 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1382691955
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3012210718
Short name T951
Test name
Test status
Simulation time 111290020 ps
CPU time 1.15 seconds
Started May 26 02:38:24 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 205896 kb
Host smart-2d89cd8c-1e6d-4247-a148-9bd0465ecafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012210718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3012210718
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.100658836
Short name T963
Test name
Test status
Simulation time 35537149 ps
CPU time 0.92 seconds
Started May 26 02:38:26 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 205740 kb
Host smart-921cd5de-58df-4d67-832d-a93fec8ab661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100658836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.100658836
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2374939154
Short name T994
Test name
Test status
Simulation time 22164479 ps
CPU time 1.39 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 205768 kb
Host smart-babd1237-9762-41cd-9db8-4c97122dea34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374939154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2374939154
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.406639810
Short name T124
Test name
Test status
Simulation time 287483115 ps
CPU time 1.78 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:25 PM PDT 24
Peak memory 214440 kb
Host smart-5f107463-09a9-40e2-8983-63ff1106fbc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406639810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.406639810
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3656240849
Short name T1072
Test name
Test status
Simulation time 781886796 ps
CPU time 4.61 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 220540 kb
Host smart-b57b5d37-c68a-4e29-952f-f913dc38904b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656240849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3656240849
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2343202205
Short name T977
Test name
Test status
Simulation time 114841516 ps
CPU time 1.69 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 213964 kb
Host smart-842eef5e-24a3-4956-a2c5-287e1f2f471c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343202205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2343202205
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1454037842
Short name T1028
Test name
Test status
Simulation time 200725791 ps
CPU time 4.53 seconds
Started May 26 02:38:28 PM PDT 24
Finished May 26 02:38:33 PM PDT 24
Peak memory 214032 kb
Host smart-197b0902-9340-4fc8-a9a8-9d6a9c54284d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454037842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1454037842
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.79789149
Short name T1045
Test name
Test status
Simulation time 62489347 ps
CPU time 2.28 seconds
Started May 26 02:38:21 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 214124 kb
Host smart-fb07371d-4e28-4866-a748-e64c56277d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79789149 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.79789149
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1433641731
Short name T978
Test name
Test status
Simulation time 18180311 ps
CPU time 1.06 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 205732 kb
Host smart-1bee8185-375d-42f4-a9d8-352a897ce5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433641731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1433641731
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2362118658
Short name T1068
Test name
Test status
Simulation time 32378880 ps
CPU time 0.77 seconds
Started May 26 02:38:30 PM PDT 24
Finished May 26 02:38:32 PM PDT 24
Peak memory 205492 kb
Host smart-9fd9d754-f172-4a70-9e91-c354e5562b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362118658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2362118658
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1004265221
Short name T992
Test name
Test status
Simulation time 91854487 ps
CPU time 2.34 seconds
Started May 26 02:38:24 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 205804 kb
Host smart-cb58e179-ba2f-4eea-b04d-eea29a7ed91f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004265221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1004265221
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.383151375
Short name T118
Test name
Test status
Simulation time 318125307 ps
CPU time 2.11 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 214384 kb
Host smart-1d71b583-aae6-406a-a218-69eb15c5962d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383151375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.383151375
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1440037705
Short name T1062
Test name
Test status
Simulation time 1574302477 ps
CPU time 14.08 seconds
Started May 26 02:38:26 PM PDT 24
Finished May 26 02:38:41 PM PDT 24
Peak memory 214632 kb
Host smart-1921cf23-3a0c-4244-90a8-ca7ae292c785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440037705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1440037705
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1277434380
Short name T1039
Test name
Test status
Simulation time 673682464 ps
CPU time 3.04 seconds
Started May 26 02:38:22 PM PDT 24
Finished May 26 02:38:26 PM PDT 24
Peak memory 214048 kb
Host smart-d53b94fc-2227-4940-b869-2537d1324770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277434380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1277434380
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.224705437
Short name T174
Test name
Test status
Simulation time 154451946 ps
CPU time 5.19 seconds
Started May 26 02:38:23 PM PDT 24
Finished May 26 02:38:30 PM PDT 24
Peak memory 214044 kb
Host smart-4714cb2c-b272-42c6-b87d-e2ac289c6a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224705437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
224705437
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3815517484
Short name T946
Test name
Test status
Simulation time 342194265 ps
CPU time 2.1 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:39 PM PDT 24
Peak memory 214064 kb
Host smart-f292032e-f42a-4118-b1a1-01414c106eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815517484 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3815517484
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2142300052
Short name T975
Test name
Test status
Simulation time 10300687 ps
CPU time 0.89 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:36 PM PDT 24
Peak memory 205708 kb
Host smart-b5ce9fda-8874-4f7a-b77a-b9b99d80aced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142300052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2142300052
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.913793135
Short name T1088
Test name
Test status
Simulation time 10341011 ps
CPU time 0.84 seconds
Started May 26 02:38:43 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 205592 kb
Host smart-9951f0fe-84c0-4de2-a1aa-eb83800fd8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913793135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.913793135
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1187920999
Short name T956
Test name
Test status
Simulation time 101671988 ps
CPU time 1.77 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:38 PM PDT 24
Peak memory 206068 kb
Host smart-a5e05ce9-addf-4b34-83a9-42fb321594ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187920999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1187920999
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2404168443
Short name T123
Test name
Test status
Simulation time 367585622 ps
CPU time 5.75 seconds
Started May 26 02:38:25 PM PDT 24
Finished May 26 02:38:31 PM PDT 24
Peak memory 214396 kb
Host smart-bedbf414-8a60-4e50-8028-0e67dc13d5e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404168443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2404168443
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2683892985
Short name T148
Test name
Test status
Simulation time 1240686782 ps
CPU time 8.46 seconds
Started May 26 02:38:20 PM PDT 24
Finished May 26 02:38:29 PM PDT 24
Peak memory 214216 kb
Host smart-b0ed7581-f08f-4a82-819d-a21c686a3e57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683892985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2683892985
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3800531908
Short name T986
Test name
Test status
Simulation time 59445611 ps
CPU time 2.43 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 215092 kb
Host smart-422d6a48-8747-44b2-a63a-24203513661a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800531908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3800531908
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3788998818
Short name T954
Test name
Test status
Simulation time 105132961 ps
CPU time 1.09 seconds
Started May 26 02:38:33 PM PDT 24
Finished May 26 02:38:35 PM PDT 24
Peak memory 205820 kb
Host smart-55a43e48-ea84-4955-b896-7b3e0d31490b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788998818 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3788998818
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3790307261
Short name T1049
Test name
Test status
Simulation time 21699247 ps
CPU time 0.89 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:37 PM PDT 24
Peak memory 205720 kb
Host smart-bdaa2350-5b78-4d48-8096-1f2792d464aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790307261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3790307261
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4026002640
Short name T997
Test name
Test status
Simulation time 13114852 ps
CPU time 0.72 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:37 PM PDT 24
Peak memory 205524 kb
Host smart-da6f30d8-1b5c-40d0-b82e-8da544872ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026002640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4026002640
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3380565815
Short name T1055
Test name
Test status
Simulation time 115486397 ps
CPU time 2.16 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:38 PM PDT 24
Peak memory 214004 kb
Host smart-76478fe7-9b1a-47e1-baa5-2209c8bd5489
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380565815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3380565815
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1821482827
Short name T1075
Test name
Test status
Simulation time 145902677 ps
CPU time 2.22 seconds
Started May 26 02:38:34 PM PDT 24
Finished May 26 02:38:38 PM PDT 24
Peak memory 214464 kb
Host smart-05597011-b6a6-4eb9-8d68-f7db221f7243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821482827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1821482827
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1764895625
Short name T1058
Test name
Test status
Simulation time 976724861 ps
CPU time 9.04 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:48 PM PDT 24
Peak memory 214560 kb
Host smart-d8a0310a-308b-443f-9344-fc374da22510
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764895625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1764895625
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3833264835
Short name T961
Test name
Test status
Simulation time 512076415 ps
CPU time 3.07 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 214044 kb
Host smart-c6c533eb-dac4-4cd2-8bfd-f55012dbdef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833264835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3833264835
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1562502534
Short name T931
Test name
Test status
Simulation time 26131185 ps
CPU time 1.88 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 214260 kb
Host smart-8dc0cf36-0c4a-4ecb-bf27-ffff7338a2cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562502534 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1562502534
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2778889076
Short name T937
Test name
Test status
Simulation time 55822929 ps
CPU time 1.06 seconds
Started May 26 02:38:33 PM PDT 24
Finished May 26 02:38:34 PM PDT 24
Peak memory 205848 kb
Host smart-384f2691-4adc-44c2-a8c0-bda47b8a51b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778889076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2778889076
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3253410339
Short name T1034
Test name
Test status
Simulation time 64069125 ps
CPU time 0.75 seconds
Started May 26 02:38:33 PM PDT 24
Finished May 26 02:38:35 PM PDT 24
Peak memory 205568 kb
Host smart-929c7185-c997-4d03-84cb-f1bcfacf9606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253410339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3253410339
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3482279884
Short name T1064
Test name
Test status
Simulation time 105059002 ps
CPU time 2.27 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 205864 kb
Host smart-0944c54d-32e8-4e09-a5a5-80a2c6583954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482279884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3482279884
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3456642675
Short name T1010
Test name
Test status
Simulation time 290274499 ps
CPU time 3.07 seconds
Started May 26 02:38:36 PM PDT 24
Finished May 26 02:38:42 PM PDT 24
Peak memory 214412 kb
Host smart-1f000e21-20ca-405c-a63f-9260a6dae028
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456642675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3456642675
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2415082891
Short name T1032
Test name
Test status
Simulation time 240709715 ps
CPU time 5.52 seconds
Started May 26 02:38:37 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 220460 kb
Host smart-6fd5eacc-83ea-4703-b85e-413ca9aa0b35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415082891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2415082891
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.294568105
Short name T991
Test name
Test status
Simulation time 174479306 ps
CPU time 3.98 seconds
Started May 26 02:38:38 PM PDT 24
Finished May 26 02:38:44 PM PDT 24
Peak memory 214172 kb
Host smart-db3996c1-d069-4ba0-94bd-642e73d7c2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294568105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.294568105
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3033655440
Short name T165
Test name
Test status
Simulation time 337028418 ps
CPU time 5.29 seconds
Started May 26 02:38:35 PM PDT 24
Finished May 26 02:38:43 PM PDT 24
Peak memory 214000 kb
Host smart-d4219a86-ecd5-41ae-9902-52fb740ea729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033655440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3033655440
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.684136277
Short name T462
Test name
Test status
Simulation time 45889795 ps
CPU time 0.94 seconds
Started May 26 02:48:29 PM PDT 24
Finished May 26 02:48:30 PM PDT 24
Peak memory 206012 kb
Host smart-2a32715c-cb13-4547-a346-9f0e1b66d65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684136277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.684136277
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2801639665
Short name T361
Test name
Test status
Simulation time 149107960 ps
CPU time 8.01 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:31 PM PDT 24
Peak memory 214376 kb
Host smart-ea719e24-6179-4cce-9db4-04a68662e61d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801639665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2801639665
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.29144037
Short name T705
Test name
Test status
Simulation time 334484350 ps
CPU time 4.19 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:27 PM PDT 24
Peak memory 207684 kb
Host smart-a05ceb4d-5926-461d-9ff5-0befe0354ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29144037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.29144037
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3472893532
Short name T704
Test name
Test status
Simulation time 45984382 ps
CPU time 1.96 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:30 PM PDT 24
Peak memory 214380 kb
Host smart-ee55a36f-ba16-4613-9740-8cb808ac76dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472893532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3472893532
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3764891125
Short name T35
Test name
Test status
Simulation time 453650452 ps
CPU time 2.53 seconds
Started May 26 02:48:28 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 222488 kb
Host smart-4f2a2b7f-1b3f-44ca-a966-3e1317c5e319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764891125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3764891125
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.417933421
Short name T735
Test name
Test status
Simulation time 119714670 ps
CPU time 4.22 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:35 PM PDT 24
Peak memory 219692 kb
Host smart-196d1113-0b5c-4ebd-a35d-e149997320d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417933421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.417933421
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2162157550
Short name T655
Test name
Test status
Simulation time 232620095 ps
CPU time 4.1 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:35 PM PDT 24
Peak memory 218816 kb
Host smart-584d82e2-9bd3-4ebb-84ef-af5248f5e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162157550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2162157550
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.538536307
Short name T41
Test name
Test status
Simulation time 1193975617 ps
CPU time 7.57 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:36 PM PDT 24
Peak memory 234076 kb
Host smart-6cedb4e9-26e4-408d-a64c-a90ef3f07be3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538536307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.538536307
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1829935588
Short name T322
Test name
Test status
Simulation time 198181458 ps
CPU time 6.96 seconds
Started May 26 02:48:19 PM PDT 24
Finished May 26 02:48:27 PM PDT 24
Peak memory 206960 kb
Host smart-f57cce44-7c53-4a78-903b-5898f60ac719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829935588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1829935588
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3023212332
Short name T720
Test name
Test status
Simulation time 594322787 ps
CPU time 5.06 seconds
Started May 26 02:48:22 PM PDT 24
Finished May 26 02:48:29 PM PDT 24
Peak memory 207036 kb
Host smart-075cb6d6-063b-464d-bd1b-734646e576bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023212332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3023212332
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1295117612
Short name T481
Test name
Test status
Simulation time 5174155235 ps
CPU time 34.11 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 207940 kb
Host smart-6dfa2c16-84f1-4535-8380-0b9de21ebc56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295117612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1295117612
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1395812057
Short name T429
Test name
Test status
Simulation time 45272044 ps
CPU time 1.84 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:25 PM PDT 24
Peak memory 206988 kb
Host smart-9edd1bf8-badd-445b-8544-bd2adf1c63f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395812057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1395812057
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1922019392
Short name T576
Test name
Test status
Simulation time 90979437 ps
CPU time 4.19 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 209444 kb
Host smart-b479ba85-d6fa-463b-9794-04a6e22ce3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922019392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1922019392
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2227158977
Short name T389
Test name
Test status
Simulation time 185139673 ps
CPU time 4.14 seconds
Started May 26 02:48:22 PM PDT 24
Finished May 26 02:48:28 PM PDT 24
Peak memory 208416 kb
Host smart-53f6ff30-ecba-490f-924f-fa9c221fcad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227158977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2227158977
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3724068168
Short name T792
Test name
Test status
Simulation time 1129032403 ps
CPU time 16.2 seconds
Started May 26 02:48:26 PM PDT 24
Finished May 26 02:48:43 PM PDT 24
Peak memory 215316 kb
Host smart-3db4c547-20f1-4300-a5c3-3f3a09c13eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724068168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3724068168
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1038736741
Short name T128
Test name
Test status
Simulation time 363867350 ps
CPU time 8.14 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:37 PM PDT 24
Peak memory 219592 kb
Host smart-12c22e99-f400-4ee8-a02e-95ad70ac3723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038736741 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1038736741
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1326181513
Short name T111
Test name
Test status
Simulation time 46639385 ps
CPU time 2.76 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 207620 kb
Host smart-ff80153e-e7b8-43fa-b4fd-f21c60186d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326181513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1326181513
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1279335938
Short name T454
Test name
Test status
Simulation time 73766803 ps
CPU time 3.15 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:31 PM PDT 24
Peak memory 210232 kb
Host smart-543ca4e4-ee06-47b6-b8ba-1b3a306689ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279335938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1279335938
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2382150185
Short name T734
Test name
Test status
Simulation time 12665625 ps
CPU time 0.89 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:46 PM PDT 24
Peak memory 205956 kb
Host smart-0fdc8229-dc02-4007-b0e0-8dbfbbe156a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382150185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2382150185
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3750571192
Short name T383
Test name
Test status
Simulation time 106514408 ps
CPU time 3.87 seconds
Started May 26 02:48:26 PM PDT 24
Finished May 26 02:48:31 PM PDT 24
Peak memory 214384 kb
Host smart-e673e95c-6a27-477f-afdc-c4b9cdca6fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750571192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3750571192
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.789236204
Short name T688
Test name
Test status
Simulation time 466407748 ps
CPU time 14.88 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:43 PM PDT 24
Peak memory 209112 kb
Host smart-67df794c-e753-4c83-b1c3-b4fb7fd3d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789236204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.789236204
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.876075081
Short name T354
Test name
Test status
Simulation time 1806354943 ps
CPU time 5.68 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:36 PM PDT 24
Peak memory 214352 kb
Host smart-873cb8e5-af17-4249-bede-3524aea47b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876075081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.876075081
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2138986720
Short name T787
Test name
Test status
Simulation time 205652499 ps
CPU time 2.52 seconds
Started May 26 02:48:28 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 219216 kb
Host smart-82b78f6b-8ea8-4d82-9b1b-17dfc0d6c585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138986720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2138986720
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.932548132
Short name T321
Test name
Test status
Simulation time 858609157 ps
CPU time 7.62 seconds
Started May 26 02:48:26 PM PDT 24
Finished May 26 02:48:35 PM PDT 24
Peak memory 208268 kb
Host smart-f5a70aca-f7d8-419b-8066-e30c048ee9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932548132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.932548132
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.183390092
Short name T8
Test name
Test status
Simulation time 552342795 ps
CPU time 5.75 seconds
Started May 26 02:48:36 PM PDT 24
Finished May 26 02:48:43 PM PDT 24
Peak memory 233632 kb
Host smart-d39314d4-fa2b-4f3c-9855-39c8b63127dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183390092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.183390092
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2966433371
Short name T749
Test name
Test status
Simulation time 302507455 ps
CPU time 4.77 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:36 PM PDT 24
Peak memory 208448 kb
Host smart-af36e565-42c0-4533-972e-3accc6a09c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966433371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2966433371
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3683427830
Short name T876
Test name
Test status
Simulation time 55653229 ps
CPU time 2.76 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 206960 kb
Host smart-e8b9de67-d3c4-4555-bb27-dc73cf406b08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683427830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3683427830
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1320053455
Short name T431
Test name
Test status
Simulation time 166728517 ps
CPU time 2.48 seconds
Started May 26 02:48:26 PM PDT 24
Finished May 26 02:48:30 PM PDT 24
Peak memory 207000 kb
Host smart-c0b8d3a1-e11f-466d-baa3-9f335f0a13fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320053455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1320053455
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3296204325
Short name T826
Test name
Test status
Simulation time 197480431 ps
CPU time 2.52 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 214376 kb
Host smart-5948eef9-6638-4f49-97b1-a8657f91608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296204325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3296204325
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.704144813
Short name T442
Test name
Test status
Simulation time 162668116 ps
CPU time 3.46 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 208464 kb
Host smart-1baa48be-8229-4174-8872-370e858b7268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704144813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.704144813
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2030181524
Short name T667
Test name
Test status
Simulation time 565369960 ps
CPU time 7.94 seconds
Started May 26 02:48:27 PM PDT 24
Finished May 26 02:48:36 PM PDT 24
Peak memory 208968 kb
Host smart-887ced10-cbfe-43fa-9435-4420941f0710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030181524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2030181524
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.927696395
Short name T283
Test name
Test status
Simulation time 420085847 ps
CPU time 11.77 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:43 PM PDT 24
Peak memory 218436 kb
Host smart-00e4afa9-a022-493b-8f75-5407ca021d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927696395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.927696395
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1558847683
Short name T878
Test name
Test status
Simulation time 837999057 ps
CPU time 7.73 seconds
Started May 26 02:48:28 PM PDT 24
Finished May 26 02:48:37 PM PDT 24
Peak memory 210852 kb
Host smart-de45939a-3fdf-4688-9f36-fd018668cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558847683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1558847683
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2070936614
Short name T547
Test name
Test status
Simulation time 25271446 ps
CPU time 0.8 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 205972 kb
Host smart-bc043c48-3049-4cb5-a025-eec0cfa4f1d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070936614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2070936614
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1840271726
Short name T471
Test name
Test status
Simulation time 56736140 ps
CPU time 2 seconds
Started May 26 02:49:16 PM PDT 24
Finished May 26 02:49:19 PM PDT 24
Peak memory 214820 kb
Host smart-db54f274-3663-478f-9d4f-ac43c0daafe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840271726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1840271726
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2963989201
Short name T677
Test name
Test status
Simulation time 63006793 ps
CPU time 2.77 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 210500 kb
Host smart-7035ec50-066f-47c6-b8ac-7fd3ef96438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963989201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2963989201
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3680261463
Short name T866
Test name
Test status
Simulation time 134981671 ps
CPU time 2.7 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:12 PM PDT 24
Peak memory 214284 kb
Host smart-5673f9f4-4eb6-43e2-88d6-f3a243e914eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680261463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3680261463
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.984467512
Short name T760
Test name
Test status
Simulation time 147387867 ps
CPU time 5.47 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:16 PM PDT 24
Peak memory 219724 kb
Host smart-80a3e670-bb57-425e-b542-33e18eea43f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984467512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.984467512
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1335310031
Short name T320
Test name
Test status
Simulation time 1915843164 ps
CPU time 37.94 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 222488 kb
Host smart-66a4ab89-8cb4-4f13-8818-8b488031b50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335310031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1335310031
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1686529790
Short name T883
Test name
Test status
Simulation time 39855460 ps
CPU time 1.84 seconds
Started May 26 02:49:13 PM PDT 24
Finished May 26 02:49:16 PM PDT 24
Peak memory 206908 kb
Host smart-b8edbcd2-f5fa-4b5b-b8d8-63d9782f8201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686529790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1686529790
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4224664757
Short name T16
Test name
Test status
Simulation time 735727359 ps
CPU time 5.8 seconds
Started May 26 02:49:14 PM PDT 24
Finished May 26 02:49:20 PM PDT 24
Peak memory 208696 kb
Host smart-060a8fb2-508b-4315-8692-6cbff8b03e7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224664757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4224664757
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.678703591
Short name T611
Test name
Test status
Simulation time 188463902 ps
CPU time 6.7 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:17 PM PDT 24
Peak memory 208148 kb
Host smart-3c64c378-8816-4237-b0c2-abd7d5457297
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678703591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.678703591
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2252195389
Short name T427
Test name
Test status
Simulation time 177044418 ps
CPU time 2.91 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 206964 kb
Host smart-85c6fbed-1844-418c-b064-72c79ca57080
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252195389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2252195389
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.103304873
Short name T116
Test name
Test status
Simulation time 203860074 ps
CPU time 4.77 seconds
Started May 26 02:49:14 PM PDT 24
Finished May 26 02:49:19 PM PDT 24
Peak memory 208076 kb
Host smart-a108d646-2a97-4e9e-be0b-6e7425ea394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103304873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.103304873
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2628118994
Short name T901
Test name
Test status
Simulation time 350177573 ps
CPU time 2.95 seconds
Started May 26 02:49:13 PM PDT 24
Finished May 26 02:49:17 PM PDT 24
Peak memory 206912 kb
Host smart-28d1fcf9-b4dc-4798-ac44-b316f948b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628118994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2628118994
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4207551875
Short name T238
Test name
Test status
Simulation time 1167332012 ps
CPU time 21.22 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:32 PM PDT 24
Peak memory 221256 kb
Host smart-29aa7e15-9dea-4bb8-b7c3-68e273845c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207551875 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4207551875
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.449303932
Short name T703
Test name
Test status
Simulation time 72214261 ps
CPU time 3.37 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 208268 kb
Host smart-23222c30-ef12-444b-873f-43fb98209f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449303932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.449303932
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2031329043
Short name T491
Test name
Test status
Simulation time 166470281 ps
CPU time 2.43 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:12 PM PDT 24
Peak memory 211196 kb
Host smart-2508353a-f2ef-4954-a6f9-c76604a6103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031329043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2031329043
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.907603924
Short name T637
Test name
Test status
Simulation time 12877958 ps
CPU time 0.74 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 205980 kb
Host smart-40bf256a-123d-474f-8d8b-f567fa6200aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907603924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.907603924
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1698723291
Short name T914
Test name
Test status
Simulation time 475940534 ps
CPU time 14.45 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:36 PM PDT 24
Peak memory 214356 kb
Host smart-6a591d6f-469f-4031-a6b3-812bf3da9d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698723291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1698723291
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.749683645
Short name T64
Test name
Test status
Simulation time 82766755 ps
CPU time 3.79 seconds
Started May 26 02:49:22 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 214348 kb
Host smart-64b76bd1-05d1-4f1a-9fe9-3129b6a3606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749683645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.749683645
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4139098816
Short name T417
Test name
Test status
Simulation time 1251996024 ps
CPU time 4.91 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 208312 kb
Host smart-6612f9f8-90a2-415e-9080-cd665351fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139098816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4139098816
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2527601025
Short name T198
Test name
Test status
Simulation time 287047845 ps
CPU time 5.67 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 208344 kb
Host smart-743b2304-c650-42d0-b716-adb653b72c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527601025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2527601025
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3409751157
Short name T909
Test name
Test status
Simulation time 228862863 ps
CPU time 2.86 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 207000 kb
Host smart-4a959ba4-08ab-4639-9956-1bd39b2c1253
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409751157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3409751157
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1740745084
Short name T898
Test name
Test status
Simulation time 27413789 ps
CPU time 2.24 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 206964 kb
Host smart-f965edf2-f689-4218-90c2-936bb4516ee2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740745084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1740745084
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1185513544
Short name T543
Test name
Test status
Simulation time 850910195 ps
CPU time 27.4 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:48 PM PDT 24
Peak memory 208260 kb
Host smart-ce9fa4d8-d573-4fe7-a7c6-61419f0b15af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185513544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1185513544
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2974039243
Short name T564
Test name
Test status
Simulation time 133526029 ps
CPU time 2 seconds
Started May 26 02:49:21 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 207904 kb
Host smart-2c1375ce-e48e-4858-a749-5d2cfcbbe9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974039243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2974039243
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4115927002
Short name T643
Test name
Test status
Simulation time 199482109 ps
CPU time 5.48 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 206984 kb
Host smart-a14ca726-9d68-4629-bd11-afbe802d5776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115927002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4115927002
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3538898853
Short name T329
Test name
Test status
Simulation time 187277476 ps
CPU time 5.7 seconds
Started May 26 02:49:16 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 218164 kb
Host smart-c74e924c-920b-4bee-8de6-36b78f9de022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538898853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3538898853
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.596052373
Short name T65
Test name
Test status
Simulation time 82554617 ps
CPU time 3.32 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 210168 kb
Host smart-337f387b-0598-45af-85a0-8b23f74caac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596052373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.596052373
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2724391154
Short name T604
Test name
Test status
Simulation time 50708739 ps
CPU time 0.94 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 206004 kb
Host smart-42f032b3-a802-4d54-908c-0fc0fcbb133f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724391154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2724391154
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2178909957
Short name T325
Test name
Test status
Simulation time 178430637 ps
CPU time 3.38 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 214376 kb
Host smart-3b1e847d-f29e-475e-b94c-92134853760f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178909957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2178909957
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.760222979
Short name T570
Test name
Test status
Simulation time 45825910 ps
CPU time 2.14 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 218800 kb
Host smart-eb733470-3a38-4254-84dd-1846863afdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760222979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.760222979
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4184197387
Short name T813
Test name
Test status
Simulation time 302634163 ps
CPU time 3.98 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 209280 kb
Host smart-c8bda7b1-49c9-4173-a942-f678e104652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184197387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4184197387
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1713223983
Short name T260
Test name
Test status
Simulation time 161039020 ps
CPU time 2.83 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 222348 kb
Host smart-43d352e8-fda3-4814-9254-ef4e9f788ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713223983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1713223983
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3187309470
Short name T814
Test name
Test status
Simulation time 106214643 ps
CPU time 4.36 seconds
Started May 26 02:49:19 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 220200 kb
Host smart-b08a8d3c-a724-432f-a7d9-cd1384d0470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187309470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3187309470
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2960713953
Short name T535
Test name
Test status
Simulation time 2608307750 ps
CPU time 7.04 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:28 PM PDT 24
Peak memory 209304 kb
Host smart-5ba7c126-2772-4171-9525-1fa144691ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960713953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2960713953
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4294399880
Short name T440
Test name
Test status
Simulation time 771572192 ps
CPU time 17.1 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 208044 kb
Host smart-e34953ae-6248-449c-8611-14a9d390faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294399880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4294399880
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1597125552
Short name T562
Test name
Test status
Simulation time 258605980 ps
CPU time 4.27 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 208544 kb
Host smart-2e03c5f8-0b15-46e5-a944-e2f20782b970
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597125552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1597125552
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.573670356
Short name T663
Test name
Test status
Simulation time 558660118 ps
CPU time 4.41 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 208552 kb
Host smart-34f20305-f209-45ef-83ce-e08c34f3842a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573670356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.573670356
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.9707651
Short name T449
Test name
Test status
Simulation time 73577990 ps
CPU time 3.41 seconds
Started May 26 02:49:20 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 208652 kb
Host smart-f16a1a5b-f931-44dc-bd13-170c241740d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9707651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.9707651
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1835992222
Short name T421
Test name
Test status
Simulation time 142743239 ps
CPU time 3.62 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 209156 kb
Host smart-9382e75f-8471-4770-ab60-85e3c28514fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835992222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1835992222
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2595386487
Short name T219
Test name
Test status
Simulation time 68607612 ps
CPU time 3.19 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 209764 kb
Host smart-9fbf8440-70a0-4833-a240-5c0041c27d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595386487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2595386487
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.266939549
Short name T680
Test name
Test status
Simulation time 977689528 ps
CPU time 8.14 seconds
Started May 26 02:49:18 PM PDT 24
Finished May 26 02:49:28 PM PDT 24
Peak memory 209368 kb
Host smart-6880e350-edc2-41b4-a67e-a87fc39a8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266939549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.266939549
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3062205535
Short name T415
Test name
Test status
Simulation time 64944537 ps
CPU time 1.87 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 210268 kb
Host smart-64fb1011-4fa7-4dac-abc0-0f674d06256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062205535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3062205535
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3460108710
Short name T902
Test name
Test status
Simulation time 29998721 ps
CPU time 0.81 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:29 PM PDT 24
Peak memory 206008 kb
Host smart-502c053b-0307-48b0-8b65-4fab0a31e48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460108710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3460108710
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1710788508
Short name T36
Test name
Test status
Simulation time 150352569 ps
CPU time 1.27 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 208120 kb
Host smart-9a3e1114-8fc1-4fd3-b39b-f59a508b7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710788508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1710788508
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1119199786
Short name T662
Test name
Test status
Simulation time 639572306 ps
CPU time 5.72 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:36 PM PDT 24
Peak memory 214380 kb
Host smart-bd84e393-91ed-451a-a7d5-28e37632a7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119199786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1119199786
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3711752751
Short name T696
Test name
Test status
Simulation time 43631403 ps
CPU time 1.74 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 214288 kb
Host smart-19e1f246-f9c5-434a-a92a-5d334b7b7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711752751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3711752751
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3466271111
Short name T647
Test name
Test status
Simulation time 128360698 ps
CPU time 3.96 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 214392 kb
Host smart-d037be45-1f07-4d40-990e-a2a343524075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466271111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3466271111
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2889162935
Short name T264
Test name
Test status
Simulation time 57852851 ps
CPU time 2.72 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 214396 kb
Host smart-a66707f3-88e8-434e-9682-a993a2cff8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889162935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2889162935
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1838971546
Short name T724
Test name
Test status
Simulation time 143145588 ps
CPU time 6.03 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 218556 kb
Host smart-8de014cb-e77b-4562-a3fb-67cb33d40658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838971546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1838971546
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3598255932
Short name T891
Test name
Test status
Simulation time 90825275 ps
CPU time 3.21 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 208800 kb
Host smart-0d9bddff-cce2-4b17-9737-8d397cebc1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598255932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3598255932
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2070125269
Short name T230
Test name
Test status
Simulation time 1724338535 ps
CPU time 24.25 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:50:04 PM PDT 24
Peak memory 208500 kb
Host smart-0dafa676-ecbf-46db-89bf-0d2151c45ec3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070125269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2070125269
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2524756243
Short name T84
Test name
Test status
Simulation time 59862571 ps
CPU time 3.2 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 208752 kb
Host smart-d7acb056-908b-4630-9c41-4c3cc5f63b44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524756243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2524756243
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3817542765
Short name T300
Test name
Test status
Simulation time 204587359 ps
CPU time 5.75 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 208080 kb
Host smart-9c448749-e6f7-4792-8459-f5f43c9814ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817542765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3817542765
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1895135480
Short name T204
Test name
Test status
Simulation time 80650227 ps
CPU time 3.77 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 222564 kb
Host smart-0b6aedd7-f81e-423f-bfd4-99a3dd9c05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895135480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1895135480
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2345736349
Short name T404
Test name
Test status
Simulation time 55754433 ps
CPU time 2.03 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 206900 kb
Host smart-69065006-e7e6-4eb4-9b51-8a9b1391757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345736349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2345736349
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2408451549
Short name T75
Test name
Test status
Simulation time 6640259828 ps
CPU time 62.47 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 217008 kb
Host smart-f72699da-1adb-42d6-9bb9-291a502c7f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408451549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2408451549
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1308265852
Short name T109
Test name
Test status
Simulation time 795214213 ps
CPU time 16.95 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 220256 kb
Host smart-a8e0f556-1b89-4314-b161-deeec9e223ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308265852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1308265852
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.656083186
Short name T284
Test name
Test status
Simulation time 380049451 ps
CPU time 3.68 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 207372 kb
Host smart-c8fd9f88-7c6f-48f1-81af-c6b7fa9755cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656083186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.656083186
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1801992727
Short name T877
Test name
Test status
Simulation time 12251254 ps
CPU time 0.75 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 205980 kb
Host smart-04cf0173-f34e-4cfa-92b6-faa2308c68af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801992727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1801992727
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2588497439
Short name T369
Test name
Test status
Simulation time 1013021118 ps
CPU time 13.64 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:51 PM PDT 24
Peak memory 214268 kb
Host smart-daba2e55-8745-4ae9-bd4a-d0f46fdad244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588497439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2588497439
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2820795348
Short name T314
Test name
Test status
Simulation time 44273449 ps
CPU time 1.94 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:31 PM PDT 24
Peak memory 219940 kb
Host smart-33478f37-f4d1-41c7-bf17-d870ca320c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820795348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2820795348
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2913085823
Short name T68
Test name
Test status
Simulation time 4265507276 ps
CPU time 31.32 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 219284 kb
Host smart-c904ab31-7371-464d-8138-c206eef85f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913085823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2913085823
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.373001867
Short name T331
Test name
Test status
Simulation time 95405016 ps
CPU time 4.57 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 209360 kb
Host smart-7784d036-8dd7-4d3a-897c-f73979933265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373001867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.373001867
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.705233251
Short name T740
Test name
Test status
Simulation time 329542231 ps
CPU time 4.84 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 206756 kb
Host smart-8c475510-b67b-430e-8d70-e0a7b2ef0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705233251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.705233251
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2795850587
Short name T834
Test name
Test status
Simulation time 442390120 ps
CPU time 5.47 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 208284 kb
Host smart-274ac0d7-a347-4ecc-bf7a-6ab12298c070
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795850587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2795850587
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3851312323
Short name T605
Test name
Test status
Simulation time 97606078 ps
CPU time 2.93 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:33 PM PDT 24
Peak memory 207460 kb
Host smart-cb898736-6860-4fb0-8f60-cb9391842bef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851312323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3851312323
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2257649710
Short name T822
Test name
Test status
Simulation time 29955252 ps
CPU time 2.26 seconds
Started May 26 02:49:30 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 207060 kb
Host smart-61803483-b890-4cfd-8e78-9140fde086e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257649710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2257649710
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2692057126
Short name T438
Test name
Test status
Simulation time 2246490347 ps
CPU time 14.27 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 210160 kb
Host smart-1f2d495d-92d0-4632-a5cf-eadddc5d5fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692057126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2692057126
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2900311953
Short name T758
Test name
Test status
Simulation time 68990428 ps
CPU time 2.3 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 206880 kb
Host smart-430b26d4-1890-4c96-8c1f-d5c422f9fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900311953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2900311953
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1213323091
Short name T701
Test name
Test status
Simulation time 1109292367 ps
CPU time 9.32 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 215108 kb
Host smart-8a384598-816e-4465-9711-de2590bef8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213323091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1213323091
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.826177297
Short name T265
Test name
Test status
Simulation time 121379335 ps
CPU time 4.37 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 209448 kb
Host smart-b0683ea2-2e58-42ea-99ce-9d00b3b55fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826177297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.826177297
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3363192034
Short name T387
Test name
Test status
Simulation time 44821550 ps
CPU time 2.89 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 215544 kb
Host smart-5ef5cf10-fb1a-4b10-b79e-6023de848350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363192034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3363192034
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1641859871
Short name T19
Test name
Test status
Simulation time 195348517 ps
CPU time 3.05 seconds
Started May 26 02:49:25 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 214704 kb
Host smart-e19a80bc-0edf-4de3-bf08-5e0335f857e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641859871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1641859871
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2448223409
Short name T839
Test name
Test status
Simulation time 115864123 ps
CPU time 1.87 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:41 PM PDT 24
Peak memory 214356 kb
Host smart-f76a92b8-413e-4191-9965-b1cdf7bb5ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448223409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2448223409
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.299992548
Short name T346
Test name
Test status
Simulation time 56458920 ps
CPU time 2.92 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 221728 kb
Host smart-e1e1eef5-fa7c-4bed-b37c-d92bb249dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299992548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.299992548
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1017001612
Short name T716
Test name
Test status
Simulation time 547236440 ps
CPU time 5.82 seconds
Started May 26 02:49:28 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 210308 kb
Host smart-76868884-1114-4500-b548-e1f388bb692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017001612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1017001612
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3258294996
Short name T592
Test name
Test status
Simulation time 483637502 ps
CPU time 4.55 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 219696 kb
Host smart-a755f90f-4d0a-4dea-912e-f0210a5f18a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258294996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3258294996
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.142831685
Short name T237
Test name
Test status
Simulation time 42350321 ps
CPU time 2.38 seconds
Started May 26 02:49:29 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 206812 kb
Host smart-a21fb0ef-466e-498c-b7cc-d48f834db9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142831685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.142831685
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3315522782
Short name T563
Test name
Test status
Simulation time 40831675 ps
CPU time 2.41 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:32 PM PDT 24
Peak memory 207020 kb
Host smart-ab550462-2b0b-48a4-82df-fbbc0c75a726
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315522782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3315522782
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3894732432
Short name T236
Test name
Test status
Simulation time 554487371 ps
CPU time 13.04 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:50 PM PDT 24
Peak memory 208696 kb
Host smart-07f3867e-5432-45a6-9a14-6bcdb5847750
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894732432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3894732432
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3908026077
Short name T436
Test name
Test status
Simulation time 187136477 ps
CPU time 6.96 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 206856 kb
Host smart-a6e04890-00f4-4ac5-bd72-de60b9997a4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908026077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3908026077
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3423329806
Short name T197
Test name
Test status
Simulation time 75382038 ps
CPU time 2.55 seconds
Started May 26 02:49:26 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 214428 kb
Host smart-fbc9dccd-e829-4119-a452-bafab9e20ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423329806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3423329806
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3766100159
Short name T520
Test name
Test status
Simulation time 64932339 ps
CPU time 2.8 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:42 PM PDT 24
Peak memory 208416 kb
Host smart-a30b3c46-d917-429f-88ea-4dcf835d53fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766100159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3766100159
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.265935693
Short name T767
Test name
Test status
Simulation time 1281237526 ps
CPU time 11.43 seconds
Started May 26 02:49:40 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 222672 kb
Host smart-94ea0f32-fd3f-4ce0-bc6e-2ec38ea86791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265935693 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.265935693
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3634624773
Short name T135
Test name
Test status
Simulation time 2288466239 ps
CPU time 8.17 seconds
Started May 26 02:49:27 PM PDT 24
Finished May 26 02:49:38 PM PDT 24
Peak memory 218532 kb
Host smart-f63b6118-a3ac-4fe1-bf78-dbf8e45ffea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634624773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3634624773
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2889634977
Short name T465
Test name
Test status
Simulation time 333732272 ps
CPU time 6.94 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 210180 kb
Host smart-2ab959fb-2be7-4727-a858-4219fbd08e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889634977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2889634977
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3142178917
Short name T406
Test name
Test status
Simulation time 8922375 ps
CPU time 0.87 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 206000 kb
Host smart-4950ace8-eb70-4603-ad66-da7e6ca3d196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142178917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3142178917
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2113767261
Short name T815
Test name
Test status
Simulation time 188284389 ps
CPU time 2.95 seconds
Started May 26 02:49:39 PM PDT 24
Finished May 26 02:49:43 PM PDT 24
Peak memory 210220 kb
Host smart-00f45781-a88a-4217-af99-0dd8650c5e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113767261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2113767261
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1041706188
Short name T469
Test name
Test status
Simulation time 204684283 ps
CPU time 7.02 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 214368 kb
Host smart-b5e4700f-88f8-42a8-8973-8e656950df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041706188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1041706188
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2188311687
Short name T761
Test name
Test status
Simulation time 122702644 ps
CPU time 2.22 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 214452 kb
Host smart-a7b97d53-c4b3-4250-8ac4-85a598723a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188311687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2188311687
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3319944692
Short name T642
Test name
Test status
Simulation time 245835234 ps
CPU time 4.44 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:42 PM PDT 24
Peak memory 222376 kb
Host smart-41b9e020-1b0e-4a3b-9e84-703427ac476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319944692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3319944692
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2720698294
Short name T249
Test name
Test status
Simulation time 166141708 ps
CPU time 7.74 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 210932 kb
Host smart-fccb14d3-48b6-42c5-9a52-7d90f658fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720698294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2720698294
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2185721388
Short name T885
Test name
Test status
Simulation time 452676621 ps
CPU time 5.65 seconds
Started May 26 02:49:33 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 207976 kb
Host smart-bb166e81-0324-4acc-a054-1d069d4588a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185721388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2185721388
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2096448353
Short name T830
Test name
Test status
Simulation time 633613506 ps
CPU time 20.55 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 208888 kb
Host smart-04c0164a-8714-4bab-b088-7218ec0b3593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096448353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2096448353
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.534927934
Short name T254
Test name
Test status
Simulation time 7343838597 ps
CPU time 30.31 seconds
Started May 26 02:49:39 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 208816 kb
Host smart-88f9ffbe-5cbc-42f1-949e-05cc3c495117
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534927934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.534927934
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1418227333
Short name T889
Test name
Test status
Simulation time 81480610 ps
CPU time 3.71 seconds
Started May 26 02:49:33 PM PDT 24
Finished May 26 02:49:38 PM PDT 24
Peak memory 208616 kb
Host smart-c7d442ff-b925-48d3-9c79-98ba8072d3bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418227333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1418227333
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3927253588
Short name T900
Test name
Test status
Simulation time 385763423 ps
CPU time 3.26 seconds
Started May 26 02:49:32 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 207444 kb
Host smart-1979b3f1-2249-46bf-85ac-df4e87b8f3d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927253588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3927253588
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2991041718
Short name T545
Test name
Test status
Simulation time 17950692 ps
CPU time 1.76 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 215368 kb
Host smart-6eedfa50-d037-4427-923f-ec51930cefd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991041718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2991041718
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1295538035
Short name T569
Test name
Test status
Simulation time 129110229 ps
CPU time 2.49 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 208424 kb
Host smart-17938e90-19ea-4606-970e-fc16feca2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295538035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1295538035
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2592419754
Short name T514
Test name
Test status
Simulation time 2125963949 ps
CPU time 10.54 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 222616 kb
Host smart-27ee5f72-53c1-4610-b1cb-1cebce8ed1dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592419754 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2592419754
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2097286038
Short name T512
Test name
Test status
Simulation time 824451482 ps
CPU time 6.48 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 218372 kb
Host smart-732c9d7c-4263-476c-84af-7834b6b15b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097286038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2097286038
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3658865519
Short name T167
Test name
Test status
Simulation time 120461867 ps
CPU time 2.83 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:39 PM PDT 24
Peak memory 209832 kb
Host smart-3fa59089-f5d0-404d-9907-699081da3062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658865519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3658865519
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1442909477
Short name T470
Test name
Test status
Simulation time 55203799 ps
CPU time 0.93 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:41 PM PDT 24
Peak memory 206020 kb
Host smart-5a06fb7c-4fde-4875-9e21-a5742ec53407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442909477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1442909477
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.652339230
Short name T386
Test name
Test status
Simulation time 34981293 ps
CPU time 2.82 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:49:38 PM PDT 24
Peak memory 214364 kb
Host smart-a98a1b0b-af95-4771-bf21-674107a864c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652339230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.652339230
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2112166314
Short name T644
Test name
Test status
Simulation time 722599686 ps
CPU time 4.14 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 214408 kb
Host smart-567129b3-bfa1-4dc3-9028-ef2cf7d08728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112166314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2112166314
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3052643026
Short name T477
Test name
Test status
Simulation time 193034436 ps
CPU time 2.52 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:41 PM PDT 24
Peak memory 207572 kb
Host smart-7c731f99-9a7c-42bd-92dd-cc7f8417699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052643026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3052643026
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3072414324
Short name T349
Test name
Test status
Simulation time 61844417 ps
CPU time 2.23 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:41 PM PDT 24
Peak memory 214408 kb
Host smart-c00d6936-69bc-4983-8acd-a897de88b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072414324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3072414324
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.22445920
Short name T347
Test name
Test status
Simulation time 279967314 ps
CPU time 2.66 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:42 PM PDT 24
Peak memory 220636 kb
Host smart-cc2d05ea-2878-416c-a550-8347dfc53b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22445920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.22445920
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3323193424
Short name T616
Test name
Test status
Simulation time 686640077 ps
CPU time 4.77 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 222544 kb
Host smart-dc69fd06-cded-40d2-9e35-2fc5da778fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323193424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3323193424
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2557808556
Short name T541
Test name
Test status
Simulation time 478545734 ps
CPU time 6.36 seconds
Started May 26 02:49:32 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 209832 kb
Host smart-37f2141c-aad4-4f1a-a335-ff9ceabad855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557808556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2557808556
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3977871741
Short name T409
Test name
Test status
Simulation time 1408900730 ps
CPU time 8.88 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 207040 kb
Host smart-06daa70a-409f-4ba7-ab19-de49c62d35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977871741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3977871741
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1446436823
Short name T367
Test name
Test status
Simulation time 566222004 ps
CPU time 17.62 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 209100 kb
Host smart-556c20c4-cf7c-430e-8def-a107232bb72d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446436823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1446436823
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.124808290
Short name T844
Test name
Test status
Simulation time 29407032 ps
CPU time 2.17 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 208716 kb
Host smart-b62b8562-d591-4e86-be2d-825d188326d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124808290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.124808290
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.531592287
Short name T319
Test name
Test status
Simulation time 177256547 ps
CPU time 6.24 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 208572 kb
Host smart-f865adc8-7a07-4386-b1ab-060ea3bfb9c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531592287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.531592287
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.994566318
Short name T633
Test name
Test status
Simulation time 68630800 ps
CPU time 1.65 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:38 PM PDT 24
Peak memory 210272 kb
Host smart-bfa8de3c-d105-40de-a7ae-ffa17bdbd4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994566318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.994566318
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3330582533
Short name T362
Test name
Test status
Simulation time 76086398 ps
CPU time 2.41 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 208020 kb
Host smart-eff14b09-8402-46b5-8dbc-079548c59a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330582533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3330582533
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3058433180
Short name T582
Test name
Test status
Simulation time 183778131 ps
CPU time 5.6 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 209500 kb
Host smart-d3c5b66e-b1a0-40ab-9ff9-44f23dccfc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058433180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3058433180
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3675411704
Short name T12
Test name
Test status
Simulation time 886025123 ps
CPU time 27.19 seconds
Started May 26 02:49:38 PM PDT 24
Finished May 26 02:50:07 PM PDT 24
Peak memory 218296 kb
Host smart-d479ba63-7303-4e2d-8db1-55ec9d1438a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675411704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3675411704
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3108753848
Short name T62
Test name
Test status
Simulation time 400262548 ps
CPU time 2.58 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:40 PM PDT 24
Peak memory 210216 kb
Host smart-c2b19a1d-3829-4fd8-b65f-a19e16605af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108753848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3108753848
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.469687160
Short name T895
Test name
Test status
Simulation time 12880945 ps
CPU time 0.73 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 205996 kb
Host smart-b66bfc78-84f6-4bdb-abea-931087bd5199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469687160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.469687160
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3294106511
Short name T368
Test name
Test status
Simulation time 116211618 ps
CPU time 4.25 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:43 PM PDT 24
Peak memory 214880 kb
Host smart-3b574cb5-b2df-4559-a876-8f93b515e33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294106511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3294106511
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4236180356
Short name T712
Test name
Test status
Simulation time 85708926 ps
CPU time 2.04 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:49:43 PM PDT 24
Peak memory 208216 kb
Host smart-6d0e4c9c-7746-44d4-bc9c-927e82889f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236180356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4236180356
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3195367913
Short name T263
Test name
Test status
Simulation time 914965621 ps
CPU time 7.11 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 220880 kb
Host smart-abe8228e-daba-447e-9d1d-59ca922f81b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195367913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3195367913
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.157775955
Short name T247
Test name
Test status
Simulation time 101848160 ps
CPU time 2.14 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 211464 kb
Host smart-6c6d4e25-0816-41cc-9674-17c531364717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157775955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.157775955
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3012983845
Short name T626
Test name
Test status
Simulation time 38666566 ps
CPU time 2.82 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 210128 kb
Host smart-13d29ec5-8859-49cb-ad52-411504496b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012983845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3012983845
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2114083929
Short name T423
Test name
Test status
Simulation time 4743433903 ps
CPU time 8.93 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 209916 kb
Host smart-209cc8fe-25fc-4c58-a7f9-5ab3829ea6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114083929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2114083929
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1799076758
Short name T15
Test name
Test status
Simulation time 2294704773 ps
CPU time 16.98 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:49:59 PM PDT 24
Peak memory 208588 kb
Host smart-6c6800bc-69d0-4029-8d3a-1b6dffaa5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799076758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1799076758
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3993770625
Short name T571
Test name
Test status
Simulation time 1357845443 ps
CPU time 31.19 seconds
Started May 26 02:49:35 PM PDT 24
Finished May 26 02:50:08 PM PDT 24
Peak memory 208208 kb
Host smart-4774a75f-a998-486e-be4e-db0f372d434d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993770625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3993770625
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.324085441
Short name T202
Test name
Test status
Simulation time 99121790 ps
CPU time 2.12 seconds
Started May 26 02:49:37 PM PDT 24
Finished May 26 02:49:41 PM PDT 24
Peak memory 208856 kb
Host smart-ebf14bf0-7e52-482e-a975-3652104c3985
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324085441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.324085441
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3274572594
Short name T843
Test name
Test status
Simulation time 219269679 ps
CPU time 6.22 seconds
Started May 26 02:49:34 PM PDT 24
Finished May 26 02:49:42 PM PDT 24
Peak memory 208956 kb
Host smart-601df8d3-f83e-49d9-8a10-3767f94df514
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274572594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3274572594
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3814147719
Short name T445
Test name
Test status
Simulation time 194759298 ps
CPU time 2.51 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 218600 kb
Host smart-10bf185a-46b7-466b-bc11-8459f1de4db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814147719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3814147719
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.751824600
Short name T880
Test name
Test status
Simulation time 4189641633 ps
CPU time 9.39 seconds
Started May 26 02:49:36 PM PDT 24
Finished May 26 02:49:48 PM PDT 24
Peak memory 207948 kb
Host smart-4d2cafb2-536d-44f9-aa17-bb7eb0f10c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751824600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.751824600
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.232548876
Short name T868
Test name
Test status
Simulation time 694808664 ps
CPU time 11.1 seconds
Started May 26 02:49:44 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 222748 kb
Host smart-a069b258-c28e-44ac-8f56-84361cb10210
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232548876 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.232548876
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.736353931
Short name T433
Test name
Test status
Simulation time 1817399953 ps
CPU time 6.38 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:49 PM PDT 24
Peak memory 208132 kb
Host smart-4d501395-8bdb-4759-ac54-2bc1c86d88a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736353931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.736353931
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1067621401
Short name T612
Test name
Test status
Simulation time 49908281 ps
CPU time 1.49 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:49:43 PM PDT 24
Peak memory 209912 kb
Host smart-6f51e83a-a4e7-454c-8537-a301f9fdd854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067621401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1067621401
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1124288010
Short name T613
Test name
Test status
Simulation time 36374835 ps
CPU time 0.74 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 205976 kb
Host smart-a8b56118-2f6a-48b7-b506-6727a78aebf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124288010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1124288010
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2176876260
Short name T136
Test name
Test status
Simulation time 58495501 ps
CPU time 4 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 214528 kb
Host smart-a71ad4a2-4a5a-40cd-b813-10d7a9f8ea29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176876260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2176876260
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.496527210
Short name T784
Test name
Test status
Simulation time 7644980582 ps
CPU time 17.13 seconds
Started May 26 02:49:40 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 214764 kb
Host smart-3be8e8e0-f281-49c9-98dd-20fc331e29fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496527210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.496527210
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2187675117
Short name T70
Test name
Test status
Simulation time 44568960 ps
CPU time 2.17 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 218492 kb
Host smart-3a2013d9-1271-4806-8f74-0815372e78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187675117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2187675117
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2555610538
Short name T850
Test name
Test status
Simulation time 477292530 ps
CPU time 5.66 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 214372 kb
Host smart-a50da7a1-39e0-4712-b8a8-7e67ed568427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555610538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2555610538
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2095304271
Short name T723
Test name
Test status
Simulation time 230924939 ps
CPU time 3.52 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:48 PM PDT 24
Peak memory 214332 kb
Host smart-45f4aab3-6fe9-458b-ad10-f18a2f8a50cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095304271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2095304271
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3901930978
Short name T209
Test name
Test status
Simulation time 65584056 ps
CPU time 2.93 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 215176 kb
Host smart-4bd5ddbf-25cb-4489-ae31-b822e5c065b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901930978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3901930978
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1521735769
Short name T378
Test name
Test status
Simulation time 1181675722 ps
CPU time 28.93 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208072 kb
Host smart-1be3f44d-320d-4d8e-a73a-9422137bed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521735769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1521735769
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2340433771
Short name T267
Test name
Test status
Simulation time 131164416 ps
CPU time 3.4 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:48 PM PDT 24
Peak memory 206848 kb
Host smart-649be082-4ca5-4afd-ab4f-def9a42bb8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340433771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2340433771
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3082318829
Short name T395
Test name
Test status
Simulation time 2682158578 ps
CPU time 13.49 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 208024 kb
Host smart-5e005a68-0f86-479e-b564-8c171ea67a78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082318829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3082318829
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.758045046
Short name T911
Test name
Test status
Simulation time 1729765944 ps
CPU time 7.16 seconds
Started May 26 02:49:45 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 208972 kb
Host smart-363b2490-7b94-405c-8cf2-eb8825691061
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758045046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.758045046
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2118679595
Short name T473
Test name
Test status
Simulation time 13495827215 ps
CPU time 66.01 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 209260 kb
Host smart-83e92f59-aa05-48de-85ce-53ea53b49bf1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118679595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2118679595
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1677662094
Short name T447
Test name
Test status
Simulation time 147059605 ps
CPU time 1.91 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 207404 kb
Host smart-3eb5d42e-0f6a-4c78-aff5-ef5fdeca51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677662094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1677662094
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.388535907
Short name T622
Test name
Test status
Simulation time 1071336818 ps
CPU time 4.2 seconds
Started May 26 02:49:44 PM PDT 24
Finished May 26 02:49:49 PM PDT 24
Peak memory 207264 kb
Host smart-dce30ad6-fa2f-4060-8f9c-866a40812efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388535907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.388535907
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1706967195
Short name T812
Test name
Test status
Simulation time 1586901529 ps
CPU time 40.89 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 216740 kb
Host smart-7e882af6-f673-4c02-9557-5e16a4435d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706967195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1706967195
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.625273668
Short name T602
Test name
Test status
Simulation time 364400178 ps
CPU time 4.39 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 207576 kb
Host smart-4119ed9d-ea1c-453c-a442-8eee79750202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625273668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.625273668
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.471475681
Short name T871
Test name
Test status
Simulation time 388526287 ps
CPU time 2.05 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 207464 kb
Host smart-f9d8242b-3d31-404a-be14-68b66e90ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471475681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.471475681
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3333282310
Short name T854
Test name
Test status
Simulation time 35428640 ps
CPU time 0.85 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:44 PM PDT 24
Peak memory 206016 kb
Host smart-bcfa0b54-1b0c-4a10-bcf9-3b5d11356e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333282310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3333282310
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2992018416
Short name T507
Test name
Test status
Simulation time 106188407 ps
CPU time 2.31 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 208180 kb
Host smart-93b3c1b9-a077-4105-bff9-2bff74376d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992018416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2992018416
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3648360751
Short name T226
Test name
Test status
Simulation time 135936675 ps
CPU time 2.14 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 214368 kb
Host smart-fd5e3232-30e6-44c7-8b0c-148f2cffeca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648360751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3648360751
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2764345692
Short name T113
Test name
Test status
Simulation time 1286163365 ps
CPU time 2.82 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:48:40 PM PDT 24
Peak memory 214296 kb
Host smart-4b67c80f-1e07-4423-9fb1-efd792646baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764345692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2764345692
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2417250255
Short name T771
Test name
Test status
Simulation time 408421154 ps
CPU time 3.95 seconds
Started May 26 02:48:36 PM PDT 24
Finished May 26 02:48:41 PM PDT 24
Peak memory 209036 kb
Host smart-24e7aa09-31ab-4972-b603-764a59e4b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417250255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2417250255
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1561364625
Short name T333
Test name
Test status
Simulation time 687219094 ps
CPU time 9.74 seconds
Started May 26 02:48:36 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 208912 kb
Host smart-95bf788a-46a5-45df-8362-bf86553f3890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561364625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1561364625
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.834196687
Short name T9
Test name
Test status
Simulation time 455592073 ps
CPU time 11.42 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:56 PM PDT 24
Peak memory 238020 kb
Host smart-8486f300-efaf-4aca-a4ad-ec381008332e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834196687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.834196687
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3258206553
Short name T460
Test name
Test status
Simulation time 34553808 ps
CPU time 2.28 seconds
Started May 26 02:48:34 PM PDT 24
Finished May 26 02:48:38 PM PDT 24
Peak memory 207124 kb
Host smart-c6c9e7ec-d7eb-4038-9303-982fc369a821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258206553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3258206553
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2577200917
Short name T841
Test name
Test status
Simulation time 69129231 ps
CPU time 3.25 seconds
Started May 26 02:48:36 PM PDT 24
Finished May 26 02:48:41 PM PDT 24
Peak memory 208800 kb
Host smart-78208057-7510-4a37-bc3c-0d981e9107ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577200917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2577200917
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.998451613
Short name T112
Test name
Test status
Simulation time 4556957468 ps
CPU time 40.34 seconds
Started May 26 02:48:33 PM PDT 24
Finished May 26 02:49:14 PM PDT 24
Peak memory 208924 kb
Host smart-8eec7a26-fb30-42c7-bcf6-e8078b8e0ab6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998451613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.998451613
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2732382223
Short name T721
Test name
Test status
Simulation time 204377445 ps
CPU time 4.31 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:48:40 PM PDT 24
Peak memory 208124 kb
Host smart-49996505-e9ed-4e49-b7a2-adf0d0abcaaf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732382223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2732382223
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3757712511
Short name T875
Test name
Test status
Simulation time 312732089 ps
CPU time 1.87 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 207216 kb
Host smart-cc4d26c1-814d-4be0-a4cb-b0a08a398db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757712511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3757712511
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1167534094
Short name T131
Test name
Test status
Simulation time 145640547 ps
CPU time 3.78 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:48:40 PM PDT 24
Peak memory 208608 kb
Host smart-32fecdf0-908c-4a16-8861-ad3c951ea3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167534094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1167534094
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1332806948
Short name T339
Test name
Test status
Simulation time 3033709216 ps
CPU time 30.92 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:49:08 PM PDT 24
Peak memory 221804 kb
Host smart-d258d5c1-6fbb-4335-a4e6-3b34e1c292df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332806948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1332806948
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1439249537
Short name T115
Test name
Test status
Simulation time 972709975 ps
CPU time 6.69 seconds
Started May 26 02:48:34 PM PDT 24
Finished May 26 02:48:42 PM PDT 24
Peak memory 207952 kb
Host smart-ab768667-6e1a-4679-b4b0-a69d4808b376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439249537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1439249537
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2420658387
Short name T762
Test name
Test status
Simulation time 70954762 ps
CPU time 2.17 seconds
Started May 26 02:48:35 PM PDT 24
Finished May 26 02:48:39 PM PDT 24
Peak memory 210176 kb
Host smart-ecd48ffe-f2b5-4135-9cf6-ec4b443dd0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420658387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2420658387
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4147248441
Short name T789
Test name
Test status
Simulation time 62596671 ps
CPU time 0.83 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 205996 kb
Host smart-2447793d-c72c-497d-9b8f-f28a3918360e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147248441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4147248441
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3739996451
Short name T206
Test name
Test status
Simulation time 570467894 ps
CPU time 3.81 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:55 PM PDT 24
Peak memory 209520 kb
Host smart-d7c4969c-310f-4150-9e23-da4f4ded7205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739996451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3739996451
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2823878424
Short name T49
Test name
Test status
Simulation time 168399735 ps
CPU time 2.15 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 207624 kb
Host smart-de250586-4559-43ae-a629-40886a935aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823878424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2823878424
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.840710819
Short name T273
Test name
Test status
Simulation time 313709439 ps
CPU time 3.53 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 214452 kb
Host smart-d0cf64b1-9c9f-404b-ac11-04fc1415fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840710819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.840710819
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3372163400
Short name T899
Test name
Test status
Simulation time 202722528 ps
CPU time 3.03 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 214372 kb
Host smart-6eae7903-d327-4ac3-b4ea-75519d278b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372163400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3372163400
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.645350891
Short name T872
Test name
Test status
Simulation time 235843829 ps
CPU time 2.94 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 207708 kb
Host smart-064a1ed8-fa81-4947-9854-b59ea8ea6ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645350891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.645350891
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1375149902
Short name T1
Test name
Test status
Simulation time 141567556 ps
CPU time 4.23 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 205644 kb
Host smart-73bab1e4-33fd-435b-98a3-8c759c6f12c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375149902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1375149902
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3354773203
Short name T645
Test name
Test status
Simulation time 1110655362 ps
CPU time 3.81 seconds
Started May 26 02:49:44 PM PDT 24
Finished May 26 02:49:49 PM PDT 24
Peak memory 208572 kb
Host smart-b09eccb7-46df-418f-9ac6-cc46f1ef604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354773203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3354773203
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2054570072
Short name T463
Test name
Test status
Simulation time 106285045 ps
CPU time 3.72 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:49 PM PDT 24
Peak memory 206984 kb
Host smart-bd1ec85c-813d-48f7-8dad-0dee118d3401
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054570072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2054570072
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1087935227
Short name T456
Test name
Test status
Simulation time 484814578 ps
CPU time 2.8 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 205268 kb
Host smart-d0cd22f7-0c7d-4a0b-bd8d-b77be13acdb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087935227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1087935227
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2940977000
Short name T277
Test name
Test status
Simulation time 287214783 ps
CPU time 2.89 seconds
Started May 26 02:49:41 PM PDT 24
Finished May 26 02:49:45 PM PDT 24
Peak memory 208804 kb
Host smart-4ef4396d-9692-4f4a-bd2a-49db2525341f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940977000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2940977000
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4121590624
Short name T728
Test name
Test status
Simulation time 108262921 ps
CPU time 1.71 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 206988 kb
Host smart-7805771a-0489-4a32-937f-b677d47b953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121590624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4121590624
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1044859246
Short name T741
Test name
Test status
Simulation time 32296155 ps
CPU time 2.08 seconds
Started May 26 02:49:42 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 206956 kb
Host smart-3625e027-3174-4ea9-914d-5b7040ae8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044859246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1044859246
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.388670992
Short name T648
Test name
Test status
Simulation time 216459307 ps
CPU time 6.25 seconds
Started May 26 02:49:43 PM PDT 24
Finished May 26 02:49:51 PM PDT 24
Peak memory 208712 kb
Host smart-92f61030-c835-4c10-8412-71a3aa8305a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388670992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.388670992
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.268496050
Short name T863
Test name
Test status
Simulation time 185424528 ps
CPU time 2.53 seconds
Started May 26 02:49:51 PM PDT 24
Finished May 26 02:49:55 PM PDT 24
Peak memory 210356 kb
Host smart-bc87ef5e-407f-463d-bdef-9cd98d828e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268496050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.268496050
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.142981155
Short name T430
Test name
Test status
Simulation time 8841851 ps
CPU time 0.83 seconds
Started May 26 02:49:52 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 205992 kb
Host smart-cf6a21ed-48bd-44e2-a70f-74cc208127a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142981155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.142981155
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4002717062
Short name T18
Test name
Test status
Simulation time 204922239 ps
CPU time 4.81 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 221164 kb
Host smart-1be220ae-12b5-4cf5-bea1-c11657f7e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002717062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4002717062
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1747003096
Short name T666
Test name
Test status
Simulation time 256591796 ps
CPU time 5.41 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 208076 kb
Host smart-16bc2b6c-542c-475e-b271-cd3d3050680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747003096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1747003096
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.56327656
Short name T245
Test name
Test status
Simulation time 25158716 ps
CPU time 1.8 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 214368 kb
Host smart-c23710ce-7604-415e-b13d-7ee511b76a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56327656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.56327656
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2840940051
Short name T246
Test name
Test status
Simulation time 175355798 ps
CPU time 3.17 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:54 PM PDT 24
Peak memory 214352 kb
Host smart-60d9c55f-29a4-4a97-94e8-da57f2e8ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840940051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2840940051
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.807359804
Short name T494
Test name
Test status
Simulation time 59631857 ps
CPU time 2.92 seconds
Started May 26 02:49:52 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 209852 kb
Host smart-dae9d89a-31e5-452e-9295-ea9b4ecc305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807359804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.807359804
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2085690567
Short name T365
Test name
Test status
Simulation time 70072846 ps
CPU time 3.61 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 209420 kb
Host smart-c9ddc452-4ac4-485d-91cf-e6ba865a80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085690567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2085690567
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.732615659
Short name T434
Test name
Test status
Simulation time 660976407 ps
CPU time 2.53 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:54 PM PDT 24
Peak memory 206756 kb
Host smart-f24b2f97-799a-40a5-a61e-f5cf1db6f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732615659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.732615659
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1594965300
Short name T791
Test name
Test status
Simulation time 1479477437 ps
CPU time 5.56 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 208264 kb
Host smart-5f75587c-b026-45b4-9e66-dbcc66d46bcb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594965300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1594965300
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.579295059
Short name T17
Test name
Test status
Simulation time 171074285 ps
CPU time 4.98 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 208624 kb
Host smart-c8632f36-2634-4339-a225-33ea30cc3928
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579295059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.579295059
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.584057087
Short name T323
Test name
Test status
Simulation time 23851929 ps
CPU time 1.89 seconds
Started May 26 02:49:48 PM PDT 24
Finished May 26 02:49:51 PM PDT 24
Peak memory 207004 kb
Host smart-a2396f89-1760-4c8d-b316-b49d363fe342
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584057087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.584057087
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1209245057
Short name T519
Test name
Test status
Simulation time 83008228 ps
CPU time 1.86 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 207056 kb
Host smart-05d57388-b215-41f7-a287-d597883d52a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209245057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1209245057
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1091270929
Short name T786
Test name
Test status
Simulation time 1484168247 ps
CPU time 4.31 seconds
Started May 26 02:49:52 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 206868 kb
Host smart-baa804cc-e9bf-47de-9ef0-0edf342ed5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091270929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1091270929
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3334346598
Short name T835
Test name
Test status
Simulation time 272892877 ps
CPU time 9.69 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 222732 kb
Host smart-4869e2f9-b61b-40ea-b3d7-373333d55a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334346598 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3334346598
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.476881065
Short name T244
Test name
Test status
Simulation time 59750163 ps
CPU time 3.25 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:55 PM PDT 24
Peak memory 210392 kb
Host smart-e58e9497-4387-475f-a187-1b39eda79b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476881065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.476881065
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.307427527
Short name T104
Test name
Test status
Simulation time 35686790 ps
CPU time 0.74 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 205984 kb
Host smart-0ed4896d-8fba-41d0-8763-dccc470415ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307427527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.307427527
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1923475930
Short name T350
Test name
Test status
Simulation time 111817476 ps
CPU time 2.54 seconds
Started May 26 02:49:51 PM PDT 24
Finished May 26 02:49:55 PM PDT 24
Peak memory 214368 kb
Host smart-d2a01259-c6f3-4076-8421-515fa04e487a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923475930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1923475930
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2606874167
Short name T220
Test name
Test status
Simulation time 1140454755 ps
CPU time 3.42 seconds
Started May 26 02:49:56 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 218356 kb
Host smart-9b984ed2-78da-4f62-87b8-0d0d3f208a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606874167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2606874167
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3282956802
Short name T540
Test name
Test status
Simulation time 70326151 ps
CPU time 2.88 seconds
Started May 26 02:49:54 PM PDT 24
Finished May 26 02:49:58 PM PDT 24
Peak memory 210556 kb
Host smart-282451c7-b27e-4b18-86b2-15e85ee1903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282956802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3282956802
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3735248907
Short name T91
Test name
Test status
Simulation time 120440524 ps
CPU time 2.1 seconds
Started May 26 02:49:51 PM PDT 24
Finished May 26 02:49:55 PM PDT 24
Peak memory 214392 kb
Host smart-61ba9723-ec4d-4fe0-8c19-a6d55083bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735248907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3735248907
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3119332247
Short name T783
Test name
Test status
Simulation time 52475091 ps
CPU time 3.3 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 214412 kb
Host smart-f523bb0d-360f-452c-beac-21f64538aeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119332247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3119332247
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.4098934886
Short name T743
Test name
Test status
Simulation time 82413162 ps
CPU time 3.14 seconds
Started May 26 02:49:52 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 207624 kb
Host smart-ff15eee2-2f24-4f8b-8f6c-169154c78b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098934886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4098934886
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2653997670
Short name T566
Test name
Test status
Simulation time 268010180 ps
CPU time 8.52 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 209496 kb
Host smart-2f33673b-1dea-49a4-bad3-2a1b31538421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653997670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2653997670
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3341227603
Short name T480
Test name
Test status
Simulation time 73958452 ps
CPU time 1.73 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:49:56 PM PDT 24
Peak memory 206976 kb
Host smart-a03913e2-6414-4f94-8684-7015cf04b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341227603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3341227603
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.785857584
Short name T879
Test name
Test status
Simulation time 822139477 ps
CPU time 5.91 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 208024 kb
Host smart-a29acb37-2ab1-4617-a49e-4a3c5e59d58b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785857584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.785857584
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3346425729
Short name T710
Test name
Test status
Simulation time 124775411 ps
CPU time 3.25 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:49:53 PM PDT 24
Peak memory 206848 kb
Host smart-ceb5d8ea-a319-4eae-ba9b-f54c4040c63a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346425729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3346425729
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.11068554
Short name T425
Test name
Test status
Simulation time 347870636 ps
CPU time 1.95 seconds
Started May 26 02:49:53 PM PDT 24
Finished May 26 02:49:57 PM PDT 24
Peak memory 207268 kb
Host smart-87101423-548a-4449-868a-122a611b078f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.11068554
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2561036452
Short name T397
Test name
Test status
Simulation time 107243853 ps
CPU time 3.63 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:04 PM PDT 24
Peak memory 218480 kb
Host smart-45fac986-dd70-4367-9474-537786efb26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561036452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2561036452
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.67489775
Short name T807
Test name
Test status
Simulation time 2386156202 ps
CPU time 3.87 seconds
Started May 26 02:49:50 PM PDT 24
Finished May 26 02:49:54 PM PDT 24
Peak memory 206964 kb
Host smart-14793913-35f3-455e-be17-baad3c59c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67489775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.67489775
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2127212570
Short name T597
Test name
Test status
Simulation time 4748729260 ps
CPU time 21.69 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:22 PM PDT 24
Peak memory 221536 kb
Host smart-e23de6f1-d531-4a73-ac22-cdbb2d8f1f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127212570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2127212570
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1719492414
Short name T63
Test name
Test status
Simulation time 1771492586 ps
CPU time 21.89 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:22 PM PDT 24
Peak memory 220776 kb
Host smart-e4af886e-dd77-4ade-9db0-d86afad62297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719492414 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1719492414
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3940175675
Short name T561
Test name
Test status
Simulation time 789673720 ps
CPU time 9.89 seconds
Started May 26 02:49:49 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 218584 kb
Host smart-c1a8df2c-dad2-4364-8384-2feb875b29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940175675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3940175675
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3680715691
Short name T163
Test name
Test status
Simulation time 552301866 ps
CPU time 8.88 seconds
Started May 26 02:50:01 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 211096 kb
Host smart-08e9ee8a-3770-4fe8-9d1f-3a99223290b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680715691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3680715691
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.460285227
Short name T842
Test name
Test status
Simulation time 61573450 ps
CPU time 0.95 seconds
Started May 26 02:50:00 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 206112 kb
Host smart-831d7498-204a-40e6-8e50-4f33c749959f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460285227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.460285227
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.567506049
Short name T382
Test name
Test status
Simulation time 61300440 ps
CPU time 2.48 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 214404 kb
Host smart-d77d4b4c-a868-47b1-9ee3-a1b8aa3c09d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567506049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.567506049
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3161539760
Short name T22
Test name
Test status
Simulation time 1425447274 ps
CPU time 10.66 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:08 PM PDT 24
Peak memory 217936 kb
Host smart-04f518bd-cd33-4456-a8ef-aace37ed1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161539760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3161539760
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3426553212
Short name T651
Test name
Test status
Simulation time 256861903 ps
CPU time 2.64 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 208200 kb
Host smart-a350d37e-885f-42ee-9ec9-e6a7ee9b8ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426553212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3426553212
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.830792223
Short name T100
Test name
Test status
Simulation time 87176798 ps
CPU time 4.42 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:05 PM PDT 24
Peak memory 214356 kb
Host smart-3bab3ba4-7a89-458d-a7f9-b68f7fd4acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830792223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.830792223
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.658533441
Short name T258
Test name
Test status
Simulation time 567607145 ps
CPU time 4.79 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:05 PM PDT 24
Peak memory 214300 kb
Host smart-2b12e312-1e20-49cc-81e8-a329b7bf9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658533441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.658533441
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4140002689
Short name T678
Test name
Test status
Simulation time 187841815 ps
CPU time 3.33 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 214356 kb
Host smart-d0057e58-6127-4f04-989e-e04512dbe43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140002689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4140002689
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1903415714
Short name T452
Test name
Test status
Simulation time 11031945307 ps
CPU time 121.11 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:52:00 PM PDT 24
Peak memory 214376 kb
Host smart-583da59c-6355-47ca-adfa-8a99c6a26bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903415714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1903415714
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1697417599
Short name T808
Test name
Test status
Simulation time 94823740 ps
CPU time 3.44 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 208084 kb
Host smart-a1482d03-b70d-4e40-9b9c-ede4ed5dba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697417599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1697417599
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.704375105
Short name T108
Test name
Test status
Simulation time 555485081 ps
CPU time 14.86 seconds
Started May 26 02:50:00 PM PDT 24
Finished May 26 02:50:16 PM PDT 24
Peak memory 208916 kb
Host smart-900ae421-c4b7-4ee8-a340-52cddb69a803
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704375105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.704375105
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.570251894
Short name T797
Test name
Test status
Simulation time 193285299 ps
CPU time 6.81 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:07 PM PDT 24
Peak memory 207024 kb
Host smart-1e4a26b9-83a2-455b-9e6c-ee4e481ef832
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570251894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.570251894
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3482018206
Short name T859
Test name
Test status
Simulation time 259108344 ps
CPU time 3.13 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 207056 kb
Host smart-92aa1955-e294-4e9c-88d2-e8f867e1c2a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482018206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3482018206
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3744664178
Short name T392
Test name
Test status
Simulation time 497639298 ps
CPU time 3.67 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:04 PM PDT 24
Peak memory 207656 kb
Host smart-2d7e2246-06ef-4dbc-a7e2-62cafdcea1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744664178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3744664178
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.977006827
Short name T873
Test name
Test status
Simulation time 1764543727 ps
CPU time 29.05 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 208748 kb
Host smart-35b9fb15-cec2-462f-878f-6ebb4183a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977006827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.977006827
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3890476611
Short name T669
Test name
Test status
Simulation time 4096855410 ps
CPU time 94.62 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:51:36 PM PDT 24
Peak memory 216956 kb
Host smart-0e5399df-c669-4497-bd58-cda2e8aed6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890476611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3890476611
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.751398438
Short name T640
Test name
Test status
Simulation time 95067612 ps
CPU time 3.5 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 207600 kb
Host smart-3cc19684-21b1-4e44-ae86-5962da5e8896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751398438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.751398438
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.786418210
Short name T634
Test name
Test status
Simulation time 19566216 ps
CPU time 0.8 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 205952 kb
Host smart-d286f33b-a70d-438f-b6ed-14b0abfd58af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786418210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.786418210
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.731844643
Short name T71
Test name
Test status
Simulation time 48675757 ps
CPU time 1.58 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:07 PM PDT 24
Peak memory 222852 kb
Host smart-e6dad2d1-48b4-4334-b8b2-8fbcc68a7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731844643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.731844643
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1080078890
Short name T280
Test name
Test status
Simulation time 295150382 ps
CPU time 2.46 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 207656 kb
Host smart-e4ac2f5c-a2af-425a-9af1-d781369566aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080078890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1080078890
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3456095383
Short name T684
Test name
Test status
Simulation time 100919412 ps
CPU time 2.67 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 214304 kb
Host smart-ad985285-43ed-403d-9d5e-f6c128d79964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456095383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3456095383
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3017196262
Short name T208
Test name
Test status
Simulation time 1038676567 ps
CPU time 3.22 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 214388 kb
Host smart-1d6d6a93-c010-4f66-9fa3-2df321196b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017196262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3017196262
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.330379757
Short name T467
Test name
Test status
Simulation time 179143207 ps
CPU time 4.43 seconds
Started May 26 02:50:01 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 218092 kb
Host smart-53377f70-b7d3-4e89-80f0-68a1d937c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330379757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.330379757
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2101888040
Short name T903
Test name
Test status
Simulation time 186542771 ps
CPU time 2.71 seconds
Started May 26 02:49:58 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 206820 kb
Host smart-5fbea91a-5836-497e-95c8-a9e413f41bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101888040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2101888040
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2365210557
Short name T286
Test name
Test status
Simulation time 48790301 ps
CPU time 2.85 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 206876 kb
Host smart-81312fcb-fb2b-4f77-8e88-77fe45636e65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365210557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2365210557
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3954425193
Short name T579
Test name
Test status
Simulation time 230743256 ps
CPU time 7.12 seconds
Started May 26 02:49:57 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 208140 kb
Host smart-9a7df88f-cd29-413f-8cc5-7fb8ad7d76a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954425193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3954425193
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1556114942
Short name T686
Test name
Test status
Simulation time 171810013 ps
CPU time 3.07 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:04 PM PDT 24
Peak memory 206984 kb
Host smart-ec3f232a-5078-440a-9f3e-eac07353b9dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556114942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1556114942
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.494160459
Short name T250
Test name
Test status
Simulation time 574175842 ps
CPU time 4.81 seconds
Started May 26 02:50:11 PM PDT 24
Finished May 26 02:50:17 PM PDT 24
Peak memory 214472 kb
Host smart-f5506595-c7c1-463b-b409-9bd2fa40a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494160459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.494160459
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3492929334
Short name T405
Test name
Test status
Simulation time 55019143 ps
CPU time 2.55 seconds
Started May 26 02:49:59 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 208584 kb
Host smart-f463e08e-6370-4e2b-aa79-7c9eb40e24f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492929334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3492929334
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.497250899
Short name T257
Test name
Test status
Simulation time 1558845012 ps
CPU time 33.51 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:40 PM PDT 24
Peak memory 215404 kb
Host smart-98a6d3c6-87d0-478b-a7de-dc081f9ef7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497250899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.497250899
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.21351534
Short name T785
Test name
Test status
Simulation time 68552042 ps
CPU time 3.71 seconds
Started May 26 02:50:01 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 207840 kb
Host smart-7ce424fa-26cc-4e00-92f5-bf46546e3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21351534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.21351534
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3196540263
Short name T34
Test name
Test status
Simulation time 40607492 ps
CPU time 1.92 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:08 PM PDT 24
Peak memory 210036 kb
Host smart-b019a074-0ff3-49e8-a33c-fdac5aa903af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196540263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3196540263
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.859419952
Short name T668
Test name
Test status
Simulation time 97557551 ps
CPU time 0.82 seconds
Started May 26 02:50:08 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 205984 kb
Host smart-23440f2b-7206-4f00-b10b-de2842965711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859419952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.859419952
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1927708996
Short name T413
Test name
Test status
Simulation time 351023200 ps
CPU time 2.79 seconds
Started May 26 02:50:04 PM PDT 24
Finished May 26 02:50:07 PM PDT 24
Peak memory 220916 kb
Host smart-93764058-7a36-49f3-89c7-68979fa10d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927708996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1927708996
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3458510136
Short name T304
Test name
Test status
Simulation time 24843582 ps
CPU time 1.37 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 208108 kb
Host smart-00efa040-7444-4788-800e-613fef50af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458510136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3458510136
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2532668585
Short name T788
Test name
Test status
Simulation time 296633853 ps
CPU time 3.52 seconds
Started May 26 02:50:04 PM PDT 24
Finished May 26 02:50:09 PM PDT 24
Peak memory 216816 kb
Host smart-2f80df21-8557-4c57-8c31-140c22c4f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532668585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2532668585
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3160437707
Short name T694
Test name
Test status
Simulation time 447035432 ps
CPU time 6.39 seconds
Started May 26 02:50:11 PM PDT 24
Finished May 26 02:50:18 PM PDT 24
Peak memory 208208 kb
Host smart-b4f8864d-c23c-44ad-a1ff-11d9432a942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160437707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3160437707
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3036801737
Short name T630
Test name
Test status
Simulation time 143612156 ps
CPU time 2.37 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 206936 kb
Host smart-2fc7a3bb-1e4c-451f-9dc2-2a10da84eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036801737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3036801737
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1845340424
Short name T439
Test name
Test status
Simulation time 109144644 ps
CPU time 4.25 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 208412 kb
Host smart-89e8c3b2-8d27-4d29-985e-303ab2e908d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845340424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1845340424
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2683829865
Short name T557
Test name
Test status
Simulation time 743549543 ps
CPU time 4.15 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:12 PM PDT 24
Peak memory 208788 kb
Host smart-78cbea73-8bbe-45d8-b781-0e4a038eea39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683829865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2683829865
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1615439258
Short name T574
Test name
Test status
Simulation time 341545375 ps
CPU time 1.9 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 206972 kb
Host smart-dc9aea95-251a-4960-bad7-d2210510bef4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615439258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1615439258
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1294419621
Short name T739
Test name
Test status
Simulation time 361892957 ps
CPU time 5.44 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:14 PM PDT 24
Peak memory 208640 kb
Host smart-28f3125c-078e-4e04-953b-622c98005e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294419621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1294419621
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2812007828
Short name T744
Test name
Test status
Simulation time 994523902 ps
CPU time 4.27 seconds
Started May 26 02:50:08 PM PDT 24
Finished May 26 02:50:13 PM PDT 24
Peak memory 206796 kb
Host smart-fdfb652f-1527-4685-bf4e-25792f3fec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812007828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2812007828
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.586506327
Short name T751
Test name
Test status
Simulation time 93112869 ps
CPU time 3.09 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 208664 kb
Host smart-2e30a767-2902-4d08-80d2-c112ad0582e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586506327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.586506327
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1181695099
Short name T858
Test name
Test status
Simulation time 1155988870 ps
CPU time 14.43 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 222592 kb
Host smart-020413c6-574a-4ef7-98bc-651c644fe325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181695099 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1181695099
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2488560865
Short name T134
Test name
Test status
Simulation time 472479230 ps
CPU time 4.87 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 214384 kb
Host smart-ca404c91-68ff-496b-9db9-8fdcfc388e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488560865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2488560865
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1637620569
Short name T824
Test name
Test status
Simulation time 119123886 ps
CPU time 3.05 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 209968 kb
Host smart-a24c7323-3b10-4e2d-b261-777731bc35d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637620569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1637620569
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1452335323
Short name T482
Test name
Test status
Simulation time 46654600 ps
CPU time 0.75 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 205960 kb
Host smart-a7f27c4e-eb5e-48ec-907b-57a43f3b7c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452335323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1452335323
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2592373752
Short name T711
Test name
Test status
Simulation time 66263908 ps
CPU time 2.74 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 214668 kb
Host smart-c8fe0d51-51d2-4977-a57e-292a007c0494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592373752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2592373752
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2113016437
Short name T508
Test name
Test status
Simulation time 233667392 ps
CPU time 3.84 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:12 PM PDT 24
Peak memory 222524 kb
Host smart-6f10d5c0-2e97-4769-8b66-a3d5e2efe21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113016437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2113016437
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2757172614
Short name T867
Test name
Test status
Simulation time 147553099 ps
CPU time 3.35 seconds
Started May 26 02:50:04 PM PDT 24
Finished May 26 02:50:09 PM PDT 24
Peak memory 214336 kb
Host smart-a7fb7317-dc13-4595-8f71-d934cc0218e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757172614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2757172614
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2412019041
Short name T882
Test name
Test status
Simulation time 426512750 ps
CPU time 3.6 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:12 PM PDT 24
Peak memory 214360 kb
Host smart-74b02572-0c44-4bf8-87a1-35fd4bb08561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412019041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2412019041
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1441642253
Short name T307
Test name
Test status
Simulation time 109213070 ps
CPU time 4.75 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 214332 kb
Host smart-2dd07ee0-cb90-48bc-974b-b0b17dda4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441642253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1441642253
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1888182425
Short name T517
Test name
Test status
Simulation time 509358982 ps
CPU time 3.96 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 214484 kb
Host smart-94e67aea-11ac-49ec-a1e8-935fea2841fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888182425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1888182425
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3562391809
Short name T195
Test name
Test status
Simulation time 250136895 ps
CPU time 3.77 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:12 PM PDT 24
Peak memory 207644 kb
Host smart-bacef7ca-19d9-4503-bc51-cc8a9d685228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562391809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3562391809
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.494408468
Short name T627
Test name
Test status
Simulation time 242323398 ps
CPU time 6.23 seconds
Started May 26 02:50:05 PM PDT 24
Finished May 26 02:50:13 PM PDT 24
Peak memory 208712 kb
Host smart-a950c2d4-8d0f-4fc1-9c9b-e32f78d87fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494408468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.494408468
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2430266764
Short name T235
Test name
Test status
Simulation time 273495952 ps
CPU time 7.36 seconds
Started May 26 02:50:08 PM PDT 24
Finished May 26 02:50:17 PM PDT 24
Peak memory 208444 kb
Host smart-edc6bfe6-d6d5-458c-bb5a-a547131acc9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430266764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2430266764
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.828787404
Short name T537
Test name
Test status
Simulation time 1809732055 ps
CPU time 25.04 seconds
Started May 26 02:50:04 PM PDT 24
Finished May 26 02:50:30 PM PDT 24
Peak memory 208936 kb
Host smart-6f75aaef-3314-404e-aff3-ae6171db8767
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828787404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.828787404
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3085847015
Short name T685
Test name
Test status
Simulation time 174987260 ps
CPU time 5.31 seconds
Started May 26 02:50:04 PM PDT 24
Finished May 26 02:50:10 PM PDT 24
Peak memory 208868 kb
Host smart-0c658e43-b674-4543-84b0-be9f1352b938
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085847015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3085847015
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.90698580
Short name T546
Test name
Test status
Simulation time 54155201 ps
CPU time 2.19 seconds
Started May 26 02:50:08 PM PDT 24
Finished May 26 02:50:11 PM PDT 24
Peak memory 208276 kb
Host smart-14d70555-8bec-4acc-bb9c-23a4510732a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90698580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.90698580
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1217760980
Short name T461
Test name
Test status
Simulation time 1211330498 ps
CPU time 18.73 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 208504 kb
Host smart-0d3edda4-8012-4b2c-8100-e95e80da4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217760980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1217760980
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.999568533
Short name T241
Test name
Test status
Simulation time 1029850114 ps
CPU time 36.91 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 222568 kb
Host smart-34359f9a-1353-4039-b068-60ce4f8485ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999568533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.999568533
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2993970756
Short name T510
Test name
Test status
Simulation time 2129787100 ps
CPU time 56 seconds
Started May 26 02:50:07 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 210512 kb
Host smart-135324e6-582a-48cd-b0b9-f473a5be900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993970756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2993970756
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1365687486
Short name T774
Test name
Test status
Simulation time 197670375 ps
CPU time 1.83 seconds
Started May 26 02:50:06 PM PDT 24
Finished May 26 02:50:09 PM PDT 24
Peak memory 210216 kb
Host smart-2214f63b-ba8f-4c57-abb0-535326afcc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365687486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1365687486
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3461666244
Short name T672
Test name
Test status
Simulation time 34474116 ps
CPU time 0.92 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 206156 kb
Host smart-35714ad6-b2f5-47d4-99b4-8c072ed35013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461666244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3461666244
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2193342617
Short name T139
Test name
Test status
Simulation time 123311700 ps
CPU time 4.39 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 215720 kb
Host smart-8a63576c-ff23-4182-9caa-654a11cfdf17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193342617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2193342617
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3997965371
Short name T30
Test name
Test status
Simulation time 683834869 ps
CPU time 10.75 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:30 PM PDT 24
Peak memory 209264 kb
Host smart-9b481337-9e1f-4573-be2c-6463eb7ed6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997965371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3997965371
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3307104517
Short name T532
Test name
Test status
Simulation time 91620888 ps
CPU time 2.25 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:18 PM PDT 24
Peak memory 208384 kb
Host smart-44b7317a-3261-4a54-8c54-3299871fa3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307104517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3307104517
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.710672951
Short name T551
Test name
Test status
Simulation time 58161058 ps
CPU time 3.08 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 214340 kb
Host smart-8e625988-810a-49a9-bbfb-8807d636ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710672951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.710672951
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.586020908
Short name T216
Test name
Test status
Simulation time 1103163307 ps
CPU time 9.11 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 214544 kb
Host smart-3f384364-13f1-422e-b809-9e48814851ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586020908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.586020908
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1368868294
Short name T82
Test name
Test status
Simulation time 394652135 ps
CPU time 4.83 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 209288 kb
Host smart-768798e5-d9a8-4b2e-84a4-6926c2c413ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368868294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1368868294
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2807492576
Short name T251
Test name
Test status
Simulation time 865725375 ps
CPU time 16.44 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 208840 kb
Host smart-c00222ba-fc59-4278-aad0-67626d70a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807492576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2807492576
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.233724234
Short name T588
Test name
Test status
Simulation time 199813993 ps
CPU time 7.27 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:25 PM PDT 24
Peak memory 208508 kb
Host smart-38519fea-3005-4718-9532-4704d829a0d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233724234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.233724234
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1518244076
Short name T337
Test name
Test status
Simulation time 245131354 ps
CPU time 5.78 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 208640 kb
Host smart-e3da23f7-5fb6-4795-94cb-21a2bcce2b35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518244076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1518244076
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4116441915
Short name T511
Test name
Test status
Simulation time 50578189 ps
CPU time 2.78 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 206928 kb
Host smart-4848e19e-38b3-45c2-aacc-de3cbf1819ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116441915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4116441915
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2716949680
Short name T506
Test name
Test status
Simulation time 183316772 ps
CPU time 4.12 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 209000 kb
Host smart-4e53f1bb-1fe6-4870-b68e-4f8a8916de60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716949680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2716949680
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.326011756
Short name T550
Test name
Test status
Simulation time 155989872 ps
CPU time 2.12 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:17 PM PDT 24
Peak memory 207140 kb
Host smart-5e2c4d84-b891-4813-adb0-57a7c44f4e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326011756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.326011756
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1823710405
Short name T59
Test name
Test status
Simulation time 637846109 ps
CPU time 23.25 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:38 PM PDT 24
Peak memory 214440 kb
Host smart-30da175c-584a-4cce-8ffc-d3783de0d9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823710405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1823710405
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.264599024
Short name T809
Test name
Test status
Simulation time 541747409 ps
CPU time 7.58 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 222544 kb
Host smart-5b0d8041-108b-4c93-a20c-d20183cd2bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264599024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.264599024
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.479737250
Short name T356
Test name
Test status
Simulation time 87128357 ps
CPU time 2.17 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 210068 kb
Host smart-1fa3ff3e-96db-4876-b6ef-515b346a38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479737250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.479737250
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.468673625
Short name T855
Test name
Test status
Simulation time 17480437 ps
CPU time 1.03 seconds
Started May 26 02:50:19 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 206176 kb
Host smart-7f4176dc-0221-4d92-8456-a2736209e2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468673625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.468673625
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.194997339
Short name T67
Test name
Test status
Simulation time 3719325287 ps
CPU time 12.47 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 209780 kb
Host smart-8ccd5f21-7e50-44a6-8b97-039e9533c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194997339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.194997339
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1529581044
Short name T732
Test name
Test status
Simulation time 121870401 ps
CPU time 2.94 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 214496 kb
Host smart-44d37ca5-37f5-477c-ba5d-f97729235988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529581044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1529581044
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4289889266
Short name T763
Test name
Test status
Simulation time 228269037 ps
CPU time 5.23 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 222444 kb
Host smart-bef3ae43-39ee-4d83-83a5-a70bac95b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289889266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4289889266
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1812681769
Short name T475
Test name
Test status
Simulation time 40069935 ps
CPU time 2.44 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 219660 kb
Host smart-541f52a1-87ba-44bc-b67d-e269e38a4b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812681769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1812681769
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2081109218
Short name T609
Test name
Test status
Simulation time 167815550 ps
CPU time 3.66 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 207468 kb
Host smart-c3a03386-9d2f-45a3-bab9-9432f4e7c4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081109218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2081109218
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.4286622297
Short name T831
Test name
Test status
Simulation time 182102980 ps
CPU time 2.75 seconds
Started May 26 02:50:13 PM PDT 24
Finished May 26 02:50:17 PM PDT 24
Peak memory 206932 kb
Host smart-785f9870-f3e1-4677-b065-65bddb2d980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286622297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.4286622297
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3058305878
Short name T621
Test name
Test status
Simulation time 185734053 ps
CPU time 7.2 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 206964 kb
Host smart-e7ac3865-5a6b-4ba0-a5d3-d3d67d4bc8b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058305878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3058305878
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1326866848
Short name T297
Test name
Test status
Simulation time 163929182 ps
CPU time 4.55 seconds
Started May 26 02:50:13 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 209040 kb
Host smart-cf5ddb03-e4b2-458a-92c7-868c203b44d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326866848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1326866848
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.428251746
Short name T489
Test name
Test status
Simulation time 43523501 ps
CPU time 1.9 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 207080 kb
Host smart-c2b8f2b9-31ca-47df-9bb4-919a3246d6dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428251746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.428251746
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3990942133
Short name T330
Test name
Test status
Simulation time 61975941 ps
CPU time 3.1 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 210032 kb
Host smart-c3be876c-533e-43e3-bc3f-df6176603b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990942133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3990942133
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3698636670
Short name T539
Test name
Test status
Simulation time 494561038 ps
CPU time 4.4 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 207900 kb
Host smart-edbe8057-f7e1-4919-8863-7369dabbbedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698636670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3698636670
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1762893070
Short name T596
Test name
Test status
Simulation time 353122107 ps
CPU time 8.94 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:25 PM PDT 24
Peak memory 210364 kb
Host smart-4c3c04fe-4f21-443d-bdf9-6672aba302c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762893070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1762893070
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3299583139
Short name T446
Test name
Test status
Simulation time 434309472 ps
CPU time 4.05 seconds
Started May 26 02:50:18 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208188 kb
Host smart-d74a9348-4141-4ab2-a95f-c8b7a9d5de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299583139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3299583139
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.277063846
Short name T472
Test name
Test status
Simulation time 520077129 ps
CPU time 8.46 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 210984 kb
Host smart-1e0d0214-1fdb-4a71-9db0-063418d90167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277063846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.277063846
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3564605618
Short name T798
Test name
Test status
Simulation time 15334972 ps
CPU time 0.92 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 206192 kb
Host smart-4c9a03be-635c-4cee-b9d6-b4391758c2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564605618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3564605618
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1156523472
Short name T381
Test name
Test status
Simulation time 6900140288 ps
CPU time 49.47 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 216116 kb
Host smart-5ffe8a72-2f07-4950-b24b-901d98a00970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156523472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1156523472
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1860931525
Short name T205
Test name
Test status
Simulation time 488813935 ps
CPU time 8.67 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 214888 kb
Host smart-3b8468e3-6543-4f25-a488-6c2a201c7916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860931525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1860931525
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1229134091
Short name T303
Test name
Test status
Simulation time 3955789189 ps
CPU time 40.31 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 209368 kb
Host smart-269613cb-e2c2-4bb7-ad3b-b1a5563504a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229134091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1229134091
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3790638622
Short name T881
Test name
Test status
Simulation time 215488209 ps
CPU time 2.23 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 222564 kb
Host smart-aaa59a90-68ea-4ca8-981d-267f0810edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790638622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3790638622
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.334859891
Short name T348
Test name
Test status
Simulation time 139077777 ps
CPU time 5.12 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 214328 kb
Host smart-a1055b8e-f796-45d8-a332-2be94ae2bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334859891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.334859891
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2312547930
Short name T14
Test name
Test status
Simulation time 125556189 ps
CPU time 2.54 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 209816 kb
Host smart-4ebcc50d-0eb6-4280-a9c3-0a184347f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312547930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2312547930
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3395057485
Short name T343
Test name
Test status
Simulation time 408473944 ps
CPU time 8.13 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 207424 kb
Host smart-588c4de4-d4eb-4130-9c9e-3c1a65f118f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395057485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3395057485
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1923089068
Short name T578
Test name
Test status
Simulation time 1696262115 ps
CPU time 15.5 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 208468 kb
Host smart-798ff45a-7d92-40fb-99b1-40f55f08772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923089068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1923089068
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1827206423
Short name T110
Test name
Test status
Simulation time 79633779 ps
CPU time 1.94 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:21 PM PDT 24
Peak memory 208844 kb
Host smart-3d0f50eb-73bc-48e0-bbbe-de8731d3eaf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827206423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1827206423
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1030451598
Short name T298
Test name
Test status
Simulation time 674686973 ps
CPU time 3.54 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:19 PM PDT 24
Peak memory 208808 kb
Host smart-d95c7614-5a44-4e37-a17b-fce7a246aabe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030451598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1030451598
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3760851729
Short name T853
Test name
Test status
Simulation time 193885615 ps
CPU time 6.9 seconds
Started May 26 02:50:15 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208228 kb
Host smart-e7ab5110-26bc-49fb-b427-9a8077c8e6b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760851729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3760851729
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2112697327
Short name T625
Test name
Test status
Simulation time 53237587 ps
CPU time 2.05 seconds
Started May 26 02:50:19 PM PDT 24
Finished May 26 02:50:22 PM PDT 24
Peak memory 208432 kb
Host smart-ac49c56c-13eb-4c5e-a839-95d9255eb2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112697327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2112697327
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1016202019
Short name T407
Test name
Test status
Simulation time 1313014495 ps
CPU time 9.04 seconds
Started May 26 02:50:14 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208008 kb
Host smart-8c47f3b5-868b-430b-acfb-64739d331672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016202019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1016202019
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1088667145
Short name T218
Test name
Test status
Simulation time 983400469 ps
CPU time 15.91 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:34 PM PDT 24
Peak memory 220588 kb
Host smart-322fd37a-e3c0-4e3a-b278-da6cab8c6aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088667145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1088667145
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.980450196
Short name T464
Test name
Test status
Simulation time 232198291 ps
CPU time 5.72 seconds
Started May 26 02:50:16 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 207396 kb
Host smart-35e1cfb4-2e93-46e9-89f4-6840b24e6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980450196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.980450196
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.617029983
Short name T575
Test name
Test status
Simulation time 229455099 ps
CPU time 1.75 seconds
Started May 26 02:50:17 PM PDT 24
Finished May 26 02:50:20 PM PDT 24
Peak memory 210504 kb
Host smart-add03201-787a-4587-8574-1940d197ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617029983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.617029983
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3714750242
Short name T753
Test name
Test status
Simulation time 14089120 ps
CPU time 0.77 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:44 PM PDT 24
Peak memory 205988 kb
Host smart-7019bdc2-9915-426b-a010-145252792d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714750242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3714750242
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3819875357
Short name T639
Test name
Test status
Simulation time 115999491 ps
CPU time 1.46 seconds
Started May 26 02:48:45 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 215484 kb
Host smart-fc0de98f-fb7f-4cca-955e-5cb044e9a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819875357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3819875357
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3727435457
Short name T312
Test name
Test status
Simulation time 117377641 ps
CPU time 2.33 seconds
Started May 26 02:48:41 PM PDT 24
Finished May 26 02:48:44 PM PDT 24
Peak memory 214352 kb
Host smart-035557a7-8c23-4299-8a4a-4756e2c0b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727435457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3727435457
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1591452719
Short name T96
Test name
Test status
Simulation time 941119320 ps
CPU time 5.59 seconds
Started May 26 02:48:46 PM PDT 24
Finished May 26 02:48:52 PM PDT 24
Peak memory 214360 kb
Host smart-b48679fc-ed29-4181-a610-041e36fd06df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591452719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1591452719
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2576095041
Short name T549
Test name
Test status
Simulation time 201473278 ps
CPU time 6.06 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 214332 kb
Host smart-88133e9f-b2c5-4e29-be09-40824a5fe516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576095041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2576095041
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.770297960
Short name T432
Test name
Test status
Simulation time 402875242 ps
CPU time 4.8 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 210100 kb
Host smart-0be3821c-3bd3-4e5f-a687-0127400fb227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770297960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.770297960
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.609144497
Short name T487
Test name
Test status
Simulation time 444202761 ps
CPU time 3.37 seconds
Started May 26 02:48:45 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 207728 kb
Host smart-7aa037d2-168c-492a-88d9-499c3ea8b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609144497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.609144497
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4239381880
Short name T10
Test name
Test status
Simulation time 915320821 ps
CPU time 6.48 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:51 PM PDT 24
Peak memory 230804 kb
Host smart-059c810e-43cb-44f2-8d9f-a1cf5f769e06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239381880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4239381880
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2855667759
Short name T829
Test name
Test status
Simulation time 124471560 ps
CPU time 3.85 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 206908 kb
Host smart-ea65acda-19ed-4ed2-b26a-592a2eaeb64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855667759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2855667759
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3838293477
Short name T568
Test name
Test status
Simulation time 796847735 ps
CPU time 15.72 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:49:00 PM PDT 24
Peak memory 208900 kb
Host smart-4885a343-2958-4fab-b7bc-d0235454fedd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838293477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3838293477
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1008058751
Short name T691
Test name
Test status
Simulation time 1447619027 ps
CPU time 4.77 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 208524 kb
Host smart-ef075023-6998-4f55-bc43-3dcddc1a3c0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008058751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1008058751
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2026005138
Short name T133
Test name
Test status
Simulation time 235705116 ps
CPU time 3.63 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:49 PM PDT 24
Peak memory 208592 kb
Host smart-2fc0e3fd-c787-46c3-8397-4991b4091478
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026005138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2026005138
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1488530064
Short name T865
Test name
Test status
Simulation time 37733084 ps
CPU time 1.79 seconds
Started May 26 02:48:41 PM PDT 24
Finished May 26 02:48:44 PM PDT 24
Peak memory 207428 kb
Host smart-7679410f-2543-41c1-bc1a-10b13cf7c611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488530064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1488530064
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3200233615
Short name T420
Test name
Test status
Simulation time 226479452 ps
CPU time 2.61 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 206976 kb
Host smart-16001fca-3d5c-4646-a4f4-89c15d4343d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200233615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3200233615
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.900965428
Short name T629
Test name
Test status
Simulation time 14249805921 ps
CPU time 28.85 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:49:14 PM PDT 24
Peak memory 216516 kb
Host smart-e0503048-c364-4c63-aaf2-4c2923d21866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900965428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.900965428
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2263299314
Short name T916
Test name
Test status
Simulation time 505402226 ps
CPU time 5.71 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:51 PM PDT 24
Peak memory 214376 kb
Host smart-61751284-e9b6-47ad-a235-07b4d75fbd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263299314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2263299314
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1804792919
Short name T623
Test name
Test status
Simulation time 74856996 ps
CPU time 1.93 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:45 PM PDT 24
Peak memory 209852 kb
Host smart-6ed53103-8a8c-46a3-9998-4b777b012dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804792919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1804792919
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.477614649
Short name T396
Test name
Test status
Simulation time 29627089 ps
CPU time 1.12 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 206184 kb
Host smart-3e29fe11-5438-4047-b67c-c064fdd31a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477614649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.477614649
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2506597057
Short name T340
Test name
Test status
Simulation time 136852228 ps
CPU time 2.96 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 214396 kb
Host smart-2553f1ed-f699-4a8f-856b-6a808fcd60f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506597057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2506597057
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1557724085
Short name T556
Test name
Test status
Simulation time 83394877 ps
CPU time 2.13 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 218400 kb
Host smart-070e941b-8486-4c68-acd9-cb1dd4f3e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557724085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1557724085
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2074672339
Short name T98
Test name
Test status
Simulation time 192344828 ps
CPU time 4.61 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 214436 kb
Host smart-f89c60b0-bcb7-441a-a3b2-b5eedc4e40fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074672339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2074672339
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1491388201
Short name T742
Test name
Test status
Simulation time 97476663 ps
CPU time 3.95 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 210484 kb
Host smart-c190c428-66fc-4431-acc9-48954e2c2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491388201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1491388201
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1029323355
Short name T402
Test name
Test status
Simulation time 104033049 ps
CPU time 2.3 seconds
Started May 26 02:50:27 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 207700 kb
Host smart-be96a173-5864-482d-a912-57d36791cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029323355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1029323355
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3276213337
Short name T279
Test name
Test status
Simulation time 181410706 ps
CPU time 2.29 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:34 PM PDT 24
Peak memory 206840 kb
Host smart-c7026649-858c-43ae-a4b3-5065d627438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276213337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3276213337
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2940601686
Short name T424
Test name
Test status
Simulation time 103995882 ps
CPU time 2.82 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 206908 kb
Host smart-2147d8e4-3845-46db-bf06-f260e004e2e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940601686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2940601686
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1983902931
Short name T890
Test name
Test status
Simulation time 57241584 ps
CPU time 2.68 seconds
Started May 26 02:50:27 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 206960 kb
Host smart-7b86b085-ac30-48d0-bff3-72ae13f0648d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983902931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1983902931
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2192389593
Short name T422
Test name
Test status
Simulation time 86317561 ps
CPU time 2.45 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 206844 kb
Host smart-0569f1e7-7f46-4ea0-9b69-dee94df04670
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192389593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2192389593
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.999992553
Short name T373
Test name
Test status
Simulation time 33583424 ps
CPU time 2.32 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 207728 kb
Host smart-de5e6b8f-dcc5-4f8b-b96c-8dc074c8b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999992553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.999992553
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.448292219
Short name T856
Test name
Test status
Simulation time 210390096 ps
CPU time 3.06 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:30 PM PDT 24
Peak memory 207132 kb
Host smart-cf55ae63-ad2d-4a3e-9f10-aebb3afefe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448292219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.448292219
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1045503631
Short name T823
Test name
Test status
Simulation time 557167113 ps
CPU time 7.82 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 207620 kb
Host smart-6c3537cc-b06b-40bd-baab-1a5f7bffc3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045503631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1045503631
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.782910839
Short name T39
Test name
Test status
Simulation time 121562184 ps
CPU time 2.32 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 209884 kb
Host smart-e05525bb-2d98-4391-93b0-bddba44f8845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782910839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.782910839
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1164391148
Short name T782
Test name
Test status
Simulation time 11683123 ps
CPU time 0.91 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 205984 kb
Host smart-e7f8019d-b841-48aa-a113-e252ac9464b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164391148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1164391148
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3235731024
Short name T85
Test name
Test status
Simulation time 49719756 ps
CPU time 3.47 seconds
Started May 26 02:50:28 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 214364 kb
Host smart-f0824a79-4db8-4dad-98d7-fa7da6df6710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235731024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3235731024
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1729908589
Short name T256
Test name
Test status
Simulation time 2578189317 ps
CPU time 14.39 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 208200 kb
Host smart-26dd5e0c-2ba0-4e23-a7eb-f231621444d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729908589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1729908589
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2295839772
Short name T88
Test name
Test status
Simulation time 278656385 ps
CPU time 3.13 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 221112 kb
Host smart-fa119272-32fe-47aa-a555-47a90cc43662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295839772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2295839772
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1988533463
Short name T223
Test name
Test status
Simulation time 131358082 ps
CPU time 3.69 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 209480 kb
Host smart-4e505e8e-e485-4af3-b086-e80c6f1fd349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988533463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1988533463
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.199975017
Short name T737
Test name
Test status
Simulation time 311595413 ps
CPU time 8.59 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 214388 kb
Host smart-514eb913-228a-4bfc-835c-343a48545a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199975017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.199975017
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3949641185
Short name T624
Test name
Test status
Simulation time 49868788 ps
CPU time 2.69 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 206980 kb
Host smart-c6fb86fd-1474-444a-8daf-5e5b1cd327fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949641185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3949641185
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3560627244
Short name T43
Test name
Test status
Simulation time 27655335 ps
CPU time 2.2 seconds
Started May 26 02:50:27 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 208868 kb
Host smart-e060eb52-58e8-4fc2-b4cd-74afccfb5b33
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560627244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3560627244
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3940082098
Short name T819
Test name
Test status
Simulation time 645393494 ps
CPU time 2.9 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:30 PM PDT 24
Peak memory 207068 kb
Host smart-6d9dd1de-1d51-445f-a5b4-51e5a669805b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940082098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3940082098
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2162288989
Short name T324
Test name
Test status
Simulation time 57028058 ps
CPU time 2.67 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 206808 kb
Host smart-a46478f3-5ec0-42ec-bc80-dcbd52802bec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162288989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2162288989
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1042738407
Short name T483
Test name
Test status
Simulation time 53546482 ps
CPU time 3.13 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 220736 kb
Host smart-efdf42c3-4458-49cc-974d-8812488c3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042738407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1042738407
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4208113702
Short name T589
Test name
Test status
Simulation time 62147271 ps
CPU time 2.11 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:30 PM PDT 24
Peak memory 206788 kb
Host smart-c97a1e1a-72bb-4f98-b1a5-a64fdbc3f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208113702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4208113702
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1768171505
Short name T179
Test name
Test status
Simulation time 432652359 ps
CPU time 8.49 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 219836 kb
Host smart-2df26431-f161-4034-a4a2-a6989a2f48dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768171505 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1768171505
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3894018628
Short name T476
Test name
Test status
Simulation time 843892800 ps
CPU time 4.4 seconds
Started May 26 02:50:21 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 218220 kb
Host smart-f90aa026-78f1-4c43-8d01-8f22f72b6e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894018628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3894018628
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1418930355
Short name T707
Test name
Test status
Simulation time 58616857 ps
CPU time 2.63 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 210408 kb
Host smart-5ef1f20a-5aeb-421b-a382-cb1c1a6b2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418930355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1418930355
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1463169563
Short name T781
Test name
Test status
Simulation time 41630062 ps
CPU time 0.75 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 205796 kb
Host smart-467a697b-8f40-4945-9740-9ecffeb5bcef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463169563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1463169563
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1979620664
Short name T385
Test name
Test status
Simulation time 39899676 ps
CPU time 2.95 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 214268 kb
Host smart-486b83ad-e67f-438f-b814-088066de5528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979620664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1979620664
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.985886976
Short name T38
Test name
Test status
Simulation time 336281010 ps
CPU time 3.11 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 219900 kb
Host smart-4890781d-c71f-4590-9390-33ab75ae269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985886976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.985886976
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1628719993
Short name T313
Test name
Test status
Simulation time 304072877 ps
CPU time 3.62 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 214340 kb
Host smart-657d33eb-aff4-4b59-802c-a4d4d98cf4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628719993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1628719993
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2732889367
Short name T269
Test name
Test status
Simulation time 40902073 ps
CPU time 2.53 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 214280 kb
Host smart-ae5dfc6c-07ea-4a0f-a74e-78ebb53ef012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732889367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2732889367
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.751123416
Short name T587
Test name
Test status
Simulation time 475941517 ps
CPU time 3.74 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 209440 kb
Host smart-cc68dedf-7a99-4638-aa87-4c2f6e05e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751123416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.751123416
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2175273301
Short name T443
Test name
Test status
Simulation time 480734574 ps
CPU time 5.5 seconds
Started May 26 02:50:21 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 208140 kb
Host smart-7f95cd29-e3d4-4dd5-a2a6-593cb0fa899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175273301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2175273301
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1610170236
Short name T285
Test name
Test status
Simulation time 2615893785 ps
CPU time 27.46 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 208504 kb
Host smart-c770c0db-3995-473b-b0dd-588779222ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610170236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1610170236
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.522136769
Short name T682
Test name
Test status
Simulation time 79960706 ps
CPU time 3.48 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 207128 kb
Host smart-a6542a4f-901a-4083-9d6e-1d05235f8c54
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522136769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.522136769
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3063821108
Short name T201
Test name
Test status
Simulation time 38066944 ps
CPU time 2.47 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 207088 kb
Host smart-7077a7db-391c-49f4-9792-939db6fe5eb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063821108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3063821108
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2026734143
Short name T11
Test name
Test status
Simulation time 106184528 ps
CPU time 4.32 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 207176 kb
Host smart-b502f4c7-2974-4b36-85ae-d11d5d248fdb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026734143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2026734143
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3068154675
Short name T730
Test name
Test status
Simulation time 37211332 ps
CPU time 2.25 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:27 PM PDT 24
Peak memory 208112 kb
Host smart-e6deb5c7-0b29-4bb3-949f-98099e81f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068154675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3068154675
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1830867081
Short name T821
Test name
Test status
Simulation time 857077028 ps
CPU time 4.93 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 208836 kb
Host smart-18c98a4b-bfab-49e7-9549-f0ce520e1dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830867081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1830867081
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3971213298
Short name T77
Test name
Test status
Simulation time 1263620811 ps
CPU time 45.08 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 216900 kb
Host smart-63916faf-e2ee-44d9-9d6a-c9326a27b094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971213298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3971213298
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1144980337
Short name T833
Test name
Test status
Simulation time 760887282 ps
CPU time 18.24 seconds
Started May 26 02:50:25 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 218560 kb
Host smart-e6c48130-b9ea-4d87-88e0-041c2da02cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144980337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1144980337
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.772858259
Short name T525
Test name
Test status
Simulation time 346983226 ps
CPU time 2.32 seconds
Started May 26 02:50:24 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 210168 kb
Host smart-8afee2ec-44bd-49c2-9fd9-4287864ad0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772858259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.772858259
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1773427198
Short name T573
Test name
Test status
Simulation time 41980051 ps
CPU time 0.77 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 205968 kb
Host smart-975ec0e7-f828-4334-8493-148e36e25b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773427198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1773427198
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.875039229
Short name T370
Test name
Test status
Simulation time 92264614 ps
CPU time 3.72 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:26 PM PDT 24
Peak memory 214336 kb
Host smart-c3424ff3-57ae-476f-8066-e0fbae794e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875039229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.875039229
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4070634593
Short name T5
Test name
Test status
Simulation time 67234342 ps
CPU time 2.34 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 216860 kb
Host smart-5b3a8e61-718f-4d9a-a308-2f70501f7f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070634593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4070634593
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3152416310
Short name T426
Test name
Test status
Simulation time 43483849 ps
CPU time 1.86 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208052 kb
Host smart-d0df409b-9534-4fb3-b12e-f6d5a771a0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152416310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3152416310
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.410477544
Short name T25
Test name
Test status
Simulation time 463865685 ps
CPU time 9.02 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:41 PM PDT 24
Peak memory 214400 kb
Host smart-7480fe88-3fd6-407e-ba69-6f217fdfbbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410477544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.410477544
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1078588743
Short name T83
Test name
Test status
Simulation time 483520605 ps
CPU time 3.93 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 214300 kb
Host smart-1740971c-6745-4acc-8ac2-cc710c86a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078588743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1078588743
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4257824886
Short name T656
Test name
Test status
Simulation time 116486024 ps
CPU time 2.85 seconds
Started May 26 02:50:26 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 208124 kb
Host smart-a31975bc-3e0d-4931-a5f7-c166f44b15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257824886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4257824886
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2813963201
Short name T706
Test name
Test status
Simulation time 242509569 ps
CPU time 5.69 seconds
Started May 26 02:50:22 PM PDT 24
Finished May 26 02:50:28 PM PDT 24
Peak memory 207616 kb
Host smart-3e628c10-cf6b-4d43-8e8b-52f4a50e335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813963201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2813963201
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3451388526
Short name T719
Test name
Test status
Simulation time 120964236 ps
CPU time 3.1 seconds
Started May 26 02:50:21 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 208536 kb
Host smart-2c30f8e8-1bc1-4060-b03a-fe675205f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451388526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3451388526
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.669198939
Short name T504
Test name
Test status
Simulation time 123406943 ps
CPU time 2.64 seconds
Started May 26 02:50:28 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 206868 kb
Host smart-d623efcd-a13a-4418-b1c1-bff9ed8d078e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669198939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.669198939
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1015412537
Short name T503
Test name
Test status
Simulation time 399164204 ps
CPU time 3.52 seconds
Started May 26 02:50:28 PM PDT 24
Finished May 26 02:50:34 PM PDT 24
Peak memory 206812 kb
Host smart-dddd206f-2ab4-429d-b8fb-545a4ff97494
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015412537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1015412537
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4100395440
Short name T874
Test name
Test status
Simulation time 224609774 ps
CPU time 4.57 seconds
Started May 26 02:50:23 PM PDT 24
Finished May 26 02:50:29 PM PDT 24
Peak memory 208780 kb
Host smart-10d263ab-f2c2-4e40-a24d-680b16ebd310
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100395440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4100395440
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.837572851
Short name T338
Test name
Test status
Simulation time 112935438 ps
CPU time 2.79 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 216020 kb
Host smart-764cbb0b-5ace-4bab-8d50-ea3e7b256049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837572851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.837572851
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1967772015
Short name T794
Test name
Test status
Simulation time 254903240 ps
CPU time 2.78 seconds
Started May 26 02:50:28 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 206840 kb
Host smart-2ea10e38-c20e-4884-8d82-b425921efc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967772015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1967772015
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3460677470
Short name T79
Test name
Test status
Simulation time 384526933 ps
CPU time 11.05 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 222636 kb
Host smart-e9c376ff-c093-4f04-9c28-78b75816c09a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460677470 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3460677470
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.769618042
Short name T495
Test name
Test status
Simulation time 1281302651 ps
CPU time 15.7 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:49 PM PDT 24
Peak memory 208860 kb
Host smart-cb8a8927-2fc9-47b1-a03a-b5fa92e9b0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769618042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.769618042
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3042977975
Short name T801
Test name
Test status
Simulation time 284339851 ps
CPU time 2.58 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 214604 kb
Host smart-8625d768-237c-4677-8215-7d2ac0fb3d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042977975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3042977975
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1229210327
Short name T524
Test name
Test status
Simulation time 34835096 ps
CPU time 0.73 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:32 PM PDT 24
Peak memory 206000 kb
Host smart-1d596e78-95d8-49da-84f9-9bec06e2c092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229210327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1229210327
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1385830592
Short name T360
Test name
Test status
Simulation time 162459597 ps
CPU time 2.28 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 215376 kb
Host smart-ca6ced7b-0a9d-45af-af88-b7d64db7b1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385830592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1385830592
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4167996517
Short name T276
Test name
Test status
Simulation time 307611294 ps
CPU time 5.96 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:39 PM PDT 24
Peak memory 218728 kb
Host smart-68f999d7-e3a0-4222-b9b2-16a8b444a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167996517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4167996517
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1498874478
Short name T748
Test name
Test status
Simulation time 113868222 ps
CPU time 2.71 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 208080 kb
Host smart-9c51c593-d1ab-479c-b01a-036809b588b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498874478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1498874478
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4066289017
Short name T660
Test name
Test status
Simulation time 301078113 ps
CPU time 2.97 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 214372 kb
Host smart-a43ac1e9-294a-47e8-a8ff-8e9c80ced3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066289017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4066289017
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2081413499
Short name T213
Test name
Test status
Simulation time 347642941 ps
CPU time 3.67 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 214364 kb
Host smart-b2d4582c-d8fc-4d8f-9679-4242dff19710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081413499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2081413499
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.531146032
Short name T311
Test name
Test status
Simulation time 2179387715 ps
CPU time 5.6 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:39 PM PDT 24
Peak memory 214480 kb
Host smart-6d4a8226-c5b4-4fbb-9111-c52afe0e798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531146032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.531146032
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4172318638
Short name T437
Test name
Test status
Simulation time 35158542 ps
CPU time 2.25 seconds
Started May 26 02:50:28 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 207204 kb
Host smart-643b30df-72f1-4b3d-b8e6-8badfca6953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172318638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4172318638
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1109784677
Short name T709
Test name
Test status
Simulation time 4971755231 ps
CPU time 48.44 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 208268 kb
Host smart-6b43c43a-c898-4a30-8ae7-7290c66d551d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109784677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1109784677
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2807344175
Short name T390
Test name
Test status
Simulation time 273643833 ps
CPU time 2.47 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 206776 kb
Host smart-89090a54-6b3c-43d2-b164-84ad6dbd4d24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807344175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2807344175
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.168571448
Short name T441
Test name
Test status
Simulation time 123725853 ps
CPU time 2.6 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 206976 kb
Host smart-9c774463-80ac-44f1-a33f-42073a3f3948
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168571448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.168571448
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.497597449
Short name T187
Test name
Test status
Simulation time 379596626 ps
CPU time 4.55 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 214364 kb
Host smart-e9050184-e171-4fae-bf29-18d4d505ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497597449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.497597449
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.487711730
Short name T764
Test name
Test status
Simulation time 1550889570 ps
CPU time 28.56 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 208804 kb
Host smart-fe14892c-7340-4d20-b089-f8e559d8ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487711730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.487711730
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3201748728
Short name T501
Test name
Test status
Simulation time 123563932 ps
CPU time 4.68 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:36 PM PDT 24
Peak memory 210576 kb
Host smart-ba8a5cab-660b-40ba-b457-0aa59335ed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201748728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3201748728
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1235246968
Short name T736
Test name
Test status
Simulation time 93608192 ps
CPU time 1.93 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:35 PM PDT 24
Peak memory 210104 kb
Host smart-715d8851-06cf-4c00-b5df-12771c523889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235246968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1235246968
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2465564418
Short name T103
Test name
Test status
Simulation time 13928928 ps
CPU time 0.77 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:40 PM PDT 24
Peak memory 206008 kb
Host smart-8130d90e-255f-4886-81a5-4fdb0595b890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465564418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2465564418
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3458351533
Short name T359
Test name
Test status
Simulation time 27927218 ps
CPU time 2.52 seconds
Started May 26 02:50:29 PM PDT 24
Finished May 26 02:50:33 PM PDT 24
Peak memory 214396 kb
Host smart-e492e092-974f-4b89-9fd8-9c16bad255d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458351533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3458351533
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.103368921
Short name T455
Test name
Test status
Simulation time 189150548 ps
CPU time 2.75 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 209812 kb
Host smart-6e29ccc7-5879-4631-bc72-b0128305e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103368921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.103368921
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1891833215
Short name T364
Test name
Test status
Simulation time 363302590 ps
CPU time 4.52 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 209352 kb
Host smart-101a57cf-8a21-41be-a693-c1871f556027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891833215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1891833215
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1569988291
Short name T23
Test name
Test status
Simulation time 53944979 ps
CPU time 2.82 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 208940 kb
Host smart-90d59033-78bf-44c3-a34e-758acd47eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569988291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1569988291
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.575675646
Short name T554
Test name
Test status
Simulation time 62440501 ps
CPU time 3.74 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:36 PM PDT 24
Peak memory 209836 kb
Host smart-a90aa1e3-2d8d-4c4c-8524-21d0942604bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575675646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.575675646
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1092984410
Short name T750
Test name
Test status
Simulation time 508218522 ps
CPU time 10.38 seconds
Started May 26 02:50:33 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 208756 kb
Host smart-89ee0017-79a0-4dc4-88d6-450a1ff10c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092984410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1092984410
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2131949872
Short name T766
Test name
Test status
Simulation time 86851565 ps
CPU time 3.64 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:43 PM PDT 24
Peak memory 208520 kb
Host smart-07899daf-4e39-49a0-a972-49cd8b58ca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131949872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2131949872
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.155785242
Short name T497
Test name
Test status
Simulation time 1235257447 ps
CPU time 11.16 seconds
Started May 26 02:50:30 PM PDT 24
Finished May 26 02:50:43 PM PDT 24
Peak memory 208892 kb
Host smart-ab6b72e0-eade-405f-bafb-76d37caec267
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155785242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.155785242
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1461423864
Short name T552
Test name
Test status
Simulation time 296628897 ps
CPU time 3.83 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 208932 kb
Host smart-637ea733-5b60-4c6e-8ace-bfc0fb72dfb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461423864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1461423864
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2912521916
Short name T81
Test name
Test status
Simulation time 331511710 ps
CPU time 3.25 seconds
Started May 26 02:50:31 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 207036 kb
Host smart-c1ffaad3-a6e3-4c2a-8c42-ea13f9963a49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912521916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2912521916
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3391128666
Short name T692
Test name
Test status
Simulation time 1704051932 ps
CPU time 28.49 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 208828 kb
Host smart-76e79563-97b8-4dfb-ae54-f76844234001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391128666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3391128666
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1824038693
Short name T884
Test name
Test status
Simulation time 41801094 ps
CPU time 2 seconds
Started May 26 02:50:32 PM PDT 24
Finished May 26 02:50:36 PM PDT 24
Peak memory 208440 kb
Host smart-b792370b-5b0a-4ef2-85be-85254279fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824038693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1824038693
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2903928328
Short name T192
Test name
Test status
Simulation time 2641206277 ps
CPU time 20.56 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:51:02 PM PDT 24
Peak memory 216172 kb
Host smart-e0501e8a-bed7-46ea-9f2d-7a213fec3559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903928328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2903928328
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4190597436
Short name T287
Test name
Test status
Simulation time 40990432 ps
CPU time 2.69 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:41 PM PDT 24
Peak memory 214320 kb
Host smart-f584f815-2d51-4fca-a3cb-c7f21bc4d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190597436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4190597436
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.701482106
Short name T173
Test name
Test status
Simulation time 164173132 ps
CPU time 6.57 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:46 PM PDT 24
Peak memory 210888 kb
Host smart-3d5e39fa-395a-45be-9e32-74e394514cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701482106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.701482106
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3207117986
Short name T832
Test name
Test status
Simulation time 26890219 ps
CPU time 0.8 seconds
Started May 26 02:50:42 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 205896 kb
Host smart-4acef39c-ce99-4d16-b92f-16e0e515158c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207117986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3207117986
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2422354957
Short name T591
Test name
Test status
Simulation time 72893747 ps
CPU time 2.28 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 208220 kb
Host smart-4a5c511e-8fdc-486c-a3a7-89ad07f05c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422354957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2422354957
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1653860802
Short name T94
Test name
Test status
Simulation time 440748325 ps
CPU time 5.69 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:49 PM PDT 24
Peak memory 214480 kb
Host smart-2f245c01-57de-4168-9073-5557f5104f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653860802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1653860802
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.712733849
Short name T795
Test name
Test status
Simulation time 89438158 ps
CPU time 4.38 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 214308 kb
Host smart-350929f3-88dc-4574-9b02-81047ccc8bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712733849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.712733849
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2505943575
Short name T523
Test name
Test status
Simulation time 193608309 ps
CPU time 1.89 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 206216 kb
Host smart-be66ebe4-52ae-4643-8188-997459592ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505943575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2505943575
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1988241605
Short name T776
Test name
Test status
Simulation time 110422184 ps
CPU time 4.63 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:48 PM PDT 24
Peak memory 218432 kb
Host smart-74ac8158-b3f6-47ea-9641-a79b1b48963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988241605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1988241605
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3803496693
Short name T773
Test name
Test status
Simulation time 2617221333 ps
CPU time 16.29 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 208068 kb
Host smart-9d3e591e-fea6-416f-9a7b-9983d817e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803496693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3803496693
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2198346155
Short name T713
Test name
Test status
Simulation time 156396575 ps
CPU time 3.65 seconds
Started May 26 02:50:35 PM PDT 24
Finished May 26 02:50:39 PM PDT 24
Peak memory 207396 kb
Host smart-e865ebfc-4207-42db-b480-94a9e4514654
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198346155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2198346155
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3417817130
Short name T802
Test name
Test status
Simulation time 86866615 ps
CPU time 2.37 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:43 PM PDT 24
Peak memory 207096 kb
Host smart-c7521dd3-0106-49e3-a51d-ecf2ee407018
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417817130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3417817130
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.279234786
Short name T466
Test name
Test status
Simulation time 170660477 ps
CPU time 2.74 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 208428 kb
Host smart-ff5f57ff-28c3-41cc-a313-a4370cbda6d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279234786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.279234786
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.315249721
Short name T606
Test name
Test status
Simulation time 1014308172 ps
CPU time 6.07 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:46 PM PDT 24
Peak memory 209116 kb
Host smart-9a1bf669-090a-45d2-9ad8-c3cd7f9d416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315249721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.315249721
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1265104865
Short name T907
Test name
Test status
Simulation time 3232255948 ps
CPU time 17.58 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:57 PM PDT 24
Peak memory 208464 kb
Host smart-cb6f4b25-ff01-42f1-9493-2666e8eb7d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265104865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1265104865
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1110037449
Short name T722
Test name
Test status
Simulation time 1989234197 ps
CPU time 11.49 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 215200 kb
Host smart-2853d3c6-b11b-40ed-b16f-dcd666a31261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110037449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1110037449
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.490367114
Short name T513
Test name
Test status
Simulation time 331242921 ps
CPU time 5.84 seconds
Started May 26 02:50:42 PM PDT 24
Finished May 26 02:50:49 PM PDT 24
Peak memory 209944 kb
Host smart-f659e75c-b448-406e-9817-bec54883db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490367114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.490367114
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1130395144
Short name T355
Test name
Test status
Simulation time 58475344 ps
CPU time 1.62 seconds
Started May 26 02:50:34 PM PDT 24
Finished May 26 02:50:37 PM PDT 24
Peak memory 209940 kb
Host smart-e0a99779-be31-4e77-9308-49e0886591b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130395144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1130395144
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1699882390
Short name T394
Test name
Test status
Simulation time 23176499 ps
CPU time 0.79 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:41 PM PDT 24
Peak memory 205988 kb
Host smart-2bd5deac-1fec-42f6-8828-ad66580f5e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699882390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1699882390
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3630984750
Short name T234
Test name
Test status
Simulation time 65542838 ps
CPU time 3.59 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 214672 kb
Host smart-9af2d8cb-ea64-4195-a178-4c45c1748cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630984750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3630984750
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3783501130
Short name T752
Test name
Test status
Simulation time 457804568 ps
CPU time 2.15 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 207012 kb
Host smart-0a676510-8c5c-4f41-8fc3-7ab1bffe680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783501130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3783501130
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4030247057
Short name T827
Test name
Test status
Simulation time 148715869 ps
CPU time 2.45 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 221840 kb
Host smart-a16d5024-fdd0-4716-9faf-70e1998fe972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030247057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4030247057
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1509420293
Short name T838
Test name
Test status
Simulation time 558143900 ps
CPU time 4.31 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 214332 kb
Host smart-3af3892f-4c39-40eb-a109-2e01086c60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509420293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1509420293
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2650933530
Short name T233
Test name
Test status
Simulation time 256028730 ps
CPU time 3.83 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 220368 kb
Host smart-142fb305-022d-4ea5-80a7-864742275582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650933530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2650933530
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3655808335
Short name T681
Test name
Test status
Simulation time 275121796 ps
CPU time 6.09 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:47 PM PDT 24
Peak memory 207640 kb
Host smart-0f4863cf-d123-4fea-bc76-402065667831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655808335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3655808335
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.854728519
Short name T225
Test name
Test status
Simulation time 61626995 ps
CPU time 2.77 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:40 PM PDT 24
Peak memory 206976 kb
Host smart-e8f6e428-3e33-47bc-950d-7fce9fd8ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854728519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.854728519
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2142812693
Short name T810
Test name
Test status
Simulation time 1806124511 ps
CPU time 58.59 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:51:41 PM PDT 24
Peak memory 208680 kb
Host smart-ff109ca9-f9d0-466b-a913-532b692c5889
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142812693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2142812693
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1996779470
Short name T851
Test name
Test status
Simulation time 450892822 ps
CPU time 5.35 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:46 PM PDT 24
Peak memory 208308 kb
Host smart-1250066a-a3f8-4960-baa2-db41dfd0289b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996779470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1996779470
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.168910009
Short name T186
Test name
Test status
Simulation time 120192717 ps
CPU time 3.36 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 208300 kb
Host smart-ec17b11a-7b10-4d8b-8744-604b8165f32c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168910009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.168910009
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1722361275
Short name T631
Test name
Test status
Simulation time 2445285259 ps
CPU time 13.14 seconds
Started May 26 02:50:36 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 209184 kb
Host smart-87a3cbbb-77a4-4862-821c-9cf557c5ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722361275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1722361275
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2844672987
Short name T700
Test name
Test status
Simulation time 75501847 ps
CPU time 2.32 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 206980 kb
Host smart-98773efe-3422-4b19-9ddf-5bad4b43f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844672987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2844672987
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.563707706
Short name T870
Test name
Test status
Simulation time 307656911 ps
CPU time 11.46 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 216672 kb
Host smart-e67cdca3-7d0f-4b8d-b360-3fc94ccea085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563707706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.563707706
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.4210139274
Short name T215
Test name
Test status
Simulation time 263039772 ps
CPU time 9.43 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:52 PM PDT 24
Peak memory 222692 kb
Host smart-1590daf1-fa2c-4ee1-9a8a-fa9b4c423d1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210139274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.4210139274
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2108350459
Short name T278
Test name
Test status
Simulation time 1148691714 ps
CPU time 4.4 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:43 PM PDT 24
Peak memory 214412 kb
Host smart-4fc39462-539c-450b-8b14-67c891036a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108350459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2108350459
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.757066572
Short name T586
Test name
Test status
Simulation time 104739926 ps
CPU time 2.02 seconds
Started May 26 02:50:41 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 210276 kb
Host smart-b5690f55-2d6f-41fe-a3b2-964969df58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757066572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.757066572
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3943183962
Short name T500
Test name
Test status
Simulation time 13125162 ps
CPU time 0.94 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:48 PM PDT 24
Peak memory 206028 kb
Host smart-82a4b35f-1883-4e94-9121-087e0465750c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943183962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3943183962
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1704854435
Short name T376
Test name
Test status
Simulation time 270507252 ps
CPU time 3.12 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 214384 kb
Host smart-ea894c9d-ddf1-439b-85ad-ecef4a6f5fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704854435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1704854435
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1935906114
Short name T140
Test name
Test status
Simulation time 79870159 ps
CPU time 3.48 seconds
Started May 26 02:50:44 PM PDT 24
Finished May 26 02:50:48 PM PDT 24
Peak memory 219360 kb
Host smart-5735807b-e000-4bf0-9f7f-0a0c288835fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935906114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1935906114
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3988820354
Short name T344
Test name
Test status
Simulation time 75741693 ps
CPU time 2.05 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 206916 kb
Host smart-5747af9c-4eb8-48cb-a58e-c216db1d0973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988820354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3988820354
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1631826683
Short name T351
Test name
Test status
Simulation time 3509671546 ps
CPU time 15.3 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 219268 kb
Host smart-2b4c3bf7-0ce0-48d5-a93b-52fb52976941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631826683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1631826683
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3409335913
Short name T910
Test name
Test status
Simulation time 384178705 ps
CPU time 3.84 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 222484 kb
Host smart-56a2de52-ab6b-4dd8-a841-db6b2f539783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409335913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3409335913
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1848033315
Short name T56
Test name
Test status
Simulation time 443265880 ps
CPU time 3.5 seconds
Started May 26 02:50:39 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 222580 kb
Host smart-c39180f4-82fc-44dc-aaf6-b34019a886f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848033315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1848033315
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3177349797
Short name T888
Test name
Test status
Simulation time 135284694 ps
CPU time 4.96 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:47 PM PDT 24
Peak memory 214320 kb
Host smart-51633c68-7aa9-44f3-816e-1d536823d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177349797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3177349797
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1644142358
Short name T590
Test name
Test status
Simulation time 75049511 ps
CPU time 2.9 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 208144 kb
Host smart-bc480621-9519-4a09-b1cb-834f60bb6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644142358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1644142358
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2092454791
Short name T641
Test name
Test status
Simulation time 198469549 ps
CPU time 3.05 seconds
Started May 26 02:50:42 PM PDT 24
Finished May 26 02:50:47 PM PDT 24
Peak memory 207036 kb
Host smart-89073444-41db-4231-a23f-837f29744268
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092454791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2092454791
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1353559112
Short name T536
Test name
Test status
Simulation time 54281602 ps
CPU time 2.64 seconds
Started May 26 02:50:40 PM PDT 24
Finished May 26 02:50:45 PM PDT 24
Peak memory 206992 kb
Host smart-cddaf62d-af99-4f44-9a73-ace2ed85e958
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353559112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1353559112
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1373742829
Short name T538
Test name
Test status
Simulation time 92231852 ps
CPU time 3.89 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 207024 kb
Host smart-cc8c94e7-ba92-4695-9681-77244b3f9048
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373742829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1373742829
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2098118082
Short name T374
Test name
Test status
Simulation time 154626918 ps
CPU time 2.8 seconds
Started May 26 02:50:47 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 208016 kb
Host smart-b96ac718-98cb-4ebb-815b-51178cd29a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098118082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2098118082
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2375577076
Short name T403
Test name
Test status
Simulation time 169989469 ps
CPU time 2.26 seconds
Started May 26 02:50:38 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 207384 kb
Host smart-dbf3cf19-4bf0-4936-ab9c-78208a95c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375577076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2375577076
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3384381601
Short name T193
Test name
Test status
Simulation time 1916473355 ps
CPU time 45.03 seconds
Started May 26 02:50:44 PM PDT 24
Finished May 26 02:51:31 PM PDT 24
Peak memory 220440 kb
Host smart-bec60b03-e6e2-4324-992d-a6a123ab877f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384381601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3384381601
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.991122930
Short name T54
Test name
Test status
Simulation time 342328458 ps
CPU time 6.45 seconds
Started May 26 02:50:49 PM PDT 24
Finished May 26 02:50:56 PM PDT 24
Peak memory 222600 kb
Host smart-21dc1e96-044a-48e0-aefd-7b907d39399e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991122930 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.991122930
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2411368603
Short name T478
Test name
Test status
Simulation time 451406844 ps
CPU time 3.86 seconds
Started May 26 02:50:37 PM PDT 24
Finished May 26 02:50:42 PM PDT 24
Peak memory 209856 kb
Host smart-346948d0-d42a-46b7-8822-f16eed7db0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411368603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2411368603
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2026216791
Short name T410
Test name
Test status
Simulation time 50167238 ps
CPU time 1.37 seconds
Started May 26 02:50:47 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 209776 kb
Host smart-7bf878f6-699b-4bb0-80f2-3fb7ade54c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026216791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2026216791
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.451440823
Short name T526
Test name
Test status
Simulation time 16800079 ps
CPU time 0.81 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:50:48 PM PDT 24
Peak memory 205996 kb
Host smart-652e9b1a-92e6-498d-b118-58373a743ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451440823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.451440823
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.59935883
Short name T796
Test name
Test status
Simulation time 456550427 ps
CPU time 7.61 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:50:55 PM PDT 24
Peak memory 215648 kb
Host smart-ebe30641-0a09-4f30-b6cf-3cb31c5552f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59935883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.59935883
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1250233502
Short name T683
Test name
Test status
Simulation time 42701084 ps
CPU time 1.68 seconds
Started May 26 02:50:51 PM PDT 24
Finished May 26 02:50:54 PM PDT 24
Peak memory 216812 kb
Host smart-e8162d78-380b-440b-816e-11dffbc2966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250233502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1250233502
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.89569786
Short name T759
Test name
Test status
Simulation time 66109981 ps
CPU time 3.17 seconds
Started May 26 02:50:47 PM PDT 24
Finished May 26 02:50:52 PM PDT 24
Peak memory 218476 kb
Host smart-a5bcf7c8-e9f3-462d-982d-ce20b33f6838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89569786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.89569786
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4269996526
Short name T291
Test name
Test status
Simulation time 221371650 ps
CPU time 3.29 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 214404 kb
Host smart-cac72f1d-c0da-4fd9-aa78-f798fe6216bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269996526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4269996526
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3117107645
Short name T363
Test name
Test status
Simulation time 195517126 ps
CPU time 4.54 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 221820 kb
Host smart-6b14d6f8-8d62-4d7d-9562-a25b118f578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117107645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3117107645
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2450654984
Short name T55
Test name
Test status
Simulation time 183010004 ps
CPU time 2.6 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 214420 kb
Host smart-9253e384-fea6-46df-b89b-e8a97e899f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450654984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2450654984
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.954219898
Short name T862
Test name
Test status
Simulation time 828348985 ps
CPU time 9.75 seconds
Started May 26 02:50:44 PM PDT 24
Finished May 26 02:50:56 PM PDT 24
Peak memory 207708 kb
Host smart-3394ed0e-27aa-4c40-8c2a-d782f8fdd20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954219898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.954219898
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4152781503
Short name T599
Test name
Test status
Simulation time 3142782171 ps
CPU time 40.72 seconds
Started May 26 02:50:44 PM PDT 24
Finished May 26 02:51:27 PM PDT 24
Peak memory 207956 kb
Host smart-523ee37f-d2f7-4109-8c4d-481f20d082c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152781503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4152781503
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1401933916
Short name T679
Test name
Test status
Simulation time 129355579 ps
CPU time 5.21 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 208836 kb
Host smart-626f82fa-40b3-4bd9-9fc3-a37f277f4624
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401933916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1401933916
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.592168272
Short name T534
Test name
Test status
Simulation time 159943925 ps
CPU time 4.32 seconds
Started May 26 02:50:48 PM PDT 24
Finished May 26 02:50:54 PM PDT 24
Peak memory 208136 kb
Host smart-aeca76d2-1891-4585-ad67-06f05a7b5957
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592168272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.592168272
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2685877298
Short name T515
Test name
Test status
Simulation time 64885673 ps
CPU time 3.21 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 207200 kb
Host smart-76c8dbad-5c3c-4ca4-a53d-b9c5f2183d5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685877298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2685877298
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2265761471
Short name T772
Test name
Test status
Simulation time 193473111 ps
CPU time 3.38 seconds
Started May 26 02:50:50 PM PDT 24
Finished May 26 02:50:54 PM PDT 24
Peak memory 218504 kb
Host smart-7daf4888-c87c-40b9-857e-6e85b171be01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265761471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2265761471
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1429385469
Short name T416
Test name
Test status
Simulation time 514500640 ps
CPU time 2.12 seconds
Started May 26 02:50:44 PM PDT 24
Finished May 26 02:50:48 PM PDT 24
Peak memory 206880 kb
Host smart-c56b6cba-75b6-4810-9f43-497557da9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429385469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1429385469
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1594532954
Short name T328
Test name
Test status
Simulation time 567388053 ps
CPU time 7.69 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:56 PM PDT 24
Peak memory 220352 kb
Host smart-e9771ce7-8f0b-4d22-b8e3-f18f031e430a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594532954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1594532954
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1772866095
Short name T114
Test name
Test status
Simulation time 1002679698 ps
CPU time 14.42 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:51:01 PM PDT 24
Peak memory 221656 kb
Host smart-87a7132a-5078-48ed-8e8f-bdd59de1725c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772866095 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1772866095
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1088213519
Short name T26
Test name
Test status
Simulation time 656506899 ps
CPU time 4.28 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 219740 kb
Host smart-6d1b7e83-0c3e-4e0e-b64c-e098a4a2fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088213519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1088213519
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.759419048
Short name T698
Test name
Test status
Simulation time 79028253 ps
CPU time 2.16 seconds
Started May 26 02:50:47 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 214460 kb
Host smart-5cdcaa14-e0bb-4a53-8c14-d8885313cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759419048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.759419048
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2186533312
Short name T770
Test name
Test status
Simulation time 10372090 ps
CPU time 0.77 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:52 PM PDT 24
Peak memory 206008 kb
Host smart-f897782d-2a27-4b57-83ff-f5e06ecc7003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186533312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2186533312
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1879753579
Short name T13
Test name
Test status
Simulation time 53429413 ps
CPU time 3.94 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:46 PM PDT 24
Peak memory 215456 kb
Host smart-be2f4a0d-0207-4114-a6fa-05d2e4b38ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879753579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1879753579
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2051901588
Short name T21
Test name
Test status
Simulation time 229561301 ps
CPU time 5.57 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:51 PM PDT 24
Peak memory 209444 kb
Host smart-95f52f1d-4048-42f1-8198-dfa4e999a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051901588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2051901588
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4022003710
Short name T915
Test name
Test status
Simulation time 53380161 ps
CPU time 2.45 seconds
Started May 26 02:48:45 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 207512 kb
Host smart-4ee6aee7-4e1f-45d9-a3aa-d9060c5c5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022003710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4022003710
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3599366388
Short name T718
Test name
Test status
Simulation time 66804367 ps
CPU time 2.67 seconds
Started May 26 02:48:42 PM PDT 24
Finished May 26 02:48:45 PM PDT 24
Peak memory 214368 kb
Host smart-d4610df9-7237-4120-add9-75effdbc7628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599366388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3599366388
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3391917703
Short name T271
Test name
Test status
Simulation time 38543367 ps
CPU time 2.05 seconds
Started May 26 02:48:45 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 214324 kb
Host smart-97210f8d-8bdb-4d05-b200-e1daf5df525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391917703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3391917703
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3362973783
Short name T207
Test name
Test status
Simulation time 96394796 ps
CPU time 5 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 214348 kb
Host smart-bdb40558-92ee-4396-ae44-bdda064a3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362973783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3362973783
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2371446537
Short name T673
Test name
Test status
Simulation time 486967551 ps
CPU time 5.55 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 207692 kb
Host smart-10f6bbba-094b-4444-98e4-225bf941defa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371446537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2371446537
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3643620567
Short name T820
Test name
Test status
Simulation time 2156017412 ps
CPU time 4.34 seconds
Started May 26 02:48:41 PM PDT 24
Finished May 26 02:48:46 PM PDT 24
Peak memory 206948 kb
Host smart-1810f846-42fa-4f20-ba0f-ebec83ca7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643620567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3643620567
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.305787575
Short name T132
Test name
Test status
Simulation time 89319874 ps
CPU time 2.64 seconds
Started May 26 02:48:44 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 206988 kb
Host smart-a3025dd0-9bf7-4bbb-b6dc-0fd394f8c657
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305787575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.305787575
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3993966941
Short name T484
Test name
Test status
Simulation time 102886129 ps
CPU time 3.05 seconds
Started May 26 02:48:45 PM PDT 24
Finished May 26 02:48:49 PM PDT 24
Peak memory 207028 kb
Host smart-ae37f604-ff05-4b75-9046-cc6bf5d702a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993966941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3993966941
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.998726402
Short name T731
Test name
Test status
Simulation time 516816351 ps
CPU time 4.01 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:49 PM PDT 24
Peak memory 206976 kb
Host smart-14d87989-c59d-42e1-b790-e8bd1461f5f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998726402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.998726402
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.268497497
Short name T332
Test name
Test status
Simulation time 1001772043 ps
CPU time 5.19 seconds
Started May 26 02:48:52 PM PDT 24
Finished May 26 02:48:59 PM PDT 24
Peak memory 218248 kb
Host smart-82695141-8f05-4bdd-aba6-a6a64c60b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268497497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.268497497
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1439551287
Short name T521
Test name
Test status
Simulation time 43710604 ps
CPU time 2.06 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 207020 kb
Host smart-e363eb80-1623-464a-8a82-f1a5f7a82aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439551287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1439551287
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1741280304
Short name T775
Test name
Test status
Simulation time 1017232166 ps
CPU time 30.98 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 216388 kb
Host smart-24f833ad-25ee-4289-a71b-14ec8ebdc231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741280304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1741280304
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4247144418
Short name T816
Test name
Test status
Simulation time 86558116 ps
CPU time 3.52 seconds
Started May 26 02:48:43 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 207456 kb
Host smart-890ea466-4cca-4470-a7b7-16df326860d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247144418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4247144418
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1621554189
Short name T600
Test name
Test status
Simulation time 220793144 ps
CPU time 2.69 seconds
Started May 26 02:48:53 PM PDT 24
Finished May 26 02:48:58 PM PDT 24
Peak memory 210324 kb
Host smart-4ab10b58-1291-4fca-92e8-60db67d2b33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621554189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1621554189
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.490731365
Short name T486
Test name
Test status
Simulation time 13397310 ps
CPU time 0.77 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:50:55 PM PDT 24
Peak memory 206012 kb
Host smart-4bbea2e9-a410-49b2-90b4-c4036ceaf9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490731365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.490731365
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4022366691
Short name T372
Test name
Test status
Simulation time 195406057 ps
CPU time 10.23 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 214308 kb
Host smart-050fa2ce-8324-482b-a590-bc984cca8f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022366691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4022366691
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1153063773
Short name T518
Test name
Test status
Simulation time 32266152 ps
CPU time 2.24 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208532 kb
Host smart-040e333d-ced3-414e-9a3a-0e57aa01d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153063773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1153063773
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1838132496
Short name T288
Test name
Test status
Simulation time 282478508 ps
CPU time 3.94 seconds
Started May 26 02:50:50 PM PDT 24
Finished May 26 02:50:55 PM PDT 24
Peak memory 218560 kb
Host smart-93f21739-f9d9-459b-8d6d-168910816ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838132496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1838132496
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1280597111
Short name T803
Test name
Test status
Simulation time 3641189637 ps
CPU time 21.92 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 214452 kb
Host smart-375302fe-d2d9-4ed7-a9b4-2346ce5c99fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280597111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1280597111
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1160150384
Short name T289
Test name
Test status
Simulation time 275421572 ps
CPU time 4.67 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:52 PM PDT 24
Peak memory 214560 kb
Host smart-b408104c-d3d8-4dae-945c-e92be37a6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160150384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1160150384
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2534193109
Short name T653
Test name
Test status
Simulation time 112097861 ps
CPU time 4.66 seconds
Started May 26 02:50:50 PM PDT 24
Finished May 26 02:50:56 PM PDT 24
Peak memory 216360 kb
Host smart-abf39789-fd4d-4c96-8d29-68c1fb4d8907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534193109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2534193109
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.792620248
Short name T695
Test name
Test status
Simulation time 76568521 ps
CPU time 3.85 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 207608 kb
Host smart-4ed45f36-0122-46fc-9097-91a048b153f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792620248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.792620248
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2614976252
Short name T836
Test name
Test status
Simulation time 42308698 ps
CPU time 2.52 seconds
Started May 26 02:50:47 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 208308 kb
Host smart-42c41804-fefc-4a6d-ba39-f505b09b788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614976252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2614976252
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1682632128
Short name T779
Test name
Test status
Simulation time 3698165977 ps
CPU time 24.2 seconds
Started May 26 02:50:45 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 208540 kb
Host smart-39ab05a3-3818-4152-afd8-fe35a094f9ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682632128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1682632128
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4030372095
Short name T652
Test name
Test status
Simulation time 845741227 ps
CPU time 6.94 seconds
Started May 26 02:50:48 PM PDT 24
Finished May 26 02:50:56 PM PDT 24
Peak memory 208660 kb
Host smart-581a421d-b87b-42b2-881a-e17bcda7fe70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030372095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4030372095
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.282457824
Short name T825
Test name
Test status
Simulation time 53534783 ps
CPU time 2.7 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:50 PM PDT 24
Peak memory 207012 kb
Host smart-07a316d3-98b3-433f-aaa8-be18a4d010ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282457824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.282457824
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2568293885
Short name T607
Test name
Test status
Simulation time 31862128 ps
CPU time 2.31 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 210096 kb
Host smart-a5c53898-8f7b-495d-b841-31a82503e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568293885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2568293885
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3550369831
Short name T502
Test name
Test status
Simulation time 472983504 ps
CPU time 2.54 seconds
Started May 26 02:50:49 PM PDT 24
Finished May 26 02:50:54 PM PDT 24
Peak memory 206916 kb
Host smart-092620d5-717a-4024-a142-d739901da767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550369831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3550369831
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2084835296
Short name T296
Test name
Test status
Simulation time 1048550226 ps
CPU time 15.14 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 216604 kb
Host smart-7009ddba-de58-4c77-ad1c-16e79a692dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084835296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2084835296
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3502604501
Short name T670
Test name
Test status
Simulation time 1273428714 ps
CPU time 18.75 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 222628 kb
Host smart-b93bfa4f-a8ee-44e5-8bef-8e6a4a90a87a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502604501 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3502604501
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1970094974
Short name T451
Test name
Test status
Simulation time 165894793 ps
CPU time 4.48 seconds
Started May 26 02:50:46 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 207468 kb
Host smart-ed09868b-39b0-4c64-9fd8-9b2326c55777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970094974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1970094974
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1966536115
Short name T614
Test name
Test status
Simulation time 186728812 ps
CPU time 2.64 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:50:57 PM PDT 24
Peak memory 210404 kb
Host smart-5e3681b6-f2ee-4670-8e25-d5d3206f084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966536115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1966536115
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3090349861
Short name T840
Test name
Test status
Simulation time 38698148 ps
CPU time 0.73 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:50:55 PM PDT 24
Peak memory 206008 kb
Host smart-051ccd42-aea8-48a1-9e78-9b6c78a04037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090349861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3090349861
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.46979275
Short name T27
Test name
Test status
Simulation time 363735342 ps
CPU time 3.25 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 214392 kb
Host smart-f3821cbd-0c42-4675-9343-d93380812740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46979275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.46979275
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3368477278
Short name T848
Test name
Test status
Simulation time 302514910 ps
CPU time 2.35 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 206928 kb
Host smart-45ba7dd6-d012-4291-9080-f3debef71573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368477278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3368477278
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2083191784
Short name T52
Test name
Test status
Simulation time 344555005 ps
CPU time 3.47 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 214380 kb
Host smart-f108432a-6332-4eb4-a996-906207a4b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083191784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2083191784
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.454913122
Short name T261
Test name
Test status
Simulation time 237310741 ps
CPU time 3.16 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 220508 kb
Host smart-cc3131a2-fca3-49cd-ae30-2989a48969a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454913122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.454913122
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.96350198
Short name T212
Test name
Test status
Simulation time 214956194 ps
CPU time 3.76 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 222648 kb
Host smart-18baf7dd-6173-4589-9bee-56a467aaf510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96350198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.96350198
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1165145080
Short name T912
Test name
Test status
Simulation time 3863144048 ps
CPU time 7.42 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:02 PM PDT 24
Peak memory 218400 kb
Host smart-923a7bad-d53c-422b-9c52-c649d0e1606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165145080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1165145080
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2278566728
Short name T581
Test name
Test status
Simulation time 1239948304 ps
CPU time 16.58 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 208324 kb
Host smart-bf4540fe-c18f-4dbe-81d5-d2e93323595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278566728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2278566728
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2186051463
Short name T450
Test name
Test status
Simulation time 32935311 ps
CPU time 2.4 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 206852 kb
Host smart-900eb14e-e059-4515-8a96-da8dcb3398a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186051463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2186051463
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.558089664
Short name T548
Test name
Test status
Simulation time 412256154 ps
CPU time 8.01 seconds
Started May 26 02:50:52 PM PDT 24
Finished May 26 02:51:02 PM PDT 24
Peak memory 207952 kb
Host smart-f76d61f1-ea5e-40dd-adf3-acbf29043892
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558089664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.558089664
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3143130700
Short name T768
Test name
Test status
Simulation time 65313010 ps
CPU time 2.66 seconds
Started May 26 02:50:52 PM PDT 24
Finished May 26 02:50:57 PM PDT 24
Peak memory 208636 kb
Host smart-9c9520f2-0545-4d2d-aaf6-28e08d8d5f4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143130700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3143130700
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3923126636
Short name T200
Test name
Test status
Simulation time 468758719 ps
CPU time 2.91 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 214372 kb
Host smart-be993410-f478-41ba-9f40-6e98e7d670f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923126636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3923126636
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.40289841
Short name T531
Test name
Test status
Simulation time 33714239 ps
CPU time 2.15 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 206800 kb
Host smart-a4ef19a0-8f50-4f18-8036-1bf7a32fd244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40289841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.40289841
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2771578852
Short name T594
Test name
Test status
Simulation time 263364800 ps
CPU time 8.95 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 222596 kb
Host smart-a1315858-73d1-4ec1-980d-77022c8fcd23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771578852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2771578852
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2018432980
Short name T274
Test name
Test status
Simulation time 115233945 ps
CPU time 4.57 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 218668 kb
Host smart-18cb3b23-4d7f-452c-9585-b1ccdaa2a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018432980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2018432980
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.198365230
Short name T777
Test name
Test status
Simulation time 41800551 ps
CPU time 1.86 seconds
Started May 26 02:50:52 PM PDT 24
Finished May 26 02:50:55 PM PDT 24
Peak memory 209852 kb
Host smart-972652ae-0f85-4c27-9f30-f9f90001e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198365230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.198365230
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1418951577
Short name T408
Test name
Test status
Simulation time 53724186 ps
CPU time 0.86 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 206008 kb
Host smart-05945086-898c-4de5-824d-a7332217aa54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418951577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1418951577
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1296228048
Short name T48
Test name
Test status
Simulation time 80630729 ps
CPU time 1.88 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 209720 kb
Host smart-38ded4f1-b124-4df3-98e8-bee4e6f3316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296228048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1296228048
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4089240053
Short name T95
Test name
Test status
Simulation time 67022445 ps
CPU time 3.29 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208684 kb
Host smart-21a742d6-a692-4d13-b97c-597a664fa108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089240053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4089240053
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.863525831
Short name T412
Test name
Test status
Simulation time 235304353 ps
CPU time 3.12 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 222508 kb
Host smart-7a47f48d-6818-4036-99fa-df11e6764dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863525831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.863525831
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3580699122
Short name T584
Test name
Test status
Simulation time 362425178 ps
CPU time 1.88 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:50:58 PM PDT 24
Peak memory 214356 kb
Host smart-fff08341-6e46-4d35-8198-fcea450ac6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580699122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3580699122
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2861979105
Short name T496
Test name
Test status
Simulation time 208207025 ps
CPU time 3.57 seconds
Started May 26 02:50:55 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208408 kb
Host smart-7b075411-a063-4dd4-986e-103ac61b7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861979105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2861979105
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2401840901
Short name T342
Test name
Test status
Simulation time 921676951 ps
CPU time 24.13 seconds
Started May 26 02:50:53 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 207996 kb
Host smart-50bc6110-beca-4e3b-822b-485e60fd338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401840901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2401840901
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2473865123
Short name T906
Test name
Test status
Simulation time 221684931 ps
CPU time 3.13 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 209048 kb
Host smart-dff7ecc4-4bce-4cd7-bcc4-35e91d5dd047
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473865123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2473865123
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3186523038
Short name T393
Test name
Test status
Simulation time 82432682 ps
CPU time 3.86 seconds
Started May 26 02:50:54 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208864 kb
Host smart-265e0de8-a8ca-4d21-b25c-250027e9318c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186523038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3186523038
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2805576310
Short name T203
Test name
Test status
Simulation time 141972930 ps
CPU time 2.68 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208664 kb
Host smart-563e78ef-3054-448f-acff-8545e9f94c6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805576310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2805576310
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1739079844
Short name T435
Test name
Test status
Simulation time 29635435 ps
CPU time 2.14 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 216124 kb
Host smart-304b2809-1272-4a3d-a2a0-5f4e16be26d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739079844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1739079844
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1653548936
Short name T636
Test name
Test status
Simulation time 145304234 ps
CPU time 2.61 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:51:00 PM PDT 24
Peak memory 208560 kb
Host smart-92fc89e7-24be-4fc7-bcc4-ff6439c941a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653548936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1653548936
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3456095229
Short name T299
Test name
Test status
Simulation time 2744151604 ps
CPU time 36.15 seconds
Started May 26 02:51:00 PM PDT 24
Finished May 26 02:51:37 PM PDT 24
Peak memory 217344 kb
Host smart-17590507-189c-468d-a7c3-9d25b23e2660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456095229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3456095229
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3163297744
Short name T828
Test name
Test status
Simulation time 594677176 ps
CPU time 10.05 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 219168 kb
Host smart-2f212398-b597-48ee-933a-2be89ae0d0e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163297744 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3163297744
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.937279411
Short name T689
Test name
Test status
Simulation time 123390519 ps
CPU time 4.42 seconds
Started May 26 02:50:56 PM PDT 24
Finished May 26 02:51:02 PM PDT 24
Peak memory 208768 kb
Host smart-378f8c20-efb6-4f6e-b5f4-bc2dd38562b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937279411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.937279411
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2613654393
Short name T358
Test name
Test status
Simulation time 531221942 ps
CPU time 2.97 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 211152 kb
Host smart-d576a376-5460-490c-80da-898434232f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613654393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2613654393
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.481757196
Short name T664
Test name
Test status
Simulation time 23839935 ps
CPU time 0.73 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 205996 kb
Host smart-d471eac7-9973-44ef-95da-3d27b1bb256b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481757196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.481757196
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2749592804
Short name T516
Test name
Test status
Simulation time 52583273 ps
CPU time 1.23 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 222516 kb
Host smart-d31c2359-1459-486f-9aa1-9065d27eee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749592804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2749592804
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.302442894
Short name T388
Test name
Test status
Simulation time 46018016 ps
CPU time 2.11 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 209816 kb
Host smart-99bc84a0-4216-414f-bc85-85febf9dead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302442894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.302442894
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.177151681
Short name T353
Test name
Test status
Simulation time 1084403714 ps
CPU time 11.7 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 214372 kb
Host smart-9dc6b2de-c0d0-4bc4-b60f-f479ecf3d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177151681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.177151681
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3814701294
Short name T817
Test name
Test status
Simulation time 1029142509 ps
CPU time 3.48 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 220232 kb
Host smart-872d37c0-9e88-4ef3-aae4-637056b80431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814701294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3814701294
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.861305936
Short name T214
Test name
Test status
Simulation time 347894418 ps
CPU time 2.94 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 216360 kb
Host smart-31de3e5f-4128-47e8-9e19-4f3d4bc4f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861305936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.861305936
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1235073516
Short name T699
Test name
Test status
Simulation time 670083530 ps
CPU time 4.39 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 208100 kb
Host smart-83d0eb88-eed8-4218-bd4c-416acf74c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235073516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1235073516
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.488714625
Short name T196
Test name
Test status
Simulation time 35840874 ps
CPU time 2.53 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 208568 kb
Host smart-3f79d6e0-3d2e-4ac7-93cc-a315eb040829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488714625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.488714625
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2330816430
Short name T565
Test name
Test status
Simulation time 161467947 ps
CPU time 3.62 seconds
Started May 26 02:50:59 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 208832 kb
Host smart-d89e480a-5790-4cbc-b69a-63a82216c4aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330816430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2330816430
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.899349908
Short name T558
Test name
Test status
Simulation time 610086470 ps
CPU time 5.22 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 209160 kb
Host smart-2a9d0b1d-ca23-4d6a-9225-07fc32c05adb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899349908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.899349908
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4258345265
Short name T302
Test name
Test status
Simulation time 73402353 ps
CPU time 2.81 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 208720 kb
Host smart-a9ee5125-8cd6-4533-8389-228eb62fa0f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258345265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4258345265
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.317902589
Short name T674
Test name
Test status
Simulation time 125459824 ps
CPU time 4.92 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 215292 kb
Host smart-1f72cee1-5500-4aae-8b53-c837552cd177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317902589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.317902589
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1869231886
Short name T400
Test name
Test status
Simulation time 170771052 ps
CPU time 2.6 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 208572 kb
Host smart-2af064c1-612d-43ec-b975-260aa4fb8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869231886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1869231886
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1954022397
Short name T628
Test name
Test status
Simulation time 123838646 ps
CPU time 5.45 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 215212 kb
Host smart-56b2bc3b-f7d5-4b02-8eb1-b33abebc2109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954022397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1954022397
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3596977202
Short name T105
Test name
Test status
Simulation time 305001694 ps
CPU time 13.27 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 222792 kb
Host smart-7d037482-c972-4c88-b653-670fad99b2cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596977202 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3596977202
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4217992922
Short name T457
Test name
Test status
Simulation time 249950770 ps
CPU time 5.94 seconds
Started May 26 02:51:06 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 214496 kb
Host smart-8f4af93c-feab-4e4b-a023-60608fb54c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217992922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4217992922
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2236736676
Short name T188
Test name
Test status
Simulation time 56482794 ps
CPU time 3.05 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 210344 kb
Host smart-2fc8d0c5-4482-45da-a711-9f7923f0928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236736676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2236736676
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1332736922
Short name T799
Test name
Test status
Simulation time 15078533 ps
CPU time 0.8 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 206000 kb
Host smart-eb34e52c-222a-44a6-b19e-5f18a48bfe21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332736922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1332736922
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3669153879
Short name T778
Test name
Test status
Simulation time 1914629827 ps
CPU time 3.18 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:09 PM PDT 24
Peak memory 209028 kb
Host smart-6bd20128-e201-4004-b48a-02e7284d3e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669153879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3669153879
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.748872875
Short name T715
Test name
Test status
Simulation time 1017904833 ps
CPU time 10.82 seconds
Started May 26 02:51:06 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 214356 kb
Host smart-360caf47-74d2-4ddb-b9de-27a91c9be895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748872875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.748872875
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.915069239
Short name T290
Test name
Test status
Simulation time 344072817 ps
CPU time 2.94 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 214400 kb
Host smart-99d0a855-ebe0-433e-8fab-d4870dea5629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915069239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.915069239
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2310304278
Short name T326
Test name
Test status
Simulation time 138766671 ps
CPU time 3.55 seconds
Started May 26 02:51:07 PM PDT 24
Finished May 26 02:51:12 PM PDT 24
Peak memory 214300 kb
Host smart-0fb595d9-0ece-40c5-a3f6-e6ba22d3d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310304278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2310304278
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3656286805
Short name T793
Test name
Test status
Simulation time 42945152 ps
CPU time 1.95 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 214356 kb
Host smart-4f7e7b05-42b2-4f52-9622-7298fef11909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656286805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3656286805
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.554280940
Short name T593
Test name
Test status
Simulation time 298822302 ps
CPU time 8.5 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:14 PM PDT 24
Peak memory 218264 kb
Host smart-d0212c1a-2e2c-4101-babc-3eeb97ba5188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554280940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.554280940
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3377248203
Short name T530
Test name
Test status
Simulation time 81853792 ps
CPU time 1.81 seconds
Started May 26 02:51:00 PM PDT 24
Finished May 26 02:51:03 PM PDT 24
Peak memory 206904 kb
Host smart-276e6ed8-175d-4965-83ce-18f13728ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377248203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3377248203
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1922867831
Short name T708
Test name
Test status
Simulation time 1174270807 ps
CPU time 23.72 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:30 PM PDT 24
Peak memory 208636 kb
Host smart-9c85aba4-e88b-468d-bc15-2fccceffb476
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922867831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1922867831
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3213430654
Short name T334
Test name
Test status
Simulation time 277758667 ps
CPU time 3.72 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 208592 kb
Host smart-3677cfb3-154e-406e-bc7a-51d42fb65a45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213430654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3213430654
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.835519661
Short name T527
Test name
Test status
Simulation time 321512666 ps
CPU time 3.44 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 208608 kb
Host smart-b6719b72-c915-439f-9955-82d16ba2854c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835519661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.835519661
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.269360771
Short name T336
Test name
Test status
Simulation time 577942837 ps
CPU time 2.2 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 214380 kb
Host smart-2a44cd46-cab0-4688-a20e-7aa1e8766109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269360771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.269360771
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1584936356
Short name T189
Test name
Test status
Simulation time 114785658 ps
CPU time 3.1 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:05 PM PDT 24
Peak memory 208604 kb
Host smart-6b49fb58-50d0-4e3e-9989-84dccbdf8a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584936356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1584936356
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3536047040
Short name T211
Test name
Test status
Simulation time 44297794507 ps
CPU time 520.55 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:59:45 PM PDT 24
Peak memory 218956 kb
Host smart-7e7f20f4-a607-4d57-9972-95366815d059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536047040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3536047040
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3754935422
Short name T275
Test name
Test status
Simulation time 61376468 ps
CPU time 3.97 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 214396 kb
Host smart-19a42823-3eee-4487-a649-9371ace444f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754935422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3754935422
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.971816087
Short name T913
Test name
Test status
Simulation time 52628141 ps
CPU time 2.52 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 210300 kb
Host smart-55fc55ca-0848-437f-8e14-1d6caf419d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971816087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.971816087
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2460457246
Short name T533
Test name
Test status
Simulation time 44831104 ps
CPU time 0.88 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 206004 kb
Host smart-7105064f-e34b-4047-b161-635e133c129d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460457246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2460457246
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2975282573
Short name T243
Test name
Test status
Simulation time 135079987 ps
CPU time 4.79 seconds
Started May 26 02:51:07 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 215376 kb
Host smart-227d42fe-03b2-4b05-9322-0f3787223d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975282573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2975282573
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4223317357
Short name T401
Test name
Test status
Simulation time 456190731 ps
CPU time 5.35 seconds
Started May 26 02:51:06 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 214784 kb
Host smart-59707e53-6125-409d-b15f-39ef9c0be223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223317357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4223317357
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1523623226
Short name T746
Test name
Test status
Simulation time 94392690 ps
CPU time 2.03 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 218556 kb
Host smart-20a73c1e-0824-4781-80cb-efcbef9f680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523623226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1523623226
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1965529972
Short name T66
Test name
Test status
Simulation time 35574590 ps
CPU time 2.79 seconds
Started May 26 02:51:06 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 220808 kb
Host smart-1c7521c9-b0d7-45f3-966c-0963a7823808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965529972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1965529972
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3414018302
Short name T738
Test name
Test status
Simulation time 148263343 ps
CPU time 2.83 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 214356 kb
Host smart-b12d8623-b37d-48da-a2f4-eb528b9f11e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414018302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3414018302
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2233737101
Short name T702
Test name
Test status
Simulation time 373393592 ps
CPU time 4.65 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 208168 kb
Host smart-5350d324-0791-4fa9-a4fa-0a9d96cb397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233737101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2233737101
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3258666580
Short name T544
Test name
Test status
Simulation time 77108809 ps
CPU time 1.99 seconds
Started May 26 02:51:01 PM PDT 24
Finished May 26 02:51:03 PM PDT 24
Peak memory 207568 kb
Host smart-39966ed0-fa4e-4ff6-a993-3a54c2a31c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258666580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3258666580
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.639494465
Short name T847
Test name
Test status
Simulation time 69102742 ps
CPU time 3.45 seconds
Started May 26 02:51:07 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 208788 kb
Host smart-27b78c5d-c0b6-436d-9c22-79b88843a5ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639494465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.639494465
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.338542941
Short name T908
Test name
Test status
Simulation time 117456113 ps
CPU time 2.31 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 206844 kb
Host smart-81c1527b-759a-45ea-9e67-52e286c17360
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338542941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.338542941
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3882275012
Short name T638
Test name
Test status
Simulation time 14975626227 ps
CPU time 28.02 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:34 PM PDT 24
Peak memory 208856 kb
Host smart-4166b90d-f1b8-4e37-bbd4-ac67b8797b61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882275012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3882275012
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.901353228
Short name T846
Test name
Test status
Simulation time 114049194 ps
CPU time 1.83 seconds
Started May 26 02:51:02 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 208416 kb
Host smart-e0f3c1ef-ff63-40e8-aed9-b9999092a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901353228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.901353228
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.556936317
Short name T765
Test name
Test status
Simulation time 34101109 ps
CPU time 2.25 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:07 PM PDT 24
Peak memory 206832 kb
Host smart-03d1a301-dcbb-4ee6-9a4f-7738cccc5a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556936317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.556936317
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.614341514
Short name T239
Test name
Test status
Simulation time 335723383 ps
CPU time 17.36 seconds
Started May 26 02:51:04 PM PDT 24
Finished May 26 02:51:23 PM PDT 24
Peak memory 222148 kb
Host smart-11c1d7cc-5e02-49f5-9636-1a7b91c1a24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614341514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.614341514
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2907366446
Short name T615
Test name
Test status
Simulation time 1272669280 ps
CPU time 21.45 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:28 PM PDT 24
Peak memory 222664 kb
Host smart-9bfa58a2-15af-4fdf-a23a-32f63e0ed7a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907366446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2907366446
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3844378632
Short name T458
Test name
Test status
Simulation time 81616560 ps
CPU time 4.45 seconds
Started May 26 02:51:05 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 209032 kb
Host smart-094dfbbb-a61b-4039-b208-cd974a2f43bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844378632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3844378632
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2613682155
Short name T175
Test name
Test status
Simulation time 131599170 ps
CPU time 2.74 seconds
Started May 26 02:51:03 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 210272 kb
Host smart-e5511f69-739d-443f-95dd-6eec50ba5300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613682155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2613682155
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3743693794
Short name T729
Test name
Test status
Simulation time 8774374 ps
CPU time 0.71 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 205992 kb
Host smart-1f85f1e6-94cf-4a0c-af07-aa812ce178b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743693794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3743693794
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2071696866
Short name T309
Test name
Test status
Simulation time 188410921 ps
CPU time 8.15 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 215732 kb
Host smart-9e0f3c7c-70e1-4dd4-b67f-5899923b4c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071696866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2071696866
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2933522878
Short name T31
Test name
Test status
Simulation time 19539338 ps
CPU time 1.63 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:12 PM PDT 24
Peak memory 215408 kb
Host smart-f7b4f2d7-7952-48b7-ac92-4d0f68089643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933522878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2933522878
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.332730521
Short name T675
Test name
Test status
Simulation time 196989886 ps
CPU time 2.57 seconds
Started May 26 02:51:06 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 209368 kb
Host smart-876deb2e-b629-4716-8838-4c1c8e5b6b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332730521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.332730521
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3903270831
Short name T620
Test name
Test status
Simulation time 154930144 ps
CPU time 4.24 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:14 PM PDT 24
Peak memory 220532 kb
Host smart-ca587e28-3e6a-4c5a-a6ad-27086c683191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903270831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3903270831
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1212100504
Short name T894
Test name
Test status
Simulation time 172069928 ps
CPU time 6.71 seconds
Started May 26 02:51:13 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 214344 kb
Host smart-35f09114-e941-40f4-9639-08ac503e9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212100504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1212100504
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4113288669
Short name T583
Test name
Test status
Simulation time 21814504 ps
CPU time 1.88 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 207012 kb
Host smart-1bfe8206-5e88-4f04-b9fa-cab52955dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113288669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4113288669
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1225326043
Short name T676
Test name
Test status
Simulation time 108421401 ps
CPU time 4.27 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:15 PM PDT 24
Peak memory 208472 kb
Host smart-1e07ebcd-3dc8-45ac-8096-dce17f2d946d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225326043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1225326043
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3584435702
Short name T800
Test name
Test status
Simulation time 1184667184 ps
CPU time 31.6 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:45 PM PDT 24
Peak memory 208096 kb
Host smart-b97d6cfa-460b-480c-96b1-dff001b1e58c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584435702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3584435702
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4100688240
Short name T560
Test name
Test status
Simulation time 187931284 ps
CPU time 3.09 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:14 PM PDT 24
Peak memory 206992 kb
Host smart-41472008-5bce-4fc4-a874-be4d6175d334
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100688240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4100688240
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.665469167
Short name T671
Test name
Test status
Simulation time 527673214 ps
CPU time 8.3 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 214348 kb
Host smart-a32ceada-29ef-421c-897c-f675d13de3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665469167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.665469167
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2977659633
Short name T905
Test name
Test status
Simulation time 135197076 ps
CPU time 2.99 seconds
Started May 26 02:51:07 PM PDT 24
Finished May 26 02:51:11 PM PDT 24
Peak memory 208340 kb
Host smart-f8f17bc2-e1ed-417a-83e1-73515b99c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977659633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2977659633
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4244366596
Short name T468
Test name
Test status
Simulation time 407037064 ps
CPU time 5.1 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 222412 kb
Host smart-035f0bfb-bff7-4be9-8395-c0a75738091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244366596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4244366596
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.611333219
Short name T488
Test name
Test status
Simulation time 92247583 ps
CPU time 2.06 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 209908 kb
Host smart-9e1c6014-bb83-46f6-a488-da5c197ac23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611333219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.611333219
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2342590027
Short name T399
Test name
Test status
Simulation time 21800796 ps
CPU time 0.73 seconds
Started May 26 02:51:08 PM PDT 24
Finished May 26 02:51:10 PM PDT 24
Peak memory 206012 kb
Host smart-57ec0f14-d5a5-47d9-b20a-066c1b79aa9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342590027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2342590027
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.197145903
Short name T282
Test name
Test status
Simulation time 64751286 ps
CPU time 2.9 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 214380 kb
Host smart-2a5eb58e-73eb-43e1-8f1b-e175fbcfa897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=197145903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.197145903
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1619791320
Short name T28
Test name
Test status
Simulation time 352068439 ps
CPU time 3.56 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:15 PM PDT 24
Peak memory 218308 kb
Host smart-367d5179-edaf-4137-9801-3fba4849cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619791320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1619791320
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3407584336
Short name T601
Test name
Test status
Simulation time 128759690 ps
CPU time 2.47 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 207556 kb
Host smart-151897fb-9da3-41d4-9bc5-b456e0ed07f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407584336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3407584336
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4141476307
Short name T292
Test name
Test status
Simulation time 97907133 ps
CPU time 3.89 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 214580 kb
Host smart-e6ad1ff5-a233-4ff2-bb81-2a2ea9716b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141476307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4141476307
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3823151274
Short name T845
Test name
Test status
Simulation time 88104177 ps
CPU time 2.93 seconds
Started May 26 02:51:13 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 209620 kb
Host smart-0aa27f72-7190-4b24-8de7-b3ed49a8494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823151274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3823151274
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1719392259
Short name T661
Test name
Test status
Simulation time 1462502461 ps
CPU time 33.15 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:49 PM PDT 24
Peak memory 207880 kb
Host smart-c8020735-2e52-488b-b468-81a9a3e646f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719392259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1719392259
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1077872923
Short name T665
Test name
Test status
Simulation time 104611467 ps
CPU time 2.82 seconds
Started May 26 02:51:14 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 206844 kb
Host smart-a6b9682c-f563-41e5-ab23-2a35fabf0153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077872923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1077872923
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4136956957
Short name T499
Test name
Test status
Simulation time 81319696 ps
CPU time 3.1 seconds
Started May 26 02:51:09 PM PDT 24
Finished May 26 02:51:13 PM PDT 24
Peak memory 206872 kb
Host smart-83a1277e-0242-43ff-b5e3-4ef049409f6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136956957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4136956957
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1360286455
Short name T419
Test name
Test status
Simulation time 284090926 ps
CPU time 2.84 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 206860 kb
Host smart-cc2a0630-891f-466d-8907-2e7b44d722fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360286455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1360286455
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.189690566
Short name T869
Test name
Test status
Simulation time 135257571 ps
CPU time 4.23 seconds
Started May 26 02:51:13 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 208352 kb
Host smart-ba041bf9-f1a5-4eee-9286-56036a38f084
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189690566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.189690566
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1785808562
Short name T485
Test name
Test status
Simulation time 153487281 ps
CPU time 3.02 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 218264 kb
Host smart-6c8ff9ed-5a0e-46e2-af79-d6e638daa40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785808562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1785808562
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3051589023
Short name T635
Test name
Test status
Simulation time 242401129 ps
CPU time 2.57 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 206936 kb
Host smart-16d2b170-1a40-4057-ba32-17cb756cb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051589023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3051589023
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.4097573353
Short name T76
Test name
Test status
Simulation time 1290433347 ps
CPU time 11.15 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:25 PM PDT 24
Peak memory 222688 kb
Host smart-fff2e357-3b7e-4fa9-b7b2-fb61a95b504e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097573353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.4097573353
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3003047339
Short name T852
Test name
Test status
Simulation time 583694074 ps
CPU time 15.34 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:30 PM PDT 24
Peak memory 210336 kb
Host smart-85fad9af-1f9e-4bd5-9e95-915bec7ae8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003047339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3003047339
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1314239903
Short name T769
Test name
Test status
Simulation time 253890454 ps
CPU time 2.48 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:20 PM PDT 24
Peak memory 210620 kb
Host smart-0c5ce26e-06fa-4444-833e-eb853ed7aa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314239903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1314239903
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2195029538
Short name T754
Test name
Test status
Simulation time 45692616 ps
CPU time 0.82 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:15 PM PDT 24
Peak memory 206012 kb
Host smart-ad5d79b6-85dc-4612-8064-ead448434feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195029538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2195029538
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3189185799
Short name T861
Test name
Test status
Simulation time 58508601 ps
CPU time 2.58 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:20 PM PDT 24
Peak memory 214384 kb
Host smart-a02b87e3-ffb3-4fb9-b8ff-294827b172cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189185799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3189185799
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2484355146
Short name T555
Test name
Test status
Simulation time 109734564 ps
CPU time 4.82 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 218592 kb
Host smart-4bdaa632-d418-48ad-a91c-b23fe08dd53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484355146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2484355146
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3207183077
Short name T58
Test name
Test status
Simulation time 4001416894 ps
CPU time 18.05 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:31 PM PDT 24
Peak memory 214448 kb
Host smart-cb91fe08-72ae-4c68-a724-835377caf2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207183077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3207183077
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.538124030
Short name T327
Test name
Test status
Simulation time 608820775 ps
CPU time 5 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 214480 kb
Host smart-d602fcc8-3ea7-4ecc-8c87-5b3d3d2b9044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538124030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.538124030
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1770037350
Short name T229
Test name
Test status
Simulation time 775440309 ps
CPU time 5.04 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 222380 kb
Host smart-cf986e80-77ef-4479-8fc7-0d561ed06868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770037350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1770037350
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1319066505
Short name T252
Test name
Test status
Simulation time 1436654317 ps
CPU time 5.87 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 206916 kb
Host smart-ee3070e6-336e-46b1-88f4-14c4339ceb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319066505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1319066505
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.271782666
Short name T509
Test name
Test status
Simulation time 167959628 ps
CPU time 4.09 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 208616 kb
Host smart-153f0134-1e61-4632-9973-da506b537401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271782666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.271782666
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2684008652
Short name T755
Test name
Test status
Simulation time 63097925 ps
CPU time 2.45 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:14 PM PDT 24
Peak memory 207620 kb
Host smart-15699e7b-7408-454a-a5ca-714362b21040
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684008652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2684008652
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3677244256
Short name T687
Test name
Test status
Simulation time 255397529 ps
CPU time 2.71 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 207168 kb
Host smart-65de45a9-454d-4851-89ec-2fda94508682
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677244256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3677244256
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1023022669
Short name T528
Test name
Test status
Simulation time 209966241 ps
CPU time 5.8 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:20 PM PDT 24
Peak memory 208616 kb
Host smart-887ccd84-d80e-4319-ae40-f52e4e554cd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023022669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1023022669
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1599972444
Short name T904
Test name
Test status
Simulation time 234186480 ps
CPU time 3.76 seconds
Started May 26 02:51:17 PM PDT 24
Finished May 26 02:51:24 PM PDT 24
Peak memory 209960 kb
Host smart-58ebfe4d-d0b1-49a5-bac4-6471adac5f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599972444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1599972444
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.770384107
Short name T585
Test name
Test status
Simulation time 424637692 ps
CPU time 3.24 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 206848 kb
Host smart-404ebe9e-6606-4144-bb36-8c18289ab6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770384107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.770384107
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.931359904
Short name T617
Test name
Test status
Simulation time 956357941 ps
CPU time 8.37 seconds
Started May 26 02:51:08 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 222392 kb
Host smart-ccf256d7-7a78-47ca-9b76-863624551200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931359904 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.931359904
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2335550192
Short name T725
Test name
Test status
Simulation time 180998733 ps
CPU time 3.31 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 207500 kb
Host smart-538c8c2e-0ec3-42f8-8c63-77f9729b3358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335550192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2335550192
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.241605202
Short name T493
Test name
Test status
Simulation time 1072825227 ps
CPU time 5.31 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 211080 kb
Host smart-e27157d9-4fbd-4547-8beb-79bdc9782f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241605202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.241605202
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4055032310
Short name T577
Test name
Test status
Simulation time 148794903 ps
CPU time 0.9 seconds
Started May 26 02:51:17 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 205992 kb
Host smart-d82022a8-a4c5-4553-8095-a66fb3015692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055032310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4055032310
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1052425452
Short name T301
Test name
Test status
Simulation time 44736335 ps
CPU time 2.88 seconds
Started May 26 02:51:13 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 215268 kb
Host smart-8ed94df9-fafc-4a10-8dd1-f5be603d2e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052425452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1052425452
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2928767375
Short name T224
Test name
Test status
Simulation time 129390108 ps
CPU time 5.44 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:24 PM PDT 24
Peak memory 218500 kb
Host smart-23f7d89e-a357-4c41-b8fb-8523efa405c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928767375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2928767375
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3334485060
Short name T74
Test name
Test status
Simulation time 2119207335 ps
CPU time 16.18 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:33 PM PDT 24
Peak memory 208596 kb
Host smart-ad7c1927-4b79-4882-9f48-6fa537789445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334485060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3334485060
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1526096519
Short name T727
Test name
Test status
Simulation time 136958743 ps
CPU time 2.42 seconds
Started May 26 02:51:14 PM PDT 24
Finished May 26 02:51:18 PM PDT 24
Peak memory 214332 kb
Host smart-704cfcae-a84d-40c2-80ab-cfab7ad0548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526096519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1526096519
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2233937480
Short name T106
Test name
Test status
Simulation time 49828924 ps
CPU time 2.26 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 222464 kb
Host smart-d774c30d-5965-4eab-9217-c7a7ca3c4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233937480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2233937480
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3322912599
Short name T897
Test name
Test status
Simulation time 110540962 ps
CPU time 3.79 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:22 PM PDT 24
Peak memory 208456 kb
Host smart-53fedef3-ad9d-41ae-9f7e-b9a8c864767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322912599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3322912599
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3416280929
Short name T567
Test name
Test status
Simulation time 325133258 ps
CPU time 3.81 seconds
Started May 26 02:51:11 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 214352 kb
Host smart-30c395d5-e598-412e-8869-b0fb60864514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416280929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3416280929
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2289464939
Short name T857
Test name
Test status
Simulation time 162764336 ps
CPU time 2.88 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:51:20 PM PDT 24
Peak memory 209004 kb
Host smart-33c93f54-c0af-4751-89d4-818574aa7cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289464939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2289464939
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.307073405
Short name T610
Test name
Test status
Simulation time 2727379039 ps
CPU time 54.06 seconds
Started May 26 02:51:16 PM PDT 24
Finished May 26 02:52:11 PM PDT 24
Peak memory 209136 kb
Host smart-3a3088aa-4ca4-48e3-8d21-6189d40e8c7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307073405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.307073405
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2584799130
Short name T107
Test name
Test status
Simulation time 24181738 ps
CPU time 1.89 seconds
Started May 26 02:51:12 PM PDT 24
Finished May 26 02:51:16 PM PDT 24
Peak memory 206744 kb
Host smart-627343e1-5891-46e2-bc04-1a34d8f40ea5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584799130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2584799130
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1992326238
Short name T733
Test name
Test status
Simulation time 215579957 ps
CPU time 4.64 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 207064 kb
Host smart-3df0091d-f74f-4405-af2e-f1ce25f2405d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992326238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1992326238
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1276719152
Short name T572
Test name
Test status
Simulation time 180445585 ps
CPU time 4.02 seconds
Started May 26 02:51:14 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 209876 kb
Host smart-93726e42-ae0b-4695-b46d-440ea300f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276719152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1276719152
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2753781276
Short name T747
Test name
Test status
Simulation time 705215274 ps
CPU time 3.15 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:15 PM PDT 24
Peak memory 206696 kb
Host smart-50f9a0f3-a8e8-4b75-b3a0-a1e87c08cea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753781276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2753781276
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.526522709
Short name T379
Test name
Test status
Simulation time 267469253 ps
CPU time 10.62 seconds
Started May 26 02:51:14 PM PDT 24
Finished May 26 02:51:26 PM PDT 24
Peak memory 221372 kb
Host smart-25c901ca-7e3d-4d3b-9a6e-0544e27b434d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526522709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.526522709
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.683507926
Short name T185
Test name
Test status
Simulation time 984241318 ps
CPU time 8.88 seconds
Started May 26 02:51:10 PM PDT 24
Finished May 26 02:51:20 PM PDT 24
Peak memory 222644 kb
Host smart-f7df2ca8-9ac1-4ade-9c42-d74944b701bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683507926 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.683507926
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3193039665
Short name T317
Test name
Test status
Simulation time 169043211 ps
CPU time 4.25 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:21 PM PDT 24
Peak memory 218580 kb
Host smart-1c157c61-7350-4f88-adbd-cef52b698144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193039665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3193039665
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2667498085
Short name T357
Test name
Test status
Simulation time 123223485 ps
CPU time 2.7 seconds
Started May 26 02:51:15 PM PDT 24
Finished May 26 02:51:19 PM PDT 24
Peak memory 210384 kb
Host smart-c16e26cf-bdfc-40eb-8fa0-a82d01ad559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667498085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2667498085
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.434684075
Short name T657
Test name
Test status
Simulation time 53014223 ps
CPU time 0.86 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 205968 kb
Host smart-eddf9bf0-13a2-43cd-9487-a09098b1e9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434684075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.434684075
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3357133299
Short name T804
Test name
Test status
Simulation time 61177630 ps
CPU time 2.14 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 214688 kb
Host smart-ea86daf3-6900-4624-9eea-03a5919fec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357133299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3357133299
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.164663110
Short name T780
Test name
Test status
Simulation time 38218931 ps
CPU time 1.6 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:48:55 PM PDT 24
Peak memory 208192 kb
Host smart-580e7409-5d28-4ddf-8059-733d8ee1898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164663110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.164663110
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2437089554
Short name T259
Test name
Test status
Simulation time 22203497 ps
CPU time 1.68 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 214372 kb
Host smart-303b41bc-f4ad-49db-96d1-c93c12fb54f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437089554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2437089554
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3538989746
Short name T92
Test name
Test status
Simulation time 118663292 ps
CPU time 5.76 seconds
Started May 26 02:48:52 PM PDT 24
Finished May 26 02:49:00 PM PDT 24
Peak memory 214328 kb
Host smart-43432b7b-381e-4b77-af8e-3a8e78f73d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538989746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3538989746
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4099581365
Short name T745
Test name
Test status
Simulation time 939750938 ps
CPU time 7.19 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:49:00 PM PDT 24
Peak memory 214352 kb
Host smart-f10e07df-2d65-4d4e-8712-4f8af68ddedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099581365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4099581365
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4151077246
Short name T522
Test name
Test status
Simulation time 182700047 ps
CPU time 2.09 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 207512 kb
Host smart-edbb7197-7d38-407e-8765-8aa947b0ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151077246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4151077246
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2166531825
Short name T505
Test name
Test status
Simulation time 213787266 ps
CPU time 2.23 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 206956 kb
Host smart-2fc7b80b-706e-4497-8a90-ac43570d1827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166531825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2166531825
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1167117668
Short name T714
Test name
Test status
Simulation time 106246455 ps
CPU time 3.71 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:55 PM PDT 24
Peak memory 207152 kb
Host smart-730ce00c-bef2-4f10-b5fe-d0dfa405df46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167117668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1167117668
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.579180160
Short name T414
Test name
Test status
Simulation time 85189702 ps
CPU time 2.76 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:48:56 PM PDT 24
Peak memory 206896 kb
Host smart-17f5ef29-7675-433d-bf44-5a210e17b4fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579180160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.579180160
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.110662900
Short name T603
Test name
Test status
Simulation time 34211689 ps
CPU time 1.95 seconds
Started May 26 02:48:49 PM PDT 24
Finished May 26 02:48:52 PM PDT 24
Peak memory 208116 kb
Host smart-480847c3-e184-498a-8db1-3164d4532860
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110662900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.110662900
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2503952307
Short name T864
Test name
Test status
Simulation time 77810842 ps
CPU time 2.82 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 208768 kb
Host smart-d653bc6d-5b65-4b3b-bbd6-bb96aa22abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503952307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2503952307
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2902988077
Short name T444
Test name
Test status
Simulation time 157422912 ps
CPU time 4.87 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 208464 kb
Host smart-ac0eaf8d-1486-4ba6-9501-56e1f0c5ae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902988077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2902988077
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2296051796
Short name T184
Test name
Test status
Simulation time 593401079 ps
CPU time 5.85 seconds
Started May 26 02:48:49 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 219264 kb
Host smart-ccf0d04c-adcd-4bec-b36c-60aa0d610a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296051796 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2296051796
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2787962826
Short name T618
Test name
Test status
Simulation time 2007874864 ps
CPU time 26.78 seconds
Started May 26 02:48:49 PM PDT 24
Finished May 26 02:49:17 PM PDT 24
Peak memory 209636 kb
Host smart-cfa0ddb1-6914-4e61-90a4-8da1c7d65517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787962826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2787962826
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2444393213
Short name T529
Test name
Test status
Simulation time 50617750 ps
CPU time 2.18 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 209924 kb
Host smart-e220f2f9-108c-479a-ac67-50e6d22504ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444393213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2444393213
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3705506177
Short name T654
Test name
Test status
Simulation time 14158548 ps
CPU time 0.75 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:02 PM PDT 24
Peak memory 206000 kb
Host smart-cd936d77-bbb6-4c4d-b6de-e0de5055ff35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705506177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3705506177
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4148102998
Short name T253
Test name
Test status
Simulation time 103991090 ps
CPU time 4.42 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:56 PM PDT 24
Peak memory 215392 kb
Host smart-67de830c-421d-457a-86f2-767ea40f96d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148102998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4148102998
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1357978621
Short name T178
Test name
Test status
Simulation time 217028860 ps
CPU time 2.14 seconds
Started May 26 02:49:01 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 210092 kb
Host smart-940666e8-ae48-452e-88b0-a0c6add88a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357978621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1357978621
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.622655918
Short name T448
Test name
Test status
Simulation time 6912164364 ps
CPU time 12.97 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 209564 kb
Host smart-191e85f2-cd67-44d6-87b7-ed7a79a1c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622655918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.622655918
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3153351321
Short name T837
Test name
Test status
Simulation time 30198894 ps
CPU time 2.24 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:04 PM PDT 24
Peak memory 214664 kb
Host smart-5b0b2a98-3f4e-4d8e-9a67-7b3fafc0fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153351321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3153351321
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1777264824
Short name T886
Test name
Test status
Simulation time 282746601 ps
CPU time 2.78 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 214304 kb
Host smart-b38776bb-38df-4b9a-a3e0-7073de43d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777264824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1777264824
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3142946092
Short name T479
Test name
Test status
Simulation time 146783987 ps
CPU time 3.58 seconds
Started May 26 02:48:49 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 220336 kb
Host smart-c72d114f-163b-4f30-842c-bca2196c4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142946092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3142946092
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2233719584
Short name T318
Test name
Test status
Simulation time 401289379 ps
CPU time 5.4 seconds
Started May 26 02:48:51 PM PDT 24
Finished May 26 02:48:59 PM PDT 24
Peak memory 218228 kb
Host smart-49f47c5c-2a69-4be1-81ca-1addf8532314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233719584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2233719584
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4055112462
Short name T80
Test name
Test status
Simulation time 108734292 ps
CPU time 2.16 seconds
Started May 26 02:48:52 PM PDT 24
Finished May 26 02:48:56 PM PDT 24
Peak memory 208672 kb
Host smart-6618a711-89ba-4e04-bb64-3a1e04561f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055112462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4055112462
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.513053977
Short name T717
Test name
Test status
Simulation time 363310266 ps
CPU time 7.53 seconds
Started May 26 02:48:53 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 208112 kb
Host smart-0b2e70d0-3af0-4a15-b564-2049b863f0ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513053977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.513053977
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1351931278
Short name T658
Test name
Test status
Simulation time 13160387836 ps
CPU time 40.16 seconds
Started May 26 02:48:52 PM PDT 24
Finished May 26 02:49:35 PM PDT 24
Peak memory 209400 kb
Host smart-ccf99e9c-3e35-49ad-a590-e1f883d5c294
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351931278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1351931278
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4280758928
Short name T649
Test name
Test status
Simulation time 895799080 ps
CPU time 5.95 seconds
Started May 26 02:48:50 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 208784 kb
Host smart-fae9e7a5-2b23-44dd-8fa3-72f5a158f6e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280758928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4280758928
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3391138662
Short name T130
Test name
Test status
Simulation time 582896385 ps
CPU time 1.5 seconds
Started May 26 02:49:01 PM PDT 24
Finished May 26 02:49:04 PM PDT 24
Peak memory 215292 kb
Host smart-1e41ae6e-92bf-4a49-926c-a746d15b49ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391138662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3391138662
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3986535641
Short name T726
Test name
Test status
Simulation time 110345276 ps
CPU time 2.48 seconds
Started May 26 02:48:52 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 206888 kb
Host smart-e9ba1ba9-4646-461c-94d2-b512255000c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986535641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3986535641
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4000164611
Short name T398
Test name
Test status
Simulation time 139238850 ps
CPU time 5.37 seconds
Started May 26 02:49:13 PM PDT 24
Finished May 26 02:49:19 PM PDT 24
Peak memory 214408 kb
Host smart-da6a6261-6941-488f-94d0-147bae4915b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000164611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4000164611
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1775302181
Short name T183
Test name
Test status
Simulation time 2642342141 ps
CPU time 24.83 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 220872 kb
Host smart-9a152b39-7ee3-4036-80ee-695703fb98ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775302181 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1775302181
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3358791701
Short name T887
Test name
Test status
Simulation time 399157761 ps
CPU time 5.94 seconds
Started May 26 02:49:01 PM PDT 24
Finished May 26 02:49:09 PM PDT 24
Peak memory 207648 kb
Host smart-59b765ef-1c5c-4ee7-b960-2ccf355d2da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358791701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3358791701
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1980262603
Short name T129
Test name
Test status
Simulation time 184670908 ps
CPU time 4.04 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 210980 kb
Host smart-2ef11b21-21bb-47b7-9bd0-53fbd86a29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980262603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1980262603
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4112000104
Short name T632
Test name
Test status
Simulation time 63372188 ps
CPU time 0.9 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:02 PM PDT 24
Peak memory 206028 kb
Host smart-f0c31bc8-1ce7-449d-908f-d8821181ad46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112000104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4112000104
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2090559528
Short name T757
Test name
Test status
Simulation time 47982348 ps
CPU time 3.04 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:07 PM PDT 24
Peak memory 214844 kb
Host smart-6557a564-d6e8-4691-bd77-b190da8d171d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090559528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2090559528
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1693035728
Short name T50
Test name
Test status
Simulation time 1554826879 ps
CPU time 3.84 seconds
Started May 26 02:49:00 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 218368 kb
Host smart-8440a6e5-52ec-4c85-87a6-c9801b76d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693035728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1693035728
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.940957892
Short name T619
Test name
Test status
Simulation time 132527865 ps
CPU time 5.11 seconds
Started May 26 02:48:57 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 209784 kb
Host smart-befa37b2-3edf-4c2d-b2ba-d321bc47bd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940957892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.940957892
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.537158249
Short name T293
Test name
Test status
Simulation time 993146294 ps
CPU time 5.56 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:09 PM PDT 24
Peak memory 215268 kb
Host smart-87f9c354-6b01-469d-8e97-4a75fe632538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537158249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.537158249
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.553542283
Short name T210
Test name
Test status
Simulation time 39108822 ps
CPU time 2.07 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 215224 kb
Host smart-5b89a513-2c39-42e5-8334-0818ad8f207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553542283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.553542283
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1848302055
Short name T650
Test name
Test status
Simulation time 401224801 ps
CPU time 5.09 seconds
Started May 26 02:49:01 PM PDT 24
Finished May 26 02:49:08 PM PDT 24
Peak memory 209228 kb
Host smart-55b4bab8-acbf-4595-b2e3-8ea153313859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848302055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1848302055
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3747240961
Short name T811
Test name
Test status
Simulation time 26810848 ps
CPU time 2.22 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 208900 kb
Host smart-97cb0020-7391-403d-a251-6f21e225bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747240961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3747240961
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3268170239
Short name T492
Test name
Test status
Simulation time 1116719129 ps
CPU time 5.72 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:10 PM PDT 24
Peak memory 207168 kb
Host smart-11934314-1dc5-49de-a00f-c69cca1d4314
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268170239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3268170239
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2322953509
Short name T366
Test name
Test status
Simulation time 94682043 ps
CPU time 3.58 seconds
Started May 26 02:49:00 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 208680 kb
Host smart-4eb5e35e-f326-4ef7-b1df-446ebaa524d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322953509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2322953509
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2425772411
Short name T490
Test name
Test status
Simulation time 236442067 ps
CPU time 6.44 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:07 PM PDT 24
Peak memory 208204 kb
Host smart-f165d69e-bceb-48cc-abcf-6816af0e4d83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425772411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2425772411
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3115351791
Short name T316
Test name
Test status
Simulation time 278579892 ps
CPU time 3.87 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 214392 kb
Host smart-91a4e505-227b-4e29-8a0d-a458f921a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115351791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3115351791
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3950937919
Short name T805
Test name
Test status
Simulation time 127118267 ps
CPU time 2.3 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 206892 kb
Host smart-318c6cc8-0ae3-4078-a9a4-81f4f277513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950937919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3950937919
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2808001837
Short name T191
Test name
Test status
Simulation time 659618807 ps
CPU time 23.44 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:25 PM PDT 24
Peak memory 219944 kb
Host smart-c3f8d785-6592-4782-a97e-ff1c2e352cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808001837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2808001837
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2918246247
Short name T806
Test name
Test status
Simulation time 93175725 ps
CPU time 6.24 seconds
Started May 26 02:49:00 PM PDT 24
Finished May 26 02:49:09 PM PDT 24
Peak memory 219260 kb
Host smart-0eb9bcdc-6801-4b6f-9b75-fc2cb9f56c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918246247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2918246247
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3779712529
Short name T418
Test name
Test status
Simulation time 191984358 ps
CPU time 3.17 seconds
Started May 26 02:49:01 PM PDT 24
Finished May 26 02:49:07 PM PDT 24
Peak memory 208068 kb
Host smart-32c36c84-03d8-494b-97a1-00a924f9e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779712529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3779712529
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3059756660
Short name T498
Test name
Test status
Simulation time 63868487 ps
CPU time 1.87 seconds
Started May 26 02:49:00 PM PDT 24
Finished May 26 02:49:04 PM PDT 24
Peak memory 209988 kb
Host smart-217b9178-3308-4cd5-9444-e693288d7546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059756660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3059756660
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2906733085
Short name T474
Test name
Test status
Simulation time 18811909 ps
CPU time 0.84 seconds
Started May 26 02:49:10 PM PDT 24
Finished May 26 02:49:12 PM PDT 24
Peak memory 206008 kb
Host smart-1094c559-4c65-4dd7-8bb6-256591396b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906733085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2906733085
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3191443669
Short name T384
Test name
Test status
Simulation time 1587806495 ps
CPU time 5.69 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 215284 kb
Host smart-c0b75009-ecf5-4a89-9429-b29a0ef461a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191443669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3191443669
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1445503322
Short name T860
Test name
Test status
Simulation time 683124135 ps
CPU time 10.14 seconds
Started May 26 02:49:06 PM PDT 24
Finished May 26 02:49:17 PM PDT 24
Peak memory 222924 kb
Host smart-4fd4a095-e556-4c58-a31a-00ba454e65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445503322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1445503322
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1632189996
Short name T459
Test name
Test status
Simulation time 72200830 ps
CPU time 2.5 seconds
Started May 26 02:48:56 PM PDT 24
Finished May 26 02:49:01 PM PDT 24
Peak memory 207292 kb
Host smart-9683a048-68ce-4e3b-bcad-0cd662fdad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632189996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1632189996
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2889376408
Short name T90
Test name
Test status
Simulation time 49988336 ps
CPU time 2.95 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 214388 kb
Host smart-5aa7655f-1b6a-48f4-b250-a4b139293cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889376408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2889376408
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1113989224
Short name T308
Test name
Test status
Simulation time 167334150 ps
CPU time 2.83 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:07 PM PDT 24
Peak memory 214400 kb
Host smart-285d6943-0a99-4d42-a43a-54804eeb38b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113989224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1113989224
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2204447201
Short name T428
Test name
Test status
Simulation time 193187793 ps
CPU time 4.82 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 214312 kb
Host smart-0e8e7a2f-d119-4a3c-aa94-93e6ea4b680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204447201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2204447201
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2066342444
Short name T756
Test name
Test status
Simulation time 1576745561 ps
CPU time 21.15 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 208520 kb
Host smart-ff39803a-83c4-434d-be17-bfd6a101f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066342444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2066342444
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4227523419
Short name T199
Test name
Test status
Simulation time 179530358 ps
CPU time 3.64 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:04 PM PDT 24
Peak memory 208676 kb
Host smart-43319010-4d9d-4d51-b444-d5c8c6b8e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227523419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4227523419
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.544140211
Short name T896
Test name
Test status
Simulation time 374046311 ps
CPU time 3.26 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 206932 kb
Host smart-9cb79674-d699-432a-b0cd-6f6bfcb76671
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544140211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.544140211
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3227056948
Short name T608
Test name
Test status
Simulation time 346154037 ps
CPU time 8.03 seconds
Started May 26 02:48:59 PM PDT 24
Finished May 26 02:49:09 PM PDT 24
Peak memory 207976 kb
Host smart-d2e5f69a-7a3f-4114-830f-33668b9b5fb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227056948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3227056948
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.510577204
Short name T391
Test name
Test status
Simulation time 1380134543 ps
CPU time 13.87 seconds
Started May 26 02:48:57 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 208224 kb
Host smart-3ff2ca22-053a-41a4-99a0-55cc64140c82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510577204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.510577204
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.271898140
Short name T542
Test name
Test status
Simulation time 2374851626 ps
CPU time 8.18 seconds
Started May 26 02:49:14 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 209576 kb
Host smart-fea692a7-0444-4e73-bf92-8cafb06d72a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271898140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.271898140
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3499190694
Short name T818
Test name
Test status
Simulation time 228492542 ps
CPU time 2.79 seconds
Started May 26 02:48:58 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 208604 kb
Host smart-5e40b24c-3f05-4447-a44d-9966854c5113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499190694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3499190694
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.416002015
Short name T697
Test name
Test status
Simulation time 45842492 ps
CPU time 2.28 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:11 PM PDT 24
Peak memory 207140 kb
Host smart-e68297cb-b24c-477e-967f-8eddf0441c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416002015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.416002015
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1623767120
Short name T182
Test name
Test status
Simulation time 6045723733 ps
CPU time 19.67 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 220572 kb
Host smart-86d54612-4996-4154-9001-3dfebc6b4b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623767120 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1623767120
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4126441926
Short name T690
Test name
Test status
Simulation time 619374484 ps
CPU time 7.02 seconds
Started May 26 02:49:02 PM PDT 24
Finished May 26 02:49:11 PM PDT 24
Peak memory 218516 kb
Host smart-ccdf577f-527b-4134-aacf-356ef98a5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126441926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4126441926
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2320791868
Short name T892
Test name
Test status
Simulation time 214169708 ps
CPU time 2.69 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 210096 kb
Host smart-7da6bfa0-15d9-458a-999e-e76014e0f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320791868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2320791868
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2601355906
Short name T559
Test name
Test status
Simulation time 29087889 ps
CPU time 0.92 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:11 PM PDT 24
Peak memory 206168 kb
Host smart-82c6e086-5ba9-4d80-8d16-769af7dd7024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601355906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2601355906
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3494708032
Short name T849
Test name
Test status
Simulation time 221768043 ps
CPU time 12.51 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:23 PM PDT 24
Peak memory 215564 kb
Host smart-37238d44-2c03-496b-9e93-14fd35c7a03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494708032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3494708032
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1259783315
Short name T32
Test name
Test status
Simulation time 65029065 ps
CPU time 2.06 seconds
Started May 26 02:49:06 PM PDT 24
Finished May 26 02:49:09 PM PDT 24
Peak memory 221548 kb
Host smart-3c50de2a-8e5c-4c29-beae-42bd15863c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259783315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1259783315
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3715504562
Short name T377
Test name
Test status
Simulation time 72234843 ps
CPU time 2.54 seconds
Started May 26 02:49:13 PM PDT 24
Finished May 26 02:49:16 PM PDT 24
Peak memory 207960 kb
Host smart-a954c1cf-4f9e-4e7b-a996-ac0f172451a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715504562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3715504562
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.140097111
Short name T352
Test name
Test status
Simulation time 45760671 ps
CPU time 2.85 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 209072 kb
Host smart-795f8cc3-9283-4f69-8c8a-4c6aae05435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140097111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.140097111
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1077730977
Short name T790
Test name
Test status
Simulation time 320693869 ps
CPU time 4.23 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:14 PM PDT 24
Peak memory 215068 kb
Host smart-54cd177d-42af-4886-8159-16eee03916f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077730977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1077730977
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2660493454
Short name T231
Test name
Test status
Simulation time 1084398863 ps
CPU time 4.64 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:15 PM PDT 24
Peak memory 222444 kb
Host smart-4d4c934d-2cd1-4c1f-92d7-04c1528ea095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660493454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2660493454
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1234147607
Short name T646
Test name
Test status
Simulation time 200778498 ps
CPU time 3.98 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:12 PM PDT 24
Peak memory 207712 kb
Host smart-3bf6bd4e-c03b-4c7a-a207-a9713bede086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234147607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1234147607
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1813322038
Short name T595
Test name
Test status
Simulation time 94832851 ps
CPU time 1.98 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:10 PM PDT 24
Peak memory 208752 kb
Host smart-95976f7d-fec0-4a87-b42b-acca6868c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813322038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1813322038
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.841003154
Short name T315
Test name
Test status
Simulation time 40154555 ps
CPU time 2.74 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:11 PM PDT 24
Peak memory 209172 kb
Host smart-8f2f9e5f-454c-482e-ba46-656152ddea6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841003154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.841003154
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.458261372
Short name T553
Test name
Test status
Simulation time 90306221 ps
CPU time 3.28 seconds
Started May 26 02:49:09 PM PDT 24
Finished May 26 02:49:14 PM PDT 24
Peak memory 207068 kb
Host smart-f9300175-a3d5-4351-beb5-95a90d6771af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458261372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.458261372
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1962269003
Short name T659
Test name
Test status
Simulation time 34713020 ps
CPU time 2.56 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 207612 kb
Host smart-86a0843d-fbe3-4174-afaf-90c72f627f44
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962269003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1962269003
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2181814705
Short name T453
Test name
Test status
Simulation time 74884595 ps
CPU time 1.63 seconds
Started May 26 02:49:16 PM PDT 24
Finished May 26 02:49:18 PM PDT 24
Peak memory 206860 kb
Host smart-92f6ff30-05e5-4a89-8522-258b4e847c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181814705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2181814705
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2661895922
Short name T580
Test name
Test status
Simulation time 92409423 ps
CPU time 2.7 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:49:11 PM PDT 24
Peak memory 206980 kb
Host smart-dbc2936a-52ab-4169-a317-62581c5de4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661895922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2661895922
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1092169619
Short name T598
Test name
Test status
Simulation time 8037569838 ps
CPU time 75.31 seconds
Started May 26 02:49:07 PM PDT 24
Finished May 26 02:50:24 PM PDT 24
Peak memory 222628 kb
Host smart-cc0c1279-8a6c-4f56-a52a-1ae63ddb79ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092169619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1092169619
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.678348468
Short name T693
Test name
Test status
Simulation time 324769582 ps
CPU time 19.47 seconds
Started May 26 02:49:08 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 222632 kb
Host smart-39b99ce3-a2db-4c56-80a5-7cc2ef5e0238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678348468 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.678348468
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3202400181
Short name T893
Test name
Test status
Simulation time 3452949492 ps
CPU time 26.8 seconds
Started May 26 02:49:06 PM PDT 24
Finished May 26 02:49:34 PM PDT 24
Peak memory 218600 kb
Host smart-8ad47646-5d90-43be-9b45-6f27af0cfda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202400181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3202400181
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1130884872
Short name T40
Test name
Test status
Simulation time 127941897 ps
CPU time 2.81 seconds
Started May 26 02:49:06 PM PDT 24
Finished May 26 02:49:10 PM PDT 24
Peak memory 210508 kb
Host smart-cab494e6-820f-4802-b53f-2f877641215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130884872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1130884872
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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