Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
55694 |
1 |
|
|
T1 |
63 |
|
T2 |
14 |
|
T3 |
9 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32565 |
1 |
|
|
T11 |
37 |
|
T4 |
110 |
|
T12 |
43 |
auto[1] |
23129 |
1 |
|
|
T1 |
63 |
|
T2 |
14 |
|
T3 |
9 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27562 |
1 |
|
|
T1 |
32 |
|
T3 |
5 |
|
T11 |
19 |
auto[1] |
28132 |
1 |
|
|
T1 |
31 |
|
T2 |
14 |
|
T3 |
4 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
15918 |
1 |
|
|
T11 |
19 |
|
T4 |
56 |
|
T12 |
23 |
all_values[0] |
auto[0] |
auto[1] |
16647 |
1 |
|
|
T11 |
18 |
|
T4 |
54 |
|
T12 |
20 |
all_values[0] |
auto[1] |
auto[0] |
11644 |
1 |
|
|
T1 |
32 |
|
T3 |
5 |
|
T12 |
40 |
all_values[0] |
auto[1] |
auto[1] |
11485 |
1 |
|
|
T1 |
31 |
|
T2 |
14 |
|
T3 |
4 |