| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 87.50 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 1 | 7 | 87.50 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| auto[OtpRootKeyValidLow] | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[OtpRootKeyInvalid] | 1 | 1 | T351 | 1 | - | - | - | - | ||||
| auto[LcStateInvalid] | 108 | 1 | T103 | 24 | T105 | 36 | T401 | 24 | ||||
| auto[OtpDevIdInvalid] | 156 | 1 | T103 | 24 | T102 | 12 | T288 | 60 | ||||
| auto[RomDigestInvalid] | 132 | 1 | T24 | 12 | T106 | 60 | T103 | 12 | ||||
| auto[RomDigestValidLow] | 84 | 1 | T103 | 24 | T402 | 12 | T288 | 12 | ||||
| auto[FlashCreatorSeedInvalid] | 48 | 1 | T93 | 12 | T288 | 12 | T403 | 24 | ||||
| auto[FlashOwnerSeedInvalid] | 72 | 1 | T22 | 12 | T19 | 12 | T104 | 36 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |