Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10962

1

T1

10

T2

4

T3

2

auto[Attestation]

7496

1

T1

13

T2

6

T11

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2648	1			T2	4		T4	7		T12	4
auto[Aes]	3327	1			T1	7		T4	3		T12	5
auto[Kmac]	3353	1			T1	6		T2	1		T11	10
auto[Otbn]	3319	1			T1	5		T2	3		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7416	1			T1	8		T2	4		T3	2
auto[OpGenId]	5811	1			T1	5		T2	2		T4	15
auto[OpGenSwOut]	5685	1			T1	10		T2	2		T4	8
auto[OpGenHwOut]	6962	1			T1	8		T2	6		T3	2
auto[OpDisable]	127	1			T4	1		T12	1		T36	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10457

1

T1

13

T2

12

T3

4

auto[OpDoneFail]

15544

1

T1

18

T2

2

T11

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6219	1			T1	1		T2	1		T3	1
auto[StInit]	3682	1			T1	3		T2	3		T3	1
auto[StCreatorRootKey]	3157	1			T1	4		T2	3		T3	2
auto[StOwnerIntKey]	2765	1			T1	5		T2	5		T11	2
auto[StOwnerKey]	2481	1			T1	2		T2	2		T11	2
auto[StDisabled]	7697	1			T1	16		T11	7		T4	13

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	309	1			T4	1		T12	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T88	1		T215	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T56	1		T39	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T62	2		T216	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T150	1		T62	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T4	1		T87	2		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	302	1			T12	1		T14	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	93	1			T57	1		T27	3		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	85	1			T133	1		T27	2		T22	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T67	1		T62	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T27	2		T217	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	234	1			T12	1		T36	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	313	1			T4	1		T14	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	90	1			T12	1		T91	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T56	1		T27	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T133	1		T27	2		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T14	1		T67	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T12	1		T91	1		T151	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	266	1			T12	1		T14	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T12	1		T150	1		T62	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T4	1		T36	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T1	2		T61	1		T220	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T62	3		T221	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	199	1			T1	1		T12	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T27	2		T68	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T2	1		T91	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T14	1		T56	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T12	1		T36	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	71	1			T27	1		T49	1		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T133	1		T87	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T6	1		T224	4		T78	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T55	1		T53	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T1	1		T74	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T36	1		T225	1		T62	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T12	1		T36	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T1	2		T4	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T62	2		T68	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	111	1			T4	2		T83	1		T67	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T4	1		T25	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T133	1		T26	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	54	1			T1	1		T68	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	216	1			T1	3		T12	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T6	1		T224	3		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	100	1			T215	1		T27	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T14	1		T67	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T133	1		T61	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	71	1			T2	1		T25	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	204	1			T25	3		T150	1		T151	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	289	1			T4	1		T14	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T12	1		T118	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T12	1		T57	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T2	2		T62	2		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T25	1		T133	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T25	1		T133	1		T62	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T4	1		T37	8		T85	15
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T14	1		T61	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	108	1			T25	2		T85	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	108	1			T4	1		T25	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T12	1		T37	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	254	1			T1	2		T37	1		T227	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	469	1			T11	2		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T1	1		T13	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T13	1		T90	1		T151	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T1	1		T25	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T2	1		T14	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	269	1			T11	1		T4	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	495	1			T4	1		T55	2		T150	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T91	1		T56	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T3	2		T4	1		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T228	1		T67	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	96	1			T133	1		T26	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	281	1			T1	1		T133	1		T137	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	48	1			T27	1		T68	2		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	76	1			T38	1		T62	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T4	1		T14	1		T62	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T2	1		T133	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T62	2		T27	2		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T4	3		T25	2		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	45	1			T27	2		T6	1		T224	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	108	1			T37	1		T55	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T1	1		T37	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T37	1		T85	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T85	1		T227	1		T109	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	299	1			T1	1		T12	1		T37	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T68	1		T6	2		T224	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T11	1		T55	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	130	1			T11	1		T86	1		T88	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T11	1		T4	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	85	1			T11	1		T13	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	268	1			T11	3		T4	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T27	7		T68	2		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	124	1			T36	1		T91	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T2	1		T88	2		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T2	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T12	1		T137	1		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	305	1			T1	1		T12	1		T91	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	191	1			T56	1		T39	1		T150	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	645	1			T4	2		T12	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	204	1			T133	1		T67	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	650	1			T12	2		T14	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	229	1			T14	1		T133	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	642	1			T4	1		T12	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	185	1			T1	2		T4	1		T36	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	586	1			T1	1		T12	3		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T12	1		T14	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	374	1			T2	1		T91	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	195	1			T1	1		T12	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	390	1			T1	2		T4	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	182	1			T1	1		T4	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	424	1			T1	3		T4	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T2	1		T14	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	392	1			T25	4		T150	1		T151	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	186	1			T2	2		T12	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	572	1			T4	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	282	1			T4	1		T12	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	882	1			T1	2		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T1	1		T2	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	876	1			T1	1		T11	3		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T3	2		T4	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	910	1			T1	1		T4	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T2	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	313	1			T4	3		T25	2		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	261	1			T1	1		T37	2		T85	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	463	1			T1	1		T12	1		T37	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	292	1			T11	3		T4	2		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	434	1			T11	4		T4	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	270	1			T2	2		T4	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	508	1			T1	1		T12	1		T36	1