Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31756

1

T1

35

T2

17

T3

5

auto[1]

314

1

T14

5

T91

10

T150

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31762	1			T1	35		T2	17		T3	5
auto[134217728:268435455]	5	1			T91	1		T140	1		T251	1
auto[268435456:402653183]	11	1			T91	1		T150	2		T139	1
auto[402653184:536870911]	11	1			T290	1		T393	1		T429	1
auto[536870912:671088639]	7	1			T275	1		T251	1		T338	1
auto[671088640:805306367]	4	1			T290	1		T332	1		T430	1
auto[805306368:939524095]	14	1			T150	1		T152	2		T138	1
auto[939524096:1073741823]	11	1			T14	1		T292	1		T140	1
auto[1073741824:1207959551]	5	1			T275	1		T292	1		T310	1
auto[1207959552:1342177279]	10	1			T14	1		T91	1		T290	1
auto[1342177280:1476395007]	11	1			T151	1		T290	1		T140	1
auto[1476395008:1610612735]	13	1			T151	2		T332	1		T250	1
auto[1610612736:1744830463]	12	1			T151	1		T275	1		T292	1
auto[1744830464:1879048191]	9	1			T152	2		T138	1		T139	1
auto[1879048192:2013265919]	8	1			T91	1		T151	1		T139	1
auto[2013265920:2147483647]	11	1			T150	2		T292	1		T142	1
auto[2147483648:2281701375]	7	1			T91	1		T151	1		T384	2
auto[2281701376:2415919103]	12	1			T150	1		T292	1		T254	1
auto[2415919104:2550136831]	12	1			T91	1		T151	1		T138	2
auto[2550136832:2684354559]	14	1			T150	1		T275	2		T140	1
auto[2684354560:2818572287]	7	1			T14	1		T150	1		T376	1
auto[2818572288:2952790015]	6	1			T141	1		T332	1		T310	1
auto[2952790016:3087007743]	6	1			T140	1		T142	1		T384	1
auto[3087007744:3221225471]	8	1			T91	1		T150	1		T138	1
auto[3221225472:3355443199]	11	1			T91	1		T150	2		T311	1
auto[3355443200:3489660927]	9	1			T91	1		T332	1		T322	1
auto[3489660928:3623878655]	18	1			T151	2		T139	1		T275	3
auto[3623878656:3758096383]	13	1			T14	1		T91	1		T151	2
auto[3758096384:3892314111]	14	1			T412	1		T251	1		T411	1
auto[3892314112:4026531839]	9	1			T152	1		T140	1		T332	2
auto[4026531840:4160749567]	11	1			T14	1		T152	1		T140	1
auto[4160749568:4294967295]	9	1			T332	1		T429	1		T310	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31756	1			T1	35		T2	17		T3	5
auto[0:134217727]	auto[1]	6	1			T150	1		T139	1		T429	1
auto[134217728:268435455]	auto[1]	5	1			T91	1		T140	1		T251	1
auto[268435456:402653183]	auto[1]	11	1			T91	1		T150	2		T139	1
auto[402653184:536870911]	auto[1]	11	1			T290	1		T393	1		T429	1
auto[536870912:671088639]	auto[1]	7	1			T275	1		T251	1		T338	1
auto[671088640:805306367]	auto[1]	4	1			T290	1		T332	1		T430	1
auto[805306368:939524095]	auto[1]	14	1			T150	1		T152	2		T138	1
auto[939524096:1073741823]	auto[1]	11	1			T14	1		T292	1		T140	1
auto[1073741824:1207959551]	auto[1]	5	1			T275	1		T292	1		T310	1
auto[1207959552:1342177279]	auto[1]	10	1			T14	1		T91	1		T290	1
auto[1342177280:1476395007]	auto[1]	11	1			T151	1		T290	1		T140	1
auto[1476395008:1610612735]	auto[1]	13	1			T151	2		T332	1		T250	1
auto[1610612736:1744830463]	auto[1]	12	1			T151	1		T275	1		T292	1
auto[1744830464:1879048191]	auto[1]	9	1			T152	2		T138	1		T139	1
auto[1879048192:2013265919]	auto[1]	8	1			T91	1		T151	1		T139	1
auto[2013265920:2147483647]	auto[1]	11	1			T150	2		T292	1		T142	1
auto[2147483648:2281701375]	auto[1]	7	1			T91	1		T151	1		T384	2
auto[2281701376:2415919103]	auto[1]	12	1			T150	1		T292	1		T254	1
auto[2415919104:2550136831]	auto[1]	12	1			T91	1		T151	1		T138	2
auto[2550136832:2684354559]	auto[1]	14	1			T150	1		T275	2		T140	1
auto[2684354560:2818572287]	auto[1]	7	1			T14	1		T150	1		T376	1
auto[2818572288:2952790015]	auto[1]	6	1			T141	1		T332	1		T310	1
auto[2952790016:3087007743]	auto[1]	6	1			T140	1		T142	1		T384	1
auto[3087007744:3221225471]	auto[1]	8	1			T91	1		T150	1		T138	1
auto[3221225472:3355443199]	auto[1]	11	1			T91	1		T150	2		T311	1
auto[3355443200:3489660927]	auto[1]	9	1			T91	1		T332	1		T322	1
auto[3489660928:3623878655]	auto[1]	18	1			T151	2		T139	1		T275	3
auto[3623878656:3758096383]	auto[1]	13	1			T14	1		T91	1		T151	2
auto[3758096384:3892314111]	auto[1]	14	1			T412	1		T251	1		T411	1
auto[3892314112:4026531839]	auto[1]	9	1			T152	1		T140	1		T332	2
auto[4026531840:4160749567]	auto[1]	11	1			T14	1		T152	1		T140	1
auto[4160749568:4294967295]	auto[1]	9	1			T332	1		T429	1		T310	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1589

1

T4

3

T14

1

T15

5

auto[1]

1732

1

T1

3

T3

1

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T15	1		T25	1		T48	1
auto[134217728:268435455]	110	1			T55	1		T60	1		T62	1
auto[268435456:402653183]	92	1			T150	1		T62	1		T27	1
auto[402653184:536870911]	101	1			T60	1		T27	2		T49	2
auto[536870912:671088639]	109	1			T25	1		T55	1		T53	1
auto[671088640:805306367]	112	1			T50	1		T62	1		T27	4
auto[805306368:939524095]	118	1			T16	2		T91	1		T55	2
auto[939524096:1073741823]	98	1			T1	1		T15	1		T36	1
auto[1073741824:1207959551]	109	1			T15	1		T91	1		T55	1
auto[1207959552:1342177279]	87	1			T4	1		T150	1		T151	1
auto[1342177280:1476395007]	108	1			T151	1		T26	1		T215	1
auto[1476395008:1610612735]	106	1			T16	1		T61	1		T67	1
auto[1610612736:1744830463]	91	1			T1	1		T36	1		T151	1
auto[1744830464:1879048191]	117	1			T56	1		T49	1		T72	1
auto[1879048192:2013265919]	115	1			T15	1		T16	1		T61	1
auto[2013265920:2147483647]	113	1			T4	1		T60	1		T48	1
auto[2147483648:2281701375]	90	1			T1	1		T14	1		T55	1
auto[2281701376:2415919103]	83	1			T12	1		T60	1		T67	1
auto[2415919104:2550136831]	121	1			T16	1		T150	2		T28	1
auto[2550136832:2684354559]	98	1			T60	1		T50	1		T40	1
auto[2684354560:2818572287]	91	1			T4	1		T28	1		T48	1
auto[2818572288:2952790015]	96	1			T26	1		T27	1		T49	2
auto[2952790016:3087007743]	98	1			T14	1		T15	1		T61	1
auto[3087007744:3221225471]	103	1			T14	1		T62	1		T27	2
auto[3221225472:3355443199]	82	1			T4	1		T27	1		T49	2
auto[3355443200:3489660927]	123	1			T4	1		T53	1		T60	1
auto[3489660928:3623878655]	115	1			T4	1		T16	1		T133	1
auto[3623878656:3758096383]	99	1			T3	1		T48	1		T274	1
auto[3758096384:3892314111]	120	1			T50	1		T27	1		T109	1
auto[3892314112:4026531839]	100	1			T14	1		T50	1		T40	1
auto[4026531840:4160749567]	99	1			T4	1		T56	1		T53	1
auto[4160749568:4294967295]	116	1			T15	1		T16	1		T36	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T15	1		T48	1		T27	1
auto[0:134217727]	auto[1]	54	1			T25	1		T27	2		T49	1
auto[134217728:268435455]	auto[0]	61	1			T55	1		T62	1		T27	2
auto[134217728:268435455]	auto[1]	49	1			T60	1		T22	1		T6	3
auto[268435456:402653183]	auto[0]	30	1			T27	1		T49	3		T280	1
auto[268435456:402653183]	auto[1]	62	1			T150	1		T62	1		T49	1
auto[402653184:536870911]	auto[0]	51	1			T27	1		T49	2		T95	1
auto[402653184:536870911]	auto[1]	50	1			T60	1		T27	1		T223	1
auto[536870912:671088639]	auto[0]	53	1			T25	1		T55	1		T53	1
auto[536870912:671088639]	auto[1]	56	1			T27	1		T109	1		T68	1
auto[671088640:805306367]	auto[0]	55	1			T50	1		T62	1		T27	3
auto[671088640:805306367]	auto[1]	57	1			T27	1		T49	1		T109	1
auto[805306368:939524095]	auto[0]	61	1			T16	2		T91	1		T55	1
auto[805306368:939524095]	auto[1]	57	1			T55	1		T62	1		T118	1
auto[939524096:1073741823]	auto[0]	47	1			T15	1		T27	1		T68	4
auto[939524096:1073741823]	auto[1]	51	1			T1	1		T36	1		T274	1
auto[1073741824:1207959551]	auto[0]	53	1			T15	1		T91	1		T61	1
auto[1073741824:1207959551]	auto[1]	56	1			T55	1		T53	1		T274	1
auto[1207959552:1342177279]	auto[0]	51	1			T4	1		T150	1		T27	2
auto[1207959552:1342177279]	auto[1]	36	1			T151	1		T272	1		T127	1
auto[1342177280:1476395007]	auto[0]	55	1			T151	1		T26	1		T27	1
auto[1342177280:1476395007]	auto[1]	53	1			T215	1		T49	1		T109	1
auto[1476395008:1610612735]	auto[0]	40	1			T16	1		T61	1		T67	1
auto[1476395008:1610612735]	auto[1]	66	1			T215	1		T40	1		T74	1
auto[1610612736:1744830463]	auto[0]	47	1			T151	1		T118	1		T113	1
auto[1610612736:1744830463]	auto[1]	44	1			T1	1		T36	1		T218	1
auto[1744830464:1879048191]	auto[0]	52	1			T49	1		T68	2		T280	1
auto[1744830464:1879048191]	auto[1]	65	1			T56	1		T72	1		T68	2
auto[1879048192:2013265919]	auto[0]	56	1			T15	1		T16	1		T274	1
auto[1879048192:2013265919]	auto[1]	59	1			T61	1		T57	1		T27	1
auto[2013265920:2147483647]	auto[0]	49	1			T26	1		T215	1		T40	1
auto[2013265920:2147483647]	auto[1]	64	1			T4	1		T60	1		T48	1
auto[2147483648:2281701375]	auto[0]	40	1			T55	1		T26	2		T62	1
auto[2147483648:2281701375]	auto[1]	50	1			T1	1		T14	1		T38	1
auto[2281701376:2415919103]	auto[0]	34	1			T27	1		T75	1		T68	1
auto[2281701376:2415919103]	auto[1]	49	1			T12	1		T60	1		T67	1
auto[2415919104:2550136831]	auto[0]	62	1			T16	1		T150	1		T27	2
auto[2415919104:2550136831]	auto[1]	59	1			T150	1		T28	1		T274	1
auto[2550136832:2684354559]	auto[0]	51	1			T60	1		T50	1		T49	1
auto[2550136832:2684354559]	auto[1]	47	1			T40	1		T27	1		T218	1
auto[2684354560:2818572287]	auto[0]	42	1			T28	1		T48	1		T6	1
auto[2684354560:2818572287]	auto[1]	49	1			T4	1		T215	1		T62	1
auto[2818572288:2952790015]	auto[0]	47	1			T49	2		T260	2		T139	1
auto[2818572288:2952790015]	auto[1]	49	1			T26	1		T27	1		T71	1
auto[2952790016:3087007743]	auto[0]	46	1			T61	1		T215	1		T6	1
auto[2952790016:3087007743]	auto[1]	52	1			T14	1		T15	1		T49	1
auto[3087007744:3221225471]	auto[0]	41	1			T27	2		T72	1		T413	1
auto[3087007744:3221225471]	auto[1]	62	1			T14	1		T62	1		T118	1
auto[3221225472:3355443199]	auto[0]	42	1			T4	1		T27	1		T49	2
auto[3221225472:3355443199]	auto[1]	40	1			T259	1		T431	1		T41	1
auto[3355443200:3489660927]	auto[0]	62	1			T53	1		T60	1		T50	1
auto[3355443200:3489660927]	auto[1]	61	1			T4	1		T27	1		T118	1
auto[3489660928:3623878655]	auto[0]	59	1			T4	1		T16	1		T53	1
auto[3489660928:3623878655]	auto[1]	56	1			T133	1		T274	1		T62	1
auto[3623878656:3758096383]	auto[0]	46	1			T274	1		T27	4		T118	1
auto[3623878656:3758096383]	auto[1]	53	1			T3	1		T48	1		T62	1
auto[3758096384:3892314111]	auto[0]	51	1			T27	1		T220	1		T68	2
auto[3758096384:3892314111]	auto[1]	69	1			T50	1		T109	1		T68	1
auto[3892314112:4026531839]	auto[0]	44	1			T14	1		T50	1		T27	1
auto[3892314112:4026531839]	auto[1]	56	1			T40	1		T27	2		T152	1
auto[4026531840:4160749567]	auto[0]	56	1			T53	1		T48	1		T215	1
auto[4026531840:4160749567]	auto[1]	43	1			T4	1		T56	1		T109	1
auto[4160749568:4294967295]	auto[0]	58	1			T15	1		T55	1		T50	1
auto[4160749568:4294967295]	auto[1]	58	1			T16	1		T36	1		T91	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1564

1

T4

2

T14

1

T15

5

auto[1]

1757

1

T1

3

T3

1

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	129	1			T91	1		T53	1		T151	1
auto[134217728:268435455]	98	1			T56	1		T53	1		T60	1
auto[268435456:402653183]	100	1			T48	1		T27	1		T54	1
auto[402653184:536870911]	82	1			T16	1		T28	1		T151	1
auto[536870912:671088639]	92	1			T62	1		T27	1		T49	2
auto[671088640:805306367]	112	1			T48	1		T26	1		T27	3
auto[805306368:939524095]	92	1			T150	1		T215	2		T49	1
auto[939524096:1073741823]	99	1			T28	1		T274	2		T215	1
auto[1073741824:1207959551]	105	1			T55	1		T56	1		T61	1
auto[1207959552:1342177279]	110	1			T16	2		T150	1		T48	1
auto[1342177280:1476395007]	122	1			T3	1		T55	2		T53	1
auto[1476395008:1610612735]	104	1			T16	1		T60	1		T27	1
auto[1610612736:1744830463]	86	1			T36	1		T60	1		T38	1
auto[1744830464:1879048191]	91	1			T67	1		T50	1		T27	2
auto[1879048192:2013265919]	123	1			T14	1		T16	1		T55	1
auto[2013265920:2147483647]	93	1			T27	1		T49	1		T272	1
auto[2147483648:2281701375]	102	1			T4	1		T15	3		T25	1
auto[2281701376:2415919103]	100	1			T4	1		T53	1		T50	1
auto[2415919104:2550136831]	96	1			T215	1		T27	1		T223	1
auto[2550136832:2684354559]	113	1			T14	1		T61	1		T274	1
auto[2684354560:2818572287]	100	1			T133	1		T55	1		T60	2
auto[2818572288:2952790015]	93	1			T14	1		T55	1		T67	1
auto[2952790016:3087007743]	101	1			T36	1		T50	1		T26	1
auto[3087007744:3221225471]	131	1			T91	1		T50	1		T26	1
auto[3221225472:3355443199]	95	1			T91	1		T274	1		T62	1
auto[3355443200:3489660927]	104	1			T16	1		T60	1		T67	1
auto[3489660928:3623878655]	103	1			T12	1		T25	1		T215	1
auto[3623878656:3758096383]	120	1			T36	1		T150	1		T40	1
auto[3758096384:3892314111]	104	1			T1	1		T55	1		T62	1
auto[3892314112:4026531839]	112	1			T1	1		T4	1		T14	1
auto[4026531840:4160749567]	99	1			T4	2		T15	1		T53	1
auto[4160749568:4294967295]	110	1			T1	1		T4	2		T215	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T53	1		T151	1		T27	3
auto[0:134217727]	auto[1]	67	1			T91	1		T49	1		T431	1
auto[134217728:268435455]	auto[0]	46	1			T53	1		T50	1		T27	1
auto[134217728:268435455]	auto[1]	52	1			T56	1		T60	1		T57	1
auto[268435456:402653183]	auto[0]	38	1			T27	1		T22	1		T259	1
auto[268435456:402653183]	auto[1]	62	1			T48	1		T54	1		T49	1
auto[402653184:536870911]	auto[0]	40	1			T16	1		T28	1		T27	1
auto[402653184:536870911]	auto[1]	42	1			T151	1		T49	1		T6	1
auto[536870912:671088639]	auto[0]	35	1			T27	1		T49	1		T118	1
auto[536870912:671088639]	auto[1]	57	1			T62	1		T49	1		T218	1
auto[671088640:805306367]	auto[0]	47	1			T48	1		T27	2		T49	1
auto[671088640:805306367]	auto[1]	65	1			T26	1		T27	1		T95	1
auto[805306368:939524095]	auto[0]	47	1			T150	1		T215	1		T223	1
auto[805306368:939524095]	auto[1]	45	1			T215	1		T49	1		T77	1
auto[939524096:1073741823]	auto[0]	51	1			T215	1		T27	2		T49	4
auto[939524096:1073741823]	auto[1]	48	1			T28	1		T274	2		T62	1
auto[1073741824:1207959551]	auto[0]	49	1			T55	1		T61	1		T28	1
auto[1073741824:1207959551]	auto[1]	56	1			T56	1		T27	2		T223	1
auto[1207959552:1342177279]	auto[0]	52	1			T16	1		T150	1		T151	1
auto[1207959552:1342177279]	auto[1]	58	1			T16	1		T48	1		T72	1
auto[1342177280:1476395007]	auto[0]	57	1			T55	2		T53	1		T61	1
auto[1342177280:1476395007]	auto[1]	65	1			T3	1		T274	1		T27	1
auto[1476395008:1610612735]	auto[0]	53	1			T16	1		T27	1		T49	1
auto[1476395008:1610612735]	auto[1]	51	1			T60	1		T68	1		T139	1
auto[1610612736:1744830463]	auto[0]	47	1			T27	2		T49	1		T41	1
auto[1610612736:1744830463]	auto[1]	39	1			T36	1		T60	1		T38	1
auto[1744830464:1879048191]	auto[0]	37	1			T67	1		T27	2		T68	1
auto[1744830464:1879048191]	auto[1]	54	1			T50	1		T110	1		T68	3
auto[1879048192:2013265919]	auto[0]	64	1			T16	1		T27	4		T49	2
auto[1879048192:2013265919]	auto[1]	59	1			T14	1		T55	1		T27	1
auto[2013265920:2147483647]	auto[0]	49	1			T27	1		T49	1		T415	1
auto[2013265920:2147483647]	auto[1]	44	1			T272	1		T66	2		T432	1
auto[2147483648:2281701375]	auto[0]	46	1			T15	3		T25	1		T26	1
auto[2147483648:2281701375]	auto[1]	56	1			T4	1		T150	1		T118	1
auto[2281701376:2415919103]	auto[0]	48	1			T4	1		T50	1		T27	1
auto[2281701376:2415919103]	auto[1]	52	1			T53	1		T27	1		T118	1
auto[2415919104:2550136831]	auto[0]	47	1			T27	1		T223	1		T68	1
auto[2415919104:2550136831]	auto[1]	49	1			T215	1		T68	1		T6	2
auto[2550136832:2684354559]	auto[0]	55	1			T14	1		T274	1		T49	1
auto[2550136832:2684354559]	auto[1]	58	1			T61	1		T40	1		T62	2
auto[2684354560:2818572287]	auto[0]	50	1			T60	2		T61	1		T26	1
auto[2684354560:2818572287]	auto[1]	50	1			T133	1		T55	1		T26	1
auto[2818572288:2952790015]	auto[0]	48	1			T55	1		T150	1		T151	1
auto[2818572288:2952790015]	auto[1]	45	1			T14	1		T67	1		T27	1
auto[2952790016:3087007743]	auto[0]	45	1			T50	1		T27	3		T260	1
auto[2952790016:3087007743]	auto[1]	56	1			T36	1		T26	1		T27	2
auto[3087007744:3221225471]	auto[0]	64	1			T91	1		T50	1		T40	1
auto[3087007744:3221225471]	auto[1]	67	1			T26	1		T27	2		T118	1
auto[3221225472:3355443199]	auto[0]	44	1			T91	1		T27	1		T280	1
auto[3221225472:3355443199]	auto[1]	51	1			T274	1		T62	1		T27	1
auto[3355443200:3489660927]	auto[0]	37	1			T16	1		T138	1		T122	1
auto[3355443200:3489660927]	auto[1]	67	1			T60	1		T67	1		T118	1
auto[3489660928:3623878655]	auto[0]	46	1			T215	1		T62	1		T49	1
auto[3489660928:3623878655]	auto[1]	57	1			T12	1		T25	1		T62	1
auto[3623878656:3758096383]	auto[0]	53	1			T36	1		T150	1		T40	1
auto[3623878656:3758096383]	auto[1]	67	1			T49	1		T219	1		T95	1
auto[3758096384:3892314111]	auto[0]	50	1			T27	1		T49	1		T110	1
auto[3758096384:3892314111]	auto[1]	54	1			T1	1		T55	1		T62	1
auto[3892314112:4026531839]	auto[0]	54	1			T15	2		T16	1		T151	1
auto[3892314112:4026531839]	auto[1]	58	1			T1	1		T4	1		T14	1
auto[4026531840:4160749567]	auto[0]	48	1			T53	1		T27	1		T49	1
auto[4026531840:4160749567]	auto[1]	51	1			T4	2		T15	1		T62	2
auto[4160749568:4294967295]	auto[0]	55	1			T4	1		T215	1		T152	1
auto[4160749568:4294967295]	auto[1]	55	1			T1	1		T4	1		T27	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1547

1

T4

2

T14

1

T15

4

auto[1]

1774

1

T1

3

T3

1

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T1	1		T55	1		T28	1
auto[134217728:268435455]	117	1			T4	1		T67	1		T150	1
auto[268435456:402653183]	104	1			T16	1		T91	1		T61	1
auto[402653184:536870911]	102	1			T50	1		T274	1		T62	2
auto[536870912:671088639]	117	1			T61	2		T28	1		T27	1
auto[671088640:805306367]	111	1			T4	1		T12	1		T62	1
auto[805306368:939524095]	89	1			T91	1		T215	1		T40	1
auto[939524096:1073741823]	110	1			T4	1		T14	1		T15	1
auto[1073741824:1207959551]	103	1			T1	1		T14	1		T151	1
auto[1207959552:1342177279]	120	1			T55	1		T56	1		T53	1
auto[1342177280:1476395007]	118	1			T60	1		T61	1		T50	1
auto[1476395008:1610612735]	94	1			T16	1		T67	1		T150	1
auto[1610612736:1744830463]	78	1			T91	1		T53	1		T38	1
auto[1744830464:1879048191]	88	1			T1	1		T55	1		T40	1
auto[1879048192:2013265919]	111	1			T15	1		T56	1		T53	1
auto[2013265920:2147483647]	100	1			T16	1		T55	1		T53	1
auto[2147483648:2281701375]	104	1			T14	1		T48	1		T215	1
auto[2281701376:2415919103]	90	1			T15	1		T60	1		T215	1
auto[2415919104:2550136831]	106	1			T4	1		T15	1		T55	1
auto[2550136832:2684354559]	103	1			T15	1		T36	1		T150	1
auto[2684354560:2818572287]	111	1			T60	1		T274	1		T62	1
auto[2818572288:2952790015]	106	1			T60	1		T27	1		T49	1
auto[2952790016:3087007743]	118	1			T3	1		T25	1		T60	1
auto[3087007744:3221225471]	113	1			T133	1		T53	1		T48	1
auto[3221225472:3355443199]	86	1			T14	1		T150	1		T50	2
auto[3355443200:3489660927]	108	1			T36	1		T55	1		T150	1
auto[3489660928:3623878655]	89	1			T4	1		T16	1		T274	1
auto[3623878656:3758096383]	104	1			T4	1		T36	1		T57	1
auto[3758096384:3892314111]	103	1			T15	1		T16	1		T151	1
auto[3892314112:4026531839]	119	1			T4	1		T16	1		T25	1
auto[4026531840:4160749567]	101	1			T48	2		T274	1		T40	1
auto[4160749568:4294967295]	104	1			T16	1		T55	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T28	1		T50	1		T27	1
auto[0:134217727]	auto[1]	50	1			T1	1		T55	1		T27	1
auto[134217728:268435455]	auto[0]	50	1			T4	1		T68	3		T63	1
auto[134217728:268435455]	auto[1]	67	1			T67	1		T150	1		T50	1
auto[268435456:402653183]	auto[0]	55	1			T16	1		T91	1		T26	1
auto[268435456:402653183]	auto[1]	49	1			T61	1		T40	1		T27	2
auto[402653184:536870911]	auto[0]	41	1			T50	1		T49	1		T22	1
auto[402653184:536870911]	auto[1]	61	1			T274	1		T62	2		T27	1
auto[536870912:671088639]	auto[0]	64	1			T61	1		T28	1		T27	1
auto[536870912:671088639]	auto[1]	53	1			T61	1		T397	1		T6	2
auto[671088640:805306367]	auto[0]	50	1			T27	1		T49	2		T223	1
auto[671088640:805306367]	auto[1]	61	1			T4	1		T12	1		T62	1
auto[805306368:939524095]	auto[0]	50	1			T91	1		T215	1		T40	1
auto[805306368:939524095]	auto[1]	39	1			T54	1		T68	1		T77	1
auto[939524096:1073741823]	auto[0]	56	1			T15	1		T27	1		T68	2
auto[939524096:1073741823]	auto[1]	54	1			T4	1		T14	1		T27	1
auto[1073741824:1207959551]	auto[0]	42	1			T27	4		T49	1		T118	1
auto[1073741824:1207959551]	auto[1]	61	1			T1	1		T14	1		T151	1
auto[1207959552:1342177279]	auto[0]	61	1			T55	1		T53	1		T27	1
auto[1207959552:1342177279]	auto[1]	59	1			T56	1		T74	1		T49	1
auto[1342177280:1476395007]	auto[0]	58	1			T50	1		T27	1		T49	3
auto[1342177280:1476395007]	auto[1]	60	1			T60	1		T61	1		T397	1
auto[1476395008:1610612735]	auto[0]	46	1			T150	1		T151	1		T27	1
auto[1476395008:1610612735]	auto[1]	48	1			T16	1		T67	1		T27	2
auto[1610612736:1744830463]	auto[0]	28	1			T53	1		T113	2		T106	1
auto[1610612736:1744830463]	auto[1]	50	1			T91	1		T38	1		T151	1
auto[1744830464:1879048191]	auto[0]	37	1			T55	1		T40	1		T27	1
auto[1744830464:1879048191]	auto[1]	51	1			T1	1		T62	2		T27	1
auto[1879048192:2013265919]	auto[0]	55	1			T53	1		T62	1		T220	1
auto[1879048192:2013265919]	auto[1]	56	1			T15	1		T56	1		T27	1
auto[2013265920:2147483647]	auto[0]	43	1			T16	1		T55	1		T53	1
auto[2013265920:2147483647]	auto[1]	57	1			T118	1		T259	1		T218	1
auto[2147483648:2281701375]	auto[0]	44	1			T48	1		T215	1		T27	1
auto[2147483648:2281701375]	auto[1]	60	1			T14	1		T222	1		T95	1
auto[2281701376:2415919103]	auto[0]	39	1			T15	1		T27	2		T96	1
auto[2281701376:2415919103]	auto[1]	51	1			T60	1		T215	1		T27	1
auto[2415919104:2550136831]	auto[0]	59	1			T62	1		T49	1		T68	2
auto[2415919104:2550136831]	auto[1]	47	1			T4	1		T15	1		T55	1
auto[2550136832:2684354559]	auto[0]	46	1			T15	1		T151	1		T26	2
auto[2550136832:2684354559]	auto[1]	57	1			T36	1		T150	1		T62	1
auto[2684354560:2818572287]	auto[0]	49	1			T60	1		T27	1		T68	1
auto[2684354560:2818572287]	auto[1]	62	1			T274	1		T62	1		T109	1
auto[2818572288:2952790015]	auto[0]	49	1			T110	1		T6	1		T117	1
auto[2818572288:2952790015]	auto[1]	57	1			T60	1		T27	1		T49	1
auto[2952790016:3087007743]	auto[0]	47	1			T60	1		T110	1		T68	1
auto[2952790016:3087007743]	auto[1]	71	1			T3	1		T25	1		T274	1
auto[3087007744:3221225471]	auto[0]	51	1			T27	1		T118	1		T68	1
auto[3087007744:3221225471]	auto[1]	62	1			T133	1		T53	1		T48	1
auto[3221225472:3355443199]	auto[0]	48	1			T14	1		T150	1		T50	2
auto[3221225472:3355443199]	auto[1]	38	1			T27	1		T22	1		T152	1
auto[3355443200:3489660927]	auto[0]	46	1			T55	1		T28	1		T27	2
auto[3355443200:3489660927]	auto[1]	62	1			T36	1		T150	1		T62	1
auto[3489660928:3623878655]	auto[0]	37	1			T16	1		T27	1		T49	1
auto[3489660928:3623878655]	auto[1]	52	1			T4	1		T274	1		T68	3
auto[3623878656:3758096383]	auto[0]	41	1			T4	1		T27	1		T68	2
auto[3623878656:3758096383]	auto[1]	63	1			T36	1		T57	1		T49	1
auto[3758096384:3892314111]	auto[0]	49	1			T15	1		T16	1		T151	1
auto[3758096384:3892314111]	auto[1]	54	1			T62	1		T74	1		T216	1
auto[3892314112:4026531839]	auto[0]	60	1			T16	1		T26	1		T27	2
auto[3892314112:4026531839]	auto[1]	59	1			T4	1		T25	1		T215	1
auto[4026531840:4160749567]	auto[0]	51	1			T48	2		T274	1		T27	1
auto[4026531840:4160749567]	auto[1]	50	1			T40	1		T49	1		T118	1
auto[4160749568:4294967295]	auto[0]	51	1			T16	1		T55	1		T48	1
auto[4160749568:4294967295]	auto[1]	53	1			T26	2		T27	2		T95	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1552

1

T4

3

T14

2

T15

5

auto[1]

1769

1

T1

3

T3

1

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T15	1		T150	1		T62	1
auto[134217728:268435455]	104	1			T36	1		T91	1		T151	1
auto[268435456:402653183]	88	1			T15	1		T16	1		T36	1
auto[402653184:536870911]	105	1			T28	1		T27	1		T220	1
auto[536870912:671088639]	88	1			T25	1		T53	1		T28	1
auto[671088640:805306367]	103	1			T16	2		T50	1		T27	3
auto[805306368:939524095]	106	1			T14	1		T26	1		T215	1
auto[939524096:1073741823]	104	1			T1	1		T12	1		T55	1
auto[1073741824:1207959551]	104	1			T16	1		T91	1		T55	1
auto[1207959552:1342177279]	109	1			T53	1		T60	1		T151	1
auto[1342177280:1476395007]	109	1			T150	1		T215	1		T27	3
auto[1476395008:1610612735]	97	1			T55	1		T61	1		T62	1
auto[1610612736:1744830463]	110	1			T1	1		T4	1		T55	1
auto[1744830464:1879048191]	105	1			T4	1		T151	2		T62	2
auto[1879048192:2013265919]	105	1			T60	1		T48	1		T26	1
auto[2013265920:2147483647]	87	1			T4	2		T27	1		T49	1
auto[2147483648:2281701375]	91	1			T4	1		T27	1		T109	1
auto[2281701376:2415919103]	111	1			T56	1		T53	1		T61	1
auto[2415919104:2550136831]	102	1			T1	1		T91	1		T67	1
auto[2550136832:2684354559]	113	1			T3	1		T14	1		T55	1
auto[2684354560:2818572287]	97	1			T15	1		T16	1		T150	1
auto[2818572288:2952790015]	102	1			T15	1		T36	1		T48	1
auto[2952790016:3087007743]	91	1			T14	1		T15	1		T55	1
auto[3087007744:3221225471]	91	1			T4	1		T67	1		T50	1
auto[3221225472:3355443199]	113	1			T26	1		T215	1		T27	3
auto[3355443200:3489660927]	89	1			T67	1		T28	1		T62	1
auto[3489660928:3623878655]	124	1			T16	1		T133	1		T38	1
auto[3623878656:3758096383]	114	1			T4	1		T14	1		T60	1
auto[3758096384:3892314111]	119	1			T15	1		T16	1		T56	1
auto[3892314112:4026531839]	137	1			T25	1		T60	1		T215	1
auto[4026531840:4160749567]	87	1			T55	1		T151	1		T50	1
auto[4160749568:4294967295]	107	1			T50	1		T40	1		T62	1