Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2914

1

T1

3

T3

1

T4

7

auto[1]

298

1

T14

1

T91

4

T150

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T28	1		T152	1		T23	1
auto[134217728:268435455]	114	1			T1	1		T150	1		T151	1
auto[268435456:402653183]	120	1			T15	1		T150	2		T151	1
auto[402653184:536870911]	86	1			T61	1		T150	2		T151	1
auto[536870912:671088639]	91	1			T91	1		T26	1		T27	2
auto[671088640:805306367]	95	1			T15	1		T91	1		T60	1
auto[805306368:939524095]	100	1			T151	1		T274	1		T40	1
auto[939524096:1073741823]	99	1			T50	1		T27	3		T109	1
auto[1073741824:1207959551]	94	1			T36	1		T150	1		T151	1
auto[1207959552:1342177279]	87	1			T150	1		T215	1		T27	1
auto[1342177280:1476395007]	105	1			T91	1		T55	1		T28	1
auto[1476395008:1610612735]	117	1			T150	1		T22	1		T222	1
auto[1610612736:1744830463]	94	1			T16	1		T91	1		T55	1
auto[1744830464:1879048191]	92	1			T4	1		T36	1		T60	1
auto[1879048192:2013265919]	106	1			T14	1		T15	1		T25	2
auto[2013265920:2147483647]	99	1			T4	1		T26	2		T62	1
auto[2147483648:2281701375]	130	1			T16	1		T91	2		T150	1
auto[2281701376:2415919103]	98	1			T50	1		T40	1		T62	1
auto[2415919104:2550136831]	106	1			T3	1		T150	1		T48	1
auto[2550136832:2684354559]	74	1			T1	1		T151	1		T62	1
auto[2684354560:2818572287]	102	1			T48	1		T57	1		T215	1
auto[2818572288:2952790015]	110	1			T1	1		T4	1		T14	1
auto[2952790016:3087007743]	102	1			T61	1		T67	1		T274	1
auto[3087007744:3221225471]	100	1			T12	1		T14	1		T55	1
auto[3221225472:3355443199]	97	1			T4	1		T16	1		T62	1
auto[3355443200:3489660927]	97	1			T36	1		T67	1		T151	2
auto[3489660928:3623878655]	99	1			T14	1		T150	1		T151	1
auto[3623878656:3758096383]	106	1			T15	1		T16	1		T91	1
auto[3758096384:3892314111]	104	1			T4	1		T15	1		T16	1
auto[3892314112:4026531839]	87	1			T4	1		T15	1		T67	1
auto[4026531840:4160749567]	104	1			T4	1		T16	1		T55	1
auto[4160749568:4294967295]	103	1			T14	1		T133	1		T62	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	86	1			T28	1		T23	1		T95	2
auto[0:134217727]	auto[1]	8	1			T152	1		T429	1		T322	1
auto[134217728:268435455]	auto[0]	104	1			T1	1		T151	1		T50	1
auto[134217728:268435455]	auto[1]	10	1			T150	1		T292	1		T376	1
auto[268435456:402653183]	auto[0]	108	1			T15	1		T49	3		T23	2
auto[268435456:402653183]	auto[1]	12	1			T150	2		T151	1		T139	1
auto[402653184:536870911]	auto[0]	76	1			T61	1		T50	1		T49	2
auto[402653184:536870911]	auto[1]	10	1			T150	2		T151	1		T376	2
auto[536870912:671088639]	auto[0]	82	1			T26	1		T27	2		T260	1
auto[536870912:671088639]	auto[1]	9	1			T91	1		T290	1		T275	1
auto[671088640:805306367]	auto[0]	89	1			T15	1		T60	1		T40	1
auto[671088640:805306367]	auto[1]	6	1			T91	1		T250	1		T251	1
auto[805306368:939524095]	auto[0]	87	1			T151	1		T274	1		T40	1
auto[805306368:939524095]	auto[1]	13	1			T142	1		T429	1		T250	1
auto[939524096:1073741823]	auto[0]	87	1			T50	1		T27	3		T109	1
auto[939524096:1073741823]	auto[1]	12	1			T152	1		T138	2		T376	1
auto[1073741824:1207959551]	auto[0]	89	1			T36	1		T150	1		T151	1
auto[1073741824:1207959551]	auto[1]	5	1			T292	1		T322	1		T437	1
auto[1207959552:1342177279]	auto[0]	78	1			T215	1		T27	1		T74	1
auto[1207959552:1342177279]	auto[1]	9	1			T150	1		T292	1		T376	1
auto[1342177280:1476395007]	auto[0]	97	1			T91	1		T55	1		T28	1
auto[1342177280:1476395007]	auto[1]	8	1			T151	1		T275	1		T140	1
auto[1476395008:1610612735]	auto[0]	104	1			T22	1		T222	1		T223	1
auto[1476395008:1610612735]	auto[1]	13	1			T150	1		T138	1		T393	2
auto[1610612736:1744830463]	auto[0]	90	1			T16	1		T55	1		T56	2
auto[1610612736:1744830463]	auto[1]	4	1			T91	1		T275	1		T349	1
auto[1744830464:1879048191]	auto[0]	81	1			T4	1		T36	1		T60	1
auto[1744830464:1879048191]	auto[1]	11	1			T138	1		T290	1		T376	1
auto[1879048192:2013265919]	auto[0]	97	1			T14	1		T15	1		T25	2
auto[1879048192:2013265919]	auto[1]	9	1			T311	1		T332	1		T251	1
auto[2013265920:2147483647]	auto[0]	93	1			T4	1		T26	2		T62	1
auto[2013265920:2147483647]	auto[1]	6	1			T311	1		T275	1		T140	1
auto[2147483648:2281701375]	auto[0]	117	1			T16	1		T91	1		T150	1
auto[2147483648:2281701375]	auto[1]	13	1			T91	1		T151	1		T290	1
auto[2281701376:2415919103]	auto[0]	90	1			T50	1		T40	1		T62	1
auto[2281701376:2415919103]	auto[1]	8	1			T117	1		T140	1		T310	1
auto[2415919104:2550136831]	auto[0]	94	1			T3	1		T48	1		T50	2
auto[2415919104:2550136831]	auto[1]	12	1			T150	1		T152	2		T275	1
auto[2550136832:2684354559]	auto[0]	70	1			T1	1		T62	1		T27	2
auto[2550136832:2684354559]	auto[1]	4	1			T151	1		T349	1		T383	2
auto[2684354560:2818572287]	auto[0]	89	1			T48	1		T57	1		T215	1
auto[2684354560:2818572287]	auto[1]	13	1			T332	2		T412	1		T434	1
auto[2818572288:2952790015]	auto[0]	96	1			T1	1		T4	1		T14	1
auto[2818572288:2952790015]	auto[1]	14	1			T151	1		T152	1		T275	1
auto[2952790016:3087007743]	auto[0]	93	1			T61	1		T67	1		T274	1
auto[2952790016:3087007743]	auto[1]	9	1			T152	1		T292	1		T376	1
auto[3087007744:3221225471]	auto[0]	91	1			T12	1		T55	1		T274	1
auto[3087007744:3221225471]	auto[1]	9	1			T14	1		T152	1		T141	1
auto[3221225472:3355443199]	auto[0]	91	1			T4	1		T16	1		T62	1
auto[3221225472:3355443199]	auto[1]	6	1			T311	1		T292	1		T386	1
auto[3355443200:3489660927]	auto[0]	90	1			T36	1		T67	1		T50	1
auto[3355443200:3489660927]	auto[1]	7	1			T151	2		T275	1		T292	1
auto[3489660928:3623878655]	auto[0]	88	1			T14	1		T49	1		T68	1
auto[3489660928:3623878655]	auto[1]	11	1			T150	1		T151	1		T376	1
auto[3623878656:3758096383]	auto[0]	96	1			T15	1		T16	1		T91	1
auto[3623878656:3758096383]	auto[1]	10	1			T138	1		T117	1		T332	1
auto[3758096384:3892314111]	auto[0]	99	1			T4	1		T15	1		T16	1
auto[3758096384:3892314111]	auto[1]	5	1			T310	1		T430	1		T251	1
auto[3892314112:4026531839]	auto[0]	76	1			T4	1		T15	1		T67	1
auto[3892314112:4026531839]	auto[1]	11	1			T150	1		T151	1		T152	1
auto[4026531840:4160749567]	auto[0]	91	1			T4	1		T16	1		T55	1
auto[4026531840:4160749567]	auto[1]	13	1			T138	1		T140	1		T430	1
auto[4160749568:4294967295]	auto[0]	95	1			T14	1		T133	1		T62	1
auto[4160749568:4294967295]	auto[1]	8	1			T152	1		T332	1		T430	1