Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6874

1

T1

6

T3

1

T4

14

auto[1]

292

1

T14

1

T91

5

T150

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2834	1			T1	3		T4	6		T12	1
auto[134217728:268435455]	164	1			T16	1		T151	1		T274	1
auto[268435456:402653183]	154	1			T16	1		T55	1		T56	1
auto[402653184:536870911]	185	1			T14	2		T150	1		T151	2
auto[536870912:671088639]	137	1			T1	1		T15	1		T36	1
auto[671088640:805306367]	144	1			T25	1		T67	1		T150	1
auto[805306368:939524095]	148	1			T4	2		T16	1		T25	1
auto[939524096:1073741823]	131	1			T4	1		T16	1		T91	1
auto[1073741824:1207959551]	147	1			T3	1		T4	1		T28	1
auto[1207959552:1342177279]	117	1			T16	1		T56	1		T61	1
auto[1342177280:1476395007]	160	1			T14	1		T55	1		T61	1
auto[1476395008:1610612735]	135	1			T1	1		T4	1		T28	1
auto[1610612736:1744830463]	155	1			T36	1		T55	1		T48	1
auto[1744830464:1879048191]	143	1			T15	1		T150	2		T151	2
auto[1879048192:2013265919]	145	1			T15	1		T16	1		T61	1
auto[2013265920:2147483647]	132	1			T25	1		T61	1		T67	1
auto[2147483648:2281701375]	149	1			T4	1		T25	1		T150	1
auto[2281701376:2415919103]	131	1			T14	1		T16	1		T49	1
auto[2415919104:2550136831]	122	1			T27	1		T109	1		T259	2
auto[2550136832:2684354559]	147	1			T91	1		T133	1		T48	1
auto[2684354560:2818572287]	124	1			T12	1		T55	1		T50	1
auto[2818572288:2952790015]	108	1			T274	1		T152	1		T68	1
auto[2952790016:3087007743]	132	1			T91	1		T150	1		T215	2
auto[3087007744:3221225471]	122	1			T28	1		T151	1		T27	1
auto[3221225472:3355443199]	125	1			T151	1		T26	2		T215	1
auto[3355443200:3489660927]	153	1			T1	1		T15	1		T150	2
auto[3489660928:3623878655]	137	1			T36	1		T25	1		T55	1
auto[3623878656:3758096383]	131	1			T15	1		T151	1		T50	1
auto[3758096384:3892314111]	140	1			T15	1		T150	1		T26	1
auto[3892314112:4026531839]	147	1			T14	1		T16	1		T91	1
auto[4026531840:4160749567]	132	1			T4	1		T25	1		T91	1
auto[4160749568:4294967295]	135	1			T4	1		T150	2		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2822	1			T1	3		T4	6		T12	1
auto[0:134217727]	auto[1]	12	1			T91	1		T150	1		T152	1
auto[134217728:268435455]	auto[0]	155	1			T16	1		T151	1		T274	1
auto[134217728:268435455]	auto[1]	9	1			T152	1		T275	1		T376	1
auto[268435456:402653183]	auto[0]	147	1			T16	1		T55	1		T56	1
auto[268435456:402653183]	auto[1]	7	1			T152	1		T332	1		T429	1
auto[402653184:536870911]	auto[0]	173	1			T14	1		T150	1		T151	1
auto[402653184:536870911]	auto[1]	12	1			T14	1		T151	1		T292	1
auto[536870912:671088639]	auto[0]	130	1			T1	1		T15	1		T36	1
auto[536870912:671088639]	auto[1]	7	1			T152	1		T434	1		T384	1
auto[671088640:805306367]	auto[0]	142	1			T25	1		T67	1		T150	1
auto[671088640:805306367]	auto[1]	2	1			T152	1		T140	1		-	-
auto[805306368:939524095]	auto[0]	142	1			T4	2		T16	1		T25	1
auto[805306368:939524095]	auto[1]	6	1			T376	1		T251	1		T411	2
auto[939524096:1073741823]	auto[0]	122	1			T4	1		T16	1		T91	1
auto[939524096:1073741823]	auto[1]	9	1			T151	1		T332	1		T393	1
auto[1073741824:1207959551]	auto[0]	136	1			T3	1		T4	1		T28	1
auto[1073741824:1207959551]	auto[1]	11	1			T311	1		T117	1		T429	1
auto[1207959552:1342177279]	auto[0]	109	1			T16	1		T56	1		T61	1
auto[1207959552:1342177279]	auto[1]	8	1			T151	1		T152	1		T140	1
auto[1342177280:1476395007]	auto[0]	153	1			T14	1		T55	1		T61	1
auto[1342177280:1476395007]	auto[1]	7	1			T140	1		T376	1		T251	1
auto[1476395008:1610612735]	auto[0]	128	1			T1	1		T4	1		T28	1
auto[1476395008:1610612735]	auto[1]	7	1			T151	1		T152	1		T376	1
auto[1610612736:1744830463]	auto[0]	148	1			T36	1		T55	1		T48	1
auto[1610612736:1744830463]	auto[1]	7	1			T139	1		T376	1		T430	1
auto[1744830464:1879048191]	auto[0]	129	1			T15	1		T27	2		T118	1
auto[1744830464:1879048191]	auto[1]	14	1			T150	2		T151	2		T138	1
auto[1879048192:2013265919]	auto[0]	135	1			T15	1		T16	1		T61	1
auto[1879048192:2013265919]	auto[1]	10	1			T139	1		T292	1		T140	1
auto[2013265920:2147483647]	auto[0]	122	1			T25	1		T61	1		T67	1
auto[2013265920:2147483647]	auto[1]	10	1			T152	1		T139	1		T311	1
auto[2147483648:2281701375]	auto[0]	139	1			T4	1		T25	1		T150	1
auto[2147483648:2281701375]	auto[1]	10	1			T376	1		T251	1		T323	1
auto[2281701376:2415919103]	auto[0]	121	1			T14	1		T16	1		T49	1
auto[2281701376:2415919103]	auto[1]	10	1			T152	1		T138	1		T292	1
auto[2415919104:2550136831]	auto[0]	111	1			T27	1		T109	1		T259	2
auto[2415919104:2550136831]	auto[1]	11	1			T275	1		T140	1		T141	1
auto[2550136832:2684354559]	auto[0]	138	1			T133	1		T48	1		T27	1
auto[2550136832:2684354559]	auto[1]	9	1			T91	1		T384	2		T430	1
auto[2684354560:2818572287]	auto[0]	115	1			T12	1		T55	1		T50	1
auto[2684354560:2818572287]	auto[1]	9	1			T275	2		T429	3		T384	1
auto[2818572288:2952790015]	auto[0]	100	1			T274	1		T68	1		T76	1
auto[2818572288:2952790015]	auto[1]	8	1			T152	1		T292	1		T140	1
auto[2952790016:3087007743]	auto[0]	118	1			T215	2		T40	1		T118	1
auto[2952790016:3087007743]	auto[1]	14	1			T91	1		T150	1		T152	1
auto[3087007744:3221225471]	auto[0]	115	1			T28	1		T151	1		T27	1
auto[3087007744:3221225471]	auto[1]	7	1			T140	2		T434	1		T384	1
auto[3221225472:3355443199]	auto[0]	120	1			T26	2		T215	1		T27	2
auto[3221225472:3355443199]	auto[1]	5	1			T151	1		T140	1		T355	1
auto[3355443200:3489660927]	auto[0]	144	1			T1	1		T15	1		T150	1
auto[3355443200:3489660927]	auto[1]	9	1			T150	1		T275	1		T434	1
auto[3489660928:3623878655]	auto[0]	128	1			T36	1		T25	1		T55	1
auto[3489660928:3623878655]	auto[1]	9	1			T152	1		T275	1		T376	1
auto[3623878656:3758096383]	auto[0]	119	1			T15	1		T50	1		T26	2
auto[3623878656:3758096383]	auto[1]	12	1			T151	1		T152	1		T138	1
auto[3758096384:3892314111]	auto[0]	137	1			T15	1		T150	1		T26	1
auto[3758096384:3892314111]	auto[1]	3	1			T290	1		T411	1		T383	1
auto[3892314112:4026531839]	auto[0]	132	1			T14	1		T16	1		T60	1
auto[3892314112:4026531839]	auto[1]	15	1			T91	1		T292	1		T140	1
auto[4026531840:4160749567]	auto[0]	118	1			T4	1		T25	1		T151	1
auto[4026531840:4160749567]	auto[1]	14	1			T91	1		T150	1		T275	1
auto[4160749568:4294967295]	auto[0]	126	1			T4	1		T26	1		T215	1
auto[4160749568:4294967295]	auto[1]	9	1			T150	2		T292	1		T142	1