Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 99.00 98.07 98.57 97.67 98.93 98.41 91.27


Total test records in report: 1077
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T1005 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1794729373 May 28 01:43:19 PM PDT 24 May 28 01:43:22 PM PDT 24 11739274 ps
T182 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1656239330 May 28 01:43:21 PM PDT 24 May 28 01:43:30 PM PDT 24 129548415 ps
T1006 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.614753463 May 28 01:43:21 PM PDT 24 May 28 01:43:26 PM PDT 24 55952218 ps
T1007 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.757703048 May 28 01:43:51 PM PDT 24 May 28 01:43:55 PM PDT 24 706968488 ps
T1008 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1190584322 May 28 01:43:19 PM PDT 24 May 28 01:43:23 PM PDT 24 657901695 ps
T1009 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1703451843 May 28 01:46:11 PM PDT 24 May 28 01:46:33 PM PDT 24 93573947 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2303115875 May 28 01:43:19 PM PDT 24 May 28 01:43:22 PM PDT 24 155808225 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.939460329 May 28 01:43:31 PM PDT 24 May 28 01:43:41 PM PDT 24 647587599 ps
T1012 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1224464933 May 28 01:43:34 PM PDT 24 May 28 01:43:38 PM PDT 24 199516117 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2682585509 May 28 01:43:20 PM PDT 24 May 28 01:43:30 PM PDT 24 133923678 ps
T1014 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2575016865 May 28 01:46:09 PM PDT 24 May 28 01:46:30 PM PDT 24 506934869 ps
T1015 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.913145543 May 28 01:46:11 PM PDT 24 May 28 01:46:34 PM PDT 24 187588419 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3480102806 May 28 01:43:22 PM PDT 24 May 28 01:43:32 PM PDT 24 565513487 ps
T1017 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.681909728 May 28 01:43:53 PM PDT 24 May 28 01:44:05 PM PDT 24 1889016385 ps
T1018 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1077517585 May 28 01:43:36 PM PDT 24 May 28 01:43:39 PM PDT 24 301866463 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3500576463 May 28 01:43:20 PM PDT 24 May 28 01:43:28 PM PDT 24 131891757 ps
T1020 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.688518840 May 28 01:43:22 PM PDT 24 May 28 01:43:28 PM PDT 24 158670201 ps
T170 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1683472261 May 28 01:43:24 PM PDT 24 May 28 01:43:30 PM PDT 24 148311972 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3300814364 May 28 01:43:23 PM PDT 24 May 28 01:43:27 PM PDT 24 311737500 ps
T1022 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1779550020 May 28 01:43:21 PM PDT 24 May 28 01:43:35 PM PDT 24 255578680 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3209867478 May 28 01:43:51 PM PDT 24 May 28 01:43:54 PM PDT 24 204075758 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.972196813 May 28 01:46:14 PM PDT 24 May 28 01:46:38 PM PDT 24 513894810 ps
T1025 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2442242580 May 28 01:43:55 PM PDT 24 May 28 01:43:58 PM PDT 24 8469821 ps
T1026 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1396805792 May 28 01:43:50 PM PDT 24 May 28 01:43:56 PM PDT 24 169760934 ps
T1027 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1828581996 May 28 01:43:37 PM PDT 24 May 28 01:43:40 PM PDT 24 56556031 ps
T1028 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2904579034 May 28 01:43:57 PM PDT 24 May 28 01:43:59 PM PDT 24 20426654 ps
T1029 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.188535268 May 28 01:43:51 PM PDT 24 May 28 01:43:53 PM PDT 24 91179576 ps
T1030 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.939488126 May 28 01:43:21 PM PDT 24 May 28 01:43:30 PM PDT 24 1856075362 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1052739234 May 28 01:43:18 PM PDT 24 May 28 01:43:24 PM PDT 24 220770392 ps
T1032 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4064811876 May 28 01:43:27 PM PDT 24 May 28 01:43:29 PM PDT 24 20222113 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3929494039 May 28 01:43:20 PM PDT 24 May 28 01:43:29 PM PDT 24 436257414 ps
T167 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2283802899 May 28 01:43:29 PM PDT 24 May 28 01:43:35 PM PDT 24 303968905 ps
T1034 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.320514481 May 28 01:43:29 PM PDT 24 May 28 01:43:32 PM PDT 24 73958588 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.36542419 May 28 01:43:16 PM PDT 24 May 28 01:43:18 PM PDT 24 13633268 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.27225232 May 28 01:43:21 PM PDT 24 May 28 01:43:27 PM PDT 24 49106851 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2964634023 May 28 01:43:20 PM PDT 24 May 28 01:43:24 PM PDT 24 68067427 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.25034199 May 28 01:43:17 PM PDT 24 May 28 01:43:20 PM PDT 24 49704273 ps
T1039 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2067575223 May 28 01:43:56 PM PDT 24 May 28 01:43:59 PM PDT 24 33008719 ps
T1040 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1042645983 May 28 01:43:51 PM PDT 24 May 28 01:43:53 PM PDT 24 39417531 ps
T1041 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2666895473 May 28 01:43:53 PM PDT 24 May 28 01:43:56 PM PDT 24 10325113 ps
T1042 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.419571605 May 28 01:43:38 PM PDT 24 May 28 01:43:42 PM PDT 24 457325513 ps
T1043 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3777257950 May 28 01:43:31 PM PDT 24 May 28 01:43:34 PM PDT 24 107989766 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.884496394 May 28 01:43:29 PM PDT 24 May 28 01:43:33 PM PDT 24 212043033 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3577741599 May 28 01:43:39 PM PDT 24 May 28 01:43:42 PM PDT 24 65054823 ps
T1046 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2872395211 May 28 01:43:51 PM PDT 24 May 28 01:43:54 PM PDT 24 16565056 ps
T1047 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1031705581 May 28 01:43:39 PM PDT 24 May 28 01:43:43 PM PDT 24 310162142 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3695172941 May 28 01:43:17 PM PDT 24 May 28 01:43:48 PM PDT 24 1115519666 ps
T1049 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4207277271 May 28 01:43:52 PM PDT 24 May 28 01:43:55 PM PDT 24 35355861 ps
T1050 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2341313056 May 28 01:43:52 PM PDT 24 May 28 01:43:56 PM PDT 24 49513853 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1195428332 May 28 01:43:22 PM PDT 24 May 28 01:43:45 PM PDT 24 1309729940 ps
T1052 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1671166113 May 28 01:43:21 PM PDT 24 May 28 01:43:26 PM PDT 24 24465459 ps
T1053 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1032311202 May 28 01:43:27 PM PDT 24 May 28 01:43:32 PM PDT 24 226675560 ps
T1054 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2116251828 May 28 01:43:21 PM PDT 24 May 28 01:43:25 PM PDT 24 47257077 ps
T1055 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1782336610 May 28 01:43:50 PM PDT 24 May 28 01:43:51 PM PDT 24 9476012 ps
T1056 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2809292090 May 28 01:43:20 PM PDT 24 May 28 01:43:33 PM PDT 24 897192547 ps
T1057 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2592279195 May 28 01:46:04 PM PDT 24 May 28 01:46:19 PM PDT 24 936399214 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2729437582 May 28 01:43:17 PM PDT 24 May 28 01:43:19 PM PDT 24 75677313 ps
T1059 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2025161817 May 28 01:43:51 PM PDT 24 May 28 01:43:53 PM PDT 24 18801271 ps
T1060 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2107995063 May 28 01:43:55 PM PDT 24 May 28 01:43:58 PM PDT 24 39452149 ps
T1061 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.119472187 May 28 01:46:10 PM PDT 24 May 28 01:46:31 PM PDT 24 388860421 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2835213716 May 28 01:43:20 PM PDT 24 May 28 01:43:26 PM PDT 24 78681884 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.212634219 May 28 01:43:20 PM PDT 24 May 28 01:43:25 PM PDT 24 150432561 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3654592649 May 28 01:43:18 PM PDT 24 May 28 01:43:21 PM PDT 24 66000109 ps
T1065 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2681888020 May 28 01:43:36 PM PDT 24 May 28 01:43:38 PM PDT 24 11512938 ps
T1066 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2096427710 May 28 01:46:12 PM PDT 24 May 28 01:46:34 PM PDT 24 84797958 ps
T1067 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.559828390 May 28 01:43:54 PM PDT 24 May 28 01:43:57 PM PDT 24 33523058 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1171184495 May 28 01:43:56 PM PDT 24 May 28 01:43:59 PM PDT 24 49864963 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2854407558 May 28 01:43:23 PM PDT 24 May 28 01:43:27 PM PDT 24 91699944 ps
T1070 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3666971242 May 28 01:43:59 PM PDT 24 May 28 01:44:01 PM PDT 24 16341749 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4269721352 May 28 01:43:22 PM PDT 24 May 28 01:43:29 PM PDT 24 65289234 ps
T171 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2287262946 May 28 01:43:16 PM PDT 24 May 28 01:43:23 PM PDT 24 799719035 ps
T1072 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1635920558 May 28 01:43:17 PM PDT 24 May 28 01:43:23 PM PDT 24 434122197 ps
T1073 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4191083403 May 28 01:43:55 PM PDT 24 May 28 01:43:58 PM PDT 24 16441662 ps
T1074 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2479088125 May 28 01:43:57 PM PDT 24 May 28 01:44:15 PM PDT 24 542352010 ps
T1075 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3329457952 May 28 01:43:38 PM PDT 24 May 28 01:43:45 PM PDT 24 336385659 ps
T1076 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.148872770 May 28 01:46:10 PM PDT 24 May 28 01:46:36 PM PDT 24 585770575 ps
T1077 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.174376082 May 28 01:43:38 PM PDT 24 May 28 01:43:48 PM PDT 24 236946485 ps

Test location /workspace/coverage/default/31.keymgr_stress_all.2633758594
Short name T4
Test name
Test status
Simulation time 216559871 ps
CPU time 7.82 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:56 PM PDT 24
Peak memory 220904 kb
Host smart-d773befb-a75e-4651-947d-db99a382825c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633758594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2633758594
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2230827025
Short name T27
Test name
Test status
Simulation time 1297215636 ps
CPU time 47.46 seconds
Started May 28 02:55:10 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 217204 kb
Host smart-2bebf112-c995-4ce6-9dc6-cb89125be729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230827025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2230827025
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4224842643
Short name T60
Test name
Test status
Simulation time 64586072 ps
CPU time 2.94 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 218952 kb
Host smart-5c399f56-4ee4-4053-a4cf-1ea4e01bfd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224842643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4224842643
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2679054546
Short name T68
Test name
Test status
Simulation time 3198684924 ps
CPU time 35.8 seconds
Started May 28 02:57:11 PM PDT 24
Finished May 28 02:57:53 PM PDT 24
Peak memory 215928 kb
Host smart-b4a9ec50-e2fb-4cbe-a2c9-2b8c85a9e9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679054546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2679054546
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4170426544
Short name T8
Test name
Test status
Simulation time 225042150 ps
CPU time 5.26 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:47 PM PDT 24
Peak memory 230664 kb
Host smart-9852354c-2ca9-41b7-92d9-8ee4c9321caf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170426544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4170426544
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3954839099
Short name T130
Test name
Test status
Simulation time 1091545684 ps
CPU time 7.27 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 220260 kb
Host smart-8efff9dc-85f3-4431-a8b6-99f022dfcad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954839099 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3954839099
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.573814637
Short name T6
Test name
Test status
Simulation time 10746043509 ps
CPU time 39.35 seconds
Started May 28 02:58:18 PM PDT 24
Finished May 28 02:59:19 PM PDT 24
Peak memory 215856 kb
Host smart-953e8ad8-d9a0-45d8-bdc2-d97b28d034e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573814637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.573814637
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.718780550
Short name T91
Test name
Test status
Simulation time 263280031 ps
CPU time 8.03 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:21 PM PDT 24
Peak memory 214388 kb
Host smart-1773242f-f6b2-4348-b81b-603f4dbb5856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718780550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.718780550
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.569070978
Short name T119
Test name
Test status
Simulation time 629959701 ps
CPU time 12.47 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 214460 kb
Host smart-cbdd243f-91fc-4f77-995b-f364771c5b39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569070978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.569070978
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3156754146
Short name T122
Test name
Test status
Simulation time 6967247115 ps
CPU time 19.05 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:26 PM PDT 24
Peak memory 222740 kb
Host smart-c06241bc-bff3-4115-ba85-8eabef8c8976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156754146 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3156754146
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2669630560
Short name T338
Test name
Test status
Simulation time 1456104360 ps
CPU time 37.04 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:38 PM PDT 24
Peak memory 222468 kb
Host smart-4794ad9e-b22c-4f6d-921a-947bed7fb123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669630560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2669630560
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3574816044
Short name T2
Test name
Test status
Simulation time 57636803 ps
CPU time 2.3 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:35 PM PDT 24
Peak memory 210080 kb
Host smart-b3540ccb-febd-4269-8e21-f52ee1d488f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574816044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3574816044
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1185374379
Short name T275
Test name
Test status
Simulation time 1795481688 ps
CPU time 46.85 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:58:13 PM PDT 24
Peak memory 215356 kb
Host smart-0687e671-7c2b-4feb-9c28-6ab76551a4e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185374379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1185374379
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1997670458
Short name T24
Test name
Test status
Simulation time 956451302 ps
CPU time 21.27 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:44 PM PDT 24
Peak memory 214364 kb
Host smart-c85c4a9f-508e-48eb-8c7a-1a129b37175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997670458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1997670458
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.983653896
Short name T150
Test name
Test status
Simulation time 727123324 ps
CPU time 10.77 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 215476 kb
Host smart-e053f552-c33e-441f-9e8f-c83bced1e485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983653896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.983653896
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2680051422
Short name T17
Test name
Test status
Simulation time 97035221 ps
CPU time 3.97 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:49 PM PDT 24
Peak memory 208548 kb
Host smart-f02dafa3-0def-463a-8695-7a960313677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680051422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2680051422
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4231041773
Short name T441
Test name
Test status
Simulation time 216091173 ps
CPU time 11.5 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:19 PM PDT 24
Peak memory 222464 kb
Host smart-d65ff7f7-0c35-4305-8a64-c8a67c3d0e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231041773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4231041773
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2740422206
Short name T118
Test name
Test status
Simulation time 290390294 ps
CPU time 9.15 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:45 PM PDT 24
Peak memory 222736 kb
Host smart-9a0c8589-3368-4c52-8f0d-bd2d7568e6f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740422206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2740422206
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.704634163
Short name T78
Test name
Test status
Simulation time 822211039 ps
CPU time 28.3 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:38 PM PDT 24
Peak memory 222560 kb
Host smart-96c2e9cf-fb55-4d6e-8247-8c2d11fa18e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704634163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.704634163
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1051788091
Short name T355
Test name
Test status
Simulation time 279790809 ps
CPU time 15.15 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 215840 kb
Host smart-f736ad8b-28b2-4dec-97a2-ca5df4b9991a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051788091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1051788091
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2862032218
Short name T15
Test name
Test status
Simulation time 130932875 ps
CPU time 3.66 seconds
Started May 28 02:55:47 PM PDT 24
Finished May 28 02:56:02 PM PDT 24
Peak memory 214352 kb
Host smart-a9e24084-83e7-451f-b674-f7037636cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862032218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2862032218
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.726011462
Short name T49
Test name
Test status
Simulation time 23465071741 ps
CPU time 222.92 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:59:32 PM PDT 24
Peak memory 230896 kb
Host smart-0e65bd66-4d67-402b-9611-98c42978db16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726011462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.726011462
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3099094436
Short name T126
Test name
Test status
Simulation time 2327925331 ps
CPU time 2.93 seconds
Started May 28 01:43:30 PM PDT 24
Finished May 28 01:43:34 PM PDT 24
Peak memory 214228 kb
Host smart-9ae390f1-acb4-48c8-bf0b-800223c8023d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099094436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3099094436
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4005782148
Short name T20
Test name
Test status
Simulation time 42032123 ps
CPU time 2.19 seconds
Started May 28 02:57:30 PM PDT 24
Finished May 28 02:57:33 PM PDT 24
Peak memory 209948 kb
Host smart-a7c060e4-aefa-4a96-9751-4e007331a03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005782148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4005782148
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.430344537
Short name T19
Test name
Test status
Simulation time 1513249749 ps
CPU time 17.06 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 219324 kb
Host smart-b88a3b57-7ead-401f-ae94-e8668cc6491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430344537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.430344537
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4033183711
Short name T31
Test name
Test status
Simulation time 345385012 ps
CPU time 4.26 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 214484 kb
Host smart-eb609e04-905f-4718-82fa-a2b1331191c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033183711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4033183711
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2067606333
Short name T724
Test name
Test status
Simulation time 68924368 ps
CPU time 3.02 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 208768 kb
Host smart-a2e702cb-926e-4651-a53c-f430c888c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067606333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2067606333
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3812163246
Short name T38
Test name
Test status
Simulation time 128627611 ps
CPU time 4.73 seconds
Started May 28 02:55:43 PM PDT 24
Finished May 28 02:56:00 PM PDT 24
Peak memory 222712 kb
Host smart-44b02e1a-672d-4b6a-bfa5-a1f1d0c20e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812163246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3812163246
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.842529007
Short name T151
Test name
Test status
Simulation time 6369837937 ps
CPU time 85.38 seconds
Started May 28 02:55:52 PM PDT 24
Finished May 28 02:57:29 PM PDT 24
Peak memory 215332 kb
Host smart-a52319b3-6bd0-4dd6-9865-8dd4b2689466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842529007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.842529007
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.240967362
Short name T332
Test name
Test status
Simulation time 6320089430 ps
CPU time 90.15 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:57:19 PM PDT 24
Peak memory 215464 kb
Host smart-cfe318a7-b74a-4a8c-a37a-58cd12ea8b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=240967362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.240967362
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3511521718
Short name T92
Test name
Test status
Simulation time 65143664 ps
CPU time 2.74 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 222576 kb
Host smart-0de22eaf-4a96-4803-995a-83945cd5d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511521718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3511521718
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2906221946
Short name T323
Test name
Test status
Simulation time 1171846705 ps
CPU time 67.48 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 216116 kb
Host smart-972d5dbe-0a5b-4a75-a7d7-25fa0510104f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906221946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2906221946
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1731187187
Short name T164
Test name
Test status
Simulation time 389957454 ps
CPU time 8.37 seconds
Started May 28 01:43:24 PM PDT 24
Finished May 28 01:43:34 PM PDT 24
Peak memory 216440 kb
Host smart-9ffd9d24-67dd-4e86-aae8-a0c8dbf9a77c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731187187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1731187187
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2746249972
Short name T469
Test name
Test status
Simulation time 22940874 ps
CPU time 0.82 seconds
Started May 28 02:55:42 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 205980 kb
Host smart-6ca0dc7b-c3e3-4eae-99e9-6e82171071eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746249972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2746249972
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2944477193
Short name T52
Test name
Test status
Simulation time 11160449582 ps
CPU time 40.55 seconds
Started May 28 02:56:27 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 222324 kb
Host smart-6c887fa9-2fe6-47c2-8b0d-8db56b59be5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944477193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2944477193
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2278614095
Short name T70
Test name
Test status
Simulation time 1387829086 ps
CPU time 52.25 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:58:15 PM PDT 24
Peak memory 222604 kb
Host smart-f8b2e5ad-91b5-4de7-b217-d30d4fdf506c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278614095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2278614095
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2471364854
Short name T224
Test name
Test status
Simulation time 2111795784 ps
CPU time 21.51 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 214344 kb
Host smart-5f8c79ac-da78-47e3-86b3-d06197b9010e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471364854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2471364854
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1175754778
Short name T140
Test name
Test status
Simulation time 193752688 ps
CPU time 10.43 seconds
Started May 28 02:55:40 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 214932 kb
Host smart-e16ac415-6d8a-4b04-a53e-f4c28fe65d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175754778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1175754778
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.251768298
Short name T85
Test name
Test status
Simulation time 306537445 ps
CPU time 4.41 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:46 PM PDT 24
Peak memory 208884 kb
Host smart-6c8f6b82-c680-4456-b212-85a59543d354
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251768298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.251768298
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2164635775
Short name T348
Test name
Test status
Simulation time 1025717086 ps
CPU time 7.9 seconds
Started May 28 02:55:50 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 214404 kb
Host smart-d528dc97-3e83-41db-9c5a-77e7e5015435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164635775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2164635775
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1600438591
Short name T191
Test name
Test status
Simulation time 354860642 ps
CPU time 3.2 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 214320 kb
Host smart-15a3b963-3e64-4b61-a3dd-20105b86b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600438591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1600438591
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2855459801
Short name T177
Test name
Test status
Simulation time 157000022 ps
CPU time 3.72 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 213852 kb
Host smart-7b4eca0b-ff78-48db-9911-19088902728e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855459801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2855459801
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1178989256
Short name T202
Test name
Test status
Simulation time 1596452373 ps
CPU time 30.16 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:38 PM PDT 24
Peak memory 220768 kb
Host smart-d54702eb-e78d-49ad-8f43-c3bf489fc148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178989256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1178989256
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2746507407
Short name T94
Test name
Test status
Simulation time 31273712 ps
CPU time 2.1 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 214604 kb
Host smart-21407405-d190-4dc6-808b-e6ffe48511d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746507407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2746507407
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1174712125
Short name T288
Test name
Test status
Simulation time 9032272115 ps
CPU time 79.11 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:57:28 PM PDT 24
Peak memory 222512 kb
Host smart-e2416815-7839-4575-8e13-1d6ae0280b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174712125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1174712125
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1703148408
Short name T374
Test name
Test status
Simulation time 76778565 ps
CPU time 3.65 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 208944 kb
Host smart-6433e82b-1c06-415f-a109-765a8849bcaf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703148408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1703148408
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3214288455
Short name T16
Test name
Test status
Simulation time 334349155 ps
CPU time 3.98 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:37 PM PDT 24
Peak memory 221696 kb
Host smart-3b232c2a-1aa9-45e3-a721-39929e70bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214288455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3214288455
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3268327213
Short name T292
Test name
Test status
Simulation time 266887247 ps
CPU time 8.52 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:56 PM PDT 24
Peak memory 214384 kb
Host smart-2a1f6ff1-e79f-49d1-a92f-58a0ecac6154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268327213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3268327213
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4139076981
Short name T247
Test name
Test status
Simulation time 1047832121 ps
CPU time 38.98 seconds
Started May 28 02:57:38 PM PDT 24
Finished May 28 02:58:21 PM PDT 24
Peak memory 222620 kb
Host smart-4b5a31e2-c528-46f3-9a6c-9ca8063dda51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139076981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4139076981
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3417799190
Short name T163
Test name
Test status
Simulation time 443543674 ps
CPU time 3.37 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:42 PM PDT 24
Peak memory 214064 kb
Host smart-ea1e8ec4-fe9d-483e-98cb-f93e45a853e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417799190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3417799190
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.987534722
Short name T166
Test name
Test status
Simulation time 82138243 ps
CPU time 2.7 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 214036 kb
Host smart-e39811b3-3aa0-4f48-ad15-3b372a9411f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987534722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.987534722
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3829061732
Short name T154
Test name
Test status
Simulation time 325202902 ps
CPU time 4.64 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 217572 kb
Host smart-5de35699-ecc5-4de4-847b-fde6c9859402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829061732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3829061732
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.675993043
Short name T157
Test name
Test status
Simulation time 62133620 ps
CPU time 3.07 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 217912 kb
Host smart-0ee81ffa-1264-4b83-afbd-a02e321fbf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675993043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.675993043
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.206390364
Short name T155
Test name
Test status
Simulation time 37336726 ps
CPU time 2.81 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:02 PM PDT 24
Peak memory 218404 kb
Host smart-f90ec09c-cb34-4df2-9798-6842662874da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206390364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.206390364
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3819071091
Short name T160
Test name
Test status
Simulation time 190285849 ps
CPU time 6.65 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:44 PM PDT 24
Peak memory 222660 kb
Host smart-ebbe6093-ff0d-4042-8063-6dcfc5ed88dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819071091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3819071091
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2893367400
Short name T237
Test name
Test status
Simulation time 1742660071 ps
CPU time 37.12 seconds
Started May 28 02:56:01 PM PDT 24
Finished May 28 02:56:47 PM PDT 24
Peak memory 222548 kb
Host smart-6105ca2f-ec88-453b-af3f-78fd8488d082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893367400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2893367400
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1695333979
Short name T139
Test name
Test status
Simulation time 199030764 ps
CPU time 3.91 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:59 PM PDT 24
Peak memory 214392 kb
Host smart-2b4be02b-56c1-41b3-b351-c180d02d698d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695333979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1695333979
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3886801297
Short name T286
Test name
Test status
Simulation time 51146476 ps
CPU time 2.95 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 214412 kb
Host smart-9245d9c6-738a-41e8-b7c0-38980699e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886801297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3886801297
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2108080827
Short name T10
Test name
Test status
Simulation time 809277726 ps
CPU time 9.39 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:48 PM PDT 24
Peak memory 237924 kb
Host smart-6fb31735-6170-47e5-a550-708be69ca2a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108080827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2108080827
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.949524351
Short name T178
Test name
Test status
Simulation time 611786435 ps
CPU time 5.99 seconds
Started May 28 01:43:29 PM PDT 24
Finished May 28 01:43:37 PM PDT 24
Peak memory 215424 kb
Host smart-a968b520-1d04-41cf-a73c-d83f16b95de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949524351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
949524351
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.120175750
Short name T364
Test name
Test status
Simulation time 56152006 ps
CPU time 2.31 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:29 PM PDT 24
Peak memory 214644 kb
Host smart-65bee3ef-08b9-4837-a5ba-a014cff4ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120175750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.120175750
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1465691361
Short name T428
Test name
Test status
Simulation time 503054768 ps
CPU time 2.25 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:49 PM PDT 24
Peak memory 209940 kb
Host smart-dbd6ee21-ff9c-4513-aaf9-97062b493249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465691361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1465691361
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1610899658
Short name T152
Test name
Test status
Simulation time 147217085 ps
CPU time 7.03 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:40 PM PDT 24
Peak memory 214388 kb
Host smart-b5063e00-0881-4a51-b0ca-7e55f8945bce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610899658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1610899658
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2663030169
Short name T267
Test name
Test status
Simulation time 10561592759 ps
CPU time 210.65 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 03:00:13 PM PDT 24
Peak memory 216360 kb
Host smart-297fd2bf-d16c-467e-a7b5-cb4dea43e10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663030169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2663030169
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.855650612
Short name T386
Test name
Test status
Simulation time 518165806 ps
CPU time 14.89 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 215652 kb
Host smart-5541c927-6dfc-41fc-bac8-58cbb07b84c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855650612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.855650612
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3030187623
Short name T153
Test name
Test status
Simulation time 234106177 ps
CPU time 4.22 seconds
Started May 28 02:57:11 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 222720 kb
Host smart-63375934-8700-4cf5-b1b4-8affaf06404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030187623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3030187623
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4054699085
Short name T159
Test name
Test status
Simulation time 29304331 ps
CPU time 2.13 seconds
Started May 28 02:57:53 PM PDT 24
Finished May 28 02:58:01 PM PDT 24
Peak memory 215992 kb
Host smart-1129d55a-fcab-44ec-8627-4405ba9a0945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054699085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4054699085
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.289823171
Short name T272
Test name
Test status
Simulation time 886139481 ps
CPU time 19.43 seconds
Started May 28 02:55:10 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 209380 kb
Host smart-e55a8b7f-edb7-4ba7-8456-8014bb768cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289823171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.289823171
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.150386099
Short name T243
Test name
Test status
Simulation time 129952372 ps
CPU time 2.6 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 214436 kb
Host smart-59e54829-db2c-41ae-88ca-e376588e83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150386099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.150386099
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1702198823
Short name T343
Test name
Test status
Simulation time 123030726 ps
CPU time 3.75 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 214360 kb
Host smart-caf54acf-5040-41b7-b93c-d69642e1a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702198823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1702198823
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3578005653
Short name T874
Test name
Test status
Simulation time 2597302891 ps
CPU time 20.15 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 217624 kb
Host smart-b404d297-d32d-4fe9-b0c4-b7a3199f49e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578005653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3578005653
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2223559916
Short name T142
Test name
Test status
Simulation time 141583930 ps
CPU time 3.43 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 222592 kb
Host smart-e6ba2ffa-533e-4489-8087-8336275a216e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223559916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2223559916
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.514778509
Short name T295
Test name
Test status
Simulation time 104864049 ps
CPU time 2.26 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 214328 kb
Host smart-cbc45a4a-dd06-4eed-bc8f-597486200e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514778509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.514778509
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3286303982
Short name T383
Test name
Test status
Simulation time 1492866303 ps
CPU time 72.5 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:58:33 PM PDT 24
Peak memory 215080 kb
Host smart-9e0cf352-a072-4662-8f62-838cd1cf7168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286303982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3286303982
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2287262946
Short name T171
Test name
Test status
Simulation time 799719035 ps
CPU time 6.6 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 213916 kb
Host smart-e76a4280-a8b7-4838-8706-b07278ca8a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287262946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2287262946
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2330665
Short name T179
Test name
Test status
Simulation time 131057718 ps
CPU time 4.51 seconds
Started May 28 01:43:27 PM PDT 24
Finished May 28 01:43:32 PM PDT 24
Peak memory 205844 kb
Host smart-84cf5944-0966-411d-977b-606a2de9cc95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.2330665
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3332079042
Short name T21
Test name
Test status
Simulation time 98309926 ps
CPU time 2.83 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 214692 kb
Host smart-131c95e8-c534-433c-9915-bb1aa3165878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332079042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3332079042
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4037296408
Short name T183
Test name
Test status
Simulation time 5297005128 ps
CPU time 12.01 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 211636 kb
Host smart-ee1afbf6-6b44-4f10-a2b1-c6b652fd0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037296408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4037296408
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1560079005
Short name T158
Test name
Test status
Simulation time 71890716 ps
CPU time 3.5 seconds
Started May 28 02:55:05 PM PDT 24
Finished May 28 02:55:15 PM PDT 24
Peak memory 218372 kb
Host smart-1f0083f6-8aec-4a34-b0d9-b0cc24b5c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560079005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1560079005
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.593333674
Short name T54
Test name
Test status
Simulation time 62602284 ps
CPU time 2.32 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 218220 kb
Host smart-5e790246-c278-496e-83e8-fa55ba011f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593333674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.593333674
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3118113780
Short name T478
Test name
Test status
Simulation time 20955709 ps
CPU time 1.76 seconds
Started May 28 02:55:04 PM PDT 24
Finished May 28 02:55:08 PM PDT 24
Peak memory 206948 kb
Host smart-f8f30ba3-0067-4009-aa9d-a70b0ef26bdb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118113780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3118113780
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3353729119
Short name T219
Test name
Test status
Simulation time 165315540 ps
CPU time 4.61 seconds
Started May 28 02:55:06 PM PDT 24
Finished May 28 02:55:17 PM PDT 24
Peak memory 208528 kb
Host smart-ae2b0551-e279-49b6-8f37-0826a5bf07b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353729119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3353729119
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2196773134
Short name T508
Test name
Test status
Simulation time 50496560 ps
CPU time 2.74 seconds
Started May 28 02:55:04 PM PDT 24
Finished May 28 02:55:09 PM PDT 24
Peak memory 207016 kb
Host smart-92dad115-391b-4c16-be2f-a10096ea2cc4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196773134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2196773134
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3840250542
Short name T388
Test name
Test status
Simulation time 945225238 ps
CPU time 4.7 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 209716 kb
Host smart-b17ceeed-1a15-42d0-a9d8-f8a0a80a9935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840250542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3840250542
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.351935569
Short name T55
Test name
Test status
Simulation time 279683902 ps
CPU time 3.26 seconds
Started May 28 02:55:41 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 210416 kb
Host smart-8d575eab-0519-4dbd-afee-d0c35d25f2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351935569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.351935569
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1803508837
Short name T351
Test name
Test status
Simulation time 242382647 ps
CPU time 6.42 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 222756 kb
Host smart-f39426ae-3edc-4e83-a51a-67260474eb24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803508837 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1803508837
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1354232139
Short name T405
Test name
Test status
Simulation time 37937734 ps
CPU time 2.1 seconds
Started May 28 02:55:51 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 209868 kb
Host smart-7eeb942f-8846-4527-8ac8-6f70d573b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354232139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1354232139
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2031633635
Short name T401
Test name
Test status
Simulation time 1821397671 ps
CPU time 38.95 seconds
Started May 28 02:55:47 PM PDT 24
Finished May 28 02:56:38 PM PDT 24
Peak memory 218588 kb
Host smart-2e90c615-c824-4063-91c5-c31346bb5060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031633635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2031633635
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4087946489
Short name T248
Test name
Test status
Simulation time 239339190 ps
CPU time 3.76 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 207924 kb
Host smart-fd45a4c9-f68e-4b22-8348-fadf37dbeacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087946489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4087946489
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.487605458
Short name T241
Test name
Test status
Simulation time 596529516 ps
CPU time 7.12 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:14 PM PDT 24
Peak memory 221812 kb
Host smart-3df7c820-a2ce-438b-8582-8ca360e8787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487605458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.487605458
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.676947918
Short name T440
Test name
Test status
Simulation time 122574497 ps
CPU time 7.23 seconds
Started May 28 02:56:01 PM PDT 24
Finished May 28 02:56:18 PM PDT 24
Peak memory 214320 kb
Host smart-de05909c-9eec-4040-a11a-1221873259c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676947918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.676947918
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.491747336
Short name T102
Test name
Test status
Simulation time 189646625 ps
CPU time 8.32 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 221836 kb
Host smart-c9b5e61a-0735-44bc-9f05-3fbd243ec08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491747336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.491747336
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.971173890
Short name T231
Test name
Test status
Simulation time 96349555 ps
CPU time 3.15 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 216080 kb
Host smart-a469bcf4-eb99-4e2e-bb9f-e5835973ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971173890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.971173890
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1259283894
Short name T203
Test name
Test status
Simulation time 3163217227 ps
CPU time 73.55 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:57:32 PM PDT 24
Peak memory 222540 kb
Host smart-78f3f850-208c-4fdd-8c6c-45afcc68a019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259283894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1259283894
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1642523854
Short name T35
Test name
Test status
Simulation time 90290834 ps
CPU time 2.72 seconds
Started May 28 02:56:30 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 222872 kb
Host smart-a58f4835-c314-49b7-a38c-815a5d9daeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642523854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1642523854
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3845691550
Short name T244
Test name
Test status
Simulation time 428364779 ps
CPU time 3.37 seconds
Started May 28 02:56:27 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 216660 kb
Host smart-843023fa-54c2-4364-a3d1-f8acbbc84a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845691550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3845691550
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1201453490
Short name T334
Test name
Test status
Simulation time 1790372263 ps
CPU time 53.46 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:58 PM PDT 24
Peak memory 222484 kb
Host smart-a67552c9-ebc1-4b3e-ab90-2396559c8cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201453490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1201453490
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1929538842
Short name T128
Test name
Test status
Simulation time 337310169 ps
CPU time 12 seconds
Started May 28 02:56:54 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 222680 kb
Host smart-82ec34d2-a312-494c-9ede-ebbd36bfbbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929538842 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1929538842
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1716225463
Short name T156
Test name
Test status
Simulation time 296349565 ps
CPU time 3.56 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 218292 kb
Host smart-9e17845d-03de-4650-a4e5-5b44b9cdce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716225463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1716225463
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.939488126
Short name T1030
Test name
Test status
Simulation time 1856075362 ps
CPU time 5.18 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 205860 kb
Host smart-dcf64855-e1ba-4723-a364-d0fa91465240
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939488126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.939488126
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3695172941
Short name T1048
Test name
Test status
Simulation time 1115519666 ps
CPU time 28.88 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:48 PM PDT 24
Peak memory 205708 kb
Host smart-5d4b8e43-26f6-4487-b7ce-d72df7144646
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695172941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
695172941
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2637675098
Short name T950
Test name
Test status
Simulation time 24075429 ps
CPU time 0.9 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:19 PM PDT 24
Peak memory 205716 kb
Host smart-c45516fe-4421-4e93-ae7a-2f809ebb8302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637675098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
637675098
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2964634023
Short name T1037
Test name
Test status
Simulation time 68067427 ps
CPU time 2.05 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:24 PM PDT 24
Peak memory 214080 kb
Host smart-27beac63-5b0d-4f65-bd8a-e3558ecfca71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964634023 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2964634023
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.36542419
Short name T1035
Test name
Test status
Simulation time 13633268 ps
CPU time 1.06 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:18 PM PDT 24
Peak memory 205828 kb
Host smart-e81cced2-71bd-4977-9c16-fad8245d0d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.36542419
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2729437582
Short name T1058
Test name
Test status
Simulation time 75677313 ps
CPU time 0.82 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:19 PM PDT 24
Peak memory 205456 kb
Host smart-6af9ec60-ccd5-4e3c-a19a-49d19008f744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729437582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2729437582
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.212634219
Short name T1063
Test name
Test status
Simulation time 150432561 ps
CPU time 2.22 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 205904 kb
Host smart-ac1aa960-6e24-4a85-ac15-f3781fd3d2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212634219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.212634219
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1635920558
Short name T1072
Test name
Test status
Simulation time 434122197 ps
CPU time 3.61 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 214360 kb
Host smart-9a0922e1-8180-4583-9714-d883c8c51313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635920558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1635920558
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2148820560
Short name T945
Test name
Test status
Simulation time 195940600 ps
CPU time 6.99 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 220592 kb
Host smart-b23a8d7e-d634-4111-8d6f-46b1a36c6ed1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148820560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2148820560
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1190584322
Short name T1008
Test name
Test status
Simulation time 657901695 ps
CPU time 2.39 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 222252 kb
Host smart-1fcc511d-9685-4a55-9eb9-787f5e192a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190584322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1190584322
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3678900143
Short name T943
Test name
Test status
Simulation time 266442870 ps
CPU time 3.79 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205784 kb
Host smart-07262b52-3084-4939-8798-669663fcf333
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678900143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
678900143
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1100349781
Short name T187
Test name
Test status
Simulation time 1736934371 ps
CPU time 18.8 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 206028 kb
Host smart-b3454d8f-527e-4187-b7d7-2cb2a7ba0a30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100349781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
100349781
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.871415295
Short name T940
Test name
Test status
Simulation time 21805774 ps
CPU time 0.95 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:20 PM PDT 24
Peak memory 205640 kb
Host smart-4f1472b7-3e44-494d-b7b4-4d840f1f68dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871415295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.871415295
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1917382013
Short name T920
Test name
Test status
Simulation time 81343588 ps
CPU time 1.78 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:24 PM PDT 24
Peak memory 214172 kb
Host smart-7b414aae-9f10-4670-a0ec-28cdf79ca59d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917382013 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1917382013
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.249828606
Short name T998
Test name
Test status
Simulation time 114180126 ps
CPU time 1.52 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 205776 kb
Host smart-e53c790e-dabc-4ed4-9f74-45dc86136346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249828606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.249828606
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3178063571
Short name T916
Test name
Test status
Simulation time 47710151 ps
CPU time 0.73 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 205528 kb
Host smart-be8520af-22cf-4128-9157-6a385640b8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178063571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3178063571
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.25034199
Short name T1038
Test name
Test status
Simulation time 49704273 ps
CPU time 1.43 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:20 PM PDT 24
Peak memory 205896 kb
Host smart-5a416bcd-8fe0-42e7-a5af-39b35501e686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same
_csr_outstanding.25034199
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1052739234
Short name T1031
Test name
Test status
Simulation time 220770392 ps
CPU time 3.71 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:24 PM PDT 24
Peak memory 214292 kb
Host smart-108098b9-cd12-4d1f-9177-81dda14558c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052739234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1052739234
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2809292090
Short name T1056
Test name
Test status
Simulation time 897192547 ps
CPU time 11.06 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 220536 kb
Host smart-6c48682c-fce4-4d4b-8793-3a35533896fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809292090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2809292090
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2167382338
Short name T973
Test name
Test status
Simulation time 95909586 ps
CPU time 1.62 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 214084 kb
Host smart-86a2dad6-7b51-4c6c-ae29-af578e5c74d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167382338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2167382338
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1656239330
Short name T182
Test name
Test status
Simulation time 129548415 ps
CPU time 5.32 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 205840 kb
Host smart-b558a850-2881-436b-8f19-505f9594ed73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656239330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1656239330
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.904310843
Short name T932
Test name
Test status
Simulation time 86299980 ps
CPU time 1.55 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:40 PM PDT 24
Peak memory 214084 kb
Host smart-8fa0f224-01cd-4e85-8f06-9c7399aa5dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904310843 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.904310843
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3064620771
Short name T961
Test name
Test status
Simulation time 11754461 ps
CPU time 0.9 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:40 PM PDT 24
Peak memory 205628 kb
Host smart-e2c735d5-7bba-4182-aacc-ee42b9245f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064620771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3064620771
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4064811876
Short name T1032
Test name
Test status
Simulation time 20222113 ps
CPU time 0.76 seconds
Started May 28 01:43:27 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 205584 kb
Host smart-8e5dea26-f767-4eac-b00f-52dac1755bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064811876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4064811876
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4266441660
Short name T941
Test name
Test status
Simulation time 322531034 ps
CPU time 3.64 seconds
Started May 28 01:43:30 PM PDT 24
Finished May 28 01:43:35 PM PDT 24
Peak memory 205748 kb
Host smart-b0b17130-d0db-4e28-b2c5-c22582957cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266441660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4266441660
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3412510636
Short name T936
Test name
Test status
Simulation time 119522167 ps
CPU time 2.19 seconds
Started May 28 01:43:35 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 214372 kb
Host smart-12c18173-d67b-42f5-985d-fdf04bb78f37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412510636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3412510636
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1183287517
Short name T120
Test name
Test status
Simulation time 549316022 ps
CPU time 7.76 seconds
Started May 28 01:43:30 PM PDT 24
Finished May 28 01:43:39 PM PDT 24
Peak memory 214228 kb
Host smart-bf234eff-d7a2-4d30-9571-36ee0c45e3aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183287517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1183287517
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1837252817
Short name T951
Test name
Test status
Simulation time 418652341 ps
CPU time 2.4 seconds
Started May 28 01:43:30 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 214116 kb
Host smart-7e58d076-51e8-4459-b7e1-34daae6203ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837252817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1837252817
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4135520784
Short name T169
Test name
Test status
Simulation time 130058074 ps
CPU time 3.37 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:41 PM PDT 24
Peak memory 214024 kb
Host smart-571b07c0-8ee2-4f6d-9219-4e3ec9a7c344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135520784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.4135520784
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3328789526
Short name T928
Test name
Test status
Simulation time 124743268 ps
CPU time 1.73 seconds
Started May 28 01:43:35 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 214152 kb
Host smart-12c6e0fd-a804-4e40-acf0-5c5b56a7fc89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328789526 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3328789526
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3577741599
Short name T1045
Test name
Test status
Simulation time 65054823 ps
CPU time 1.02 seconds
Started May 28 01:43:39 PM PDT 24
Finished May 28 01:43:42 PM PDT 24
Peak memory 205864 kb
Host smart-34b8591b-217b-43c1-805b-4f9ad47bf4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577741599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3577741599
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2386824092
Short name T968
Test name
Test status
Simulation time 43076538 ps
CPU time 0.73 seconds
Started May 28 01:43:35 PM PDT 24
Finished May 28 01:43:37 PM PDT 24
Peak memory 205568 kb
Host smart-715993e9-30a9-4da7-953a-243ddacaef6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386824092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2386824092
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.419571605
Short name T1042
Test name
Test status
Simulation time 457325513 ps
CPU time 1.96 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:42 PM PDT 24
Peak memory 205852 kb
Host smart-eceaf839-5db0-421d-869a-24e830718f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419571605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.419571605
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.657256245
Short name T1001
Test name
Test status
Simulation time 388223567 ps
CPU time 13.43 seconds
Started May 28 01:43:35 PM PDT 24
Finished May 28 01:43:50 PM PDT 24
Peak memory 214408 kb
Host smart-9078b14c-9251-4240-8c76-767a91e1d49a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657256245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.657256245
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.320514481
Short name T1034
Test name
Test status
Simulation time 73958588 ps
CPU time 1.77 seconds
Started May 28 01:43:29 PM PDT 24
Finished May 28 01:43:32 PM PDT 24
Peak memory 214036 kb
Host smart-7b1e09fe-923c-485e-bce9-cdbe5873c029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320514481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.320514481
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2283802899
Short name T167
Test name
Test status
Simulation time 303968905 ps
CPU time 4.34 seconds
Started May 28 01:43:29 PM PDT 24
Finished May 28 01:43:35 PM PDT 24
Peak memory 213964 kb
Host smart-72f40d7a-ede0-4c2c-9361-11f14b1c771a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283802899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2283802899
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1031705581
Short name T1047
Test name
Test status
Simulation time 310162142 ps
CPU time 1.86 seconds
Started May 28 01:43:39 PM PDT 24
Finished May 28 01:43:43 PM PDT 24
Peak memory 214096 kb
Host smart-9058e81b-1034-4f04-b04b-a7a70ce0885a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031705581 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1031705581
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2681888020
Short name T1065
Test name
Test status
Simulation time 11512938 ps
CPU time 0.99 seconds
Started May 28 01:43:36 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 205864 kb
Host smart-c7e5ca9f-906a-44c6-8638-e0b787b62c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681888020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2681888020
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2537362396
Short name T990
Test name
Test status
Simulation time 10346744 ps
CPU time 0.71 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:39 PM PDT 24
Peak memory 205552 kb
Host smart-8c8ba988-bd7a-4924-a3c0-7a6bb138733c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537362396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2537362396
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3154058834
Short name T143
Test name
Test status
Simulation time 90470466 ps
CPU time 1.77 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:41 PM PDT 24
Peak memory 205848 kb
Host smart-ad3a8371-3042-4e98-8cb6-8c484cd564c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154058834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3154058834
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3254113302
Short name T981
Test name
Test status
Simulation time 396455493 ps
CPU time 2.36 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:43 PM PDT 24
Peak memory 214388 kb
Host smart-b53f7f5e-558b-47ae-ab51-fb36ea955e49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254113302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3254113302
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3754505344
Short name T947
Test name
Test status
Simulation time 261940299 ps
CPU time 3.65 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:44 PM PDT 24
Peak memory 214428 kb
Host smart-69e59869-d0b1-4b6c-8888-b8599f0d9708
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754505344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3754505344
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1828581996
Short name T1027
Test name
Test status
Simulation time 56556031 ps
CPU time 2.03 seconds
Started May 28 01:43:37 PM PDT 24
Finished May 28 01:43:40 PM PDT 24
Peak memory 214032 kb
Host smart-6f96b457-7e3f-4580-a8ee-0f1d905d0763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828581996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1828581996
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1703451843
Short name T1009
Test name
Test status
Simulation time 93573947 ps
CPU time 1.56 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 218392 kb
Host smart-b09dab60-98e5-40cb-bc39-bf0414afe3b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703451843 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1703451843
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1960279006
Short name T992
Test name
Test status
Simulation time 16281672 ps
CPU time 1.23 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 205724 kb
Host smart-f2b485d9-cad4-468d-996a-d7268c885ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960279006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1960279006
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.550741942
Short name T965
Test name
Test status
Simulation time 82215421 ps
CPU time 0.82 seconds
Started May 28 01:43:32 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 205472 kb
Host smart-303fa1ba-9f6c-4616-8cfa-ce9baa6a43e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550741942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.550741942
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.972196813
Short name T1024
Test name
Test status
Simulation time 513894810 ps
CPU time 3.87 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 205856 kb
Host smart-b526fe96-a96d-4187-bcb4-4ef07d788723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972196813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.972196813
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1077517585
Short name T1018
Test name
Test status
Simulation time 301866463 ps
CPU time 2.31 seconds
Started May 28 01:43:36 PM PDT 24
Finished May 28 01:43:39 PM PDT 24
Peak memory 214352 kb
Host smart-63fc5b56-53b1-4e10-80df-09ab23ca65eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077517585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1077517585
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.819448678
Short name T199
Test name
Test status
Simulation time 980121371 ps
CPU time 8.19 seconds
Started May 28 01:43:39 PM PDT 24
Finished May 28 01:43:49 PM PDT 24
Peak memory 214400 kb
Host smart-5dc39194-57dd-4dbc-8be9-2ec9e4beaf1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819448678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.819448678
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3777257950
Short name T1043
Test name
Test status
Simulation time 107989766 ps
CPU time 2.05 seconds
Started May 28 01:43:31 PM PDT 24
Finished May 28 01:43:34 PM PDT 24
Peak memory 213916 kb
Host smart-a2a31d15-d4fd-4215-915d-87ce333ef939
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777257950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3777257950
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.939460329
Short name T1011
Test name
Test status
Simulation time 647587599 ps
CPU time 8.31 seconds
Started May 28 01:43:31 PM PDT 24
Finished May 28 01:43:41 PM PDT 24
Peak memory 205784 kb
Host smart-8eb10fb1-d82a-485b-8cb8-63515ffc92d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939460329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.939460329
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2823875914
Short name T985
Test name
Test status
Simulation time 559983203 ps
CPU time 1.56 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 214108 kb
Host smart-fb5a177a-111a-4ec2-a60f-8b412f7d4a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823875914 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2823875914
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3666971242
Short name T1070
Test name
Test status
Simulation time 16341749 ps
CPU time 1.17 seconds
Started May 28 01:43:59 PM PDT 24
Finished May 28 01:44:01 PM PDT 24
Peak memory 205760 kb
Host smart-468b0673-9108-4d0a-a55d-41a6cd1f1cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666971242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3666971242
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1895417336
Short name T926
Test name
Test status
Simulation time 17787932 ps
CPU time 0.7 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 205584 kb
Host smart-0134c23e-ac51-4652-8497-61a250c8a41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895417336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1895417336
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3359153674
Short name T144
Test name
Test status
Simulation time 83645269 ps
CPU time 2.53 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 205580 kb
Host smart-3bccf497-eab8-483b-9d34-bcdf70522960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359153674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3359153674
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2050566763
Short name T930
Test name
Test status
Simulation time 570976584 ps
CPU time 1.28 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:35 PM PDT 24
Peak memory 214400 kb
Host smart-ed612dbd-2254-43cb-a935-e8bd9e7790b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050566763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2050566763
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3282843212
Short name T146
Test name
Test status
Simulation time 281567239 ps
CPU time 5.07 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 214264 kb
Host smart-91b88943-bea2-4c44-8a7e-bfe0259c2681
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282843212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3282843212
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.420902999
Short name T1002
Test name
Test status
Simulation time 271713123 ps
CPU time 2.24 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:36 PM PDT 24
Peak memory 214036 kb
Host smart-95768e3d-2c94-4319-b6d6-166bea4df931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420902999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.420902999
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2723298444
Short name T934
Test name
Test status
Simulation time 33507017 ps
CPU time 1.15 seconds
Started May 28 01:46:01 PM PDT 24
Finished May 28 01:46:07 PM PDT 24
Peak memory 205896 kb
Host smart-6c09c826-79ad-4641-bdb5-0db82dc99628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723298444 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2723298444
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3038693833
Short name T149
Test name
Test status
Simulation time 55670498 ps
CPU time 1.25 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 205840 kb
Host smart-5d20e884-517e-43b7-babb-feb661c4fbf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038693833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3038693833
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1915846988
Short name T956
Test name
Test status
Simulation time 46780679 ps
CPU time 0.71 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:28 PM PDT 24
Peak memory 205516 kb
Host smart-53f37163-d147-4ecf-80cb-abc1bb62d2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915846988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1915846988
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2575016865
Short name T1014
Test name
Test status
Simulation time 506934869 ps
CPU time 3.44 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 205848 kb
Host smart-a5dec325-5046-42de-98bf-d500d1de4873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575016865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2575016865
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.9251573
Short name T974
Test name
Test status
Simulation time 46131362 ps
CPU time 1.53 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:39 PM PDT 24
Peak memory 214384 kb
Host smart-a49c883d-8733-44e7-b6b2-bcd32e289bd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9251573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_
reg_errors.9251573
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2592279195
Short name T1057
Test name
Test status
Simulation time 936399214 ps
CPU time 5.88 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:46:19 PM PDT 24
Peak memory 214380 kb
Host smart-08120410-fc34-4a24-bfc7-fd1712d5acc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592279195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2592279195
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.60270428
Short name T929
Test name
Test status
Simulation time 191426731 ps
CPU time 3.2 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 214108 kb
Host smart-f084ba36-b1d4-4c01-98e7-1a10eeef6222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60270428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.60270428
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4215763227
Short name T173
Test name
Test status
Simulation time 417169755 ps
CPU time 4.33 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 214040 kb
Host smart-162ca9e2-5087-4e2c-a4f9-563c7d7947dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215763227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4215763227
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2096427710
Short name T1066
Test name
Test status
Simulation time 84797958 ps
CPU time 1.43 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 214020 kb
Host smart-7b11cf1f-6309-4a25-a7bb-4617ac27addb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096427710 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2096427710
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4033800563
Short name T190
Test name
Test status
Simulation time 124595214 ps
CPU time 1.17 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 205884 kb
Host smart-374ff8d0-50b0-47aa-8e12-3b0933be6b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033800563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4033800563
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.278800953
Short name T937
Test name
Test status
Simulation time 11108836 ps
CPU time 0.73 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 205512 kb
Host smart-d9e7432b-580e-4948-8d78-4322b10ee5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278800953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.278800953
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.119472187
Short name T1061
Test name
Test status
Simulation time 388860421 ps
CPU time 1.86 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:31 PM PDT 24
Peak memory 205868 kb
Host smart-82d67e75-3f0d-4d00-9832-caf9cca0b8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119472187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.119472187
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3393825577
Short name T984
Test name
Test status
Simulation time 160274561 ps
CPU time 1.51 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 214420 kb
Host smart-c39f2351-ada1-43d5-8adb-364969e3d642
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393825577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3393825577
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.210105822
Short name T949
Test name
Test status
Simulation time 190968607 ps
CPU time 3.22 seconds
Started May 28 01:46:01 PM PDT 24
Finished May 28 01:46:08 PM PDT 24
Peak memory 216728 kb
Host smart-02d97561-945c-4726-9053-319780775b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210105822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.210105822
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3205862208
Short name T922
Test name
Test status
Simulation time 134865102 ps
CPU time 2.88 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 214148 kb
Host smart-fbe00fa5-c377-46f1-9605-b98667219903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205862208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3205862208
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.360296784
Short name T1004
Test name
Test status
Simulation time 29982783 ps
CPU time 1.46 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:54 PM PDT 24
Peak memory 213964 kb
Host smart-4b8c21b4-a0ad-46ab-af02-49d5ef8dace1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360296784 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.360296784
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2341313056
Short name T1050
Test name
Test status
Simulation time 49513853 ps
CPU time 1.1 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205704 kb
Host smart-0b189a10-6016-4d1c-88a0-0b9f834f80bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341313056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2341313056
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.355588964
Short name T959
Test name
Test status
Simulation time 31832696 ps
CPU time 0.83 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205468 kb
Host smart-c36edc88-5a00-4fa9-b3c2-9fae86ba45ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355588964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.355588964
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3152112402
Short name T147
Test name
Test status
Simulation time 92886255 ps
CPU time 3.67 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:44:02 PM PDT 24
Peak memory 205848 kb
Host smart-45e5c769-49d2-4417-a75a-edc5a17b739b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152112402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3152112402
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2800903320
Short name T942
Test name
Test status
Simulation time 154433538 ps
CPU time 1.82 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 214412 kb
Host smart-73779159-9237-45e7-a995-f8f8119f8ed1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800903320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2800903320
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.148872770
Short name T1076
Test name
Test status
Simulation time 585770575 ps
CPU time 7.96 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:36 PM PDT 24
Peak memory 214328 kb
Host smart-21aec5b4-0cf8-4b8b-9553-b8eee4fe147e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148872770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.148872770
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.913145543
Short name T1015
Test name
Test status
Simulation time 187588419 ps
CPU time 2.82 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 214000 kb
Host smart-31e38143-b9a7-44bc-ac99-fe82b7b1b5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913145543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.913145543
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.681909728
Short name T1017
Test name
Test status
Simulation time 1889016385 ps
CPU time 10 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:44:05 PM PDT 24
Peak memory 215368 kb
Host smart-dfe35657-3c07-4d17-ad32-0a130088f6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681909728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.681909728
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1222554697
Short name T989
Test name
Test status
Simulation time 660702092 ps
CPU time 2.62 seconds
Started May 28 01:43:50 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 214000 kb
Host smart-54aaa36d-5ad6-4bf8-93c6-e709cbe22150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222554697 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1222554697
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2618018330
Short name T946
Test name
Test status
Simulation time 11518091 ps
CPU time 1 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205788 kb
Host smart-9eba845f-5d2c-4410-bf0b-6ec95380cc91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618018330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2618018330
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2442242580
Short name T1025
Test name
Test status
Simulation time 8469821 ps
CPU time 0.73 seconds
Started May 28 01:43:55 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 205592 kb
Host smart-e88841d9-9d1c-47f3-a938-b3239e5cdc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442242580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2442242580
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2543762984
Short name T977
Test name
Test status
Simulation time 33380588 ps
CPU time 2.37 seconds
Started May 28 01:43:57 PM PDT 24
Finished May 28 01:44:01 PM PDT 24
Peak memory 205872 kb
Host smart-c1e1434c-dc78-44e3-ae43-c8c4f0fd307e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543762984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2543762984
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.757703048
Short name T1007
Test name
Test status
Simulation time 706968488 ps
CPU time 1.88 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 214484 kb
Host smart-dcb39f0c-7293-4910-aee6-53280a4d0202
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757703048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.757703048
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1396805792
Short name T1026
Test name
Test status
Simulation time 169760934 ps
CPU time 4.58 seconds
Started May 28 01:43:50 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 220512 kb
Host smart-d711398d-d758-4d51-a12d-7e11cf9e2f33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396805792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1396805792
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3011661506
Short name T979
Test name
Test status
Simulation time 65508511 ps
CPU time 2.14 seconds
Started May 28 01:43:50 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 214060 kb
Host smart-80a8879a-e7da-4b4b-b4f1-e1fbb2d8d18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011661506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3011661506
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3409150802
Short name T957
Test name
Test status
Simulation time 52938153 ps
CPU time 2.68 seconds
Started May 28 01:43:58 PM PDT 24
Finished May 28 01:44:02 PM PDT 24
Peak memory 205828 kb
Host smart-e27be76e-589c-4aa6-ab1e-2066c45251f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409150802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3409150802
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3531840342
Short name T409
Test name
Test status
Simulation time 115424050 ps
CPU time 2.12 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 214156 kb
Host smart-620e7185-1a35-4f84-8499-d20f4cf8e3eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531840342 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3531840342
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.149398314
Short name T948
Test name
Test status
Simulation time 297643620 ps
CPU time 1.25 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205900 kb
Host smart-d8c9987a-dff0-4902-952d-591313a3e6cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149398314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.149398314
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1171184495
Short name T1068
Test name
Test status
Simulation time 49864963 ps
CPU time 0.71 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205536 kb
Host smart-36a96835-2560-40ba-a003-e5dfae6594c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171184495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1171184495
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3209867478
Short name T1023
Test name
Test status
Simulation time 204075758 ps
CPU time 1.89 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:54 PM PDT 24
Peak memory 205824 kb
Host smart-3527e1ab-7fbf-4e44-a868-a37d0216b277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209867478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3209867478
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.306618454
Short name T123
Test name
Test status
Simulation time 193653000 ps
CPU time 2.79 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 214404 kb
Host smart-90ced395-4fc6-43b4-8eb6-769cd8959002
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306618454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.306618454
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2479088125
Short name T1074
Test name
Test status
Simulation time 542352010 ps
CPU time 16.3 seconds
Started May 28 01:43:57 PM PDT 24
Finished May 28 01:44:15 PM PDT 24
Peak memory 214408 kb
Host smart-c7176971-f1fc-4405-8939-8998bc817407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479088125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2479088125
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.904682177
Short name T960
Test name
Test status
Simulation time 477895814 ps
CPU time 2.55 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:57 PM PDT 24
Peak memory 214036 kb
Host smart-fb489238-780d-4a1c-bb82-1223f5c9bf40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904682177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.904682177
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.29668960
Short name T972
Test name
Test status
Simulation time 204124247 ps
CPU time 3.22 seconds
Started May 28 01:43:57 PM PDT 24
Finished May 28 01:44:02 PM PDT 24
Peak memory 213916 kb
Host smart-b786038c-a8c7-493f-ae87-fc6870cfde14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.29668960
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2682585509
Short name T1013
Test name
Test status
Simulation time 133923678 ps
CPU time 7.1 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 205664 kb
Host smart-0296b505-f5fa-46d5-837f-3dd013c88108
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682585509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
682585509
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1779550020
Short name T1022
Test name
Test status
Simulation time 255578680 ps
CPU time 11.33 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:35 PM PDT 24
Peak memory 205664 kb
Host smart-216dd72d-0b73-4f3c-9630-e5cf8cde9336
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779550020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
779550020
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.816942650
Short name T991
Test name
Test status
Simulation time 80980686 ps
CPU time 1.39 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 205784 kb
Host smart-8f72fc69-12aa-4df9-8f59-f920a48e3213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816942650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.816942650
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3129297864
Short name T999
Test name
Test status
Simulation time 279823738 ps
CPU time 1.64 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 214036 kb
Host smart-4f7c2f46-0f60-424d-b612-c372a3095593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129297864 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3129297864
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3035472792
Short name T988
Test name
Test status
Simulation time 107312228 ps
CPU time 1.56 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 205828 kb
Host smart-5c394a50-3239-405a-b7c5-5e110398d38b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035472792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3035472792
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3391892007
Short name T1000
Test name
Test status
Simulation time 54268262 ps
CPU time 0.76 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 205588 kb
Host smart-faa6d9ce-e5bf-4910-9e12-a8dce5211a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391892007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3391892007
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1910435667
Short name T983
Test name
Test status
Simulation time 165078535 ps
CPU time 2.14 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 205780 kb
Host smart-52f3e071-9bfc-47d7-898e-858d726a0f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910435667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1910435667
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4054016783
Short name T994
Test name
Test status
Simulation time 534658435 ps
CPU time 2.98 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 214464 kb
Host smart-ac75f087-8e06-4727-aa3d-2d02d68d850a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054016783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4054016783
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3619771930
Short name T982
Test name
Test status
Simulation time 205178668 ps
CPU time 7.1 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 214456 kb
Host smart-a86776a8-a690-4d19-bbdb-57ccd4cb4cee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619771930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3619771930
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2040885735
Short name T924
Test name
Test status
Simulation time 25007154 ps
CPU time 1.59 seconds
Started May 28 01:43:16 PM PDT 24
Finished May 28 01:43:19 PM PDT 24
Peak memory 214120 kb
Host smart-331cf8ed-ecc6-484e-8992-16317625a9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040885735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2040885735
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2835213716
Short name T1062
Test name
Test status
Simulation time 78681884 ps
CPU time 2.5 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 214036 kb
Host smart-15b5ca2e-45f8-496c-bfa3-7b328f9a9583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835213716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2835213716
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.188535268
Short name T1029
Test name
Test status
Simulation time 91179576 ps
CPU time 0.76 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 205532 kb
Host smart-2d5f8792-5e4c-44d6-9d90-d3cfff42fc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188535268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.188535268
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.90252810
Short name T970
Test name
Test status
Simulation time 13155387 ps
CPU time 0.74 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205584 kb
Host smart-fdfd47d9-ecc6-4362-b523-f93899e39a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90252810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.90252810
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2025161817
Short name T1059
Test name
Test status
Simulation time 18801271 ps
CPU time 0.7 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 205532 kb
Host smart-46ff7b27-ad27-4caa-b80f-4f84bb357a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025161817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2025161817
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4191083403
Short name T1073
Test name
Test status
Simulation time 16441662 ps
CPU time 0.9 seconds
Started May 28 01:43:55 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 205704 kb
Host smart-1d9339fc-4283-4794-b27e-21afc578c4a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191083403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4191083403
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2904579034
Short name T1028
Test name
Test status
Simulation time 20426654 ps
CPU time 0.79 seconds
Started May 28 01:43:57 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205524 kb
Host smart-3431dedf-3748-493a-800c-144751c6e9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904579034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2904579034
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1042645983
Short name T1040
Test name
Test status
Simulation time 39417531 ps
CPU time 0.83 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 205588 kb
Host smart-72de75a7-e0d7-49c3-9459-97ee45162475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042645983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1042645983
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2315693213
Short name T939
Test name
Test status
Simulation time 11323295 ps
CPU time 0.73 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:54 PM PDT 24
Peak memory 205584 kb
Host smart-03bd766a-cf09-47e1-97e9-eb318c451387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315693213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2315693213
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1503302025
Short name T938
Test name
Test status
Simulation time 146689848 ps
CPU time 0.73 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:54 PM PDT 24
Peak memory 205456 kb
Host smart-ab26a4ff-cd7b-4702-9454-754f1025f657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503302025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1503302025
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1602796648
Short name T933
Test name
Test status
Simulation time 18417477 ps
CPU time 0.83 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 205528 kb
Host smart-2351061b-ab4c-4c79-8f16-74a268b7cfca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602796648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1602796648
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.291446608
Short name T954
Test name
Test status
Simulation time 12722818 ps
CPU time 0.72 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205468 kb
Host smart-94b1e73f-c9c6-4a7f-ae8b-872d64011f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291446608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.291446608
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3500576463
Short name T1019
Test name
Test status
Simulation time 131891757 ps
CPU time 4.79 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 205804 kb
Host smart-266e1bcb-7e60-4a9a-85ab-4c8988312c2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500576463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
500576463
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4228409252
Short name T980
Test name
Test status
Simulation time 446426519 ps
CPU time 12.7 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:36 PM PDT 24
Peak memory 205704 kb
Host smart-710b1915-89c4-4fba-8d47-9a5763b986f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228409252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4
228409252
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2512710160
Short name T997
Test name
Test status
Simulation time 58102982 ps
CPU time 0.87 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 205508 kb
Host smart-6db17487-9111-42dd-9e17-def545ce968f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512710160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
512710160
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2303115875
Short name T1010
Test name
Test status
Simulation time 155808225 ps
CPU time 1.24 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 214080 kb
Host smart-5af066a9-d035-4fde-b67c-aab8dd36309d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303115875 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2303115875
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2116251828
Short name T1054
Test name
Test status
Simulation time 47257077 ps
CPU time 1.43 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 205788 kb
Host smart-eae8c1b3-ddda-40c5-9f2a-7487fb3ea3ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116251828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2116251828
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1794729373
Short name T1005
Test name
Test status
Simulation time 11739274 ps
CPU time 0.7 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 205620 kb
Host smart-577c5c48-213e-4d59-b173-af23e4faafd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794729373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1794729373
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1671166113
Short name T1052
Test name
Test status
Simulation time 24465459 ps
CPU time 1.6 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 205876 kb
Host smart-13f0cb5c-53c5-4861-afc8-7b2737f143e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671166113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1671166113
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3654592649
Short name T1064
Test name
Test status
Simulation time 66000109 ps
CPU time 1.76 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:21 PM PDT 24
Peak memory 214320 kb
Host smart-a3ba405b-2ec8-4570-aba0-ed2810202cc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654592649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3654592649
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2267134553
Short name T964
Test name
Test status
Simulation time 317690318 ps
CPU time 4.2 seconds
Started May 28 01:43:17 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 220064 kb
Host smart-e9fe2a4e-35d5-4368-9502-d5da590ee93e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267134553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2267134553
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4269721352
Short name T1071
Test name
Test status
Simulation time 65289234 ps
CPU time 3.86 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 213964 kb
Host smart-f4f56294-03f1-41a8-87ac-c63ac16d73c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269721352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4269721352
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1060969587
Short name T975
Test name
Test status
Simulation time 50442277 ps
CPU time 0.88 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205540 kb
Host smart-222379bb-a240-46e1-8dd4-416a7e97a5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060969587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1060969587
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4207277271
Short name T1049
Test name
Test status
Simulation time 35355861 ps
CPU time 0.9 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205584 kb
Host smart-bacd78b2-02b3-4ffc-b341-8f8f07f973f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207277271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4207277271
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1004807190
Short name T987
Test name
Test status
Simulation time 12875493 ps
CPU time 0.75 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205524 kb
Host smart-f6b5e6ce-75c5-486d-a2aa-1e038fcc8b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004807190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1004807190
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1782336610
Short name T1055
Test name
Test status
Simulation time 9476012 ps
CPU time 0.69 seconds
Started May 28 01:43:50 PM PDT 24
Finished May 28 01:43:51 PM PDT 24
Peak memory 205452 kb
Host smart-9fbe526d-53e8-4c5f-b66b-5fb35f80357c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782336610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1782336610
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.650767462
Short name T923
Test name
Test status
Simulation time 12097237 ps
CPU time 0.73 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 205596 kb
Host smart-053058a7-b865-4822-8bd2-57c0c3ca5545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650767462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.650767462
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1122641585
Short name T925
Test name
Test status
Simulation time 43228140 ps
CPU time 0.71 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:55 PM PDT 24
Peak memory 205492 kb
Host smart-c828dfcb-3e75-4328-87be-5743402df162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122641585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1122641585
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3090422444
Short name T918
Test name
Test status
Simulation time 39586920 ps
CPU time 0.76 seconds
Started May 28 01:43:52 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205524 kb
Host smart-116d291a-1b86-41ed-ae3e-5a20dc74c895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090422444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3090422444
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.192772688
Short name T995
Test name
Test status
Simulation time 10502829 ps
CPU time 0.75 seconds
Started May 28 01:43:57 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205512 kb
Host smart-f5aa4b5c-ee4f-4f99-8af2-8a0e8a718afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192772688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.192772688
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2872395211
Short name T1046
Test name
Test status
Simulation time 16565056 ps
CPU time 0.82 seconds
Started May 28 01:43:51 PM PDT 24
Finished May 28 01:43:54 PM PDT 24
Peak memory 205532 kb
Host smart-19c0512e-4b95-4714-bdf6-a1293b98de91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872395211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2872395211
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3402227498
Short name T986
Test name
Test status
Simulation time 33380305 ps
CPU time 0.81 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:43:57 PM PDT 24
Peak memory 205548 kb
Host smart-2df0a28b-b53d-4ce2-9d26-7586e35d9ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402227498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3402227498
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2000222207
Short name T931
Test name
Test status
Simulation time 196490663 ps
CPU time 5.64 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:31 PM PDT 24
Peak memory 205784 kb
Host smart-04d4d111-ae38-45a8-b6b7-2f4ecb9d1c94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000222207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
000222207
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1195428332
Short name T1051
Test name
Test status
Simulation time 1309729940 ps
CPU time 20.09 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:45 PM PDT 24
Peak memory 205840 kb
Host smart-11bb6163-bbbe-4928-bd68-0dada3d492f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195428332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
195428332
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2481761658
Short name T188
Test name
Test status
Simulation time 34453609 ps
CPU time 1.45 seconds
Started May 28 01:43:19 PM PDT 24
Finished May 28 01:43:22 PM PDT 24
Peak memory 205912 kb
Host smart-9229cf2b-18d3-476c-a187-358ddc8d0174
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481761658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
481761658
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3300814364
Short name T1021
Test name
Test status
Simulation time 311737500 ps
CPU time 1.29 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205680 kb
Host smart-bb66b1d7-a428-4423-abae-2794175121ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300814364 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3300814364
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.257735560
Short name T214
Test name
Test status
Simulation time 50596587 ps
CPU time 1.26 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205464 kb
Host smart-cf26ed89-c0bd-4234-99fe-5f41baa2b5f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257735560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.257735560
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.135907765
Short name T921
Test name
Test status
Simulation time 10616272 ps
CPU time 0.87 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 205400 kb
Host smart-73aa3560-6d6a-4fc3-aba9-998bbda3eca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135907765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.135907765
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.27225232
Short name T1036
Test name
Test status
Simulation time 49106851 ps
CPU time 2.19 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205704 kb
Host smart-8dbabf79-67d9-4ebf-ae0d-f5c8ad165045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same
_csr_outstanding.27225232
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1302806881
Short name T189
Test name
Test status
Simulation time 121999825 ps
CPU time 3.6 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:25 PM PDT 24
Peak memory 214424 kb
Host smart-75fa0cb2-e606-45b3-b2f6-cf7880bd2a66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302806881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1302806881
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3929494039
Short name T1033
Test name
Test status
Simulation time 436257414 ps
CPU time 6.15 seconds
Started May 28 01:43:20 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 214480 kb
Host smart-cf3ca36a-948e-4f4e-bf9f-946520bfee28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929494039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3929494039
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.961907896
Short name T952
Test name
Test status
Simulation time 556986958 ps
CPU time 3.52 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:23 PM PDT 24
Peak memory 214096 kb
Host smart-b632945a-ff83-4219-8b06-46604cc0cfd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961907896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.961907896
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2433103426
Short name T161
Test name
Test status
Simulation time 186713708 ps
CPU time 4.63 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 213928 kb
Host smart-0c6def77-c546-4ac7-8cff-de36d49a9e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433103426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2433103426
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2067575223
Short name T1039
Test name
Test status
Simulation time 33008719 ps
CPU time 0.72 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205536 kb
Host smart-c2724655-3f01-4f63-994f-aae4a98f88ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067575223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2067575223
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.559828390
Short name T1067
Test name
Test status
Simulation time 33523058 ps
CPU time 0.78 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:43:57 PM PDT 24
Peak memory 205604 kb
Host smart-a0fce3a5-13f7-42fb-a5ff-7efa951e2a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559828390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.559828390
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4153764017
Short name T969
Test name
Test status
Simulation time 11022231 ps
CPU time 0.7 seconds
Started May 28 01:43:55 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205460 kb
Host smart-c16762d5-7573-4971-93a4-351e26458eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153764017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4153764017
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2110538123
Short name T978
Test name
Test status
Simulation time 15495374 ps
CPU time 0.74 seconds
Started May 28 01:43:58 PM PDT 24
Finished May 28 01:44:00 PM PDT 24
Peak memory 205500 kb
Host smart-c7258cf8-fcb7-4671-8f51-d5dec4d3c5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110538123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2110538123
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.811094138
Short name T953
Test name
Test status
Simulation time 10508904 ps
CPU time 0.82 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205512 kb
Host smart-3b0ad4ef-6d19-4ae6-8612-cccad807efee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811094138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.811094138
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2036510742
Short name T967
Test name
Test status
Simulation time 61077515 ps
CPU time 0.76 seconds
Started May 28 01:43:56 PM PDT 24
Finished May 28 01:43:59 PM PDT 24
Peak memory 205472 kb
Host smart-f02e8b4c-0e7c-4772-864e-dc3261a5d849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036510742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2036510742
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2107995063
Short name T1060
Test name
Test status
Simulation time 39452149 ps
CPU time 0.74 seconds
Started May 28 01:43:55 PM PDT 24
Finished May 28 01:43:58 PM PDT 24
Peak memory 205536 kb
Host smart-a151b1fb-78ee-4b45-ad7c-aa8f97b00b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107995063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2107995063
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3162285668
Short name T927
Test name
Test status
Simulation time 14607989 ps
CPU time 0.73 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:43:57 PM PDT 24
Peak memory 205468 kb
Host smart-4e41429d-027f-4494-a489-7742c892e526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162285668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3162285668
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.860005616
Short name T914
Test name
Test status
Simulation time 20018136 ps
CPU time 0.73 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205456 kb
Host smart-19462924-7dc2-47c7-8206-65247f30126e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860005616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.860005616
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2666895473
Short name T1041
Test name
Test status
Simulation time 10325113 ps
CPU time 0.76 seconds
Started May 28 01:43:53 PM PDT 24
Finished May 28 01:43:56 PM PDT 24
Peak memory 205520 kb
Host smart-56c616a5-7a90-4ff6-9fa0-5631c8854b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666895473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2666895473
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4271233708
Short name T165
Test name
Test status
Simulation time 19512732 ps
CPU time 1.51 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 214120 kb
Host smart-47d005b4-3729-4cb6-8976-f86361ca9061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271233708 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4271233708
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.382443863
Short name T944
Test name
Test status
Simulation time 100937410 ps
CPU time 1.08 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205888 kb
Host smart-257735b7-1bf0-4c22-bd8e-e3c77d94f9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382443863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.382443863
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1967527405
Short name T919
Test name
Test status
Simulation time 172981675 ps
CPU time 0.9 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 205476 kb
Host smart-dff519f5-59ba-42de-8716-fee1f64db564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967527405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1967527405
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4185196811
Short name T971
Test name
Test status
Simulation time 129828125 ps
CPU time 4.26 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 205872 kb
Host smart-072c3c92-5cf7-41d2-b948-a1953942cf83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185196811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4185196811
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2112920286
Short name T955
Test name
Test status
Simulation time 71569545 ps
CPU time 2.35 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 214312 kb
Host smart-5c4a0456-595b-442e-8b3e-01f8e9ede3e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112920286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2112920286
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3480102806
Short name T1016
Test name
Test status
Simulation time 565513487 ps
CPU time 7.47 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:32 PM PDT 24
Peak memory 214264 kb
Host smart-8728fb24-d57a-4219-8f35-51a3fcb7cb48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480102806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3480102806
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3710005161
Short name T197
Test name
Test status
Simulation time 60304012 ps
CPU time 2.4 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 216036 kb
Host smart-f62d5e1e-695f-47e0-a05f-c74e467c4863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710005161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3710005161
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1683472261
Short name T170
Test name
Test status
Simulation time 148311972 ps
CPU time 4.47 seconds
Started May 28 01:43:24 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 214036 kb
Host smart-73506774-831c-4756-86e3-364099caa971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683472261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1683472261
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.140533624
Short name T917
Test name
Test status
Simulation time 29073170 ps
CPU time 1.48 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 214048 kb
Host smart-29773337-f2d7-418e-ae65-6d9381b27e1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140533624 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.140533624
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2854407558
Short name T1069
Test name
Test status
Simulation time 91699944 ps
CPU time 1.27 seconds
Started May 28 01:43:23 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205784 kb
Host smart-d69a6e3e-d82e-4087-aad8-a9744977966e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854407558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2854407558
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3713465104
Short name T996
Test name
Test status
Simulation time 8841586 ps
CPU time 0.8 seconds
Started May 28 01:43:18 PM PDT 24
Finished May 28 01:43:21 PM PDT 24
Peak memory 205496 kb
Host smart-b2a636b6-ac96-44c6-84b4-c1eff2424a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713465104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3713465104
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2771305734
Short name T1003
Test name
Test status
Simulation time 234686027 ps
CPU time 2.5 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 205808 kb
Host smart-eb9bb18c-beeb-4f7a-9110-1f4ba5b21cd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771305734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2771305734
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.614753463
Short name T1006
Test name
Test status
Simulation time 55952218 ps
CPU time 1.85 seconds
Started May 28 01:43:21 PM PDT 24
Finished May 28 01:43:26 PM PDT 24
Peak memory 214332 kb
Host smart-5eb8d29d-315a-4c96-a836-60efb9162842
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614753463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.614753463
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2430710932
Short name T963
Test name
Test status
Simulation time 187660199 ps
CPU time 4.93 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 220068 kb
Host smart-b9ab386b-2eb4-4f9a-8dde-96fa76ba3354
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430710932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2430710932
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.688518840
Short name T1020
Test name
Test status
Simulation time 158670201 ps
CPU time 3.3 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 213936 kb
Host smart-258f11c9-4216-4009-a1b5-777cf9e4a995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688518840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.688518840
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.884496394
Short name T1044
Test name
Test status
Simulation time 212043033 ps
CPU time 2.15 seconds
Started May 28 01:43:29 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 214092 kb
Host smart-65ee4ca9-8a0f-4a02-ac97-014efa12bc9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884496394 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.884496394
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4181351537
Short name T200
Test name
Test status
Simulation time 68858858 ps
CPU time 0.95 seconds
Started May 28 01:43:34 PM PDT 24
Finished May 28 01:43:36 PM PDT 24
Peak memory 205720 kb
Host smart-7a6cb91a-bff6-4fdc-b651-605d0d47d392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181351537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4181351537
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2870271890
Short name T993
Test name
Test status
Simulation time 35370620 ps
CPU time 0.73 seconds
Started May 28 01:43:27 PM PDT 24
Finished May 28 01:43:28 PM PDT 24
Peak memory 205512 kb
Host smart-1afe278c-5a6b-4fbc-9327-60b6beda1dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870271890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2870271890
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1834090505
Short name T148
Test name
Test status
Simulation time 164104279 ps
CPU time 2.53 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:42 PM PDT 24
Peak memory 205864 kb
Host smart-4d83dbde-0cec-4137-91b3-64d1b9d2cbf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834090505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1834090505
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4288168466
Short name T976
Test name
Test status
Simulation time 45361341 ps
CPU time 1.51 seconds
Started May 28 01:43:22 PM PDT 24
Finished May 28 01:43:27 PM PDT 24
Peak memory 214416 kb
Host smart-ed451115-e493-4209-b5f5-d2143f314fba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288168466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4288168466
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3329457952
Short name T1075
Test name
Test status
Simulation time 336385659 ps
CPU time 4.86 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:45 PM PDT 24
Peak memory 222600 kb
Host smart-9582b1ad-3709-493e-a399-a7e7273fde71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329457952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3329457952
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1032311202
Short name T1053
Test name
Test status
Simulation time 226675560 ps
CPU time 4.35 seconds
Started May 28 01:43:27 PM PDT 24
Finished May 28 01:43:32 PM PDT 24
Peak memory 215032 kb
Host smart-6af49fbc-1f68-44da-9bd7-25fabf4657d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032311202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1032311202
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.10486103
Short name T958
Test name
Test status
Simulation time 118884850 ps
CPU time 1.24 seconds
Started May 28 01:43:35 PM PDT 24
Finished May 28 01:43:37 PM PDT 24
Peak memory 214104 kb
Host smart-9c32b842-29df-402e-82de-bcb59f938c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486103 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.10486103
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1302104409
Short name T198
Test name
Test status
Simulation time 27690273 ps
CPU time 1.03 seconds
Started May 28 01:43:28 PM PDT 24
Finished May 28 01:43:30 PM PDT 24
Peak memory 205840 kb
Host smart-d93f96f9-e6ff-48e7-b673-3e42ff028457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302104409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1302104409
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1655999555
Short name T962
Test name
Test status
Simulation time 14469413 ps
CPU time 0.87 seconds
Started May 28 01:43:34 PM PDT 24
Finished May 28 01:43:36 PM PDT 24
Peak memory 205588 kb
Host smart-3a14a016-c10f-4277-900f-003f13aaa530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655999555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1655999555
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3510059032
Short name T145
Test name
Test status
Simulation time 101648897 ps
CPU time 1.55 seconds
Started May 28 01:43:36 PM PDT 24
Finished May 28 01:43:39 PM PDT 24
Peak memory 205816 kb
Host smart-483d9419-508c-48ca-b57f-1e25dad8d880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510059032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3510059032
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.710355924
Short name T124
Test name
Test status
Simulation time 381818512 ps
CPU time 3.8 seconds
Started May 28 01:43:28 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 214416 kb
Host smart-ea2242a0-b063-4b57-a445-20b534a5d799
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710355924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.710355924
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.174376082
Short name T1077
Test name
Test status
Simulation time 236946485 ps
CPU time 7.39 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:48 PM PDT 24
Peak memory 214264 kb
Host smart-5acb72e6-3e8b-4465-b542-50c6ea89fa02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174376082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.174376082
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2712661287
Short name T186
Test name
Test status
Simulation time 57306840 ps
CPU time 1.66 seconds
Started May 28 01:43:30 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 215084 kb
Host smart-f513fb06-7728-4523-88ef-61842d25dba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712661287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2712661287
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2606580538
Short name T408
Test name
Test status
Simulation time 53265306 ps
CPU time 1.61 seconds
Started May 28 01:43:31 PM PDT 24
Finished May 28 01:43:34 PM PDT 24
Peak memory 214180 kb
Host smart-540ea67c-0804-4121-bc06-2e0774f7fd74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606580538 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2606580538
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.708492473
Short name T966
Test name
Test status
Simulation time 15414846 ps
CPU time 0.96 seconds
Started May 28 01:43:27 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 205792 kb
Host smart-c42f0b0c-5836-4509-ad73-5efe89d90335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708492473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.708492473
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3741577809
Short name T915
Test name
Test status
Simulation time 14156334 ps
CPU time 0.77 seconds
Started May 28 01:43:34 PM PDT 24
Finished May 28 01:43:35 PM PDT 24
Peak memory 205512 kb
Host smart-bd3b2c48-747d-4724-955d-c95d008e4358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741577809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3741577809
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3367506708
Short name T935
Test name
Test status
Simulation time 149961915 ps
CPU time 2.22 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:42 PM PDT 24
Peak memory 205692 kb
Host smart-b327cad0-a510-4f03-a8a4-400e6bd53f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367506708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3367506708
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2767456935
Short name T125
Test name
Test status
Simulation time 521637607 ps
CPU time 3.23 seconds
Started May 28 01:43:28 PM PDT 24
Finished May 28 01:43:33 PM PDT 24
Peak memory 214464 kb
Host smart-dd424ee6-bfd2-4b90-a408-343c987a133f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767456935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2767456935
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.402329709
Short name T121
Test name
Test status
Simulation time 646444923 ps
CPU time 12.92 seconds
Started May 28 01:43:38 PM PDT 24
Finished May 28 01:43:53 PM PDT 24
Peak memory 214288 kb
Host smart-5af7c30a-38a8-4684-a2c1-2098505e1d1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402329709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.402329709
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1224464933
Short name T1012
Test name
Test status
Simulation time 199516117 ps
CPU time 3.76 seconds
Started May 28 01:43:34 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 214064 kb
Host smart-1ea6c7c3-3fd3-4393-9396-8a23ea1caf5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224464933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1224464933
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.326961558
Short name T181
Test name
Test status
Simulation time 565137945 ps
CPU time 3.66 seconds
Started May 28 01:43:34 PM PDT 24
Finished May 28 01:43:38 PM PDT 24
Peak memory 214036 kb
Host smart-735626ab-d263-4634-8384-231684e79a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326961558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
326961558
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2611148654
Short name T741
Test name
Test status
Simulation time 15528324 ps
CPU time 0.82 seconds
Started May 28 02:55:06 PM PDT 24
Finished May 28 02:55:13 PM PDT 24
Peak memory 206004 kb
Host smart-0d3936a2-3fdf-4f34-b24d-b72e6bec93ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611148654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2611148654
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2580596570
Short name T442
Test name
Test status
Simulation time 88454806 ps
CPU time 3.46 seconds
Started May 28 02:55:10 PM PDT 24
Finished May 28 02:55:21 PM PDT 24
Peak memory 214384 kb
Host smart-145929bb-8901-4424-8808-62522afad031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580596570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2580596570
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.550353906
Short name T647
Test name
Test status
Simulation time 419219285 ps
CPU time 3.44 seconds
Started May 28 02:55:07 PM PDT 24
Finished May 28 02:55:18 PM PDT 24
Peak memory 210220 kb
Host smart-0f13ef15-771f-46a0-bf68-6c137085cd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550353906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.550353906
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1863046012
Short name T666
Test name
Test status
Simulation time 41477866 ps
CPU time 2.81 seconds
Started May 28 02:55:07 PM PDT 24
Finished May 28 02:55:18 PM PDT 24
Peak memory 209256 kb
Host smart-f185d464-4d27-4c4c-9fa1-a76d2bc8c8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863046012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1863046012
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2523926603
Short name T344
Test name
Test status
Simulation time 37082979 ps
CPU time 2.57 seconds
Started May 28 02:55:05 PM PDT 24
Finished May 28 02:55:14 PM PDT 24
Peak memory 220684 kb
Host smart-e7731c79-a0cd-44a7-a25e-24d4319a0ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523926603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2523926603
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1768688693
Short name T230
Test name
Test status
Simulation time 69057148 ps
CPU time 3.32 seconds
Started May 28 02:55:07 PM PDT 24
Finished May 28 02:55:18 PM PDT 24
Peak memory 219336 kb
Host smart-b15b63a3-75b9-483f-9073-4bac8f3684ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768688693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1768688693
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3283936080
Short name T856
Test name
Test status
Simulation time 162836712 ps
CPU time 6.37 seconds
Started May 28 02:55:07 PM PDT 24
Finished May 28 02:55:21 PM PDT 24
Peak memory 207512 kb
Host smart-3e964119-1865-4757-ab2b-fec276063a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283936080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3283936080
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4254555006
Short name T111
Test name
Test status
Simulation time 2067510818 ps
CPU time 13.65 seconds
Started May 28 02:55:31 PM PDT 24
Finished May 28 02:56:00 PM PDT 24
Peak memory 239240 kb
Host smart-38cc2a3d-a960-4317-a4d6-c81d9f8b7fd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254555006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4254555006
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3728952208
Short name T354
Test name
Test status
Simulation time 90915007 ps
CPU time 2.03 seconds
Started May 28 02:55:04 PM PDT 24
Finished May 28 02:55:10 PM PDT 24
Peak memory 208576 kb
Host smart-a1ca511e-1cba-44df-85e4-0a6ed319cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728952208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3728952208
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1049485620
Short name T350
Test name
Test status
Simulation time 519998999 ps
CPU time 3.55 seconds
Started May 28 02:55:04 PM PDT 24
Finished May 28 02:55:10 PM PDT 24
Peak memory 208976 kb
Host smart-b1114abd-bdb5-419d-9e5a-177d8ae82650
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049485620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1049485620
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4158667196
Short name T794
Test name
Test status
Simulation time 106720615 ps
CPU time 4.17 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 208612 kb
Host smart-4f461413-9702-43d8-9758-a6724a06f96e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158667196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4158667196
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1113135534
Short name T696
Test name
Test status
Simulation time 270102446 ps
CPU time 5.55 seconds
Started May 28 02:55:06 PM PDT 24
Finished May 28 02:55:19 PM PDT 24
Peak memory 208688 kb
Host smart-4610f0c3-0b29-4661-b3cc-6dc673e43333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113135534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1113135534
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4140640896
Short name T180
Test name
Test status
Simulation time 290950081 ps
CPU time 2.41 seconds
Started May 28 02:55:09 PM PDT 24
Finished May 28 02:55:19 PM PDT 24
Peak memory 210296 kb
Host smart-798ee9fd-4df7-4393-9a01-a5977ab05891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140640896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4140640896
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2287821108
Short name T789
Test name
Test status
Simulation time 64961152 ps
CPU time 0.97 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 206172 kb
Host smart-0562a88f-cfd9-460c-bdc0-de99c29a2e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287821108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2287821108
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1539428130
Short name T625
Test name
Test status
Simulation time 404356690 ps
CPU time 3.25 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:35 PM PDT 24
Peak memory 208508 kb
Host smart-0e54eaf4-9e3d-487e-99dd-104215e1d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539428130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1539428130
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2108477565
Short name T746
Test name
Test status
Simulation time 234634915 ps
CPU time 4.06 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 207632 kb
Host smart-26e8b8e3-e7f4-4c52-8a9f-c253cf297c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108477565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2108477565
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3052442764
Short name T704
Test name
Test status
Simulation time 28553825 ps
CPU time 2.47 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:29 PM PDT 24
Peak memory 208988 kb
Host smart-494d74aa-34da-4c8a-b98f-f9bd65ce4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052442764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3052442764
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3431324182
Short name T282
Test name
Test status
Simulation time 165899482 ps
CPU time 2.7 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 222496 kb
Host smart-5f03fa7c-0c99-41fa-a293-df86d4c2bd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431324182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3431324182
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1274458423
Short name T689
Test name
Test status
Simulation time 36484758 ps
CPU time 2.01 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 219960 kb
Host smart-128d9c58-95ab-4ee5-b823-1ec7475f2a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274458423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1274458423
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.517856439
Short name T703
Test name
Test status
Simulation time 38535991 ps
CPU time 2.87 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 208440 kb
Host smart-3926697f-3311-4a94-b617-9152b74b04d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517856439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.517856439
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2735817035
Short name T47
Test name
Test status
Simulation time 1712672582 ps
CPU time 11.91 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 237576 kb
Host smart-a1a83f5e-ad21-4551-b1c5-71d5ba5a50e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735817035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2735817035
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1039018380
Short name T700
Test name
Test status
Simulation time 597217274 ps
CPU time 4.67 seconds
Started May 28 02:55:06 PM PDT 24
Finished May 28 02:55:17 PM PDT 24
Peak memory 207012 kb
Host smart-bd2bd013-c7f3-4f4c-86a5-b69351631952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039018380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1039018380
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1186272882
Short name T394
Test name
Test status
Simulation time 22094618 ps
CPU time 1.99 seconds
Started May 28 02:55:31 PM PDT 24
Finished May 28 02:55:48 PM PDT 24
Peak memory 208864 kb
Host smart-86cb44ac-c5bc-4f1b-9c51-3379ca0ceac5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186272882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1186272882
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2592002686
Short name T452
Test name
Test status
Simulation time 484401871 ps
CPU time 4.49 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:55:32 PM PDT 24
Peak memory 208568 kb
Host smart-188adf5b-b955-492a-8459-5f529415d44e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592002686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2592002686
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1026307760
Short name T353
Test name
Test status
Simulation time 57470413 ps
CPU time 2.82 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 215524 kb
Host smart-47cfadb9-bf5b-4f46-83ed-5c0ef3d2678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026307760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1026307760
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2240898268
Short name T841
Test name
Test status
Simulation time 208480122 ps
CPU time 3.53 seconds
Started May 28 02:55:06 PM PDT 24
Finished May 28 02:55:17 PM PDT 24
Peak memory 208680 kb
Host smart-39d6fbd7-bb33-4d3d-aa7d-ffb8fa62074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240898268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2240898268
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.839347440
Short name T51
Test name
Test status
Simulation time 2088675978 ps
CPU time 36.21 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 216120 kb
Host smart-1fe2f46b-1cf8-49a9-a624-16b90a304df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839347440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.839347440
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1163557358
Short name T831
Test name
Test status
Simulation time 91865633 ps
CPU time 0.81 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 206004 kb
Host smart-04b521f6-32b0-4058-9831-be7a36bcb0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163557358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1163557358
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.670690645
Short name T349
Test name
Test status
Simulation time 10421928716 ps
CPU time 135.44 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:58:08 PM PDT 24
Peak memory 215720 kb
Host smart-3fe49f6e-e1fa-4102-844d-6e0970104d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670690645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.670690645
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1549357960
Short name T913
Test name
Test status
Simulation time 173795122 ps
CPU time 2.63 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 214380 kb
Host smart-650727b5-c29f-4e1f-a8bd-e6efa2836ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549357960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1549357960
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2414823948
Short name T95
Test name
Test status
Simulation time 13236472763 ps
CPU time 93.39 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 214908 kb
Host smart-575b54ba-9527-4503-a244-59f321055b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414823948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2414823948
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3120474593
Short name T284
Test name
Test status
Simulation time 52255935 ps
CPU time 2.19 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 219840 kb
Host smart-ccd179cd-8d2e-464c-b3f0-b31f0edfe91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120474593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3120474593
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.773840741
Short name T753
Test name
Test status
Simulation time 1621156217 ps
CPU time 4.43 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 218032 kb
Host smart-6b776ac0-eab7-40da-a600-ba5ab0805fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773840741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.773840741
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.279014478
Short name T616
Test name
Test status
Simulation time 126456834 ps
CPU time 5.6 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 209728 kb
Host smart-9a641d1d-4cd8-4939-9304-4e98fe0b9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279014478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.279014478
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1591586182
Short name T795
Test name
Test status
Simulation time 118327711 ps
CPU time 3.34 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 208556 kb
Host smart-ee052f0f-2d59-41ca-b0a6-ef7c3faea3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591586182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1591586182
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1447235570
Short name T607
Test name
Test status
Simulation time 88950283 ps
CPU time 3.45 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 208840 kb
Host smart-6a6ab720-3e4d-4b25-8505-8c1b456e32a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447235570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1447235570
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3275376383
Short name T211
Test name
Test status
Simulation time 1505756325 ps
CPU time 4.78 seconds
Started May 28 02:55:33 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 208968 kb
Host smart-50725f47-b0da-47a9-b859-d71a3ee5f00b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275376383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3275376383
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3127394013
Short name T603
Test name
Test status
Simulation time 78685439 ps
CPU time 3.55 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 208980 kb
Host smart-27182f39-0908-4035-b35f-8c9aa8481f31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127394013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3127394013
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3767877214
Short name T270
Test name
Test status
Simulation time 436660768 ps
CPU time 3.44 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 214356 kb
Host smart-5be87f5e-5ca2-4644-aee4-9dadf6d25753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767877214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3767877214
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.4212247787
Short name T419
Test name
Test status
Simulation time 259221444 ps
CPU time 5.73 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 207768 kb
Host smart-ff3e2a20-9480-4b58-9c1d-750a923fa8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212247787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4212247787
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3239754803
Short name T357
Test name
Test status
Simulation time 895717256 ps
CPU time 29.13 seconds
Started May 28 02:55:43 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 216912 kb
Host smart-8250e6bf-2be9-49e8-b755-7dc86347e611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239754803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3239754803
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.244443336
Short name T561
Test name
Test status
Simulation time 237605769 ps
CPU time 3.7 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 207736 kb
Host smart-818a3fb4-c363-4622-909b-f038769a5418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244443336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.244443336
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3050456859
Short name T424
Test name
Test status
Simulation time 76526660 ps
CPU time 1.47 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 208756 kb
Host smart-10dbbd2f-cf8f-452e-a900-c3a402ee4f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050456859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3050456859
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1673495088
Short name T765
Test name
Test status
Simulation time 964967825 ps
CPU time 4 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 215228 kb
Host smart-a12733d7-d6bb-41c4-881d-c81d0329704f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673495088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1673495088
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3502468611
Short name T75
Test name
Test status
Simulation time 67163220 ps
CPU time 1.45 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 208192 kb
Host smart-36438cd6-c3b1-438e-b7b3-89769e595db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502468611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3502468611
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2071638288
Short name T22
Test name
Test status
Simulation time 939481999 ps
CPU time 5.43 seconds
Started May 28 02:55:41 PM PDT 24
Finished May 28 02:56:00 PM PDT 24
Peak memory 209248 kb
Host smart-ca621493-7073-4942-a921-adf978c9cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071638288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2071638288
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2445035086
Short name T577
Test name
Test status
Simulation time 330806205 ps
CPU time 2.47 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 214364 kb
Host smart-2a9877f1-90bc-4588-9af2-d0cf74c49174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445035086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2445035086
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.2659352464
Short name T518
Test name
Test status
Simulation time 741441508 ps
CPU time 8.53 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:56:01 PM PDT 24
Peak memory 214364 kb
Host smart-5c62cfc2-7529-44e9-9b31-20fb2f329f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659352464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2659352464
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1604100697
Short name T824
Test name
Test status
Simulation time 110686749 ps
CPU time 2.65 seconds
Started May 28 02:55:41 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 208744 kb
Host smart-1f6169f7-009e-4c1c-8d61-22e1012adff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604100697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1604100697
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1228436873
Short name T294
Test name
Test status
Simulation time 175467640 ps
CPU time 4.99 seconds
Started May 28 02:55:42 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 208028 kb
Host smart-6f8f7a1d-3713-4a6f-9d77-8926d3a75f46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228436873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1228436873
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.637662270
Short name T579
Test name
Test status
Simulation time 578407464 ps
CPU time 3.94 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 207040 kb
Host smart-21c8a01a-6600-4e6d-96f3-b47fb37f33e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637662270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.637662270
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3638987404
Short name T744
Test name
Test status
Simulation time 75505354 ps
CPU time 1.87 seconds
Started May 28 02:56:11 PM PDT 24
Finished May 28 02:56:17 PM PDT 24
Peak memory 207224 kb
Host smart-d2d0d514-4ddb-4cbf-93f9-b7ef7e281e86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638987404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3638987404
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3918073832
Short name T767
Test name
Test status
Simulation time 138662062 ps
CPU time 3.47 seconds
Started May 28 02:55:41 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 208536 kb
Host smart-993bab46-bb3f-4e58-b2b1-cc0439471ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918073832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3918073832
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1289405341
Short name T611
Test name
Test status
Simulation time 96003531 ps
CPU time 2.29 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 206836 kb
Host smart-af9b844b-77ca-4c84-b7aa-8a927cc06087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289405341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1289405341
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.774299641
Short name T239
Test name
Test status
Simulation time 754355917 ps
CPU time 24.56 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:56:18 PM PDT 24
Peak memory 219076 kb
Host smart-481544fe-1301-4271-884d-a62eebaefc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774299641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.774299641
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1654496502
Short name T371
Test name
Test status
Simulation time 144929531 ps
CPU time 3.56 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 218548 kb
Host smart-489dc5e3-2312-45c5-985f-30efba284e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654496502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1654496502
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4200719826
Short name T58
Test name
Test status
Simulation time 199703958 ps
CPU time 4.34 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 211008 kb
Host smart-5ad4da02-58b4-4190-829b-0ef8562b1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200719826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4200719826
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1078886884
Short name T546
Test name
Test status
Simulation time 26882611 ps
CPU time 0.91 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:06 PM PDT 24
Peak memory 206176 kb
Host smart-2893d5c3-0866-49cd-bc01-efa17de9e141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078886884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1078886884
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4238551586
Short name T854
Test name
Test status
Simulation time 28169221 ps
CPU time 1.46 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 206176 kb
Host smart-f8a75ee2-2fa0-4fd7-a186-c977214774ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238551586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4238551586
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4244500608
Short name T325
Test name
Test status
Simulation time 45608289 ps
CPU time 2.1 seconds
Started May 28 02:55:40 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 214444 kb
Host smart-d6e22fc3-67da-49c5-87fe-e1fc44417a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244500608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4244500608
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2860810853
Short name T732
Test name
Test status
Simulation time 315865110 ps
CPU time 7.51 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 214488 kb
Host smart-c6df714a-d6be-4559-8a91-88a542d1596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860810853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2860810853
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1188652629
Short name T400
Test name
Test status
Simulation time 812690958 ps
CPU time 6.75 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 214324 kb
Host smart-eec0ea4e-2087-4716-b8e6-ceb173213c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188652629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1188652629
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2147723973
Short name T474
Test name
Test status
Simulation time 40738616 ps
CPU time 1.72 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 214384 kb
Host smart-7cbfb461-8627-4961-bbc7-26d04a665a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147723973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2147723973
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2850855342
Short name T783
Test name
Test status
Simulation time 218424177 ps
CPU time 3.35 seconds
Started May 28 02:55:40 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 214372 kb
Host smart-90732885-fee8-48f0-96c5-fe60566a789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850855342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2850855342
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2669380253
Short name T316
Test name
Test status
Simulation time 589243158 ps
CPU time 3.93 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 207024 kb
Host smart-94cd083c-4fad-4037-843b-4d82942573c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669380253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2669380253
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2798758358
Short name T749
Test name
Test status
Simulation time 39799805 ps
CPU time 1.76 seconds
Started May 28 02:55:41 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 207360 kb
Host smart-2c7942f3-669b-4387-8215-6714cbe5ae10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798758358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2798758358
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2190626140
Short name T691
Test name
Test status
Simulation time 53200180 ps
CPU time 2.64 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 208196 kb
Host smart-aba5d105-cc4d-41b8-9b8a-80a5770810ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190626140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2190626140
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2237679429
Short name T538
Test name
Test status
Simulation time 488164482 ps
CPU time 4.6 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:57 PM PDT 24
Peak memory 207004 kb
Host smart-9d9abba5-15ad-4355-b19c-af92cc37e144
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237679429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2237679429
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1894816438
Short name T656
Test name
Test status
Simulation time 95736724 ps
CPU time 3.9 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 208928 kb
Host smart-740ef439-af16-43f6-91c7-bfdfabec1f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894816438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1894816438
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2184605553
Short name T501
Test name
Test status
Simulation time 21746489 ps
CPU time 1.62 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 206848 kb
Host smart-d86d9bcc-ae2a-4d1a-969a-848cdff49cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184605553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2184605553
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2398849643
Short name T417
Test name
Test status
Simulation time 2103524674 ps
CPU time 20.79 seconds
Started May 28 02:55:45 PM PDT 24
Finished May 28 02:56:17 PM PDT 24
Peak memory 215112 kb
Host smart-058e6b8c-ebfb-46cd-a434-847f05472655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398849643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2398849643
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3914184096
Short name T276
Test name
Test status
Simulation time 646409649 ps
CPU time 15.82 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 208672 kb
Host smart-cc3af950-79d0-4c55-a69d-9911cb27b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914184096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3914184096
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2429069260
Short name T699
Test name
Test status
Simulation time 82004656 ps
CPU time 2.67 seconds
Started May 28 02:55:45 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 210512 kb
Host smart-fa7d114c-569e-41b5-ad2e-2626787479aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429069260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2429069260
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3460660179
Short name T547
Test name
Test status
Simulation time 37368638 ps
CPU time 0.8 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 205944 kb
Host smart-68e9364c-fe11-4c11-94a5-f0cb788bef37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460660179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3460660179
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3738472421
Short name T411
Test name
Test status
Simulation time 173664468 ps
CPU time 4.56 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 215880 kb
Host smart-911f25cc-e6dc-41c7-9074-f2dca6662f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738472421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3738472421
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3460231934
Short name T61
Test name
Test status
Simulation time 3403347251 ps
CPU time 10 seconds
Started May 28 02:55:45 PM PDT 24
Finished May 28 02:56:06 PM PDT 24
Peak memory 214464 kb
Host smart-39b324fe-8a73-4865-8353-277675f385de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460231934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3460231934
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1965112740
Short name T717
Test name
Test status
Simulation time 141398987 ps
CPU time 3.68 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 222428 kb
Host smart-68a60387-9d8c-4469-a6a5-e0e764e3d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965112740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1965112740
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1227976012
Short name T48
Test name
Test status
Simulation time 91030741 ps
CPU time 2.99 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 209940 kb
Host smart-21d474de-bc5e-4806-8790-9418a0200c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227976012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1227976012
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1201115856
Short name T763
Test name
Test status
Simulation time 606454936 ps
CPU time 3.13 seconds
Started May 28 02:55:50 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 208420 kb
Host smart-c09da4e7-c5d8-470a-b64d-f4e0a97d82a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201115856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1201115856
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3570220247
Short name T444
Test name
Test status
Simulation time 222380741 ps
CPU time 6.01 seconds
Started May 28 02:55:51 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 208800 kb
Host smart-1c23da92-4ed0-4f09-b72c-ee32ab5bb898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570220247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3570220247
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2776983070
Short name T227
Test name
Test status
Simulation time 106083566 ps
CPU time 2.74 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 208312 kb
Host smart-b4e8445c-fc1c-47a5-b30a-eb33d50921e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776983070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2776983070
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1482399800
Short name T390
Test name
Test status
Simulation time 178504599 ps
CPU time 3.94 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 206984 kb
Host smart-38205b97-ff10-449c-b097-9419aed46004
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482399800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1482399800
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4045455637
Short name T491
Test name
Test status
Simulation time 342172478 ps
CPU time 3.76 seconds
Started May 28 02:55:51 PM PDT 24
Finished May 28 02:56:06 PM PDT 24
Peak memory 208696 kb
Host smart-19e71e4d-3cb6-4568-98bf-e43b86b7db6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045455637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4045455637
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2024979463
Short name T557
Test name
Test status
Simulation time 170974628 ps
CPU time 2.31 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 207660 kb
Host smart-89bd9dcf-83d0-4fc3-a1d4-23d8018917cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024979463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2024979463
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2705267560
Short name T490
Test name
Test status
Simulation time 553608116 ps
CPU time 4.53 seconds
Started May 28 02:55:45 PM PDT 24
Finished May 28 02:56:01 PM PDT 24
Peak memory 208368 kb
Host smart-57b79874-8d97-4086-b198-41db07212368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705267560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2705267560
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.909585378
Short name T676
Test name
Test status
Simulation time 3410255629 ps
CPU time 8.2 seconds
Started May 28 02:55:53 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 218352 kb
Host smart-8f0ba565-7888-40a4-8075-ad9581e8b6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909585378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.909585378
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2535864579
Short name T210
Test name
Test status
Simulation time 222846668 ps
CPU time 4.21 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 210628 kb
Host smart-48791154-57a9-4b3e-b60e-4c07b9e7664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535864579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2535864579
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.938521166
Short name T655
Test name
Test status
Simulation time 10546981 ps
CPU time 0.73 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 205924 kb
Host smart-494244b2-0d63-4a4d-a7ca-eaa353d254d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938521166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.938521166
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1273512654
Short name T108
Test name
Test status
Simulation time 106997789 ps
CPU time 3.16 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 210476 kb
Host smart-26e21bc5-586b-4681-8b57-98f3c52899eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273512654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1273512654
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3829977398
Short name T57
Test name
Test status
Simulation time 81985300 ps
CPU time 1.97 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 207816 kb
Host smart-9c6632e8-68e6-4d31-8009-8e411887f4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829977398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3829977398
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1617868387
Short name T845
Test name
Test status
Simulation time 62705520 ps
CPU time 2.31 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 208444 kb
Host smart-80dd9a0e-542f-4048-ada8-5fece3be20e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617868387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1617868387
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.940868905
Short name T540
Test name
Test status
Simulation time 91177964 ps
CPU time 3.18 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 214316 kb
Host smart-04929326-9607-42f9-bdd4-7a2de6ae1e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940868905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.940868905
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3188815989
Short name T233
Test name
Test status
Simulation time 42800524 ps
CPU time 2.72 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 214296 kb
Host smart-0fabd9a6-4e21-4402-b856-ae2fbd5370ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188815989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3188815989
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2301217297
Short name T213
Test name
Test status
Simulation time 354205281 ps
CPU time 4.44 seconds
Started May 28 02:55:52 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 209204 kb
Host smart-b062fa98-a3dd-46e9-93a0-0b4f6eab1177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301217297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2301217297
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.986332354
Short name T489
Test name
Test status
Simulation time 165931355 ps
CPU time 1.87 seconds
Started May 28 02:55:51 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 206940 kb
Host smart-642f7d2d-882d-4cea-b8ac-1a581d14215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986332354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.986332354
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1582772193
Short name T306
Test name
Test status
Simulation time 58453813 ps
CPU time 2.31 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 206980 kb
Host smart-bffd4463-abea-4ab2-ab77-bdd8c9487153
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582772193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1582772193
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3870922413
Short name T463
Test name
Test status
Simulation time 780022782 ps
CPU time 9.07 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 208168 kb
Host smart-be42e3e5-0a0f-4265-80d7-c6aa55996e0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870922413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3870922413
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2109977373
Short name T687
Test name
Test status
Simulation time 677338621 ps
CPU time 7.83 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:16 PM PDT 24
Peak memory 208664 kb
Host smart-ab19485b-83cb-41e0-ae68-fe27560c9e0c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109977373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2109977373
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.858875661
Short name T738
Test name
Test status
Simulation time 36572745 ps
CPU time 1.58 seconds
Started May 28 02:55:53 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 208276 kb
Host smart-33df9e9b-4a2d-4bec-a93f-99e4028cb336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858875661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.858875661
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2413969712
Short name T446
Test name
Test status
Simulation time 286783686 ps
CPU time 3.17 seconds
Started May 28 02:55:50 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 208056 kb
Host smart-93a981a0-584c-4ec4-97e6-ea7458fc7301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413969712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2413969712
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1976756814
Short name T389
Test name
Test status
Simulation time 86159143 ps
CPU time 5.12 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 215036 kb
Host smart-35d56abf-fa5a-4940-ac68-9d55b4955bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976756814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1976756814
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3806890728
Short name T568
Test name
Test status
Simulation time 506858161 ps
CPU time 6.85 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 207596 kb
Host smart-194210ed-c798-45f3-b534-ef26dc7d41b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806890728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3806890728
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4173267306
Short name T459
Test name
Test status
Simulation time 12132763 ps
CPU time 0.71 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 206004 kb
Host smart-4222f43b-4a87-4d73-9178-77ee4f561017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173267306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4173267306
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.209093360
Short name T14
Test name
Test status
Simulation time 65372113 ps
CPU time 3.59 seconds
Started May 28 02:55:52 PM PDT 24
Finished May 28 02:56:07 PM PDT 24
Peak memory 214924 kb
Host smart-2d7e5019-6c5e-41ef-81e5-64e4808e5afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209093360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.209093360
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3549898907
Short name T679
Test name
Test status
Simulation time 78677056 ps
CPU time 3.09 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 210184 kb
Host smart-d3663c69-c33f-4b05-bf3a-db25006fc6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549898907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3549898907
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4104276726
Short name T301
Test name
Test status
Simulation time 1541389582 ps
CPU time 14.57 seconds
Started May 28 02:55:46 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 218432 kb
Host smart-f47a8a98-c8fd-4140-8356-b707be7f079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104276726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4104276726
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3283177406
Short name T843
Test name
Test status
Simulation time 92232668 ps
CPU time 3.01 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 217288 kb
Host smart-6bc05667-aeec-4c25-bd21-9f6dbf4e2111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283177406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3283177406
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.1970790345
Short name T842
Test name
Test status
Simulation time 243285991 ps
CPU time 4.03 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 222544 kb
Host smart-3484b279-1318-462f-9904-7e0badaf6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970790345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1970790345
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1306657521
Short name T834
Test name
Test status
Simulation time 31365674 ps
CPU time 2.23 seconds
Started May 28 02:55:50 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 207040 kb
Host smart-398c174f-5b5f-4e66-8099-dfa1107cb8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306657521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1306657521
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.980810466
Short name T336
Test name
Test status
Simulation time 28536045 ps
CPU time 1.92 seconds
Started May 28 02:55:52 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 207192 kb
Host smart-5c95fe27-d42b-4675-b4fa-cb7e88fb7db4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980810466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.980810466
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3592600562
Short name T574
Test name
Test status
Simulation time 3288430023 ps
CPU time 23.53 seconds
Started May 28 02:55:51 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 208572 kb
Host smart-59ec3652-a422-49b0-938b-cfb9749b9cac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592600562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3592600562
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1593537642
Short name T510
Test name
Test status
Simulation time 89367459 ps
CPU time 3.49 seconds
Started May 28 02:55:49 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 208952 kb
Host smart-83935091-8f8b-4060-aef5-7148c46edbdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593537642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1593537642
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3850819905
Short name T838
Test name
Test status
Simulation time 187046460 ps
CPU time 2.17 seconds
Started May 28 02:55:53 PM PDT 24
Finished May 28 02:56:06 PM PDT 24
Peak memory 215292 kb
Host smart-f03741ea-12a6-4246-a62b-13b582562b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850819905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3850819905
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3427171651
Short name T225
Test name
Test status
Simulation time 99849844 ps
CPU time 2.91 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 206880 kb
Host smart-7994d959-6094-40e2-86e6-e326da14963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427171651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3427171651
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4183106966
Short name T277
Test name
Test status
Simulation time 7164299273 ps
CPU time 130.15 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:58:16 PM PDT 24
Peak memory 217328 kb
Host smart-f4605eb4-160e-44f8-9923-61bcfca0f8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183106966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4183106966
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2297183841
Short name T397
Test name
Test status
Simulation time 131585275 ps
CPU time 4.05 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 207360 kb
Host smart-372c59b4-a10c-4a97-8408-543e09ffc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297183841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2297183841
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2082390775
Short name T565
Test name
Test status
Simulation time 397220526 ps
CPU time 2.87 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 210432 kb
Host smart-1494c650-d5cb-4a7d-9d3a-9595005bf956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082390775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2082390775
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2108304718
Short name T445
Test name
Test status
Simulation time 20107585 ps
CPU time 0.88 seconds
Started May 28 02:55:46 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 205992 kb
Host smart-f77a8864-c614-4b8c-888a-f9010df6edda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108304718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2108304718
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2676528921
Short name T384
Test name
Test status
Simulation time 1179278975 ps
CPU time 16.7 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 215736 kb
Host smart-2ea3af03-e48e-4f06-bb18-e7fedfdcd2d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676528921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2676528921
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.538232455
Short name T499
Test name
Test status
Simulation time 161317546 ps
CPU time 2.3 seconds
Started May 28 02:55:50 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 208336 kb
Host smart-9ba99c22-494a-48d0-8176-ddc3d0ae7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538232455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.538232455
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1614764462
Short name T685
Test name
Test status
Simulation time 1619705417 ps
CPU time 7.93 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:16 PM PDT 24
Peak memory 222600 kb
Host smart-1422263d-05ce-47ed-9f3e-1fb14a88e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614764462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1614764462
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3714817488
Short name T296
Test name
Test status
Simulation time 88620508 ps
CPU time 3.1 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 214296 kb
Host smart-c6640ced-5b96-4636-975f-b28c02ad9676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714817488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3714817488
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.981651063
Short name T59
Test name
Test status
Simulation time 96025729 ps
CPU time 2.65 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 220048 kb
Host smart-e39744d4-e6f1-42d7-a88d-ea5ec9722ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981651063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.981651063
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3478278519
Short name T223
Test name
Test status
Simulation time 367127021 ps
CPU time 4.2 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 208880 kb
Host smart-0b08aabc-35b9-4b5d-acc1-1799bd3f74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478278519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3478278519
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1961054641
Short name T114
Test name
Test status
Simulation time 157892187 ps
CPU time 4.66 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 208700 kb
Host smart-59c24a99-b262-4a56-b3c8-1481e98ef672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961054641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1961054641
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2633171919
Short name T543
Test name
Test status
Simulation time 402811292 ps
CPU time 13.15 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 209076 kb
Host smart-b52413ea-947f-435a-a307-87c235badfdd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633171919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2633171919
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1249241522
Short name T681
Test name
Test status
Simulation time 1318592460 ps
CPU time 20.55 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:27 PM PDT 24
Peak memory 208680 kb
Host smart-e342f1e6-3548-491f-af86-0e888ffa2047
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249241522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1249241522
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.863737518
Short name T773
Test name
Test status
Simulation time 206762836 ps
CPU time 2.81 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 209156 kb
Host smart-6336d3f4-c7d3-4eb9-8ac6-47295ccc809d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863737518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.863737518
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2821588099
Short name T416
Test name
Test status
Simulation time 322309463 ps
CPU time 3.24 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 214384 kb
Host smart-5952edb6-52df-47ee-b53f-f7aa54f7f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821588099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2821588099
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.667197940
Short name T639
Test name
Test status
Simulation time 71573514 ps
CPU time 3.25 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 208792 kb
Host smart-9556f160-ab8d-4c67-82c6-2a1ac54be821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667197940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.667197940
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4179542370
Short name T855
Test name
Test status
Simulation time 468806834 ps
CPU time 5.15 seconds
Started May 28 02:55:46 PM PDT 24
Finished May 28 02:56:03 PM PDT 24
Peak memory 220400 kb
Host smart-fdb346b0-7978-46fe-9e84-27226874db77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179542370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4179542370
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3702479907
Short name T852
Test name
Test status
Simulation time 531023814 ps
CPU time 22.49 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 221716 kb
Host smart-83c6cb83-9b15-4065-8c4a-3d3e7d892fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702479907 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3702479907
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3382271546
Short name T872
Test name
Test status
Simulation time 352847077 ps
CPU time 4.32 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 214408 kb
Host smart-c3f0235f-8511-4ef2-bd2c-f71b7112ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382271546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3382271546
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3116701301
Short name T624
Test name
Test status
Simulation time 667814737 ps
CPU time 1.34 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 209916 kb
Host smart-31d15a5a-ba2f-4ff0-b4a6-86006132ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116701301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3116701301
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.191467967
Short name T494
Test name
Test status
Simulation time 39067128 ps
CPU time 0.95 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 206144 kb
Host smart-f91cc0b5-27a5-4d48-b460-358735736f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191467967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.191467967
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1041471457
Short name T138
Test name
Test status
Simulation time 9520506012 ps
CPU time 71.01 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:57:19 PM PDT 24
Peak memory 215764 kb
Host smart-b9e3f9cd-8f50-4499-a386-08d7947dfe80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041471457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1041471457
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.745629144
Short name T701
Test name
Test status
Simulation time 159777066 ps
CPU time 4.5 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 214396 kb
Host smart-13168b82-72e7-49a5-a615-395af6bdcb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745629144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.745629144
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1189994306
Short name T281
Test name
Test status
Simulation time 166089283 ps
CPU time 1.85 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:02 PM PDT 24
Peak memory 209880 kb
Host smart-56b3ef5d-e3e6-4de5-98b4-45ccfc053501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189994306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1189994306
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1678884406
Short name T861
Test name
Test status
Simulation time 170863928 ps
CPU time 5.86 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:06 PM PDT 24
Peak memory 221396 kb
Host smart-fdf9a808-bb3c-4eba-bddf-35ce3fa2b165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678884406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1678884406
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_random.3350399298
Short name T356
Test name
Test status
Simulation time 353444980 ps
CPU time 5.35 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:05 PM PDT 24
Peak memory 218496 kb
Host smart-cf5440ee-844b-4d31-bebc-e4d75d8d9a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350399298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3350399298
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.257894877
Short name T573
Test name
Test status
Simulation time 65531114 ps
CPU time 3.43 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:03 PM PDT 24
Peak memory 208788 kb
Host smart-7a377559-edda-4c3f-b612-f843cfd27591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257894877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.257894877
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2902878361
Short name T780
Test name
Test status
Simulation time 53651032 ps
CPU time 2.46 seconds
Started May 28 02:55:55 PM PDT 24
Finished May 28 02:56:08 PM PDT 24
Peak memory 208636 kb
Host smart-1b7fc764-dc82-4805-a91c-ebd0ebd6bb7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902878361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2902878361
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.700626887
Short name T722
Test name
Test status
Simulation time 32193522 ps
CPU time 2.03 seconds
Started May 28 02:55:47 PM PDT 24
Finished May 28 02:56:00 PM PDT 24
Peak memory 208960 kb
Host smart-4b05eb0c-4fd6-4187-9aed-106d85623243
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700626887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.700626887
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4033034827
Short name T866
Test name
Test status
Simulation time 110770046 ps
CPU time 3.72 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 208532 kb
Host smart-4cc967a0-ba5a-40db-8124-669d99b9eef0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033034827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4033034827
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.4293395392
Short name T614
Test name
Test status
Simulation time 1034467785 ps
CPU time 3.76 seconds
Started May 28 02:55:48 PM PDT 24
Finished May 28 02:56:04 PM PDT 24
Peak memory 208996 kb
Host smart-41ead083-aed2-4203-8ba2-f3feccaa0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293395392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.4293395392
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1253003708
Short name T909
Test name
Test status
Simulation time 101239301 ps
CPU time 3.51 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 208352 kb
Host smart-c9e05283-3e88-43fe-b6db-439642014f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253003708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1253003708
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.897195547
Short name T242
Test name
Test status
Simulation time 583160200 ps
CPU time 22.94 seconds
Started May 28 02:55:54 PM PDT 24
Finished May 28 02:56:28 PM PDT 24
Peak memory 215244 kb
Host smart-fc893392-9d57-4911-b6fd-71cff6141920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897195547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.897195547
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.246057691
Short name T879
Test name
Test status
Simulation time 284976456 ps
CPU time 6.3 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 210288 kb
Host smart-8e31f4e0-fb4d-4ddd-8c1b-ae547df86a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246057691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.246057691
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2315111271
Short name T541
Test name
Test status
Simulation time 1249524093 ps
CPU time 13.35 seconds
Started May 28 02:55:49 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 210996 kb
Host smart-a4bf8215-0486-4818-8145-32fa52680bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315111271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2315111271
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2958865221
Short name T84
Test name
Test status
Simulation time 23396148 ps
CPU time 0.84 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 205996 kb
Host smart-41d19a46-4a51-4a93-bd1f-ac5ba0d15c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958865221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2958865221
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2270505195
Short name T431
Test name
Test status
Simulation time 41810620 ps
CPU time 2.38 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 208064 kb
Host smart-dfc922b7-191a-4340-a5b2-f0481d359768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270505195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2270505195
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.299240295
Short name T728
Test name
Test status
Simulation time 732043903 ps
CPU time 3.72 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 222476 kb
Host smart-6bc05061-d827-4057-824b-4fd8bdd96a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299240295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.299240295
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.433940842
Short name T5
Test name
Test status
Simulation time 43845617 ps
CPU time 2.75 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 215412 kb
Host smart-742412b3-1b84-4f99-8779-14fbf28ab256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433940842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.433940842
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2284375462
Short name T450
Test name
Test status
Simulation time 640254101 ps
CPU time 5.62 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 208248 kb
Host smart-c84b538a-3d34-4b48-85f2-c59a87512148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284375462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2284375462
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3266921250
Short name T331
Test name
Test status
Simulation time 33573051 ps
CPU time 2.33 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 206900 kb
Host smart-28018de1-9f1c-463a-818f-2288e04d6e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266921250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3266921250
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2924008529
Short name T576
Test name
Test status
Simulation time 256154090 ps
CPU time 3.56 seconds
Started May 28 02:56:11 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 208252 kb
Host smart-046c7fe1-9478-49fc-aaa5-2627a8115c5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924008529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2924008529
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2136146631
Short name T506
Test name
Test status
Simulation time 144439623 ps
CPU time 4.42 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 206992 kb
Host smart-c6895ffd-3c5b-4d03-a9f7-fe16568a4832
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136146631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2136146631
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3284283587
Short name T606
Test name
Test status
Simulation time 283681551 ps
CPU time 9.01 seconds
Started May 28 02:55:57 PM PDT 24
Finished May 28 02:56:17 PM PDT 24
Peak memory 208268 kb
Host smart-c8905a30-2fc9-46e9-b85c-5d964a8cfa22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284283587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3284283587
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.658496818
Short name T862
Test name
Test status
Simulation time 154282524 ps
CPU time 3.25 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 207988 kb
Host smart-e368e8f3-62f8-49eb-9a42-a21af38a9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658496818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.658496818
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1265452963
Short name T801
Test name
Test status
Simulation time 89850904 ps
CPU time 2.62 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 206780 kb
Host smart-01544596-b1a5-4d2a-9ecc-faa75b73e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265452963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1265452963
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1511708527
Short name T733
Test name
Test status
Simulation time 1734410061 ps
CPU time 15.84 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:26 PM PDT 24
Peak memory 222648 kb
Host smart-14e3f9e1-fe35-4ec7-81ad-749ab851502f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511708527 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1511708527
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1020540773
Short name T315
Test name
Test status
Simulation time 2380859517 ps
CPU time 55.09 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 208752 kb
Host smart-d76e4acf-4c23-4911-859d-f441ee3a9047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020540773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1020540773
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1860061163
Short name T184
Test name
Test status
Simulation time 209524244 ps
CPU time 2.46 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 210528 kb
Host smart-c2dc482a-569a-47e4-be4c-ccdac43fb988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860061163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1860061163
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1815585267
Short name T764
Test name
Test status
Simulation time 22624223 ps
CPU time 0.72 seconds
Started May 28 02:57:00 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 205992 kb
Host smart-1cec5636-339c-4687-82f6-8518d4684f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815585267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1815585267
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3850427638
Short name T376
Test name
Test status
Simulation time 1804111181 ps
CPU time 94.08 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:57:43 PM PDT 24
Peak memory 214472 kb
Host smart-a2de87e9-86cd-4ebc-aa53-ab1014891ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850427638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3850427638
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3210380621
Short name T598
Test name
Test status
Simulation time 218448697 ps
CPU time 2.01 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 218312 kb
Host smart-35dfa8f5-3bd3-4a6e-a0fd-efc9516f90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210380621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3210380621
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.391703962
Short name T74
Test name
Test status
Simulation time 45932078 ps
CPU time 2.04 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:11 PM PDT 24
Peak memory 209312 kb
Host smart-f78e4393-1d6b-45d1-af3a-bcb3ccf9dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391703962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.391703962
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1528920584
Short name T360
Test name
Test status
Simulation time 91955719 ps
CPU time 2.92 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 214300 kb
Host smart-97e0b770-95a2-446b-8f72-a37705eb3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528920584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1528920584
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.586599951
Short name T571
Test name
Test status
Simulation time 436517189 ps
CPU time 3.6 seconds
Started May 28 02:55:59 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 218156 kb
Host smart-6f11a505-78e9-474b-b5d4-609bf324cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586599951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.586599951
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.875614449
Short name T891
Test name
Test status
Simulation time 163184234 ps
CPU time 5.45 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 207568 kb
Host smart-526d686c-6896-449f-aed9-d4e53029c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875614449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.875614449
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.58430245
Short name T321
Test name
Test status
Simulation time 113078793 ps
CPU time 4.4 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:13 PM PDT 24
Peak memory 208956 kb
Host smart-da5c273f-249f-4bc3-82b3-856cb9931768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58430245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.58430245
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2338935483
Short name T771
Test name
Test status
Simulation time 398075017 ps
CPU time 5.69 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:16 PM PDT 24
Peak memory 208608 kb
Host smart-c7d5015b-00f7-4396-981f-6e9706f8f0ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338935483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2338935483
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.611473191
Short name T517
Test name
Test status
Simulation time 126795801 ps
CPU time 2.93 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:12 PM PDT 24
Peak memory 207020 kb
Host smart-f426d417-77ec-4df7-8ad3-a93951392d02
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611473191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.611473191
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3682886982
Short name T373
Test name
Test status
Simulation time 1357795599 ps
CPU time 4.02 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:14 PM PDT 24
Peak memory 209052 kb
Host smart-5f70eac5-0816-430c-a87b-e3a82bbb3876
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682886982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3682886982
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.436696262
Short name T712
Test name
Test status
Simulation time 59204907 ps
CPU time 2.73 seconds
Started May 28 02:56:18 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 208772 kb
Host smart-112107dc-5359-47dc-acc5-d741c4a10472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436696262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.436696262
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1160713826
Short name T511
Test name
Test status
Simulation time 655400498 ps
CPU time 4.59 seconds
Started May 28 02:56:00 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 208580 kb
Host smart-9185a6bf-045b-4303-8e38-34b7cca76996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160713826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1160713826
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2889607492
Short name T871
Test name
Test status
Simulation time 865074765 ps
CPU time 5 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 207672 kb
Host smart-2364c72e-0432-4dd7-b7b5-482c2316ac68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889607492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2889607492
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1477124396
Short name T729
Test name
Test status
Simulation time 440604467 ps
CPU time 4.8 seconds
Started May 28 02:55:58 PM PDT 24
Finished May 28 02:56:14 PM PDT 24
Peak memory 209716 kb
Host smart-57431b45-a22f-4aa4-abb1-acb27043e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477124396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1477124396
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1049583470
Short name T174
Test name
Test status
Simulation time 130300585 ps
CPU time 1.8 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 210000 kb
Host smart-63aaa7ae-7415-4ea8-bbb0-3cc54be4d849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049583470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1049583470
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2070246360
Short name T590
Test name
Test status
Simulation time 27841396 ps
CPU time 0.83 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:33 PM PDT 24
Peak memory 206008 kb
Host smart-8c366f10-b80e-4298-bf3a-3db98a87885e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070246360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2070246360
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1503741200
Short name T29
Test name
Test status
Simulation time 84972474 ps
CPU time 3.77 seconds
Started May 28 02:55:24 PM PDT 24
Finished May 28 02:55:42 PM PDT 24
Peak memory 211756 kb
Host smart-1e1ae796-194a-4e5b-a4c2-6f99a377a30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503741200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1503741200
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3212456395
Short name T578
Test name
Test status
Simulation time 33810133 ps
CPU time 1.59 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:55:30 PM PDT 24
Peak memory 207724 kb
Host smart-e8e8d971-2837-40fa-bc15-b3d38757f33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212456395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3212456395
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.494561039
Short name T695
Test name
Test status
Simulation time 62908308 ps
CPU time 2.93 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 214356 kb
Host smart-45d7bb1f-9bec-4d77-9c56-1d89d2aa59d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494561039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.494561039
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.346233090
Short name T326
Test name
Test status
Simulation time 377896091 ps
CPU time 4.49 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 220412 kb
Host smart-099956e6-a829-402b-b863-357cf7cc7b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346233090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.346233090
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3084435939
Short name T369
Test name
Test status
Simulation time 118985187 ps
CPU time 2.83 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 214364 kb
Host smart-20de9e4d-1e5a-44d8-85c8-55a8d62e596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084435939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3084435939
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3194521864
Short name T9
Test name
Test status
Simulation time 1876301601 ps
CPU time 15.6 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:51 PM PDT 24
Peak memory 239236 kb
Host smart-8f90ddb3-2f4e-43b4-a019-e6c3c68152f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194521864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3194521864
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1707754168
Short name T828
Test name
Test status
Simulation time 512392956 ps
CPU time 4.87 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:31 PM PDT 24
Peak memory 208908 kb
Host smart-9d49d855-2820-42f0-bdb9-3a7aeead58be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707754168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1707754168
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.174527064
Short name T601
Test name
Test status
Simulation time 22201759 ps
CPU time 1.8 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 206984 kb
Host smart-907966d7-34c3-4e11-9e0b-fa57280d6ea3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174527064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.174527064
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1116238409
Short name T713
Test name
Test status
Simulation time 199964493 ps
CPU time 2.61 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:55:30 PM PDT 24
Peak memory 208772 kb
Host smart-964cc7a9-3be7-4a53-a7a0-310b065ada7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116238409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1116238409
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1656800832
Short name T471
Test name
Test status
Simulation time 979863568 ps
CPU time 17.09 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 208952 kb
Host smart-570bf407-aa91-47b9-ac21-8d7bb76a3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656800832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1656800832
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.4160170831
Short name T739
Test name
Test status
Simulation time 4396263985 ps
CPU time 19.81 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 215492 kb
Host smart-6bfe2cb6-b854-4180-aef2-24c8da663832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160170831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4160170831
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1896960846
Short name T622
Test name
Test status
Simulation time 490745680 ps
CPU time 7.43 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 214460 kb
Host smart-342e59bb-afba-46bd-9314-6ad7f13d9fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896960846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1896960846
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3205702255
Short name T664
Test name
Test status
Simulation time 149349840 ps
CPU time 2.5 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:29 PM PDT 24
Peak memory 210352 kb
Host smart-0ec85e0f-4071-46de-8fc4-6f2e7e47e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205702255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3205702255
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4064035142
Short name T89
Test name
Test status
Simulation time 16188097 ps
CPU time 0.71 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 205992 kb
Host smart-d8561345-5eb1-4705-9eda-e052e03ab39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064035142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4064035142
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3293390522
Short name T310
Test name
Test status
Simulation time 581329376 ps
CPU time 8.83 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:29 PM PDT 24
Peak memory 214384 kb
Host smart-10c9d0aa-d617-4328-97a5-1f6257e2d04c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293390522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3293390522
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4152972888
Short name T71
Test name
Test status
Simulation time 152513423 ps
CPU time 4.36 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:24 PM PDT 24
Peak memory 218656 kb
Host smart-b1d1d581-2909-438a-b0c5-3702f32bba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152972888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4152972888
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3284117773
Short name T79
Test name
Test status
Simulation time 54696188 ps
CPU time 2.46 seconds
Started May 28 02:56:18 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 208972 kb
Host smart-ea09d0f3-af09-4593-8ccc-e01968f5fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284117773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3284117773
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3257574124
Short name T790
Test name
Test status
Simulation time 59751421 ps
CPU time 1.98 seconds
Started May 28 02:56:11 PM PDT 24
Finished May 28 02:56:17 PM PDT 24
Peak memory 214392 kb
Host smart-1b306cd0-9e39-4adc-a575-ce2d907ff6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257574124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3257574124
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3300311794
Short name T816
Test name
Test status
Simulation time 94277491 ps
CPU time 4.49 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 219624 kb
Host smart-2b930d24-045a-4ee2-a879-6b825442b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300311794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3300311794
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2870911272
Short name T249
Test name
Test status
Simulation time 171694796 ps
CPU time 4.2 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 220700 kb
Host smart-f8916e12-534b-4b2b-ac88-14fc2fd88f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870911272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2870911272
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.726925852
Short name T260
Test name
Test status
Simulation time 264372341 ps
CPU time 5.4 seconds
Started May 28 02:56:17 PM PDT 24
Finished May 28 02:56:26 PM PDT 24
Peak memory 209980 kb
Host smart-912c0cab-e620-470d-bfd9-b1da15adaf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726925852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.726925852
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3340539217
Short name T392
Test name
Test status
Simulation time 872525267 ps
CPU time 23.32 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:40 PM PDT 24
Peak memory 208324 kb
Host smart-45a16247-5ebe-4de6-a2d2-d6d58741d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340539217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3340539217
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4104963313
Short name T867
Test name
Test status
Simulation time 56885566 ps
CPU time 2.6 seconds
Started May 28 02:56:18 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 206916 kb
Host smart-3876bd57-d968-4dff-98ce-afec3a38c01d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104963313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4104963313
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.221641306
Short name T721
Test name
Test status
Simulation time 101505073 ps
CPU time 3.1 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 206976 kb
Host smart-f177c64a-a093-498f-9767-ba11b3cf2f73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221641306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.221641306
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3847093882
Short name T819
Test name
Test status
Simulation time 544811368 ps
CPU time 4.68 seconds
Started May 28 02:56:17 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 208488 kb
Host smart-7d9cabf9-79ef-4d11-886c-7b825eb2d407
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847093882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3847093882
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2292066345
Short name T352
Test name
Test status
Simulation time 51647729 ps
CPU time 2.64 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 215592 kb
Host smart-b8aadb2d-328b-4c67-878b-0e9f96e90c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292066345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2292066345
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2819947875
Short name T580
Test name
Test status
Simulation time 198591522 ps
CPU time 3.03 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 207040 kb
Host smart-2749cd11-07e0-4c3a-a679-1d9d443d85fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819947875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2819947875
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2083139777
Short name T378
Test name
Test status
Simulation time 9951185837 ps
CPU time 43.44 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 216200 kb
Host smart-5bda42d6-47f2-4ac9-a598-c799c606ac7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083139777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2083139777
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.871201255
Short name T309
Test name
Test status
Simulation time 202501920 ps
CPU time 4.6 seconds
Started May 28 02:56:18 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 214376 kb
Host smart-85d03f75-a482-4556-8fab-481686114427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871201255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.871201255
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.4005257349
Short name T651
Test name
Test status
Simulation time 66469371 ps
CPU time 2.4 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 210748 kb
Host smart-3c8b18ed-e449-4cb6-951a-c2f7c3361575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005257349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4005257349
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1567523892
Short name T774
Test name
Test status
Simulation time 16394462 ps
CPU time 0.88 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:18 PM PDT 24
Peak memory 206196 kb
Host smart-0d2caecc-2dbd-4546-89c7-66460cbc0f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567523892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1567523892
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2843005491
Short name T439
Test name
Test status
Simulation time 61453058 ps
CPU time 3.29 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 215276 kb
Host smart-10e92db7-3b5e-48c4-a043-23f81da4ced9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843005491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2843005491
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1023956196
Short name T193
Test name
Test status
Simulation time 142970295 ps
CPU time 2.16 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:18 PM PDT 24
Peak memory 207376 kb
Host smart-3692a8a5-c21e-4567-b774-9bc0394e7b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023956196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1023956196
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1586634640
Short name T100
Test name
Test status
Simulation time 442790116 ps
CPU time 4.24 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 220044 kb
Host smart-e485a45a-1def-4db6-aa1b-57537d551a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586634640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1586634640
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2819660680
Short name T805
Test name
Test status
Simulation time 48532660 ps
CPU time 1.87 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 214328 kb
Host smart-72f38037-ef8a-412d-ac14-510c6f43967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819660680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2819660680
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2952896774
Short name T72
Test name
Test status
Simulation time 120569797 ps
CPU time 2.6 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:22 PM PDT 24
Peak memory 209496 kb
Host smart-bb033ad3-aa22-4deb-ae0f-a3994dd9a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952896774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2952896774
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3106437480
Short name T305
Test name
Test status
Simulation time 293818748 ps
CPU time 4.09 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 208136 kb
Host smart-0696caab-a16d-47a4-a9cd-827ed931a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106437480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3106437480
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3635484361
Short name T391
Test name
Test status
Simulation time 403077128 ps
CPU time 11.41 seconds
Started May 28 02:56:16 PM PDT 24
Finished May 28 02:56:31 PM PDT 24
Peak memory 208168 kb
Host smart-cc7abc4c-5340-4980-9516-282daaac5ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635484361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3635484361
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2443227447
Short name T327
Test name
Test status
Simulation time 36059894 ps
CPU time 2.49 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 208652 kb
Host smart-9850a0d8-df65-4744-bf46-128a734dd0e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443227447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2443227447
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1332848291
Short name T447
Test name
Test status
Simulation time 165450720 ps
CPU time 4.9 seconds
Started May 28 02:56:17 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 208776 kb
Host smart-9b0ed4e4-8d75-4e46-87b5-2f7bbcd0b4df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332848291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1332848291
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3601021997
Short name T766
Test name
Test status
Simulation time 201236069 ps
CPU time 5.83 seconds
Started May 28 02:56:22 PM PDT 24
Finished May 28 02:56:30 PM PDT 24
Peak memory 208588 kb
Host smart-bcbdb2a2-177f-458f-9a19-7e6cebf85fdc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601021997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3601021997
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.322946803
Short name T821
Test name
Test status
Simulation time 411395754 ps
CPU time 4.1 seconds
Started May 28 02:56:11 PM PDT 24
Finished May 28 02:56:19 PM PDT 24
Peak memory 208748 kb
Host smart-060f42e6-abd6-42e0-8a95-9770f4c0eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322946803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.322946803
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2122236585
Short name T837
Test name
Test status
Simulation time 639103498 ps
CPU time 3.92 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 206860 kb
Host smart-f5db76eb-3b4f-4411-ac9f-750b66880d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122236585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2122236585
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2907641537
Short name T134
Test name
Test status
Simulation time 1157894814 ps
CPU time 16.49 seconds
Started May 28 02:56:15 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 222640 kb
Host smart-e6189825-175c-44ee-bd33-f04f8e8a5a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907641537 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2907641537
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1772435746
Short name T864
Test name
Test status
Simulation time 1152030625 ps
CPU time 10.74 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:28 PM PDT 24
Peak memory 208596 kb
Host smart-e8879313-c154-4283-a4f3-bf912763fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772435746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1772435746
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4000558804
Short name T674
Test name
Test status
Simulation time 3217763647 ps
CPU time 18.27 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 211860 kb
Host smart-1727e6f9-6dcd-455e-9212-6305349a5683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000558804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4000558804
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1973470289
Short name T107
Test name
Test status
Simulation time 11192089 ps
CPU time 0.75 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 205996 kb
Host smart-1f0e7065-4563-42ac-89cc-d39d0028f214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973470289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1973470289
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.763569435
Short name T322
Test name
Test status
Simulation time 255988318 ps
CPU time 7.8 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:25 PM PDT 24
Peak memory 215772 kb
Host smart-02ad78f0-da1c-4c2b-95a2-4872d14b7314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763569435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.763569435
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3700456001
Short name T273
Test name
Test status
Simulation time 208075243 ps
CPU time 4.64 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 209752 kb
Host smart-c9ad183c-58c1-4ea6-b97a-a4bed196422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700456001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3700456001
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.587820147
Short name T346
Test name
Test status
Simulation time 403396641 ps
CPU time 4.26 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:31 PM PDT 24
Peak memory 221144 kb
Host smart-d2aa9c69-9f9b-4aba-b568-0a8c96d8ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587820147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.587820147
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.335117323
Short name T238
Test name
Test status
Simulation time 260683908 ps
CPU time 2.91 seconds
Started May 28 02:56:19 PM PDT 24
Finished May 28 02:56:24 PM PDT 24
Peak memory 209872 kb
Host smart-5291e334-a163-48ba-85cf-4d001e98ef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335117323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.335117323
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2543779532
Short name T640
Test name
Test status
Simulation time 59647973 ps
CPU time 3.64 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 210144 kb
Host smart-bfef6466-8063-49c0-8d2e-e30b48ccfcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543779532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2543779532
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2478568128
Short name T372
Test name
Test status
Simulation time 71359377 ps
CPU time 2.7 seconds
Started May 28 02:56:19 PM PDT 24
Finished May 28 02:56:24 PM PDT 24
Peak memory 208820 kb
Host smart-9e1c67a5-b9bd-4498-ae87-08f61f11d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478568128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2478568128
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3996316103
Short name T747
Test name
Test status
Simulation time 480834493 ps
CPU time 3.41 seconds
Started May 28 02:56:13 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 208940 kb
Host smart-8a0eb116-98d0-4511-8627-5a45c8cfac9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996316103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3996316103
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2963173656
Short name T359
Test name
Test status
Simulation time 135932486 ps
CPU time 3.07 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 207060 kb
Host smart-72fbe249-ae22-417f-b1a5-a182b80f1673
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963173656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2963173656
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3759718542
Short name T735
Test name
Test status
Simulation time 161263826 ps
CPU time 4.15 seconds
Started May 28 02:56:12 PM PDT 24
Finished May 28 02:56:20 PM PDT 24
Peak memory 206960 kb
Host smart-83df2a16-4f27-4ddf-bb55-c9cf53fb6a7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759718542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3759718542
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1894350574
Short name T670
Test name
Test status
Simulation time 36229594 ps
CPU time 2.31 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:28 PM PDT 24
Peak memory 218492 kb
Host smart-5ab1f701-416e-441c-a0ab-749925a0cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894350574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1894350574
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3957001061
Short name T583
Test name
Test status
Simulation time 307338112 ps
CPU time 5.28 seconds
Started May 28 02:56:14 PM PDT 24
Finished May 28 02:56:23 PM PDT 24
Peak memory 208728 kb
Host smart-5c074315-4404-46d1-998e-5eaa3675a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957001061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3957001061
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1842584163
Short name T784
Test name
Test status
Simulation time 308382028 ps
CPU time 8.52 seconds
Started May 28 02:56:30 PM PDT 24
Finished May 28 02:56:41 PM PDT 24
Peak memory 207924 kb
Host smart-2c653df3-02ba-46cb-9f32-c3c6f0088d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842584163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1842584163
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.791655738
Short name T406
Test name
Test status
Simulation time 457544073 ps
CPU time 2.94 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:30 PM PDT 24
Peak memory 209836 kb
Host smart-f9f00a72-6179-4a34-8088-bdcf98675b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791655738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.791655738
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4101591030
Short name T492
Test name
Test status
Simulation time 10893369 ps
CPU time 0.87 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:33 PM PDT 24
Peak memory 205980 kb
Host smart-9a34a5dd-6f24-4afe-a5ae-b933ca82a349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101591030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4101591030
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1099975510
Short name T251
Test name
Test status
Simulation time 322985560 ps
CPU time 17.26 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:52 PM PDT 24
Peak memory 214384 kb
Host smart-e8faa328-489c-404e-b97d-168e002607da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099975510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1099975510
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1174485506
Short name T42
Test name
Test status
Simulation time 427889787 ps
CPU time 4.34 seconds
Started May 28 02:56:25 PM PDT 24
Finished May 28 02:56:32 PM PDT 24
Peak memory 209372 kb
Host smart-a879be73-6bc4-445c-a868-93cc5b51d689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174485506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1174485506
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2758525712
Short name T912
Test name
Test status
Simulation time 180170932 ps
CPU time 4.67 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:37 PM PDT 24
Peak memory 214360 kb
Host smart-8d84a7fa-8da5-4a32-967f-47558f53fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758525712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2758525712
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3283536191
Short name T345
Test name
Test status
Simulation time 64299390 ps
CPU time 3.77 seconds
Started May 28 02:56:25 PM PDT 24
Finished May 28 02:56:31 PM PDT 24
Peak memory 215192 kb
Host smart-00caa848-e2ea-4be4-b940-b55a569a3458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283536191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3283536191
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1534660233
Short name T545
Test name
Test status
Simulation time 77295387 ps
CPU time 2.69 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 215308 kb
Host smart-4648b329-ed8b-4161-b412-fec33724172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534660233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1534660233
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3037684581
Short name T1
Test name
Test status
Simulation time 1463835329 ps
CPU time 15.93 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:48 PM PDT 24
Peak memory 209656 kb
Host smart-d78f3315-16e9-4d88-819c-ecd5774303b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037684581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3037684581
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2226363151
Short name T586
Test name
Test status
Simulation time 877090928 ps
CPU time 6.37 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:41 PM PDT 24
Peak memory 208784 kb
Host smart-739c5c44-7cf3-4d18-bdd8-3c4edab3ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226363151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2226363151
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.175796320
Short name T449
Test name
Test status
Simulation time 608209907 ps
CPU time 2.54 seconds
Started May 28 02:56:25 PM PDT 24
Finished May 28 02:56:30 PM PDT 24
Peak memory 206868 kb
Host smart-7f638fda-5abe-4a25-af88-888c8d44a87d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175796320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.175796320
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3842580908
Short name T690
Test name
Test status
Simulation time 688577120 ps
CPU time 9.92 seconds
Started May 28 02:56:25 PM PDT 24
Finished May 28 02:56:37 PM PDT 24
Peak memory 208648 kb
Host smart-48fc1902-916c-4690-aee6-9f4df9852e41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842580908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3842580908
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1484144258
Short name T752
Test name
Test status
Simulation time 313630596 ps
CPU time 3.71 seconds
Started May 28 02:56:27 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 208640 kb
Host smart-9765b9b7-e0eb-4a59-b1f5-a3287169a8cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484144258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1484144258
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4254064914
Short name T705
Test name
Test status
Simulation time 30554343 ps
CPU time 1.56 seconds
Started May 28 02:56:23 PM PDT 24
Finished May 28 02:56:26 PM PDT 24
Peak memory 208624 kb
Host smart-1182799c-076a-44c9-8320-34f6c11d261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254064914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4254064914
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1821382181
Short name T618
Test name
Test status
Simulation time 174485203 ps
CPU time 2.34 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:37 PM PDT 24
Peak memory 206968 kb
Host smart-a8431587-6b38-437d-ae53-03ef61458b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821382181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1821382181
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2188670724
Short name T895
Test name
Test status
Simulation time 3309617119 ps
CPU time 36.92 seconds
Started May 28 02:56:26 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 222364 kb
Host smart-2244b9ab-f803-4822-a805-36c1d0210875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188670724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2188670724
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3759129027
Short name T185
Test name
Test status
Simulation time 465135549 ps
CPU time 14.44 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:49 PM PDT 24
Peak memory 223628 kb
Host smart-8630a612-9bb7-4dba-9b61-feddff4a9817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759129027 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3759129027
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.466573131
Short name T324
Test name
Test status
Simulation time 1085370531 ps
CPU time 33.45 seconds
Started May 28 02:56:30 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 218436 kb
Host smart-09863fd3-1498-4d9e-8547-3d6db69998b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466573131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.466573131
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2700977172
Short name T906
Test name
Test status
Simulation time 71206328 ps
CPU time 2.85 seconds
Started May 28 02:56:30 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 210184 kb
Host smart-6799a3eb-9c10-45d2-a254-90391445130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700977172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2700977172
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2249325196
Short name T558
Test name
Test status
Simulation time 8859006 ps
CPU time 0.79 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:33 PM PDT 24
Peak memory 205984 kb
Host smart-44ff916e-1ee9-4e4e-b7e0-1e5007a1cc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249325196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2249325196
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1305389170
Short name T250
Test name
Test status
Simulation time 116590395 ps
CPU time 4.02 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 215212 kb
Host smart-005899bb-a112-41aa-9b11-d88674c62fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305389170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1305389170
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3050710058
Short name T33
Test name
Test status
Simulation time 61810984 ps
CPU time 2.38 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:28 PM PDT 24
Peak memory 216100 kb
Host smart-5098688d-ef57-4f20-88c6-860c62e98f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050710058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3050710058
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2626086231
Short name T36
Test name
Test status
Simulation time 757334883 ps
CPU time 22.72 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 208492 kb
Host smart-441812f6-81c0-4d44-be87-0c66be9e2581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626086231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2626086231
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2268721847
Short name T403
Test name
Test status
Simulation time 59479173 ps
CPU time 3.85 seconds
Started May 28 02:56:25 PM PDT 24
Finished May 28 02:56:31 PM PDT 24
Peak memory 222420 kb
Host smart-2247003a-253f-4202-b4d3-0bdbfba3926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268721847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2268721847
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.1735567787
Short name T692
Test name
Test status
Simulation time 199381864 ps
CPU time 3.27 seconds
Started May 28 02:56:27 PM PDT 24
Finished May 28 02:56:33 PM PDT 24
Peak memory 208300 kb
Host smart-02900617-2b37-4ce2-95a4-5f4d650a32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735567787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1735567787
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.565464135
Short name T632
Test name
Test status
Simulation time 41057117 ps
CPU time 2.78 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 208900 kb
Host smart-13b05ce8-410c-4b7d-b4b3-92b6e450e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565464135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.565464135
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3081003862
Short name T840
Test name
Test status
Simulation time 48486306 ps
CPU time 2.65 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 206964 kb
Host smart-7a0b62bc-d9af-45c3-851c-6bf4759fdd52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081003862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3081003862
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3852408891
Short name T212
Test name
Test status
Simulation time 281260057 ps
CPU time 2.81 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 206888 kb
Host smart-afa82abe-8c44-473a-b1bf-6f1ccb8a4a3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852408891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3852408891
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.876215554
Short name T427
Test name
Test status
Simulation time 91216700 ps
CPU time 2.35 seconds
Started May 28 02:56:26 PM PDT 24
Finished May 28 02:56:30 PM PDT 24
Peak memory 207020 kb
Host smart-ab451e99-ade1-4d00-827a-6b87dd79501d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876215554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.876215554
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.893265776
Short name T308
Test name
Test status
Simulation time 297302471 ps
CPU time 4.68 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:37 PM PDT 24
Peak memory 214380 kb
Host smart-e12b6a15-e7a0-4f8b-ae50-9fc0a87e3b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893265776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.893265776
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1343734494
Short name T495
Test name
Test status
Simulation time 293685764 ps
CPU time 4.44 seconds
Started May 28 02:56:34 PM PDT 24
Finished May 28 02:56:40 PM PDT 24
Peak memory 208436 kb
Host smart-34563443-288c-4a1c-89de-738c2621eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343734494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1343734494
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1052971934
Short name T69
Test name
Test status
Simulation time 1554545032 ps
CPU time 15.62 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:48 PM PDT 24
Peak memory 216392 kb
Host smart-26594399-d554-496c-ab46-fed86fa56f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052971934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1052971934
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1087395711
Short name T802
Test name
Test status
Simulation time 380569866 ps
CPU time 18.07 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 222660 kb
Host smart-df52645c-3533-4dc9-b581-aff1144ea83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087395711 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1087395711
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2708112449
Short name T414
Test name
Test status
Simulation time 2000356700 ps
CPU time 12.53 seconds
Started May 28 02:56:24 PM PDT 24
Finished May 28 02:56:39 PM PDT 24
Peak memory 209292 kb
Host smart-847148d5-52c6-4231-a07d-6c782445a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708112449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2708112449
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3856614061
Short name T827
Test name
Test status
Simulation time 32759620 ps
CPU time 1.97 seconds
Started May 28 02:56:30 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 210276 kb
Host smart-93a66553-05e4-4929-84dd-fc3cfe27f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856614061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3856614061
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1067483067
Short name T482
Test name
Test status
Simulation time 13686963 ps
CPU time 0.77 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:45 PM PDT 24
Peak memory 205968 kb
Host smart-da0ad5af-72a3-4c9f-a0ec-5af2ae05946f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067483067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1067483067
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2115949817
Short name T254
Test name
Test status
Simulation time 32131460 ps
CPU time 2.55 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 215008 kb
Host smart-a8c6798a-168b-4544-b925-972a44977f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115949817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2115949817
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1102459087
Short name T28
Test name
Test status
Simulation time 452458510 ps
CPU time 3.77 seconds
Started May 28 02:56:32 PM PDT 24
Finished May 28 02:56:38 PM PDT 24
Peak memory 222776 kb
Host smart-db6909ea-b45d-4fc8-9b4d-fe7da93c1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102459087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1102459087
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3938322488
Short name T256
Test name
Test status
Simulation time 53826923 ps
CPU time 2.58 seconds
Started May 28 02:56:22 PM PDT 24
Finished May 28 02:56:26 PM PDT 24
Peak memory 209416 kb
Host smart-1a2c55cb-afb3-4ac6-9988-94aadf5297c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938322488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3938322488
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1268447998
Short name T195
Test name
Test status
Simulation time 264990249 ps
CPU time 3.84 seconds
Started May 28 02:56:32 PM PDT 24
Finished May 28 02:56:38 PM PDT 24
Peak memory 214392 kb
Host smart-e12b898a-ead7-4a9d-a729-02678abbb29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268447998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1268447998
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3139840876
Short name T361
Test name
Test status
Simulation time 76599711 ps
CPU time 4.1 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 219988 kb
Host smart-b10b57d5-7283-49b0-9cab-71c84ff8156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139840876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3139840876
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3399818429
Short name T535
Test name
Test status
Simulation time 148784528 ps
CPU time 2.76 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:36 PM PDT 24
Peak memory 220548 kb
Host smart-b1ee10ec-ba0c-44c4-96cb-b67de7557dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399818429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3399818429
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.340647770
Short name T637
Test name
Test status
Simulation time 319204120 ps
CPU time 7.22 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:39 PM PDT 24
Peak memory 210224 kb
Host smart-31f05521-8290-4867-a46c-eab7868e6c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340647770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.340647770
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2785044568
Short name T709
Test name
Test status
Simulation time 52216817 ps
CPU time 3.01 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 207392 kb
Host smart-b64ca9e3-8f69-4da7-b812-791129013f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785044568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2785044568
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3700211897
Short name T621
Test name
Test status
Simulation time 767556774 ps
CPU time 9.76 seconds
Started May 28 02:56:33 PM PDT 24
Finished May 28 02:56:44 PM PDT 24
Peak memory 209180 kb
Host smart-8cfa257e-a1e8-44e5-8068-04547d08c5e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700211897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3700211897
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3289147294
Short name T610
Test name
Test status
Simulation time 3801767377 ps
CPU time 26.02 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:59 PM PDT 24
Peak memory 208352 kb
Host smart-7fb244c5-2c32-4f52-a327-43d8f235fcfb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289147294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3289147294
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1215522150
Short name T137
Test name
Test status
Simulation time 13731308223 ps
CPU time 67.53 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 208300 kb
Host smart-7d2fef0d-82d2-4e2b-8690-3430bb1971a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215522150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1215522150
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3833239186
Short name T443
Test name
Test status
Simulation time 5976967568 ps
CPU time 14.23 seconds
Started May 28 02:56:26 PM PDT 24
Finished May 28 02:56:42 PM PDT 24
Peak memory 216808 kb
Host smart-79127d63-b704-4592-b451-627ef975f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833239186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3833239186
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4041353803
Short name T675
Test name
Test status
Simulation time 1439576684 ps
CPU time 13.91 seconds
Started May 28 02:56:29 PM PDT 24
Finished May 28 02:56:46 PM PDT 24
Peak memory 208540 kb
Host smart-cc3f22bd-b965-4c49-bd09-7f94f7d7f305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041353803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4041353803
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3071911005
Short name T718
Test name
Test status
Simulation time 209448475 ps
CPU time 3.37 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:41 PM PDT 24
Peak memory 208296 kb
Host smart-62868881-d4a6-4939-8cc9-657b40a5c205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071911005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3071911005
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2166098412
Short name T778
Test name
Test status
Simulation time 1756260425 ps
CPU time 18.56 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 222788 kb
Host smart-19090748-87cd-4a89-a7ae-c65dbc56bee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166098412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2166098412
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3783766759
Short name T259
Test name
Test status
Simulation time 99166362 ps
CPU time 2.76 seconds
Started May 28 02:56:28 PM PDT 24
Finished May 28 02:56:35 PM PDT 24
Peak memory 209748 kb
Host smart-60c34985-5073-472f-96d3-8b9434e50da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783766759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3783766759
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4126993536
Short name T818
Test name
Test status
Simulation time 579851971 ps
CPU time 6 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 211184 kb
Host smart-02819331-43c6-4d2b-9235-c37fea939f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126993536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4126993536
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2047238866
Short name T684
Test name
Test status
Simulation time 49258925 ps
CPU time 0.77 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:45 PM PDT 24
Peak memory 206008 kb
Host smart-039b68cb-d962-4a93-9671-8094e5e2f1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047238866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2047238866
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2593055502
Short name T438
Test name
Test status
Simulation time 147652797 ps
CPU time 3.52 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:44 PM PDT 24
Peak memory 215524 kb
Host smart-6a893074-e0bb-4dfa-98da-1e58b3022c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593055502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2593055502
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3705270284
Short name T815
Test name
Test status
Simulation time 221078605 ps
CPU time 2.23 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:44 PM PDT 24
Peak memory 207716 kb
Host smart-9f99bad8-fec7-4b4a-8385-d1dd94dd8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705270284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3705270284
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3511130740
Short name T283
Test name
Test status
Simulation time 238875052 ps
CPU time 2.11 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:47 PM PDT 24
Peak memory 214384 kb
Host smart-779ee8d7-8f20-4d39-8f44-876e2bab714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511130740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3511130740
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.516543760
Short name T615
Test name
Test status
Simulation time 43984302 ps
CPU time 2.57 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 220928 kb
Host smart-8f074c0f-8bbf-416d-a52e-4fa3b3da7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516543760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.516543760
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3339887512
Short name T770
Test name
Test status
Simulation time 154786100 ps
CPU time 2.61 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 209508 kb
Host smart-16a16094-b79b-4df0-ae9b-7879b9ea4137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339887512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3339887512
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.261153063
Short name T133
Test name
Test status
Simulation time 1206297361 ps
CPU time 4.85 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 210100 kb
Host smart-16664eea-eaae-49d0-a7ec-a201ccc68008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261153063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.261153063
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.427267029
Short name T661
Test name
Test status
Simulation time 709473278 ps
CPU time 2.65 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:47 PM PDT 24
Peak memory 208180 kb
Host smart-dabca259-121b-44c0-ae03-842c7ccd3abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427267029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.427267029
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1614003483
Short name T678
Test name
Test status
Simulation time 478359650 ps
CPU time 4.52 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:44 PM PDT 24
Peak memory 207000 kb
Host smart-92b8d6b7-60a5-464e-b23c-7f55b3c007dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614003483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1614003483
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.328916997
Short name T908
Test name
Test status
Simulation time 32660878 ps
CPU time 2.29 seconds
Started May 28 02:56:36 PM PDT 24
Finished May 28 02:56:39 PM PDT 24
Peak memory 208584 kb
Host smart-ef993558-93d9-418f-bef9-7277406babaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328916997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.328916997
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1802887836
Short name T470
Test name
Test status
Simulation time 453657184 ps
CPU time 6.25 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 208432 kb
Host smart-25dbf862-776c-4796-98ca-5dda4fa5713f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802887836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1802887836
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2787215349
Short name T498
Test name
Test status
Simulation time 1570796650 ps
CPU time 7.97 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 209000 kb
Host smart-66521b2b-efb6-44c6-9d10-9cb8cc826ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787215349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2787215349
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3209240310
Short name T464
Test name
Test status
Simulation time 76231912 ps
CPU time 1.57 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 206960 kb
Host smart-bcfdcb75-d179-407a-a1e7-0f8f54b41de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209240310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3209240310
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.463386264
Short name T293
Test name
Test status
Simulation time 1634474038 ps
CPU time 32.14 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 215596 kb
Host smart-3b3a25d1-7af4-4a86-930b-0621394eb0bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463386264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.463386264
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1335887438
Short name T289
Test name
Test status
Simulation time 179854572 ps
CPU time 7.15 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:58 PM PDT 24
Peak memory 218536 kb
Host smart-7145d13c-48ee-4a9f-b1ee-e7a4cc15a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335887438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1335887438
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2273848741
Short name T162
Test name
Test status
Simulation time 331093527 ps
CPU time 2.48 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:43 PM PDT 24
Peak memory 210172 kb
Host smart-5e8a7052-f2f6-4975-86bc-40a228c5f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273848741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2273848741
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3687230561
Short name T503
Test name
Test status
Simulation time 58646784 ps
CPU time 0.92 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 206160 kb
Host smart-9eecad93-7f17-4b7d-881e-be49c4632aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687230561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3687230561
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1723479280
Short name T236
Test name
Test status
Simulation time 221714822 ps
CPU time 3.24 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 221964 kb
Host smart-a25774a4-1d06-4d88-84b9-fbb84a9290b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723479280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1723479280
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1964092071
Short name T859
Test name
Test status
Simulation time 554438533 ps
CPU time 16.42 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 218436 kb
Host smart-8d817083-ff0d-475a-ad86-ef3c251d0358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964092071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1964092071
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3055812719
Short name T797
Test name
Test status
Simulation time 31235168 ps
CPU time 2.02 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:52 PM PDT 24
Peak memory 214372 kb
Host smart-6b65b420-3121-421b-b8fb-aea28c764bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055812719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3055812719
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1219497968
Short name T63
Test name
Test status
Simulation time 325675853 ps
CPU time 8.95 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:59 PM PDT 24
Peak memory 214340 kb
Host smart-d3acb6f6-c151-4e7f-bce1-a65a05354dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219497968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1219497968
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2139876831
Short name T899
Test name
Test status
Simulation time 51740699 ps
CPU time 2.59 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 218972 kb
Host smart-27fe481e-c369-4f70-8d2a-26391bc3fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139876831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2139876831
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4004837444
Short name T643
Test name
Test status
Simulation time 268775109 ps
CPU time 4.85 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:46 PM PDT 24
Peak memory 218476 kb
Host smart-da912c98-078d-4187-97b4-a46132acd858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004837444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4004837444
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2942701115
Short name T221
Test name
Test status
Simulation time 504816374 ps
CPU time 6.62 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:45 PM PDT 24
Peak memory 208580 kb
Host smart-13690a65-45cf-4a15-b372-094b15d14358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942701115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2942701115
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3753697972
Short name T11
Test name
Test status
Simulation time 1629400176 ps
CPU time 39.77 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:57:28 PM PDT 24
Peak memory 208792 kb
Host smart-33acf68f-2313-4612-a244-206781092ffb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753697972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3753697972
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2419697253
Short name T636
Test name
Test status
Simulation time 35639445 ps
CPU time 2.11 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 208796 kb
Host smart-bb476a06-932c-43a9-b9fc-de67bcdc8b7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419697253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2419697253
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3410297751
Short name T799
Test name
Test status
Simulation time 194995792 ps
CPU time 4.36 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:47 PM PDT 24
Peak memory 210012 kb
Host smart-a310b0cf-12d4-4096-97af-3b7e46968f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410297751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3410297751
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1726671330
Short name T514
Test name
Test status
Simulation time 358578102 ps
CPU time 2.92 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 206732 kb
Host smart-24c81a14-708f-4b3f-a1b5-48835496a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726671330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1726671330
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2503794848
Short name T782
Test name
Test status
Simulation time 1005013426 ps
CPU time 6.94 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:52 PM PDT 24
Peak memory 208620 kb
Host smart-a458b26a-0d31-409e-9543-74cc7d18bfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503794848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2503794848
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.533720499
Short name T553
Test name
Test status
Simulation time 27864794 ps
CPU time 0.76 seconds
Started May 28 02:57:00 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 205996 kb
Host smart-10d24064-ef25-40af-a837-f1f78f00f883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533720499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.533720499
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3089449890
Short name T43
Test name
Test status
Simulation time 781963041 ps
CPU time 22.31 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:57:08 PM PDT 24
Peak memory 214372 kb
Host smart-2a0873a9-620f-46a6-9363-41c286cb6544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089449890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3089449890
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.902639698
Short name T112
Test name
Test status
Simulation time 53375654 ps
CPU time 2.61 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 218452 kb
Host smart-b0ae1193-087d-425a-a85e-ab1526899e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902639698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.902639698
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2762794219
Short name T105
Test name
Test status
Simulation time 3631711312 ps
CPU time 18.92 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 222512 kb
Host smart-a06343a2-901e-48d2-8aa2-fb0725cc5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762794219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2762794219
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1727412660
Short name T347
Test name
Test status
Simulation time 270629620 ps
CPU time 3.53 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 221500 kb
Host smart-dbee172c-406a-456d-bf5f-193a4bff8e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727412660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1727412660
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1945491290
Short name T487
Test name
Test status
Simulation time 115203408 ps
CPU time 2.33 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:44 PM PDT 24
Peak memory 208336 kb
Host smart-b3e0dca5-3d4f-40dd-a760-2e6860ee1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945491290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1945491290
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.835610525
Short name T604
Test name
Test status
Simulation time 305034508 ps
CPU time 4.25 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:48 PM PDT 24
Peak memory 207652 kb
Host smart-bb51fcc4-b18b-4838-81df-fb96a401db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835610525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.835610525
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3155773635
Short name T720
Test name
Test status
Simulation time 74978769 ps
CPU time 2.67 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 206960 kb
Host smart-1784fe18-ef0b-494b-bdd0-7a485ad319b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155773635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3155773635
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2633967410
Short name T258
Test name
Test status
Simulation time 45305483 ps
CPU time 1.9 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 207088 kb
Host smart-adefacfe-17aa-4052-a25d-121caa5a633b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633967410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2633967410
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2354741176
Short name T533
Test name
Test status
Simulation time 213633874 ps
CPU time 4.36 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 209108 kb
Host smart-144701b7-4af7-48eb-8056-c04ccd087b98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354741176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2354741176
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.827792278
Short name T597
Test name
Test status
Simulation time 152064115 ps
CPU time 1.94 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:43 PM PDT 24
Peak memory 207028 kb
Host smart-2a7c4e2c-8396-4104-b008-b051069df2cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827792278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.827792278
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.769856624
Short name T420
Test name
Test status
Simulation time 332568110 ps
CPU time 4.19 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 215916 kb
Host smart-5ec69628-f6b9-492f-9953-b5d944a7f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769856624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.769856624
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1944654048
Short name T524
Test name
Test status
Simulation time 191937610 ps
CPU time 2.75 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 207364 kb
Host smart-8f5cdb8c-544e-4875-a123-fa541a5f6e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944654048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1944654048
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3168940764
Short name T62
Test name
Test status
Simulation time 306432030 ps
CPU time 15.03 seconds
Started May 28 02:56:35 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 215116 kb
Host smart-76694c8a-7cf8-4a08-89d2-5368af594c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168940764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3168940764
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1729668868
Short name T365
Test name
Test status
Simulation time 670150910 ps
CPU time 6.01 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 214484 kb
Host smart-6cf0538d-3bbb-415f-b15f-7c138a91e887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729668868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1729668868
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.901558901
Short name T792
Test name
Test status
Simulation time 1109677018 ps
CPU time 10.3 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 210920 kb
Host smart-7e00b4d7-d154-4e33-9259-e7cd9606d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901558901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.901558901
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.565055313
Short name T505
Test name
Test status
Simulation time 15915544 ps
CPU time 0.77 seconds
Started May 28 02:56:45 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 206012 kb
Host smart-6587c535-3965-42bc-a570-78f6676ea07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565055313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.565055313
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2314135279
Short name T268
Test name
Test status
Simulation time 283987785 ps
CPU time 5.59 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:52 PM PDT 24
Peak memory 214712 kb
Host smart-21708fb8-74b4-43e6-a6bb-8c13eb3ebcb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314135279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2314135279
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3841569308
Short name T73
Test name
Test status
Simulation time 144251064 ps
CPU time 2.52 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:47 PM PDT 24
Peak memory 221256 kb
Host smart-02c5f03e-2645-481c-adf4-eae01835ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841569308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3841569308
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.889407731
Short name T421
Test name
Test status
Simulation time 1022249940 ps
CPU time 18.76 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 214384 kb
Host smart-6723a616-a960-4195-bf69-102263cfb9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889407731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.889407731
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3721594651
Short name T465
Test name
Test status
Simulation time 265649800 ps
CPU time 4.81 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 214484 kb
Host smart-57a80d63-1a0e-4017-b45f-9e5baa6e6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721594651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3721594651
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1153147441
Short name T857
Test name
Test status
Simulation time 207088336 ps
CPU time 3.14 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 214344 kb
Host smart-5b7a9196-b58d-464f-bc20-703d920d15b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153147441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1153147441
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1148500057
Short name T683
Test name
Test status
Simulation time 798196403 ps
CPU time 4.75 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 210400 kb
Host smart-dcc4ae83-24bf-4c04-a114-b47e0e002324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148500057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1148500057
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.688879822
Short name T215
Test name
Test status
Simulation time 179166461 ps
CPU time 5.73 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 218284 kb
Host smart-579ccf46-0f43-4080-84c6-75d9cd395ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688879822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.688879822
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3569142927
Short name T115
Test name
Test status
Simulation time 126829869 ps
CPU time 3.52 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 208176 kb
Host smart-18cdb14c-1d51-4b02-9c39-1b5015bc88e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569142927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3569142927
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.506645707
Short name T37
Test name
Test status
Simulation time 172606408 ps
CPU time 6.54 seconds
Started May 28 02:57:00 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 208720 kb
Host smart-d92c47a9-300e-4614-9009-745e499e4ba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506645707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.506645707
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1052227748
Short name T807
Test name
Test status
Simulation time 2699659268 ps
CPU time 28.89 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 208628 kb
Host smart-828ba3b6-0eb5-435d-b298-44d4d92654ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052227748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1052227748
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.188740922
Short name T672
Test name
Test status
Simulation time 230023290 ps
CPU time 2.25 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 207032 kb
Host smart-4d3da49c-301f-4e7c-b4ca-a3efb3d2cf6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188740922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.188740922
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3694888020
Short name T776
Test name
Test status
Simulation time 152093080 ps
CPU time 2.02 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 209152 kb
Host smart-6aa0ae53-075d-465f-b18e-d4bfe68a8d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694888020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3694888020
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1644277633
Short name T536
Test name
Test status
Simulation time 59290064 ps
CPU time 2.65 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:49 PM PDT 24
Peak memory 208472 kb
Host smart-5be366bb-869c-46a5-8205-5a1c631b5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644277633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1644277633
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.309934114
Short name T269
Test name
Test status
Simulation time 3283089036 ps
CPU time 13.53 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 220888 kb
Host smart-e6719a41-ee4c-48f3-baf0-89e2fce87b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309934114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.309934114
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2083296470
Short name T113
Test name
Test status
Simulation time 174524625 ps
CPU time 4.78 seconds
Started May 28 02:58:26 PM PDT 24
Finished May 28 02:58:51 PM PDT 24
Peak memory 218540 kb
Host smart-b21ff34a-80fd-4873-b95b-4874347302ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083296470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2083296470
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1884896341
Short name T502
Test name
Test status
Simulation time 4496608334 ps
CPU time 27.32 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 211516 kb
Host smart-9ba81510-cfc6-4de9-a845-3f57118393b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884896341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1884896341
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2716821708
Short name T209
Test name
Test status
Simulation time 43501555 ps
CPU time 0.74 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 205952 kb
Host smart-0de56aec-eac6-4611-8f89-ef96b0a45972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716821708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2716821708
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3372555799
Short name T796
Test name
Test status
Simulation time 314524974 ps
CPU time 2.94 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:39 PM PDT 24
Peak memory 214384 kb
Host smart-a498439a-3dd5-4381-8a2e-e6514ab5f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372555799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3372555799
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3933261935
Short name T377
Test name
Test status
Simulation time 779678065 ps
CPU time 19.11 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 218092 kb
Host smart-4ed9b788-0e52-4523-b170-0d1b884145ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933261935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3933261935
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3909330896
Short name T911
Test name
Test status
Simulation time 145417030 ps
CPU time 2.6 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:29 PM PDT 24
Peak memory 222284 kb
Host smart-b9c5449c-2007-44ef-a456-36c4b84c86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909330896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3909330896
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2998494339
Short name T229
Test name
Test status
Simulation time 506606031 ps
CPU time 2.06 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 214372 kb
Host smart-97b138f7-c39b-4326-86df-d13a79050fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998494339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2998494339
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4102528367
Short name T663
Test name
Test status
Simulation time 397260807 ps
CPU time 4.98 seconds
Started May 28 02:55:18 PM PDT 24
Finished May 28 02:55:29 PM PDT 24
Peak memory 207440 kb
Host smart-bd7f14fa-28b6-4205-a83d-4e817ad99bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102528367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4102528367
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.970783055
Short name T278
Test name
Test status
Simulation time 5773125145 ps
CPU time 32.57 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:56:00 PM PDT 24
Peak memory 207972 kb
Host smart-216fa0bf-9c49-4e7e-b721-3e70ffa2cb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970783055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.970783055
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3863872174
Short name T813
Test name
Test status
Simulation time 85818608 ps
CPU time 3.91 seconds
Started May 28 02:55:19 PM PDT 24
Finished May 28 02:55:30 PM PDT 24
Peak memory 208736 kb
Host smart-ca9daa6b-01d1-489e-a932-79189681c946
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863872174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3863872174
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.743215167
Short name T328
Test name
Test status
Simulation time 205002677 ps
CPU time 2.83 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:42 PM PDT 24
Peak memory 208904 kb
Host smart-7366e676-6903-42e3-a567-e5c376efd22f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743215167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.743215167
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.610793405
Short name T896
Test name
Test status
Simulation time 97761366 ps
CPU time 2.24 seconds
Started May 28 02:55:18 PM PDT 24
Finished May 28 02:55:27 PM PDT 24
Peak memory 208868 kb
Host smart-53cb78da-862f-40cf-9379-2fa8ae2b8ccd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610793405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.610793405
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4289780150
Short name T436
Test name
Test status
Simulation time 131131184 ps
CPU time 3.99 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 222632 kb
Host smart-33c8d2c3-1594-4ff6-aa76-02a10f31c685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289780150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4289780150
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.58903458
Short name T562
Test name
Test status
Simulation time 55725633 ps
CPU time 2.03 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:55:31 PM PDT 24
Peak memory 206884 kb
Host smart-36d967e5-b831-41b9-8ba7-967fb1039fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58903458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.58903458
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3521309399
Short name T653
Test name
Test status
Simulation time 444754806 ps
CPU time 17.86 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 222532 kb
Host smart-46af20bf-5eb3-4188-9548-9bd99d1371d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521309399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3521309399
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3070458374
Short name T760
Test name
Test status
Simulation time 417758900 ps
CPU time 8.04 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:45 PM PDT 24
Peak memory 222612 kb
Host smart-ad69f54a-6a85-4657-88c6-0a158e062824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070458374 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3070458374
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2775452246
Short name T892
Test name
Test status
Simulation time 384053475 ps
CPU time 7.22 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 218476 kb
Host smart-23db6ad8-d1c9-4364-a3af-e0f3eee704d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775452246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2775452246
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1311116808
Short name T725
Test name
Test status
Simulation time 91138980 ps
CPU time 2.65 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 210096 kb
Host smart-4ff13cfa-04b5-48a8-a269-fec272ab956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311116808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1311116808
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3746544367
Short name T605
Test name
Test status
Simulation time 25762932 ps
CPU time 0.77 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 206004 kb
Host smart-91227e10-a742-4c73-a4c1-ff388c1e83e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746544367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3746544367
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2136086800
Short name T437
Test name
Test status
Simulation time 9042319706 ps
CPU time 104.08 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:58:39 PM PDT 24
Peak memory 214444 kb
Host smart-5c1a86bf-269a-4682-a6a1-a75c1ee8e782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136086800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2136086800
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2337514651
Short name T32
Test name
Test status
Simulation time 542533627 ps
CPU time 3.92 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 208888 kb
Host smart-ec0df879-b2a1-4891-8e09-aef03fcf895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337514651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2337514651
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1213130943
Short name T878
Test name
Test status
Simulation time 455814106 ps
CPU time 5.54 seconds
Started May 28 02:58:23 PM PDT 24
Finished May 28 02:58:49 PM PDT 24
Peak memory 209156 kb
Host smart-31ed51f7-bc51-48f7-877e-7420df361b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213130943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1213130943
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3681184839
Short name T23
Test name
Test status
Simulation time 238794699 ps
CPU time 5.17 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:57 PM PDT 24
Peak memory 214480 kb
Host smart-3eaa30d3-ea58-4438-b991-26d760ba0511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681184839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3681184839
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.645208566
Short name T232
Test name
Test status
Simulation time 65906316 ps
CPU time 2.66 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 215052 kb
Host smart-9e6c7ca3-cc61-4898-962e-8784d70d9f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645208566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.645208566
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2676449292
Short name T476
Test name
Test status
Simulation time 116967690 ps
CPU time 2 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 207556 kb
Host smart-0eb52257-3126-4b79-9438-c782b1a3e7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676449292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2676449292
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.4005509916
Short name T500
Test name
Test status
Simulation time 495352249 ps
CPU time 4.51 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 208664 kb
Host smart-a407e050-e6f5-4c04-a0f1-bb69bc83df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005509916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4005509916
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2312752638
Short name T484
Test name
Test status
Simulation time 293301272 ps
CPU time 3.54 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:56 PM PDT 24
Peak memory 207040 kb
Host smart-54e10a2b-3f63-42ae-86a6-ded7e66f5ade
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312752638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2312752638
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1003987899
Short name T549
Test name
Test status
Simulation time 94134602 ps
CPU time 1.82 seconds
Started May 28 02:58:23 PM PDT 24
Finished May 28 02:58:46 PM PDT 24
Peak memory 207412 kb
Host smart-48859233-890d-4a6e-8583-2b14f126bed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003987899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1003987899
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.4094682447
Short name T588
Test name
Test status
Simulation time 131991907 ps
CPU time 2.42 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 207388 kb
Host smart-a85cc1c6-5ea1-401c-9d79-3671ae54c51e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094682447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4094682447
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2133853828
Short name T435
Test name
Test status
Simulation time 24830982 ps
CPU time 1.81 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:54 PM PDT 24
Peak memory 209272 kb
Host smart-6d88c84c-d080-47df-a2bd-6abf7abe140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133853828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2133853828
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.41093743
Short name T83
Test name
Test status
Simulation time 151985480 ps
CPU time 3.12 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 208488 kb
Host smart-e500b694-1846-4339-a2a6-8c310903365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41093743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.41093743
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1092863515
Short name T613
Test name
Test status
Simulation time 153256657 ps
CPU time 2.52 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 207672 kb
Host smart-1d55bec6-3951-4784-826d-f92b3f6a893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092863515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1092863515
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3407090943
Short name T192
Test name
Test status
Simulation time 788777366 ps
CPU time 2.18 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 210264 kb
Host smart-24969828-395a-44ff-8aa9-27fcdfd8a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407090943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3407090943
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3294839538
Short name T847
Test name
Test status
Simulation time 40692218 ps
CPU time 0.73 seconds
Started May 28 02:56:38 PM PDT 24
Finished May 28 02:56:42 PM PDT 24
Peak memory 205888 kb
Host smart-a4bccd39-99e7-43bb-92ca-411705b6b733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294839538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3294839538
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1472795109
Short name T252
Test name
Test status
Simulation time 32398888 ps
CPU time 2.43 seconds
Started May 28 02:56:47 PM PDT 24
Finished May 28 02:56:58 PM PDT 24
Peak memory 214460 kb
Host smart-8da0594a-8d3a-4db4-951e-906b082f2a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472795109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1472795109
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1714092255
Short name T240
Test name
Test status
Simulation time 107377892 ps
CPU time 3.12 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 210580 kb
Host smart-8d657c15-a8d5-4793-b5c7-b47d6e0adef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714092255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1714092255
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4102320853
Short name T496
Test name
Test status
Simulation time 140696824 ps
CPU time 3.3 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:56:58 PM PDT 24
Peak memory 210392 kb
Host smart-eaf7cf9b-eae7-4131-8d91-867ab98a14d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102320853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4102320853
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.963702955
Short name T97
Test name
Test status
Simulation time 100477986 ps
CPU time 3.55 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:56:58 PM PDT 24
Peak memory 208764 kb
Host smart-aee364bf-03e2-49c5-8d65-ffda2474b92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963702955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.963702955
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3768706507
Short name T362
Test name
Test status
Simulation time 697910819 ps
CPU time 5.4 seconds
Started May 28 02:56:47 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 222524 kb
Host smart-bd8c23d6-077b-4100-ad45-5501d28d838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768706507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3768706507
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.527011126
Short name T883
Test name
Test status
Simulation time 106685378 ps
CPU time 3.4 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 217948 kb
Host smart-3cf3352c-eee6-424f-afb5-8dd4403c1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527011126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.527011126
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2885523339
Short name T274
Test name
Test status
Simulation time 44962255 ps
CPU time 2.91 seconds
Started May 28 02:56:46 PM PDT 24
Finished May 28 02:56:58 PM PDT 24
Peak memory 208352 kb
Host smart-c8f16d25-476e-45c6-b869-be3c7b2167a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885523339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2885523339
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3567458473
Short name T488
Test name
Test status
Simulation time 106382013 ps
CPU time 2.6 seconds
Started May 28 02:56:45 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 206956 kb
Host smart-9266ce09-78f5-4824-a5e0-958348ade8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567458473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3567458473
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3608468045
Short name T337
Test name
Test status
Simulation time 561443610 ps
CPU time 4.9 seconds
Started May 28 02:56:43 PM PDT 24
Finished May 28 02:56:56 PM PDT 24
Peak memory 208088 kb
Host smart-080f8c50-95c8-4e2f-ae10-33ee80521faf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608468045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3608468045
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2356992957
Short name T516
Test name
Test status
Simulation time 206355756 ps
CPU time 7.87 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 208080 kb
Host smart-405bae81-d530-4598-a571-62f3e1f8200f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356992957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2356992957
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3728691600
Short name T865
Test name
Test status
Simulation time 62407961 ps
CPU time 2.83 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 208656 kb
Host smart-64038325-84cf-4a58-8f67-df2efff86bef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728691600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3728691600
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3132820693
Short name T88
Test name
Test status
Simulation time 13738857 ps
CPU time 1.39 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:53 PM PDT 24
Peak memory 207264 kb
Host smart-4c769d9f-69ca-47df-96be-907058d5f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132820693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3132820693
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3218002447
Short name T631
Test name
Test status
Simulation time 352888248 ps
CPU time 7.59 seconds
Started May 28 02:56:39 PM PDT 24
Finished May 28 02:56:52 PM PDT 24
Peak memory 208616 kb
Host smart-81276732-4d01-4cc4-bdbe-79f7b89ca60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218002447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3218002447
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3041105449
Short name T798
Test name
Test status
Simulation time 142073921 ps
CPU time 5.2 seconds
Started May 28 02:56:37 PM PDT 24
Finished May 28 02:56:43 PM PDT 24
Peak memory 219012 kb
Host smart-baffadb8-0d51-4ece-bb4f-30b4525dc0a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041105449 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3041105449
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1757099996
Short name T877
Test name
Test status
Simulation time 157403321 ps
CPU time 2.78 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 208352 kb
Host smart-f63699e1-4588-4a2c-8d17-296557e1c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757099996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1757099996
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3558179994
Short name T39
Test name
Test status
Simulation time 456273995 ps
CPU time 2.83 seconds
Started May 28 02:56:44 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 209884 kb
Host smart-e0d9f4b7-e031-4d5b-aa5f-d4e5b265aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558179994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3558179994
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.409732310
Short name T486
Test name
Test status
Simulation time 43913764 ps
CPU time 0.76 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 206016 kb
Host smart-e115c3e2-eed7-4914-9941-8e5a12b37d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409732310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.409732310
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2350811145
Short name T734
Test name
Test status
Simulation time 4404336625 ps
CPU time 59.1 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:58:01 PM PDT 24
Peak memory 215728 kb
Host smart-33c60dd0-6833-404d-9936-b2a9ad871935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350811145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2350811145
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2927311657
Short name T34
Test name
Test status
Simulation time 72611725 ps
CPU time 3.09 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:02 PM PDT 24
Peak memory 214692 kb
Host smart-e1559bfd-cd8e-4868-a149-3213cfd91454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927311657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2927311657
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1594896008
Short name T587
Test name
Test status
Simulation time 39460257 ps
CPU time 1.9 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 208012 kb
Host smart-610a2853-3fff-4234-a987-238e5b1a3445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594896008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1594896008
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3531924207
Short name T887
Test name
Test status
Simulation time 2334290290 ps
CPU time 11.12 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:09 PM PDT 24
Peak memory 214592 kb
Host smart-aa748e83-fffc-40ad-aad0-6852a735773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531924207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3531924207
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3807371046
Short name T265
Test name
Test status
Simulation time 250458880 ps
CPU time 4.72 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 222484 kb
Host smart-d9d250c6-ab0f-42b0-bc18-df61e22c6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807371046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3807371046
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1234664770
Short name T846
Test name
Test status
Simulation time 156678705 ps
CPU time 2.92 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 219384 kb
Host smart-4d55eb08-1999-4a5d-b1df-03312cc7b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234664770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1234664770
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2819496874
Short name T415
Test name
Test status
Simulation time 740249696 ps
CPU time 6.39 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 209060 kb
Host smart-2ae42af1-408f-4129-9b58-edec6d140150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819496874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2819496874
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.415206264
Short name T550
Test name
Test status
Simulation time 24109739 ps
CPU time 1.85 seconds
Started May 28 02:56:42 PM PDT 24
Finished May 28 02:56:51 PM PDT 24
Peak memory 208744 kb
Host smart-eff1bf3e-60e3-4a41-b236-07a002aa23d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415206264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.415206264
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1535998247
Short name T556
Test name
Test status
Simulation time 72989938 ps
CPU time 1.7 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 207008 kb
Host smart-9f8ac631-0893-40ec-b7ba-5d5a9bab1052
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535998247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1535998247
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.489969064
Short name T422
Test name
Test status
Simulation time 44750279 ps
CPU time 2.34 seconds
Started May 28 02:56:40 PM PDT 24
Finished May 28 02:56:49 PM PDT 24
Peak memory 208188 kb
Host smart-fd2cf9fa-986e-409e-9be7-616b9e8bbe67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489969064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.489969064
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3353461450
Short name T116
Test name
Test status
Simulation time 58600414 ps
CPU time 2.87 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 208592 kb
Host smart-31ee6f8e-8b7d-4e14-baee-61af353c774b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353461450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3353461450
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3502970043
Short name T905
Test name
Test status
Simulation time 60424639 ps
CPU time 2.25 seconds
Started May 28 02:58:39 PM PDT 24
Finished May 28 02:59:00 PM PDT 24
Peak memory 207428 kb
Host smart-d55b26ab-2a54-4ff4-8cf7-88973f9aa995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502970043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3502970043
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2588978105
Short name T425
Test name
Test status
Simulation time 274918997 ps
CPU time 2.63 seconds
Started May 28 02:56:41 PM PDT 24
Finished May 28 02:56:50 PM PDT 24
Peak memory 207348 kb
Host smart-02ae2f0b-019c-4415-b3c0-1a1b5557083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588978105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2588978105
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1051707012
Short name T132
Test name
Test status
Simulation time 5100803895 ps
CPU time 25.64 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 222672 kb
Host smart-64729187-0b19-4312-ac9e-f7dd56c2074a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051707012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1051707012
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3399076800
Short name T617
Test name
Test status
Simulation time 34683237 ps
CPU time 2.46 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 208316 kb
Host smart-ec7c9587-2c40-4c93-abf4-3abbb5d4d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399076800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3399076800
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.267157653
Short name T175
Test name
Test status
Simulation time 36709074 ps
CPU time 1.71 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 209812 kb
Host smart-ff74b810-d21a-43c5-99a9-04f5d72d3038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267157653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.267157653
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.267802543
Short name T708
Test name
Test status
Simulation time 15021859 ps
CPU time 0.93 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 206152 kb
Host smart-ba320068-2639-4ab8-bce8-aaba9e46f0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267802543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.267802543
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3094103630
Short name T900
Test name
Test status
Simulation time 475269055 ps
CPU time 8.28 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 222488 kb
Host smart-f2a4e23c-8df0-46c4-ab8a-3589d276ea93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094103630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3094103630
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.937482126
Short name T18
Test name
Test status
Simulation time 57645281 ps
CPU time 2.38 seconds
Started May 28 02:58:24 PM PDT 24
Finished May 28 02:58:47 PM PDT 24
Peak memory 214736 kb
Host smart-2cf1fc80-ed04-4588-baee-6328171bf376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937482126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.937482126
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2612337866
Short name T726
Test name
Test status
Simulation time 46524932 ps
CPU time 1.61 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 207368 kb
Host smart-4aef1d36-b6a9-4333-bd1b-a21a9b632cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612337866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2612337866
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3212523271
Short name T98
Test name
Test status
Simulation time 555475204 ps
CPU time 6.98 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 209516 kb
Host smart-297a3819-e505-484e-b028-2c22a5b4c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212523271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3212523271
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4278130481
Short name T635
Test name
Test status
Simulation time 93244434 ps
CPU time 4.1 seconds
Started May 28 02:57:00 PM PDT 24
Finished May 28 02:57:10 PM PDT 24
Peak memory 214324 kb
Host smart-068da9ed-2096-4d66-8191-b286592c7871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278130481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4278130481
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2475754485
Short name T788
Test name
Test status
Simulation time 84681421 ps
CPU time 2.97 seconds
Started May 28 02:56:54 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 214420 kb
Host smart-6a02f0c6-2beb-47a4-888d-c3c7f805b9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475754485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2475754485
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1303376936
Short name T560
Test name
Test status
Simulation time 158444755 ps
CPU time 5.55 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 209540 kb
Host smart-089ea686-2140-4d74-9831-a345701eb56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303376936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1303376936
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2643875300
Short name T833
Test name
Test status
Simulation time 90487550 ps
CPU time 3.68 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 208052 kb
Host smart-9c8ff6ce-306c-4ba8-96cf-0c1661cb6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643875300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2643875300
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3859449781
Short name T693
Test name
Test status
Simulation time 665368860 ps
CPU time 4.87 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 208876 kb
Host smart-b9f699b1-ea1d-4df8-babe-5145befdf23d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859449781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3859449781
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4122371621
Short name T755
Test name
Test status
Simulation time 268670945 ps
CPU time 2.79 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 209156 kb
Host smart-5720035c-0a31-4d0a-8b8a-db26bf65ea45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122371621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4122371621
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4193074472
Short name T630
Test name
Test status
Simulation time 1231740875 ps
CPU time 27.62 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 208376 kb
Host smart-cafc7394-7816-4a7d-8aee-332fee5cdef2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193074472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4193074472
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1282609568
Short name T368
Test name
Test status
Simulation time 53567797 ps
CPU time 2.56 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 218532 kb
Host smart-092ce93e-e91a-46a6-9901-ed2b0ac5aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282609568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1282609568
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1815173566
Short name T563
Test name
Test status
Simulation time 21576254 ps
CPU time 1.75 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 206976 kb
Host smart-93e3681a-bf78-42a2-8a75-36a5643dc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815173566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1815173566
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3097879932
Short name T648
Test name
Test status
Simulation time 184092979 ps
CPU time 4.57 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 209808 kb
Host smart-95597112-700f-4649-a1bd-c4f1936095c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097879932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3097879932
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2902572450
Short name T46
Test name
Test status
Simulation time 107278507 ps
CPU time 3.03 seconds
Started May 28 02:57:18 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 210824 kb
Host smart-ed95a297-569a-4cb0-9121-14eff2e05fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902572450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2902572450
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2791779622
Short name T907
Test name
Test status
Simulation time 13360633 ps
CPU time 0.78 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 206000 kb
Host smart-e16abc0a-76f0-495b-8d18-71e6f58cfc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791779622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2791779622
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2511014888
Short name T659
Test name
Test status
Simulation time 185418404 ps
CPU time 2.83 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:04 PM PDT 24
Peak memory 214672 kb
Host smart-ab067179-b7ab-4236-abce-e96095a2c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511014888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2511014888
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2027341077
Short name T869
Test name
Test status
Simulation time 69714947 ps
CPU time 1.69 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 207700 kb
Host smart-6b7f1629-c26f-4cb1-8d12-8e778ff22903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027341077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2027341077
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.424298744
Short name T297
Test name
Test status
Simulation time 23577029796 ps
CPU time 93.05 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:58:35 PM PDT 24
Peak memory 222556 kb
Host smart-0e0ebee0-5c56-433c-b2d9-901cd8572287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424298744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.424298744
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3074556531
Short name T567
Test name
Test status
Simulation time 319588239 ps
CPU time 4.05 seconds
Started May 28 02:56:59 PM PDT 24
Finished May 28 02:57:09 PM PDT 24
Peak memory 222524 kb
Host smart-6bfd6c53-ec00-4770-a834-5d480f6430af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074556531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3074556531
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1833696828
Short name T218
Test name
Test status
Simulation time 643932527 ps
CPU time 5.34 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:08 PM PDT 24
Peak memory 218424 kb
Host smart-9c7bfc0d-4f0b-4ffc-a9f0-7b5ba6a00b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833696828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1833696828
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4202927292
Short name T715
Test name
Test status
Simulation time 924759915 ps
CPU time 12.81 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 208740 kb
Host smart-62d0c5fd-c93b-440b-afdc-8b889610dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202927292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4202927292
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1057579976
Short name T529
Test name
Test status
Simulation time 21165815 ps
CPU time 1.79 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:00 PM PDT 24
Peak memory 206844 kb
Host smart-8a18335d-04b7-48f2-a62a-d95e62062e6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057579976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1057579976
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2524609904
Short name T513
Test name
Test status
Simulation time 96552836 ps
CPU time 3.54 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 206968 kb
Host smart-a4031c1f-f241-480e-90bf-50ab61c7e87f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524609904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2524609904
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3824137209
Short name T466
Test name
Test status
Simulation time 51144490 ps
CPU time 2.68 seconds
Started May 28 02:56:54 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 208000 kb
Host smart-9ded1f12-1945-4f1b-bbf6-4724d641b83e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824137209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3824137209
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.319439769
Short name T216
Test name
Test status
Simulation time 167405372 ps
CPU time 2.89 seconds
Started May 28 02:58:10 PM PDT 24
Finished May 28 02:58:31 PM PDT 24
Peak memory 218480 kb
Host smart-c40d552c-8417-4e8b-955a-ddcbbe2c4b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319439769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.319439769
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2714351611
Short name T863
Test name
Test status
Simulation time 59925625 ps
CPU time 3.09 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 206692 kb
Host smart-10a262a8-a308-474a-819d-9c08072ac304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714351611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2714351611
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2966947746
Short name T201
Test name
Test status
Simulation time 471875718 ps
CPU time 17.82 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 216928 kb
Host smart-5ffcccc5-5980-44fc-ab9c-03e915da008c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966947746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2966947746
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2514716698
Short name T366
Test name
Test status
Simulation time 2710873628 ps
CPU time 6.9 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 218512 kb
Host smart-c4a6c895-ac43-4aee-a93a-346265f8750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514716698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2514716698
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.328401176
Short name T521
Test name
Test status
Simulation time 271429833 ps
CPU time 2.25 seconds
Started May 28 02:57:00 PM PDT 24
Finished May 28 02:57:09 PM PDT 24
Peak memory 209924 kb
Host smart-ab3cdecb-f39f-4afe-a12a-d39bf6f9957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328401176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.328401176
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.614761327
Short name T719
Test name
Test status
Simulation time 85140046 ps
CPU time 0.82 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 205980 kb
Host smart-b93aaf0e-21b9-4e6a-82f7-99e95673ac36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614761327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.614761327
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2592056002
Short name T81
Test name
Test status
Simulation time 101116483 ps
CPU time 2.37 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 207744 kb
Host smart-59aa1b2b-e2d6-4745-bef6-4041d47a2b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592056002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2592056002
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1991917435
Short name T848
Test name
Test status
Simulation time 1419896140 ps
CPU time 6.91 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 209660 kb
Host smart-58474326-e1d9-402d-90c0-1b00d749f516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991917435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1991917435
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2362218056
Short name T319
Test name
Test status
Simulation time 263715553 ps
CPU time 2.4 seconds
Started May 28 02:56:59 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 214516 kb
Host smart-b07e3994-38e7-4670-b264-dd7dd9106235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362218056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2362218056
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.3959373015
Short name T335
Test name
Test status
Simulation time 37569824 ps
CPU time 2.48 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 209744 kb
Host smart-55e208bb-7f5d-42ae-affe-f8096b4684ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959373015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3959373015
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2325770552
Short name T253
Test name
Test status
Simulation time 147853465 ps
CPU time 5.04 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 206924 kb
Host smart-b76e2350-e36c-4fb3-8bc6-efdcbb43249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325770552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2325770552
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1272340065
Short name T642
Test name
Test status
Simulation time 635708046 ps
CPU time 4.39 seconds
Started May 28 02:56:50 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 209132 kb
Host smart-d8fcb76c-5f73-450a-863a-a3f602646394
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272340065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1272340065
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2821168302
Short name T266
Test name
Test status
Simulation time 378326170 ps
CPU time 4.31 seconds
Started May 28 02:58:17 PM PDT 24
Finished May 28 02:58:48 PM PDT 24
Peak memory 208948 kb
Host smart-e73379f4-0da5-4e1a-8f58-9261256a03b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821168302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2821168302
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1955118857
Short name T820
Test name
Test status
Simulation time 40214350 ps
CPU time 2.24 seconds
Started May 28 02:56:51 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 207072 kb
Host smart-cfe367ff-ff6f-41a6-8213-9d4e28776bf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955118857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1955118857
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1950392816
Short name T800
Test name
Test status
Simulation time 142227206 ps
CPU time 2.82 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:07 PM PDT 24
Peak memory 210240 kb
Host smart-e49e41c4-f57c-483a-9ab1-9fa1e6f60c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950392816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1950392816
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.788283424
Short name T897
Test name
Test status
Simulation time 753034323 ps
CPU time 4.36 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 208244 kb
Host smart-fe4ef0fd-a003-496e-b17e-240f5b26ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788283424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.788283424
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1195244984
Short name T581
Test name
Test status
Simulation time 2050679471 ps
CPU time 29.22 seconds
Started May 28 02:56:58 PM PDT 24
Finished May 28 02:57:34 PM PDT 24
Peak memory 214972 kb
Host smart-be0d23ee-4c48-413d-8cfe-940b0f73f633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195244984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1195244984
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1083382440
Short name T80
Test name
Test status
Simulation time 202439905 ps
CPU time 11.99 seconds
Started May 28 02:56:59 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 222608 kb
Host smart-28f70958-86ad-486f-8325-1f10bd7157b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083382440 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1083382440
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1103575579
Short name T812
Test name
Test status
Simulation time 223306260 ps
CPU time 7.63 seconds
Started May 28 02:56:57 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 208120 kb
Host smart-d3f13fbb-cb0e-4480-a59c-5538c30d2807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103575579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1103575579
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.250803267
Short name T168
Test name
Test status
Simulation time 61169498 ps
CPU time 2.19 seconds
Started May 28 02:56:53 PM PDT 24
Finished May 28 02:57:03 PM PDT 24
Peak memory 210472 kb
Host smart-19ef9acb-c67b-40ce-b88e-30d38889c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250803267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.250803267
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2569331133
Short name T537
Test name
Test status
Simulation time 20239445 ps
CPU time 0.99 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 206160 kb
Host smart-e9bfeaee-18ba-49b2-a553-85a43d86d0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569331133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2569331133
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2164044522
Short name T410
Test name
Test status
Simulation time 210499985 ps
CPU time 3.03 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:02 PM PDT 24
Peak memory 214452 kb
Host smart-edf5c563-0728-487f-926f-9daace14276b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164044522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2164044522
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1939650526
Short name T234
Test name
Test status
Simulation time 269664602 ps
CPU time 6.35 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 221904 kb
Host smart-53e2d5f5-a914-4dfc-975c-4e7e332f3d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939650526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1939650526
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.478030869
Short name T769
Test name
Test status
Simulation time 29804722 ps
CPU time 2.03 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:01 PM PDT 24
Peak memory 214384 kb
Host smart-40cec40d-0a16-4c08-848c-1f23eeb6cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478030869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.478030869
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.20276280
Short name T633
Test name
Test status
Simulation time 7361036649 ps
CPU time 76.8 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:58:16 PM PDT 24
Peak memory 214428 kb
Host smart-92ddefb4-25d9-4867-9641-93c4c7df550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20276280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.20276280
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2827992819
Short name T263
Test name
Test status
Simulation time 1014179497 ps
CPU time 3.87 seconds
Started May 28 02:56:55 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 214316 kb
Host smart-31110050-a4ea-4f38-a3bd-9faf64742270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827992819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2827992819
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_random.3623502447
Short name T339
Test name
Test status
Simulation time 63469794 ps
CPU time 3.63 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 218372 kb
Host smart-d7872a98-1acc-4859-9661-baa6fdc6f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623502447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3623502447
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1380314922
Short name T542
Test name
Test status
Simulation time 116009554 ps
CPU time 2.27 seconds
Started May 28 02:58:26 PM PDT 24
Finished May 28 02:58:48 PM PDT 24
Peak memory 206856 kb
Host smart-6dc0eb77-52ef-424b-a08f-4109f8aaf679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380314922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1380314922
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3703981726
Short name T628
Test name
Test status
Simulation time 74842159 ps
CPU time 1.71 seconds
Started May 28 02:58:18 PM PDT 24
Finished May 28 02:58:41 PM PDT 24
Peak memory 207280 kb
Host smart-4b6788e8-cca0-4c9b-912b-17f012c74bac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703981726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3703981726
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.493340906
Short name T523
Test name
Test status
Simulation time 228039761 ps
CPU time 3.15 seconds
Started May 28 02:56:52 PM PDT 24
Finished May 28 02:57:02 PM PDT 24
Peak memory 208872 kb
Host smart-8804768d-ec8d-485b-9986-64cafa13b910
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493340906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.493340906
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.653796957
Short name T786
Test name
Test status
Simulation time 262338549 ps
CPU time 6.06 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:08 PM PDT 24
Peak memory 208400 kb
Host smart-ea552a1e-c61a-4cbc-85e7-e2fe328298ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653796957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.653796957
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1537199285
Short name T596
Test name
Test status
Simulation time 36851309 ps
CPU time 1.47 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 208172 kb
Host smart-94a5aa06-a9d5-4b1e-996f-22864f6ef5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537199285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1537199285
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1776474450
Short name T804
Test name
Test status
Simulation time 61378866 ps
CPU time 2.7 seconds
Started May 28 02:56:59 PM PDT 24
Finished May 28 02:57:08 PM PDT 24
Peak memory 206856 kb
Host smart-8533ed7b-b6b4-4f17-9d1d-3f2e627a3ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776474450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1776474450
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2279773696
Short name T750
Test name
Test status
Simulation time 2530858280 ps
CPU time 7.98 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 222704 kb
Host smart-576abfaa-5052-48f2-a0ef-90db4cd395f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279773696 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2279773696
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2333771912
Short name T413
Test name
Test status
Simulation time 144721117 ps
CPU time 2.92 seconds
Started May 28 02:56:56 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 209040 kb
Host smart-8f96e965-af1c-4648-b313-d6395debb273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333771912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2333771912
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1081485165
Short name T206
Test name
Test status
Simulation time 123428618 ps
CPU time 1.5 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 209912 kb
Host smart-c2e0eded-df55-43eb-9ea5-6282293cd0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081485165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1081485165
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.385973761
Short name T868
Test name
Test status
Simulation time 18880375 ps
CPU time 0.83 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 205992 kb
Host smart-5a7ff4bd-dfd4-4cc1-aa2e-e5a0ba86d405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385973761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.385973761
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3517432864
Short name T398
Test name
Test status
Simulation time 248083131 ps
CPU time 4.35 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 207008 kb
Host smart-99b09244-c2ab-4bce-8ff6-87777b57b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517432864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3517432864
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1666013518
Short name T101
Test name
Test status
Simulation time 110054239 ps
CPU time 5.21 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:18 PM PDT 24
Peak memory 222532 kb
Host smart-e213ee9f-b07a-4ece-b5e8-0da0a3ceb1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666013518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1666013518
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3213886129
Short name T823
Test name
Test status
Simulation time 59202524 ps
CPU time 2.64 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 214344 kb
Host smart-04d3d268-5803-495d-acd2-06c9f7f3be98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213886129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3213886129
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3122133214
Short name T303
Test name
Test status
Simulation time 286639602 ps
CPU time 3.93 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 220600 kb
Host smart-f829714e-20f3-4543-88d7-06e15300bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122133214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3122133214
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1217962474
Short name T811
Test name
Test status
Simulation time 2338595770 ps
CPU time 39.56 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:49 PM PDT 24
Peak memory 209272 kb
Host smart-73bb05e7-166c-44ff-b494-323c3708bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217962474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1217962474
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2540392134
Short name T226
Test name
Test status
Simulation time 162778872 ps
CPU time 2.71 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208188 kb
Host smart-e8c6f7d2-dc3b-46fd-ad6e-568854da96f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540392134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2540392134
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3712163909
Short name T313
Test name
Test status
Simulation time 200327788 ps
CPU time 1.83 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:10 PM PDT 24
Peak memory 206996 kb
Host smart-2f32c0b8-95b7-4724-9ec9-ea820dab4eee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712163909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3712163909
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1397698568
Short name T485
Test name
Test status
Simulation time 2395750322 ps
CPU time 22.22 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:30 PM PDT 24
Peak memory 209348 kb
Host smart-c6edb409-1f02-4db2-8130-4c14ca5a6b40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397698568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1397698568
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.536055616
Short name T257
Test name
Test status
Simulation time 1132686447 ps
CPU time 8.96 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:21 PM PDT 24
Peak memory 208760 kb
Host smart-74bc91ee-925f-4eea-92e6-fdec147156bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536055616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.536055616
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2952832907
Short name T456
Test name
Test status
Simulation time 24875046 ps
CPU time 2.06 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 214956 kb
Host smart-5a2e47ee-2e8b-4687-a7fd-ac8f8231b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952832907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2952832907
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.520485694
Short name T531
Test name
Test status
Simulation time 45546268 ps
CPU time 2.13 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208272 kb
Host smart-c41ce285-4298-4a98-9395-fd6e13c3d356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520485694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.520485694
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2271619776
Short name T291
Test name
Test status
Simulation time 870708706 ps
CPU time 5.48 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 208044 kb
Host smart-157293cb-3e1c-431c-ad81-e46516830318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271619776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2271619776
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3694271096
Short name T888
Test name
Test status
Simulation time 278994401 ps
CPU time 1.87 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 209672 kb
Host smart-c6f3e45e-7ed4-4015-989a-ea4d800b6b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694271096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3694271096
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3323465155
Short name T641
Test name
Test status
Simulation time 53503323 ps
CPU time 1.11 seconds
Started May 28 02:57:08 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 206172 kb
Host smart-3f1973a4-9237-46e6-85c5-4a22241aefb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323465155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3323465155
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2622791565
Short name T612
Test name
Test status
Simulation time 512551716 ps
CPU time 6.31 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 214376 kb
Host smart-ae8ba602-ad2e-413c-af41-03e0ae727bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622791565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2622791565
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2819078494
Short name T379
Test name
Test status
Simulation time 149184534 ps
CPU time 2.29 seconds
Started May 28 02:57:10 PM PDT 24
Finished May 28 02:57:18 PM PDT 24
Peak memory 210100 kb
Host smart-879d23a5-6e42-4185-ad62-ecd4fbf94ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819078494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2819078494
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2968913932
Short name T261
Test name
Test status
Simulation time 187464067 ps
CPU time 2.06 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:10 PM PDT 24
Peak memory 214364 kb
Host smart-5f17135b-1d42-4784-bec1-625e0cb230d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968913932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2968913932
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1045012855
Short name T426
Test name
Test status
Simulation time 858591038 ps
CPU time 2.92 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 221192 kb
Host smart-fb68490a-24bf-4bab-b372-f9d9659decbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045012855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1045012855
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.518847333
Short name T836
Test name
Test status
Simulation time 213340522 ps
CPU time 3.96 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 210488 kb
Host smart-3dd2b586-4096-4c93-8156-a61fcaf86314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518847333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.518847333
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4283016476
Short name T736
Test name
Test status
Simulation time 605145837 ps
CPU time 4.82 seconds
Started May 28 02:58:17 PM PDT 24
Finished May 28 02:58:44 PM PDT 24
Peak memory 208908 kb
Host smart-a151cd73-af1b-4b83-95bb-3ae2bdd92477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283016476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4283016476
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.589195424
Short name T340
Test name
Test status
Simulation time 438878839 ps
CPU time 5.62 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 208852 kb
Host smart-c8afaefc-a95b-431e-b30f-58e32a7de194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589195424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.589195424
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1847461624
Short name T898
Test name
Test status
Simulation time 46929399 ps
CPU time 2.04 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 208668 kb
Host smart-491a206f-043c-48f8-84c1-8a27d3fb4df4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847461624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1847461624
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1740256758
Short name T657
Test name
Test status
Simulation time 171105242 ps
CPU time 5.96 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 208060 kb
Host smart-c74a3bf2-09f1-4d3d-bb68-922ba03063d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740256758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1740256758
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3413878564
Short name T472
Test name
Test status
Simulation time 131377995 ps
CPU time 3.18 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208696 kb
Host smart-2d75ba4f-d7ea-4a93-9c46-7d9048af9383
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413878564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3413878564
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2680684890
Short name T539
Test name
Test status
Simulation time 141639732 ps
CPU time 2.67 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 215424 kb
Host smart-cde288a3-343a-4264-9e04-39b520cc8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680684890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2680684890
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3403658184
Short name T467
Test name
Test status
Simulation time 459465588 ps
CPU time 5.6 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:21 PM PDT 24
Peak memory 206156 kb
Host smart-d8492291-13dc-4c8a-9d9a-0fed9fd76367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403658184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3403658184
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4068461044
Short name T205
Test name
Test status
Simulation time 962822807 ps
CPU time 32.35 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 216588 kb
Host smart-4ae363c1-7319-457d-8d9e-d7222709d954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068461044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4068461044
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3970906925
Short name T329
Test name
Test status
Simulation time 515203445 ps
CPU time 21.26 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:29 PM PDT 24
Peak memory 222608 kb
Host smart-039adf33-a36d-466c-af6e-42c13b80b4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970906925 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3970906925
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2711847515
Short name T302
Test name
Test status
Simulation time 60389573 ps
CPU time 4.08 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 218264 kb
Host smart-1ce7d1e1-5e60-4104-8eba-035fcf7ca996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711847515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2711847515
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.894744697
Short name T65
Test name
Test status
Simulation time 74454915 ps
CPU time 2.4 seconds
Started May 28 02:57:01 PM PDT 24
Finished May 28 02:57:10 PM PDT 24
Peak memory 210040 kb
Host smart-35980766-83a0-439e-9582-897c829fe756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894744697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.894744697
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1729721999
Short name T638
Test name
Test status
Simulation time 21645148 ps
CPU time 0.88 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 205988 kb
Host smart-1f205b2a-7a3c-42fd-b7e9-333cfe8ecf00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729721999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1729721999
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3945576092
Short name T117
Test name
Test status
Simulation time 147713102 ps
CPU time 2.74 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 215472 kb
Host smart-cf6bdfc1-5632-4f46-ab8b-01d89b1ba9fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945576092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3945576092
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3268337920
Short name T56
Test name
Test status
Simulation time 18219827 ps
CPU time 1.47 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:11 PM PDT 24
Peak memory 207328 kb
Host smart-f488d81f-7ead-44ce-8461-2820ffa8209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268337920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3268337920
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3804692882
Short name T849
Test name
Test status
Simulation time 187567657 ps
CPU time 2.08 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 214760 kb
Host smart-90bc35dc-5889-4bf1-9c25-5c3572e9ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804692882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3804692882
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1921180344
Short name T320
Test name
Test status
Simulation time 951132817 ps
CPU time 3.11 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 215552 kb
Host smart-27ebbcea-52c0-4247-9e5b-86681190f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921180344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1921180344
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2067597231
Short name T528
Test name
Test status
Simulation time 299378784 ps
CPU time 1.87 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:13 PM PDT 24
Peak memory 214836 kb
Host smart-5f2380d2-698c-441a-9c74-defe132e96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067597231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2067597231
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.154590619
Short name T222
Test name
Test status
Simulation time 281486809 ps
CPU time 4.01 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 216048 kb
Host smart-b18ddc91-ea6e-49fc-962c-e5ab74611468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154590619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.154590619
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.229404311
Short name T902
Test name
Test status
Simulation time 341530882 ps
CPU time 5.09 seconds
Started May 28 02:57:08 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 208932 kb
Host smart-9ba0f079-0007-4e12-99d7-3c01fdea141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229404311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.229404311
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.662688361
Short name T458
Test name
Test status
Simulation time 215033320 ps
CPU time 3.07 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208156 kb
Host smart-f7be8c0f-974b-4d19-822f-61851dd47f72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662688361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.662688361
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.117734688
Short name T609
Test name
Test status
Simulation time 278317504 ps
CPU time 3.61 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 208736 kb
Host smart-a506dafb-bb2c-461b-9ba1-221ee8e2c5f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117734688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.117734688
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1031344476
Short name T886
Test name
Test status
Simulation time 91635553 ps
CPU time 3.57 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208536 kb
Host smart-918c8e6e-7b82-4276-a714-4cf125885dc2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031344476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1031344476
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2102113864
Short name T660
Test name
Test status
Simulation time 28317571 ps
CPU time 1.52 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 217984 kb
Host smart-93850e08-5e2c-4f88-8da5-050cbb02d7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102113864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2102113864
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2879966363
Short name T481
Test name
Test status
Simulation time 975060756 ps
CPU time 2.99 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:19 PM PDT 24
Peak memory 208472 kb
Host smart-01781050-1c8f-4edc-a64c-6906d875a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879966363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2879966363
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1615420069
Short name T12
Test name
Test status
Simulation time 1466077030 ps
CPU time 11.37 seconds
Started May 28 02:58:18 PM PDT 24
Finished May 28 02:58:51 PM PDT 24
Peak memory 222900 kb
Host smart-31b63ad5-0b3c-488d-852c-32d30bc24442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615420069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1615420069
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2039496511
Short name T591
Test name
Test status
Simulation time 163136477 ps
CPU time 4.18 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 214424 kb
Host smart-353d3584-1b63-4cf4-a530-44104aebc757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039496511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2039496511
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2888874170
Short name T742
Test name
Test status
Simulation time 216410163 ps
CPU time 2.43 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 210044 kb
Host smart-64f14ba2-ca88-4529-bb02-02b9892dd9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888874170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2888874170
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3630801055
Short name T569
Test name
Test status
Simulation time 17816615 ps
CPU time 0.75 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:31 PM PDT 24
Peak memory 205992 kb
Host smart-75090e3d-4a02-4653-8e85-57339c8c44bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630801055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3630801055
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1008694705
Short name T412
Test name
Test status
Simulation time 259046241 ps
CPU time 2.54 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:39 PM PDT 24
Peak memory 214368 kb
Host smart-5d1627fa-0d96-49d6-909d-bc84062b38b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008694705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1008694705
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3718816363
Short name T527
Test name
Test status
Simulation time 540505771 ps
CPU time 5.1 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 222040 kb
Host smart-084d6c27-a16e-40d3-9fa4-84067ea953f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718816363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3718816363
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2909750321
Short name T399
Test name
Test status
Simulation time 89050867 ps
CPU time 3.11 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 214452 kb
Host smart-96f4fe93-21e8-4c7d-aa86-29c62f9959d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909750321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2909750321
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2629239648
Short name T96
Test name
Test status
Simulation time 93809985 ps
CPU time 2.16 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 214580 kb
Host smart-1d795be9-759a-42dd-a647-afc45b731f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629239648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2629239648
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.410460318
Short name T768
Test name
Test status
Simulation time 642528197 ps
CPU time 4.67 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:39 PM PDT 24
Peak memory 222380 kb
Host smart-ebc41e2d-9f60-4030-bb39-fce80cb6d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410460318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.410460318
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1753030204
Short name T245
Test name
Test status
Simulation time 213335486 ps
CPU time 3.07 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 208140 kb
Host smart-ca1a3d39-6cb6-46ca-a2b2-f14c88e960e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753030204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1753030204
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.707792357
Short name T730
Test name
Test status
Simulation time 1364708361 ps
CPU time 4.15 seconds
Started May 28 02:55:20 PM PDT 24
Finished May 28 02:55:32 PM PDT 24
Peak memory 209052 kb
Host smart-a00ffbbe-f6a5-4af1-83ba-10e6717ce0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707792357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.707792357
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3065477646
Short name T658
Test name
Test status
Simulation time 137395614 ps
CPU time 3.27 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 206844 kb
Host smart-94a7c343-6091-4d0e-93ac-86325ecc2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065477646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3065477646
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.304113150
Short name T507
Test name
Test status
Simulation time 39250033 ps
CPU time 2.67 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 208712 kb
Host smart-21da3526-c7b3-497a-b7a6-7116e3a545ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304113150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.304113150
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3993407681
Short name T461
Test name
Test status
Simulation time 201385272 ps
CPU time 3.18 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:40 PM PDT 24
Peak memory 208712 kb
Host smart-28c3fc59-9dd4-4a49-8160-8cbaaa117736
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993407681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3993407681
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4273567999
Short name T810
Test name
Test status
Simulation time 111193866 ps
CPU time 3.01 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 208752 kb
Host smart-3a7eb494-39e4-40f8-847e-fb87606f2911
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273567999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4273567999
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4245542079
Short name T483
Test name
Test status
Simulation time 201895814 ps
CPU time 4.31 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 215492 kb
Host smart-74a52124-b62e-43c2-971a-2064799f2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245542079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4245542079
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4009491621
Short name T548
Test name
Test status
Simulation time 35012817 ps
CPU time 2.26 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 208752 kb
Host smart-cec3b0b4-9ae5-4c64-b09b-b56d8218a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009491621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4009491621
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3260459364
Short name T7
Test name
Test status
Simulation time 9211307227 ps
CPU time 85.65 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:57:05 PM PDT 24
Peak memory 216828 kb
Host smart-4fbd7356-e017-4581-bcb9-272843da8845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260459364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3260459364
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2612610229
Short name T396
Test name
Test status
Simulation time 122200071 ps
CPU time 4.73 seconds
Started May 28 02:55:26 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 218296 kb
Host smart-df188705-4638-41a6-9af8-787bd90b99b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612610229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2612610229
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1939678450
Short name T593
Test name
Test status
Simulation time 67527360 ps
CPU time 2.11 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:37 PM PDT 24
Peak memory 209740 kb
Host smart-41e9d456-534d-4b75-bcd3-cfebf29abb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939678450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1939678450
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1536827960
Short name T668
Test name
Test status
Simulation time 41117788 ps
CPU time 0.8 seconds
Started May 28 02:57:09 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 206004 kb
Host smart-95cecc1c-0054-485e-b908-f91c3f27a0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536827960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1536827960
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.164153846
Short name T333
Test name
Test status
Simulation time 78343323 ps
CPU time 5.15 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 215692 kb
Host smart-8b1bbc33-dd8b-48c0-af97-be16deefb80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164153846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.164153846
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.702547879
Short name T220
Test name
Test status
Simulation time 77574878 ps
CPU time 1.95 seconds
Started May 28 02:57:12 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 209624 kb
Host smart-b281d961-47b2-4d51-a833-d936d0d4478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702547879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.702547879
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1632666415
Short name T402
Test name
Test status
Simulation time 239256433 ps
CPU time 6.07 seconds
Started May 28 02:57:02 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 214408 kb
Host smart-564ebb85-397e-4010-8bd1-e1860e9eb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632666415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1632666415
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.294197108
Short name T317
Test name
Test status
Simulation time 50747441 ps
CPU time 2.14 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 221756 kb
Host smart-55b4a5dc-62d5-437d-92f4-aade928c340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294197108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.294197108
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3003564278
Short name T53
Test name
Test status
Simulation time 121059581 ps
CPU time 3.38 seconds
Started May 28 02:57:06 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 208944 kb
Host smart-0472eba8-4d79-4956-8998-0ef88cc2b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003564278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3003564278
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.124998183
Short name T667
Test name
Test status
Simulation time 174221814 ps
CPU time 5.52 seconds
Started May 28 02:57:10 PM PDT 24
Finished May 28 02:57:23 PM PDT 24
Peak memory 208300 kb
Host smart-d199fde9-29e1-46dc-b0f6-3faee63bed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124998183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.124998183
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1646388394
Short name T669
Test name
Test status
Simulation time 239082844 ps
CPU time 3.36 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:18 PM PDT 24
Peak memory 208824 kb
Host smart-cca6c452-a5fe-4433-8d0f-8ddd9f1aaca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646388394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1646388394
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3845836639
Short name T395
Test name
Test status
Simulation time 31920473 ps
CPU time 2.35 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 207524 kb
Host smart-307c835e-0a82-483a-b364-5e2159f4c76f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845836639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3845836639
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.344757574
Short name T646
Test name
Test status
Simulation time 132418995 ps
CPU time 1.84 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 207028 kb
Host smart-ef04c763-0e61-43e5-84ed-ec3e26a175e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344757574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.344757574
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.362974163
Short name T677
Test name
Test status
Simulation time 5606829780 ps
CPU time 58.32 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:58:11 PM PDT 24
Peak memory 209036 kb
Host smart-ef68a4eb-325a-4494-a2d7-796c016766a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362974163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.362974163
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2529324872
Short name T3
Test name
Test status
Simulation time 15778632 ps
CPU time 1.33 seconds
Started May 28 02:57:10 PM PDT 24
Finished May 28 02:57:18 PM PDT 24
Peak memory 209412 kb
Host smart-9523b437-5bbe-4727-aa43-a722c0dc6bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529324872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2529324872
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.572992493
Short name T457
Test name
Test status
Simulation time 34765305 ps
CPU time 1.96 seconds
Started May 28 02:57:12 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 206856 kb
Host smart-495f8fb6-ffc9-430b-b97e-c2cdf25df220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572992493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.572992493
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1840295535
Short name T890
Test name
Test status
Simulation time 623165803 ps
CPU time 15.44 seconds
Started May 28 02:57:10 PM PDT 24
Finished May 28 02:57:32 PM PDT 24
Peak memory 215888 kb
Host smart-950a750e-8824-4f75-9ff3-ff6344e40417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840295535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1840295535
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1129090805
Short name T814
Test name
Test status
Simulation time 101223834 ps
CPU time 2.3 seconds
Started May 28 02:57:03 PM PDT 24
Finished May 28 02:57:12 PM PDT 24
Peak memory 208128 kb
Host smart-8c80f53a-18e6-4136-a7b9-b5cc416cec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129090805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1129090805
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3703283285
Short name T740
Test name
Test status
Simulation time 1938784724 ps
CPU time 7.08 seconds
Started May 28 02:57:10 PM PDT 24
Finished May 28 02:57:23 PM PDT 24
Peak memory 211224 kb
Host smart-32e8a2b3-e4ee-4061-aeeb-813db2f7a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703283285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3703283285
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4294714617
Short name T727
Test name
Test status
Simulation time 13729266 ps
CPU time 0.9 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 206012 kb
Host smart-d824d218-32ec-48bc-a822-b623f0f3cd9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294714617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4294714617
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3543336696
Short name T434
Test name
Test status
Simulation time 115394706 ps
CPU time 4.3 seconds
Started May 28 02:57:12 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 215476 kb
Host smart-91b62e32-7666-41d2-b5fa-b31865a2c1b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543336696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3543336696
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3982668893
Short name T77
Test name
Test status
Simulation time 212839163 ps
CPU time 2.67 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 210220 kb
Host smart-10649093-430b-46a3-aa32-f6f644f7e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982668893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3982668893
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2891428318
Short name T264
Test name
Test status
Simulation time 206322269 ps
CPU time 2.44 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:16 PM PDT 24
Peak memory 214412 kb
Host smart-9ec55755-9b78-46d9-98ae-b976bdf4abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891428318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2891428318
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1865105789
Short name T731
Test name
Test status
Simulation time 144645093 ps
CPU time 1.96 seconds
Started May 28 02:57:05 PM PDT 24
Finished May 28 02:57:15 PM PDT 24
Peak memory 214520 kb
Host smart-cdb9d695-3775-4266-86f6-0a20b2e71502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865105789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1865105789
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2923543057
Short name T599
Test name
Test status
Simulation time 100990580 ps
CPU time 4.24 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 214376 kb
Host smart-44bae79e-8d41-4870-a214-83a9ec5627e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923543057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2923543057
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1784836729
Short name T300
Test name
Test status
Simulation time 633749774 ps
CPU time 4.95 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:19 PM PDT 24
Peak memory 218172 kb
Host smart-fb0c2dfa-43a5-4f0f-9bde-89ab47a43c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784836729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1784836729
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.4072525911
Short name T600
Test name
Test status
Simulation time 163552592 ps
CPU time 3.11 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 207004 kb
Host smart-3fa2a5fc-57f1-49b2-ae72-9b2954bef197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072525911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.4072525911
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2397267545
Short name T448
Test name
Test status
Simulation time 241148864 ps
CPU time 3 seconds
Started May 28 02:57:06 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 206880 kb
Host smart-24348483-1bfb-46b5-9f6a-555c78a70086
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397267545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2397267545
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4216506801
Short name T497
Test name
Test status
Simulation time 624322065 ps
CPU time 5.22 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208076 kb
Host smart-a348a8d4-6139-482c-b087-debf6bc7693c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216506801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4216506801
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1035249485
Short name T479
Test name
Test status
Simulation time 56383142 ps
CPU time 2.97 seconds
Started May 28 02:57:12 PM PDT 24
Finished May 28 02:57:21 PM PDT 24
Peak memory 208160 kb
Host smart-bf5fa2c4-8f1c-470b-985c-4027da6641b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035249485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1035249485
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2515135426
Short name T367
Test name
Test status
Simulation time 466992513 ps
CPU time 11.79 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:33 PM PDT 24
Peak memory 214416 kb
Host smart-6688ba80-5d86-4510-9839-31d1f3736c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515135426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2515135426
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1706643516
Short name T743
Test name
Test status
Simulation time 201361381 ps
CPU time 3.95 seconds
Started May 28 02:57:04 PM PDT 24
Finished May 28 02:57:14 PM PDT 24
Peak memory 208592 kb
Host smart-280943dc-c52c-47d1-b971-ed47e47dd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706643516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1706643516
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2830863962
Short name T762
Test name
Test status
Simulation time 226828361 ps
CPU time 6.95 seconds
Started May 28 02:57:13 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 214448 kb
Host smart-733d889a-6478-4088-9996-b40be6cd42c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830863962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2830863962
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2714599884
Short name T312
Test name
Test status
Simulation time 46468908 ps
CPU time 3.17 seconds
Started May 28 02:57:07 PM PDT 24
Finished May 28 02:57:17 PM PDT 24
Peak memory 207880 kb
Host smart-55d7be86-564e-4eec-8f5b-fe55c4dc6198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714599884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2714599884
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.156537905
Short name T45
Test name
Test status
Simulation time 195527890 ps
CPU time 2.65 seconds
Started May 28 02:57:11 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 210596 kb
Host smart-8e772092-cfad-4313-9bf8-186b88ec8d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156537905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.156537905
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2539953780
Short name T626
Test name
Test status
Simulation time 22485351 ps
CPU time 1.07 seconds
Started May 28 02:57:13 PM PDT 24
Finished May 28 02:57:20 PM PDT 24
Peak memory 206176 kb
Host smart-2291dae9-b3dd-4af7-8810-91c5c6873c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539953780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2539953780
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1826412581
Short name T429
Test name
Test status
Simulation time 415291271 ps
CPU time 6.08 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 215132 kb
Host smart-54707373-46ce-4802-9447-342e9a37dba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826412581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1826412581
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.372753365
Short name T714
Test name
Test status
Simulation time 181174096 ps
CPU time 3.54 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 208180 kb
Host smart-0ad154ee-3f02-4b0b-b10d-d362c7537af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372753365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.372753365
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3737383694
Short name T544
Test name
Test status
Simulation time 89259918 ps
CPU time 3.56 seconds
Started May 28 02:57:13 PM PDT 24
Finished May 28 02:57:23 PM PDT 24
Peak memory 214376 kb
Host smart-0bcbe490-d737-4838-a10d-7a7242bf3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737383694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3737383694
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.86963637
Short name T50
Test name
Test status
Simulation time 1305233321 ps
CPU time 4.46 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 221648 kb
Host smart-b650fcaa-54f5-4fac-9a0d-2a0e747e86c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86963637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.86963637
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3188244442
Short name T873
Test name
Test status
Simulation time 271928833 ps
CPU time 1.69 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:23 PM PDT 24
Peak memory 216680 kb
Host smart-698b7e5c-9269-4d20-84d5-ed48c8115170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188244442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3188244442
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.874847930
Short name T194
Test name
Test status
Simulation time 760816410 ps
CPU time 3.76 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 218188 kb
Host smart-45afec09-8c17-4d7a-8228-12e11f868433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874847930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.874847930
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3852828279
Short name T387
Test name
Test status
Simulation time 2005878092 ps
CPU time 9.27 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:32 PM PDT 24
Peak memory 214148 kb
Host smart-d293a7aa-38a0-4e70-95ce-f5cbabbd06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852828279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3852828279
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3260494615
Short name T512
Test name
Test status
Simulation time 207169669 ps
CPU time 2.68 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 206976 kb
Host smart-64cb4f2e-bcea-4511-80f4-8961d32b93c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260494615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3260494615
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3056119624
Short name T454
Test name
Test status
Simulation time 63496738 ps
CPU time 3.35 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 209004 kb
Host smart-d958202d-9a0e-4036-9a0f-63e6b1de0ae5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056119624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3056119624
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.705698172
Short name T90
Test name
Test status
Simulation time 523832924 ps
CPU time 5.39 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 208080 kb
Host smart-a55527cf-ef6a-455e-95d3-04fb50893e58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705698172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.705698172
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1850165618
Short name T519
Test name
Test status
Simulation time 1134810693 ps
CPU time 5.28 seconds
Started May 28 02:57:19 PM PDT 24
Finished May 28 02:57:29 PM PDT 24
Peak memory 207924 kb
Host smart-c265d665-a379-45bd-a1d0-b4864602cab9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850165618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1850165618
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.777369333
Short name T423
Test name
Test status
Simulation time 1376129433 ps
CPU time 4.69 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 217392 kb
Host smart-e3188a1b-d5be-4920-83f2-16eabf1e8d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777369333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.777369333
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3962715755
Short name T623
Test name
Test status
Simulation time 612445586 ps
CPU time 2.82 seconds
Started May 28 02:57:12 PM PDT 24
Finished May 28 02:57:21 PM PDT 24
Peak memory 206920 kb
Host smart-b01925c7-9d9f-49e0-ba75-28593edeb3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962715755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3962715755
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.424926024
Short name T287
Test name
Test status
Simulation time 1139251127 ps
CPU time 16.11 seconds
Started May 28 02:57:22 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 222528 kb
Host smart-c8751f9a-ea04-4579-ab20-752e3e7fc427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424926024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.424926024
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3455518748
Short name T559
Test name
Test status
Simulation time 4474742880 ps
CPU time 78.46 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:58:41 PM PDT 24
Peak memory 208672 kb
Host smart-5f5f2f32-5bdf-48a8-b570-6784d252da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455518748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3455518748
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2016626999
Short name T136
Test name
Test status
Simulation time 219591625 ps
CPU time 1.84 seconds
Started May 28 02:57:21 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 209816 kb
Host smart-af4682f8-43e0-4a79-82e0-d6789788d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016626999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2016626999
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3045625981
Short name T493
Test name
Test status
Simulation time 26702115 ps
CPU time 0.83 seconds
Started May 28 02:57:22 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 205908 kb
Host smart-ca39b313-595c-4db0-8db9-ae7f912c21b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045625981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3045625981
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3936596871
Short name T41
Test name
Test status
Simulation time 806524565 ps
CPU time 4.26 seconds
Started May 28 02:57:18 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 209964 kb
Host smart-7342f49b-2c5a-4282-b755-196b268c7520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936596871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3936596871
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3704526588
Short name T76
Test name
Test status
Simulation time 520630912 ps
CPU time 4.25 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 219796 kb
Host smart-03853cb6-a97e-4820-87df-cced8d7a4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704526588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3704526588
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1452520340
Short name T363
Test name
Test status
Simulation time 128663145 ps
CPU time 5.47 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 222400 kb
Host smart-4381108e-983d-4cff-888e-ea61c915902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452520340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1452520340
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_random.3076194637
Short name T893
Test name
Test status
Simulation time 1596479709 ps
CPU time 42.03 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:58:05 PM PDT 24
Peak memory 219116 kb
Host smart-b3a5a14d-4ab9-4cbd-a71a-06a2e2a854da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076194637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3076194637
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4188321847
Short name T217
Test name
Test status
Simulation time 97925270 ps
CPU time 3.05 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208564 kb
Host smart-ed3b7705-d70e-43ed-8f60-3468c2c9ffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188321847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4188321847
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1876437364
Short name T468
Test name
Test status
Simulation time 86137341 ps
CPU time 1.84 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 206840 kb
Host smart-2700d436-3128-4706-ac03-5b15cc06a256
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876437364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1876437364
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.47973336
Short name T822
Test name
Test status
Simulation time 38124141 ps
CPU time 2.42 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 206940 kb
Host smart-e8375e2e-40f0-4d58-b4fc-8133f5833162
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47973336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.47973336
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2611929344
Short name T825
Test name
Test status
Simulation time 51459379 ps
CPU time 2.28 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208644 kb
Host smart-090762c8-0131-4897-b418-9f9dea5ac191
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611929344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2611929344
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2509832303
Short name T654
Test name
Test status
Simulation time 875742044 ps
CPU time 4.04 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208780 kb
Host smart-5bdbdac3-ce37-42e2-a4bb-aa29d3f7e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509832303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2509832303
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2389110376
Short name T515
Test name
Test status
Simulation time 109481822 ps
CPU time 2.78 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 208340 kb
Host smart-bc2b5672-b3c4-4d86-b5d9-a147c4c7c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389110376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2389110376
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4289443878
Short name T330
Test name
Test status
Simulation time 1103601528 ps
CPU time 10.18 seconds
Started May 28 02:57:13 PM PDT 24
Finished May 28 02:57:29 PM PDT 24
Peak memory 222656 kb
Host smart-094ffb4e-acfa-4f91-8e25-c506ca129584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289443878 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4289443878
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3065396438
Short name T552
Test name
Test status
Simulation time 261437140 ps
CPU time 4.03 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 222484 kb
Host smart-94b2b25a-012a-40f3-979e-a6f066e99b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065396438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3065396438
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.500803623
Short name T650
Test name
Test status
Simulation time 125352509 ps
CPU time 2.85 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 210428 kb
Host smart-4f6b9241-d421-49be-890b-45730085e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500803623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.500803623
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2785005228
Short name T652
Test name
Test status
Simulation time 53004802 ps
CPU time 0.75 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 206004 kb
Host smart-366e04f2-368e-49c9-9dce-59dcd2e7a728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785005228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2785005228
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.593379399
Short name T382
Test name
Test status
Simulation time 346229463 ps
CPU time 4.4 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 221400 kb
Host smart-a487c288-1d5a-43d8-8084-000e2c599680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593379399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.593379399
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1060145493
Short name T554
Test name
Test status
Simulation time 102676049 ps
CPU time 1.91 seconds
Started May 28 02:57:14 PM PDT 24
Finished May 28 02:57:22 PM PDT 24
Peak memory 206464 kb
Host smart-5e418038-7a1b-41a0-8095-11a01f707928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060145493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1060145493
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.657280809
Short name T99
Test name
Test status
Simulation time 394075484 ps
CPU time 5.36 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:28 PM PDT 24
Peak memory 222500 kb
Host smart-3837ef7f-8b5e-4552-bf2d-2c8ac769ba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657280809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.657280809
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.2067973030
Short name T381
Test name
Test status
Simulation time 906965821 ps
CPU time 17.79 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:39 PM PDT 24
Peak memory 214452 kb
Host smart-ba8aa7c9-243e-4823-9e61-b129ade589a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067973030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2067973030
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3679116667
Short name T532
Test name
Test status
Simulation time 445511739 ps
CPU time 3.85 seconds
Started May 28 02:57:18 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 208724 kb
Host smart-04d448d5-1858-42ae-8f52-90665d5b01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679116667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3679116667
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3192134773
Short name T480
Test name
Test status
Simulation time 64490004 ps
CPU time 2.45 seconds
Started May 28 02:57:22 PM PDT 24
Finished May 28 02:57:27 PM PDT 24
Peak memory 208748 kb
Host smart-8eb844a2-6fdb-4496-afd5-fe96c1259282
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192134773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3192134773
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2316084042
Short name T13
Test name
Test status
Simulation time 48452917 ps
CPU time 2.3 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 207064 kb
Host smart-da2d31ba-c15b-492b-850a-f98cbf25acac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316084042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2316084042
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3814345821
Short name T375
Test name
Test status
Simulation time 27690288 ps
CPU time 2.17 seconds
Started May 28 02:57:18 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208760 kb
Host smart-22bf149a-1150-417f-be65-5711269d3873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814345821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3814345821
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.661896390
Short name T702
Test name
Test status
Simulation time 106131024 ps
CPU time 2.79 seconds
Started May 28 02:57:15 PM PDT 24
Finished May 28 02:57:24 PM PDT 24
Peak memory 215900 kb
Host smart-fd8ca1e6-6825-4960-898b-4891c5974dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661896390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.661896390
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.622760503
Short name T904
Test name
Test status
Simulation time 199903624 ps
CPU time 2.71 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:25 PM PDT 24
Peak memory 208496 kb
Host smart-6ee62a9c-aad7-4a7b-9e4c-b89a2e227c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622760503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.622760503
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3094335984
Short name T358
Test name
Test status
Simulation time 625938499 ps
CPU time 9.14 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:57:35 PM PDT 24
Peak memory 220564 kb
Host smart-5e652379-8c32-4454-9215-b7e8adf3ec7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094335984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3094335984
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1469832385
Short name T109
Test name
Test status
Simulation time 204378392 ps
CPU time 8.71 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:57:35 PM PDT 24
Peak memory 220484 kb
Host smart-147f8e9d-7143-4114-8a78-13dbb9b79581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469832385 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1469832385
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2499380031
Short name T608
Test name
Test status
Simulation time 1621087906 ps
CPU time 8.54 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:31 PM PDT 24
Peak memory 208816 kb
Host smart-33bc266b-04dd-4194-936b-fe6601e1415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499380031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2499380031
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1243184778
Short name T44
Test name
Test status
Simulation time 510936517 ps
CPU time 3.4 seconds
Started May 28 02:57:17 PM PDT 24
Finished May 28 02:57:26 PM PDT 24
Peak memory 211024 kb
Host smart-c1d827c9-e5e0-4481-a35e-eb997631acb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243184778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1243184778
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2519191790
Short name T453
Test name
Test status
Simulation time 44923712 ps
CPU time 0.77 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:39 PM PDT 24
Peak memory 206004 kb
Host smart-85cff656-77f4-416b-b26d-547d29891c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519191790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2519191790
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1828942493
Short name T141
Test name
Test status
Simulation time 62664194 ps
CPU time 3.83 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 215248 kb
Host smart-cc40c83a-c6fe-40cc-84b1-6ccae0f37685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828942493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1828942493
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.310547476
Short name T418
Test name
Test status
Simulation time 63190100 ps
CPU time 2.76 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 214448 kb
Host smart-0d28f3fb-f915-4609-af11-a8d811708f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310547476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.310547476
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1865333449
Short name T262
Test name
Test status
Simulation time 528731234 ps
CPU time 5.43 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:45 PM PDT 24
Peak memory 222544 kb
Host smart-f5528094-774d-4470-b417-c00517ddee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865333449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1865333449
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1830937968
Short name T853
Test name
Test status
Simulation time 382876696 ps
CPU time 3.5 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:37 PM PDT 24
Peak memory 217728 kb
Host smart-9176ac3c-4673-4611-8ca7-fc413b3903bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830937968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1830937968
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2762404637
Short name T314
Test name
Test status
Simulation time 228348838 ps
CPU time 6.34 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:45 PM PDT 24
Peak memory 214372 kb
Host smart-1426238a-983c-4f58-8cb8-b44b211e3e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762404637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2762404637
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3281113510
Short name T644
Test name
Test status
Simulation time 7435180131 ps
CPU time 73.71 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:58:36 PM PDT 24
Peak memory 208680 kb
Host smart-37c58723-1eed-44d4-8c68-f769d7ba09e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281113510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3281113510
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1229650991
Short name T475
Test name
Test status
Simulation time 170818572 ps
CPU time 6.78 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:57:33 PM PDT 24
Peak memory 208020 kb
Host smart-c9351b2f-767d-4d00-896a-435eafaa8094
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229650991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1229650991
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.638667374
Short name T520
Test name
Test status
Simulation time 196371564 ps
CPU time 4.54 seconds
Started May 28 02:57:24 PM PDT 24
Finished May 28 02:57:31 PM PDT 24
Peak memory 208992 kb
Host smart-ee104818-db95-4278-bc43-3851296b65da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638667374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.638667374
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2283049645
Short name T671
Test name
Test status
Simulation time 107097468 ps
CPU time 3.9 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 208764 kb
Host smart-1ad8057b-72f8-4309-ad75-a1a9702d1962
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283049645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2283049645
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2080719022
Short name T304
Test name
Test status
Simulation time 73430126 ps
CPU time 2.31 seconds
Started May 28 02:57:30 PM PDT 24
Finished May 28 02:57:34 PM PDT 24
Peak memory 207336 kb
Host smart-349f7865-4ee4-4e1d-a387-43e233bb1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080719022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2080719022
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3479628519
Short name T585
Test name
Test status
Simulation time 970461464 ps
CPU time 25.62 seconds
Started May 28 02:57:16 PM PDT 24
Finished May 28 02:57:47 PM PDT 24
Peak memory 208992 kb
Host smart-8ee0528c-d2d7-4494-8e4e-2f8d64f0f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479628519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3479628519
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2723514406
Short name T754
Test name
Test status
Simulation time 236835702 ps
CPU time 8.61 seconds
Started May 28 02:57:37 PM PDT 24
Finished May 28 02:57:49 PM PDT 24
Peak memory 216124 kb
Host smart-185bba23-d785-44ef-8731-17ec27036efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723514406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2723514406
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3526003398
Short name T555
Test name
Test status
Simulation time 158736768 ps
CPU time 3.15 seconds
Started May 28 02:57:31 PM PDT 24
Finished May 28 02:57:35 PM PDT 24
Peak memory 207236 kb
Host smart-2c83ecf2-f16a-494f-97c2-59491f7e56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526003398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3526003398
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2285291398
Short name T404
Test name
Test status
Simulation time 61594657 ps
CPU time 2.83 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 210312 kb
Host smart-3bb18661-199a-48a8-a6b0-9a8e1e05ebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285291398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2285291398
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.734866457
Short name T504
Test name
Test status
Simulation time 29083000 ps
CPU time 0.73 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:39 PM PDT 24
Peak memory 206000 kb
Host smart-79e5ffc1-09b9-4e18-adf9-e69758e09413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734866457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.734866457
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2392152856
Short name T393
Test name
Test status
Simulation time 120981003 ps
CPU time 2.8 seconds
Started May 28 02:57:32 PM PDT 24
Finished May 28 02:57:36 PM PDT 24
Peak memory 214396 kb
Host smart-c47c7706-8a3c-4f59-8a42-d3650a9fa709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392152856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2392152856
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2382651656
Short name T280
Test name
Test status
Simulation time 417332343 ps
CPU time 2.69 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 210416 kb
Host smart-f1dbfadd-ebe5-456f-8280-53a8da088f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382651656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2382651656
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.275610413
Short name T686
Test name
Test status
Simulation time 125260028 ps
CPU time 3.71 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 214388 kb
Host smart-be83d1cf-43e2-4dc8-911b-1745d7d110a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275610413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.275610413
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3410185094
Short name T298
Test name
Test status
Simulation time 123651673 ps
CPU time 1.95 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:36 PM PDT 24
Peak memory 214324 kb
Host smart-45101511-3529-4056-a6bb-d920722a7102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410185094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3410185094
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.677151823
Short name T66
Test name
Test status
Simulation time 234117051 ps
CPU time 5.04 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:43 PM PDT 24
Peak memory 222528 kb
Host smart-9fbde7d7-d969-455b-8f24-e2948abb1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677151823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.677151823
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.621646094
Short name T745
Test name
Test status
Simulation time 467191233 ps
CPU time 5.03 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 213888 kb
Host smart-64efe5a6-027f-4194-a5ac-12776be3e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621646094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.621646094
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2878034328
Short name T737
Test name
Test status
Simulation time 42244140 ps
CPU time 2.4 seconds
Started May 28 02:57:31 PM PDT 24
Finished May 28 02:57:34 PM PDT 24
Peak memory 208640 kb
Host smart-903293af-7b95-4f61-98fa-23d1e7d2c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878034328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2878034328
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.40199754
Short name T662
Test name
Test status
Simulation time 473683379 ps
CPU time 2.44 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 207056 kb
Host smart-31a14ece-7185-4f34-95df-36fe23742223
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.40199754
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3021217853
Short name T830
Test name
Test status
Simulation time 697566396 ps
CPU time 5.52 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:43 PM PDT 24
Peak memory 208936 kb
Host smart-e8bf0cc5-16c6-4a77-8e54-0b3648b74221
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021217853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3021217853
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1928917979
Short name T564
Test name
Test status
Simulation time 2508784622 ps
CPU time 7.67 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:45 PM PDT 24
Peak memory 208164 kb
Host smart-8df4e8e4-f4cf-457d-a55a-cca94c8f1b84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928917979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1928917979
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2912358128
Short name T885
Test name
Test status
Simulation time 175572818 ps
CPU time 1.81 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:38 PM PDT 24
Peak memory 207652 kb
Host smart-75ced17d-773a-4f5c-96d4-02dbc306a6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912358128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2912358128
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3952694239
Short name T787
Test name
Test status
Simulation time 425399748 ps
CPU time 4.49 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:42 PM PDT 24
Peak memory 208908 kb
Host smart-9299e545-5322-4ac4-9fee-27f1d0e17def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952694239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3952694239
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4104932372
Short name T82
Test name
Test status
Simulation time 29167548050 ps
CPU time 178.61 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 03:00:36 PM PDT 24
Peak memory 222536 kb
Host smart-9475650a-d316-48ef-b025-e289fc3f3613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104932372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4104932372
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1777677492
Short name T25
Test name
Test status
Simulation time 893745099 ps
CPU time 4.84 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:43 PM PDT 24
Peak memory 207092 kb
Host smart-d3c15049-f36d-44bf-8a94-8141e979e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777677492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1777677492
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.386093904
Short name T135
Test name
Test status
Simulation time 38871028 ps
CPU time 2.35 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 210432 kb
Host smart-e96e18e2-c4d4-4085-a9ed-f2171d9409e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386093904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.386093904
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3474809082
Short name T582
Test name
Test status
Simulation time 28502998 ps
CPU time 0.73 seconds
Started May 28 02:57:36 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 205964 kb
Host smart-dc48fd85-933f-483e-ad18-f55520d88df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474809082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3474809082
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1554227122
Short name T290
Test name
Test status
Simulation time 213437335 ps
CPU time 4.13 seconds
Started May 28 02:57:38 PM PDT 24
Finished May 28 02:57:46 PM PDT 24
Peak memory 215096 kb
Host smart-5bae02a2-0f38-47bc-8639-097df8480d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554227122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1554227122
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3124547075
Short name T566
Test name
Test status
Simulation time 315993073 ps
CPU time 3.24 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 222968 kb
Host smart-bcd4def4-b662-4ecc-8737-5b75c760bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124547075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3124547075
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2492948461
Short name T903
Test name
Test status
Simulation time 825199861 ps
CPU time 2.92 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 209920 kb
Host smart-65a23a22-a71a-4cb1-8fbf-c78c04da1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492948461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2492948461
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3686548396
Short name T748
Test name
Test status
Simulation time 46118240 ps
CPU time 3.05 seconds
Started May 28 02:57:37 PM PDT 24
Finished May 28 02:57:44 PM PDT 24
Peak memory 209352 kb
Host smart-d7119c01-daab-4ae4-9499-726eea108b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686548396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3686548396
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.282224659
Short name T882
Test name
Test status
Simulation time 116294042 ps
CPU time 2.71 seconds
Started May 28 02:57:37 PM PDT 24
Finished May 28 02:57:43 PM PDT 24
Peak memory 214364 kb
Host smart-3552bf69-2a32-467c-8a5d-cbb0e673225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282224659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.282224659
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1133901926
Short name T881
Test name
Test status
Simulation time 30708374 ps
CPU time 2.39 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:39 PM PDT 24
Peak memory 207860 kb
Host smart-9408516f-dcfc-4b61-ac87-6cff2e7be8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133901926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1133901926
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2925530411
Short name T522
Test name
Test status
Simulation time 130160762 ps
CPU time 4.3 seconds
Started May 28 02:57:32 PM PDT 24
Finished May 28 02:57:38 PM PDT 24
Peak memory 208148 kb
Host smart-0f3fbdfc-e017-471a-a5f3-1e3fa56fa29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925530411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2925530411
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3005459691
Short name T279
Test name
Test status
Simulation time 401423872 ps
CPU time 5.13 seconds
Started May 28 02:57:33 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 208060 kb
Host smart-f0ecc3cf-fa38-4d7f-a4cb-844f2613ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005459691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3005459691
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3994976021
Short name T534
Test name
Test status
Simulation time 1931921847 ps
CPU time 45.04 seconds
Started May 28 02:57:37 PM PDT 24
Finished May 28 02:58:26 PM PDT 24
Peak memory 208052 kb
Host smart-5728ad0c-efff-480d-9964-a34a4f445fdf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994976021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3994976021
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3166750244
Short name T665
Test name
Test status
Simulation time 74843873 ps
CPU time 3.83 seconds
Started May 28 02:58:22 PM PDT 24
Finished May 28 02:58:47 PM PDT 24
Peak memory 208864 kb
Host smart-5e90ad98-5467-413c-84e1-d582835c6ee3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166750244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3166750244
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1962730077
Short name T228
Test name
Test status
Simulation time 48551521 ps
CPU time 2.58 seconds
Started May 28 02:57:31 PM PDT 24
Finished May 28 02:57:35 PM PDT 24
Peak memory 207068 kb
Host smart-9010c02f-43d1-477c-8c20-fbcd8b5d21d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962730077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1962730077
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4156087646
Short name T473
Test name
Test status
Simulation time 35888107 ps
CPU time 2.22 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 215592 kb
Host smart-bd59ccd9-dadd-4d39-a11a-745a7b995e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156087646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4156087646
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.144270206
Short name T620
Test name
Test status
Simulation time 3815335561 ps
CPU time 36.54 seconds
Started May 28 02:57:36 PM PDT 24
Finished May 28 02:58:17 PM PDT 24
Peak memory 208400 kb
Host smart-79bcfdb2-b42e-4e16-bfef-bb01b6750783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144270206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.144270206
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2899018739
Short name T884
Test name
Test status
Simulation time 734206566 ps
CPU time 8.44 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:47 PM PDT 24
Peak memory 209016 kb
Host smart-2de7d6b2-3824-4309-be44-b927440773f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899018739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2899018739
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1454073971
Short name T407
Test name
Test status
Simulation time 53267975 ps
CPU time 2.21 seconds
Started May 28 02:57:32 PM PDT 24
Finished May 28 02:57:36 PM PDT 24
Peak memory 210328 kb
Host smart-a13c96fb-f895-4054-a704-76d8b90409f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454073971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1454073971
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.717371435
Short name T781
Test name
Test status
Simulation time 32017118 ps
CPU time 0.84 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:00 PM PDT 24
Peak memory 206008 kb
Host smart-651baf6a-db88-42c7-90c4-50e77cada6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717371435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.717371435
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4030293078
Short name T634
Test name
Test status
Simulation time 47815637 ps
CPU time 3.09 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:00 PM PDT 24
Peak memory 214396 kb
Host smart-d9f8aa63-3afe-4f73-9bd9-20df68486437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030293078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4030293078
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3238485700
Short name T106
Test name
Test status
Simulation time 548453756 ps
CPU time 5.3 seconds
Started May 28 02:57:53 PM PDT 24
Finished May 28 02:58:05 PM PDT 24
Peak memory 214380 kb
Host smart-1604d91b-69e2-4b4b-a6d1-068ad52802ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238485700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3238485700
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3236202080
Short name T318
Test name
Test status
Simulation time 259090482 ps
CPU time 2.82 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:58 PM PDT 24
Peak memory 222496 kb
Host smart-29fdaa64-3675-4182-9175-a9ced4bf29aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236202080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3236202080
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4002887390
Short name T246
Test name
Test status
Simulation time 1766330081 ps
CPU time 27.32 seconds
Started May 28 02:57:55 PM PDT 24
Finished May 28 02:58:31 PM PDT 24
Peak memory 222560 kb
Host smart-ca39ca9b-bf2b-4455-8564-2edaceeb72e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002887390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4002887390
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2037829428
Short name T707
Test name
Test status
Simulation time 2657346917 ps
CPU time 7.53 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:04 PM PDT 24
Peak memory 208848 kb
Host smart-5d29d7c4-6580-4108-840d-bd4ab7fc4760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037829428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2037829428
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1165993897
Short name T716
Test name
Test status
Simulation time 142372833 ps
CPU time 2.66 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 206924 kb
Host smart-375b5c77-1379-494f-a4f4-44b9478811c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165993897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1165993897
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2939039596
Short name T589
Test name
Test status
Simulation time 110180875 ps
CPU time 2.91 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:59 PM PDT 24
Peak memory 208956 kb
Host smart-5a932ca2-83bf-45a9-9add-a429e1283801
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939039596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2939039596
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1734294282
Short name T602
Test name
Test status
Simulation time 55258176 ps
CPU time 2.61 seconds
Started May 28 02:57:34 PM PDT 24
Finished May 28 02:57:40 PM PDT 24
Peak memory 208096 kb
Host smart-b1c35682-09bc-4e5a-861d-2cf9942842eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734294282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1734294282
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3089002994
Short name T477
Test name
Test status
Simulation time 45048374 ps
CPU time 2.44 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:54 PM PDT 24
Peak memory 207072 kb
Host smart-2de40283-e16a-4ca4-bf71-f9a9f63e0f55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089002994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3089002994
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2990052461
Short name T803
Test name
Test status
Simulation time 119843421 ps
CPU time 3.4 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:59 PM PDT 24
Peak memory 214408 kb
Host smart-564555ba-84c4-4fa0-9973-f25ef376ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990052461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2990052461
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.276329779
Short name T87
Test name
Test status
Simulation time 273409784 ps
CPU time 2.92 seconds
Started May 28 02:57:35 PM PDT 24
Finished May 28 02:57:41 PM PDT 24
Peak memory 207972 kb
Host smart-2c77bb1b-8832-46d0-9747-4b4f42a57509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276329779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.276329779
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4173833064
Short name T204
Test name
Test status
Simulation time 8933776149 ps
CPU time 74.15 seconds
Started May 28 02:57:56 PM PDT 24
Finished May 28 02:59:21 PM PDT 24
Peak memory 215880 kb
Host smart-2c620533-0d0f-4010-b907-5b850645fd7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173833064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4173833064
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3023590781
Short name T129
Test name
Test status
Simulation time 204061158 ps
CPU time 6.37 seconds
Started May 28 02:57:56 PM PDT 24
Finished May 28 02:58:12 PM PDT 24
Peak memory 218640 kb
Host smart-3676547a-832c-45cc-8f1f-e952df378ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023590781 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3023590781
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3097625559
Short name T26
Test name
Test status
Simulation time 333081592 ps
CPU time 4.76 seconds
Started May 28 02:57:48 PM PDT 24
Finished May 28 02:57:53 PM PDT 24
Peak memory 214476 kb
Host smart-f3981e86-f1c1-4d49-b782-93911c407c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097625559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3097625559
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3181437412
Short name T172
Test name
Test status
Simulation time 54163701 ps
CPU time 2.9 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:59 PM PDT 24
Peak memory 210416 kb
Host smart-d41d9376-4d87-4805-adb0-8b2a456d46f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181437412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3181437412
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4151497976
Short name T832
Test name
Test status
Simulation time 28279631 ps
CPU time 0.88 seconds
Started May 28 02:57:56 PM PDT 24
Finished May 28 02:58:07 PM PDT 24
Peak memory 206004 kb
Host smart-700216ec-0983-472a-b7d6-220f59ddcdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151497976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4151497976
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2338070766
Short name T311
Test name
Test status
Simulation time 303453851 ps
CPU time 4.1 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:03 PM PDT 24
Peak memory 214380 kb
Host smart-36b8777d-23f9-4d20-8090-8d99a2aba287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338070766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2338070766
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.927744233
Short name T894
Test name
Test status
Simulation time 531521397 ps
CPU time 2.83 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:55 PM PDT 24
Peak memory 218160 kb
Host smart-abcb479d-6cdd-4ff1-af83-efa2d0f1bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927744233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.927744233
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2527112813
Short name T207
Test name
Test status
Simulation time 60268760 ps
CPU time 2.21 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:54 PM PDT 24
Peak memory 207476 kb
Host smart-f9a34c4c-f117-4179-9eaf-5a7341beaf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527112813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2527112813
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1007026624
Short name T901
Test name
Test status
Simulation time 153520797 ps
CPU time 2.89 seconds
Started May 28 02:57:53 PM PDT 24
Finished May 28 02:58:03 PM PDT 24
Peak memory 209100 kb
Host smart-e6eaa8d2-9bda-4eba-bcbf-04fe6eebfc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007026624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1007026624
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1044459870
Short name T870
Test name
Test status
Simulation time 165210517 ps
CPU time 4.09 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:56 PM PDT 24
Peak memory 214324 kb
Host smart-0a82d2da-0f0e-452d-aeeb-e8636013d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044459870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1044459870
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1478475621
Short name T844
Test name
Test status
Simulation time 100840959 ps
CPU time 3.95 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:54 PM PDT 24
Peak memory 209588 kb
Host smart-185b9641-bb22-4682-84db-cd8ab58df9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478475621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1478475621
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3916545012
Short name T370
Test name
Test status
Simulation time 154750204 ps
CPU time 3.23 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:55 PM PDT 24
Peak memory 209856 kb
Host smart-ec2914c4-6bb4-4324-9e8e-5b77fe24ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916545012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3916545012
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2099678086
Short name T595
Test name
Test status
Simulation time 218216642 ps
CPU time 2.23 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:54 PM PDT 24
Peak memory 206912 kb
Host smart-c0e841b1-64cb-48e0-b28e-c684bd4258c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099678086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2099678086
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1733165613
Short name T772
Test name
Test status
Simulation time 152987584 ps
CPU time 2.3 seconds
Started May 28 02:57:56 PM PDT 24
Finished May 28 02:58:09 PM PDT 24
Peak memory 206988 kb
Host smart-da15daea-17e6-489b-8bef-a94c4c142705
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733165613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1733165613
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1258884259
Short name T385
Test name
Test status
Simulation time 4899247071 ps
CPU time 46.47 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:58:38 PM PDT 24
Peak memory 209200 kb
Host smart-8d7ab125-7a9b-4c12-8c3c-568bc278762c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258884259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1258884259
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3941453495
Short name T680
Test name
Test status
Simulation time 62834097 ps
CPU time 2.94 seconds
Started May 28 02:57:51 PM PDT 24
Finished May 28 02:57:59 PM PDT 24
Peak memory 208144 kb
Host smart-6d8d7487-4f40-4d5c-876d-8605a156dad9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941453495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3941453495
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2658054449
Short name T850
Test name
Test status
Simulation time 62787645 ps
CPU time 3.11 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:02 PM PDT 24
Peak memory 209080 kb
Host smart-17256038-a8a8-4fd5-ae08-6784e45f9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658054449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2658054449
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.394188575
Short name T761
Test name
Test status
Simulation time 117912202 ps
CPU time 1.65 seconds
Started May 28 02:57:50 PM PDT 24
Finished May 28 02:57:52 PM PDT 24
Peak memory 206904 kb
Host smart-ba3faaff-f8a4-4b6d-a060-3f67bdea7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394188575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.394188575
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2964515450
Short name T698
Test name
Test status
Simulation time 58672913 ps
CPU time 3.47 seconds
Started May 28 02:57:48 PM PDT 24
Finished May 28 02:57:52 PM PDT 24
Peak memory 209416 kb
Host smart-932d6f39-6100-4bc6-b5ec-cf115ec6df95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964515450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2964515450
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3622727613
Short name T688
Test name
Test status
Simulation time 155720064 ps
CPU time 3.12 seconds
Started May 28 02:57:53 PM PDT 24
Finished May 28 02:58:02 PM PDT 24
Peak memory 207436 kb
Host smart-56dfe75f-6fa5-49c3-ba8f-7ae2304348c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622727613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3622727613
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.868588028
Short name T131
Test name
Test status
Simulation time 168696511 ps
CPU time 3.39 seconds
Started May 28 02:57:52 PM PDT 24
Finished May 28 02:58:01 PM PDT 24
Peak memory 219380 kb
Host smart-6fec195b-6c26-4b90-96f4-73091c3115c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868588028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.868588028
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.986988702
Short name T759
Test name
Test status
Simulation time 10453473 ps
CPU time 0.83 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 206000 kb
Host smart-00729b8a-2e3a-4d6a-9841-e2f9e6136417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986988702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.986988702
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.932846462
Short name T30
Test name
Test status
Simulation time 369623943 ps
CPU time 5 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:45 PM PDT 24
Peak memory 217196 kb
Host smart-17e90c89-5e58-487e-bcd7-f6c296c95ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932846462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.932846462
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2137602589
Short name T460
Test name
Test status
Simulation time 181154659 ps
CPU time 5.49 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:47 PM PDT 24
Peak memory 209524 kb
Host smart-7acd3939-84ca-4d1a-888a-74e59161ecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137602589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2137602589
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2020752120
Short name T104
Test name
Test status
Simulation time 65416470 ps
CPU time 2.41 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 210132 kb
Host smart-6cd50929-c4a6-44b3-901d-33e067d4a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020752120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2020752120
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1056243806
Short name T455
Test name
Test status
Simulation time 222912949 ps
CPU time 3.11 seconds
Started May 28 02:55:26 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 222460 kb
Host smart-a897f486-dc11-4119-b3ec-23b6c742163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056243806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1056243806
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3598599808
Short name T235
Test name
Test status
Simulation time 297530092 ps
CPU time 3.05 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:45 PM PDT 24
Peak memory 219772 kb
Host smart-64452842-3dca-4df3-8c12-f63519b5db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598599808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3598599808
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1510951094
Short name T880
Test name
Test status
Simulation time 137669048 ps
CPU time 5.74 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 214384 kb
Host smart-1b5be829-f07d-423c-9d81-d1a608cd06f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510951094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1510951094
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2171117516
Short name T751
Test name
Test status
Simulation time 371122319 ps
CPU time 3.3 seconds
Started May 28 02:55:24 PM PDT 24
Finished May 28 02:55:41 PM PDT 24
Peak memory 207200 kb
Host smart-5717fa88-bf52-4084-a246-1087edda7ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171117516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2171117516
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3355446530
Short name T791
Test name
Test status
Simulation time 161693955 ps
CPU time 4.27 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 208592 kb
Host smart-95589bd9-40e0-43f2-b001-87b2ba6b518f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355446530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3355446530
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.535312546
Short name T86
Test name
Test status
Simulation time 348022477 ps
CPU time 5.41 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:48 PM PDT 24
Peak memory 207924 kb
Host smart-2a1b61b4-e937-4a22-9a7b-5f97ac056bbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535312546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.535312546
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.463466324
Short name T775
Test name
Test status
Simulation time 39481695 ps
CPU time 1.71 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 207016 kb
Host smart-ff365a0b-310f-4009-aa36-2431d59b860e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463466324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.463466324
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2489391069
Short name T451
Test name
Test status
Simulation time 71717852 ps
CPU time 1.93 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:44 PM PDT 24
Peak memory 218368 kb
Host smart-10f445ea-c797-4a83-b718-19c791f08b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489391069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2489391069
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2855476609
Short name T817
Test name
Test status
Simulation time 132084553 ps
CPU time 2.42 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 207544 kb
Host smart-c7cf3a96-6daf-4139-bdb6-c0cb90ac240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855476609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2855476609
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.748545124
Short name T706
Test name
Test status
Simulation time 267837974 ps
CPU time 14.53 seconds
Started May 28 02:55:26 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 215600 kb
Host smart-a721625c-a34a-47ec-9956-b5cc1d37f1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748545124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.748545124
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3397969209
Short name T127
Test name
Test status
Simulation time 1556996096 ps
CPU time 8.4 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 220400 kb
Host smart-4f36deda-bc81-4f0c-a222-c9fc39e120a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397969209 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3397969209
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.984250231
Short name T619
Test name
Test status
Simulation time 367166657 ps
CPU time 7.17 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:50 PM PDT 24
Peak memory 214364 kb
Host smart-40614dca-271a-4adb-91c8-733afb35107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984250231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.984250231
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3201684341
Short name T829
Test name
Test status
Simulation time 71297896 ps
CPU time 2.46 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:47 PM PDT 24
Peak memory 210352 kb
Host smart-ab64e71f-bd01-4d35-b9d1-02bd11337549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201684341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3201684341
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1468218500
Short name T551
Test name
Test status
Simulation time 25857366 ps
CPU time 0.75 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:33 PM PDT 24
Peak memory 205724 kb
Host smart-50b9293d-61fb-4698-91ab-e1c695d29224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468218500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1468218500
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3038152472
Short name T723
Test name
Test status
Simulation time 201257048 ps
CPU time 3.76 seconds
Started May 28 02:55:21 PM PDT 24
Finished May 28 02:55:36 PM PDT 24
Peak memory 214388 kb
Host smart-f27a91e8-4083-4c67-9cf3-43a2900714d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038152472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3038152472
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2453985942
Short name T806
Test name
Test status
Simulation time 629619151 ps
CPU time 3.78 seconds
Started May 28 02:55:24 PM PDT 24
Finished May 28 02:55:42 PM PDT 24
Peak memory 208236 kb
Host smart-3ad4f4c8-abbf-415d-bfed-97525558aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453985942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2453985942
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.499730080
Short name T103
Test name
Test status
Simulation time 188771506 ps
CPU time 5.17 seconds
Started May 28 02:55:27 PM PDT 24
Finished May 28 02:55:47 PM PDT 24
Peak memory 214432 kb
Host smart-96a543b2-4b6d-4658-b521-8ce420858a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499730080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.499730080
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2152404378
Short name T380
Test name
Test status
Simulation time 46081909 ps
CPU time 1.78 seconds
Started May 28 02:55:26 PM PDT 24
Finished May 28 02:55:42 PM PDT 24
Peak memory 219272 kb
Host smart-b902cf61-006f-4514-93c2-741d557d0154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152404378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2152404378
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1443475743
Short name T570
Test name
Test status
Simulation time 633901086 ps
CPU time 3.99 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 210004 kb
Host smart-8e2fd453-8fa2-4427-ba7a-60ebee909961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443475743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1443475743
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.528645535
Short name T526
Test name
Test status
Simulation time 1903879270 ps
CPU time 21.44 seconds
Started May 28 02:55:24 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 209124 kb
Host smart-6177c6e5-646f-4948-a596-d386edd90cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528645535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.528645535
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3800891368
Short name T710
Test name
Test status
Simulation time 84233933 ps
CPU time 3.41 seconds
Started May 28 02:55:28 PM PDT 24
Finished May 28 02:55:47 PM PDT 24
Peak memory 208656 kb
Host smart-ac2323e9-304b-4d83-8d5f-bf3d207aa231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800891368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3800891368
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3600294780
Short name T645
Test name
Test status
Simulation time 24838128 ps
CPU time 1.87 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 207408 kb
Host smart-5fe6f8ad-f923-4712-b691-124a0bc3983e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600294780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3600294780
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2350011550
Short name T584
Test name
Test status
Simulation time 24737611 ps
CPU time 1.97 seconds
Started May 28 02:55:24 PM PDT 24
Finished May 28 02:55:40 PM PDT 24
Peak memory 208624 kb
Host smart-2d066f5d-7cd5-4d44-ad62-563ab5fc80c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350011550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2350011550
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4186282955
Short name T758
Test name
Test status
Simulation time 411763428 ps
CPU time 3.55 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:43 PM PDT 24
Peak memory 207468 kb
Host smart-4ee73afa-82e2-4646-b7cb-7b94a9081acd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186282955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4186282955
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3094033009
Short name T711
Test name
Test status
Simulation time 266620826 ps
CPU time 3.55 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:38 PM PDT 24
Peak memory 208744 kb
Host smart-d504b5fe-7d7a-45d3-a931-8161ff0a1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094033009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3094033009
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2306525184
Short name T757
Test name
Test status
Simulation time 787976425 ps
CPU time 13.39 seconds
Started May 28 02:55:23 PM PDT 24
Finished May 28 02:55:50 PM PDT 24
Peak memory 208820 kb
Host smart-e424d7bf-7313-4b0f-aa3c-466b96970fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306525184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2306525184
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.339157632
Short name T839
Test name
Test status
Simulation time 4018035552 ps
CPU time 41.37 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 222616 kb
Host smart-6bc2c4cb-3736-41ad-8dfd-0bc8f644e4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339157632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.339157632
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3783281826
Short name T629
Test name
Test status
Simulation time 110626620 ps
CPU time 2.39 seconds
Started May 28 02:55:22 PM PDT 24
Finished May 28 02:55:35 PM PDT 24
Peak memory 208880 kb
Host smart-44935a69-279a-4ba2-97fe-01bfee5163c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783281826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3783281826
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1988911998
Short name T779
Test name
Test status
Simulation time 120727019 ps
CPU time 0.87 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:50 PM PDT 24
Peak memory 206004 kb
Host smart-74d7eee5-c86e-4e2d-917b-644976f56421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988911998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1988911998
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1293874198
Short name T694
Test name
Test status
Simulation time 40821812 ps
CPU time 2.76 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 215608 kb
Host smart-ae44a073-7b7e-44e3-9635-776894e58b82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293874198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1293874198
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3746111472
Short name T808
Test name
Test status
Simulation time 204002024 ps
CPU time 2.79 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 218244 kb
Host smart-5a63a0ef-de58-4f65-9240-46e286458466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746111472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3746111472
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3578908736
Short name T67
Test name
Test status
Simulation time 78206193 ps
CPU time 2.72 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:10 PM PDT 24
Peak memory 210108 kb
Host smart-ce649c49-98db-46c2-8379-65856d4c3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578908736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3578908736
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3446806990
Short name T594
Test name
Test status
Simulation time 1026436354 ps
CPU time 3.39 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 209016 kb
Host smart-653a44e2-7f9c-437f-b50a-c12ad962653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446806990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3446806990
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3597858045
Short name T40
Test name
Test status
Simulation time 157594456 ps
CPU time 4.25 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 218744 kb
Host smart-b46c6901-d017-4b58-9e66-b2b6d9bfc383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597858045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3597858045
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.16217250
Short name T777
Test name
Test status
Simulation time 33796003 ps
CPU time 2.54 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 209200 kb
Host smart-107255ce-c908-43d4-931f-818c0c57a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16217250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.16217250
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.204267231
Short name T299
Test name
Test status
Simulation time 469856725 ps
CPU time 5.3 seconds
Started May 28 02:55:32 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 219536 kb
Host smart-ba7df0db-5c0c-4e04-b1a6-c62c8fd96d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204267231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.204267231
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.319794416
Short name T525
Test name
Test status
Simulation time 306186269 ps
CPU time 2.88 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 208508 kb
Host smart-81e1d956-d161-48fa-a19a-1f4c612743fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319794416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.319794416
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1415284494
Short name T875
Test name
Test status
Simulation time 500747688 ps
CPU time 3.86 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 208856 kb
Host smart-3a59df5c-3f1f-4994-b671-5b607abee055
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415284494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1415284494
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.885030744
Short name T756
Test name
Test status
Simulation time 281891677 ps
CPU time 4.3 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 208916 kb
Host smart-7f0bd92b-7f91-4242-af9f-63c2a17f48b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885030744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.885030744
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2694890235
Short name T858
Test name
Test status
Simulation time 171027736 ps
CPU time 5.39 seconds
Started May 28 02:55:33 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 208100 kb
Host smart-3f7b67a6-e616-4f85-ac49-06be1301890e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694890235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2694890235
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.907562687
Short name T572
Test name
Test status
Simulation time 87455974 ps
CPU time 1.54 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:49 PM PDT 24
Peak memory 208124 kb
Host smart-7b9f350f-3fc6-401f-804b-4aa644015a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907562687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.907562687
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1773588261
Short name T682
Test name
Test status
Simulation time 709353281 ps
CPU time 5.69 seconds
Started May 28 02:55:25 PM PDT 24
Finished May 28 02:55:45 PM PDT 24
Peak memory 208620 kb
Host smart-130c55bb-e7db-4f7b-a362-86919ccac5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773588261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1773588261
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4079930554
Short name T255
Test name
Test status
Simulation time 3023018263 ps
CPU time 32.59 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:56:21 PM PDT 24
Peak memory 222512 kb
Host smart-738ff1f1-7159-4e53-b346-0a21e879b83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079930554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4079930554
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1450016967
Short name T592
Test name
Test status
Simulation time 1305330776 ps
CPU time 4.8 seconds
Started May 28 02:55:33 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 208020 kb
Host smart-aefc2183-a41a-4770-8446-afcb4aef525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450016967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1450016967
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3020256195
Short name T64
Test name
Test status
Simulation time 537090657 ps
CPU time 1.94 seconds
Started May 28 02:55:32 PM PDT 24
Finished May 28 02:55:48 PM PDT 24
Peak memory 209828 kb
Host smart-ee7c28b4-cfdf-4a9f-bb62-456bdb641870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020256195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3020256195
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3657358972
Short name T627
Test name
Test status
Simulation time 21450429 ps
CPU time 0.97 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:49 PM PDT 24
Peak memory 206168 kb
Host smart-a465ee1f-824e-444a-81b7-97a3d7e9f022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657358972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3657358972
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4008617124
Short name T430
Test name
Test status
Simulation time 102026306 ps
CPU time 5.93 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 214380 kb
Host smart-5d79254e-9645-4804-bcc2-9777e7e5fb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008617124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4008617124
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3400146653
Short name T649
Test name
Test status
Simulation time 232870319 ps
CPU time 2 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:09 PM PDT 24
Peak memory 220020 kb
Host smart-296575ff-a159-45b7-a657-90065c0f8c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400146653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3400146653
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.750424974
Short name T433
Test name
Test status
Simulation time 109489792 ps
CPU time 1.46 seconds
Started May 28 02:55:33 PM PDT 24
Finished May 28 02:55:49 PM PDT 24
Peak memory 207424 kb
Host smart-1dbd03eb-8163-487f-9fc3-31eeda436bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750424974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.750424974
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4101069876
Short name T285
Test name
Test status
Simulation time 39073322 ps
CPU time 2.92 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 215252 kb
Host smart-2709e6b8-7087-46f0-821a-0b8f97647b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101069876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4101069876
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1004392198
Short name T889
Test name
Test status
Simulation time 454546508 ps
CPU time 5.55 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 222476 kb
Host smart-e112de5c-1cb8-462a-9350-7392e265d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004392198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1004392198
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3907456294
Short name T196
Test name
Test status
Simulation time 664984557 ps
CPU time 5.68 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 209540 kb
Host smart-b9956dfb-57a2-49ff-b92a-5eef860df8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907456294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3907456294
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2929229432
Short name T697
Test name
Test status
Simulation time 843171492 ps
CPU time 5.48 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 208044 kb
Host smart-d6b1f7a4-1af6-48d7-9317-b9e551af18f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929229432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2929229432
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1400969739
Short name T271
Test name
Test status
Simulation time 111147138 ps
CPU time 3.46 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:52 PM PDT 24
Peak memory 208476 kb
Host smart-c4c8866b-8a62-41ed-b5f4-081daaa79ab9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400969739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1400969739
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.396208669
Short name T860
Test name
Test status
Simulation time 3464477126 ps
CPU time 47.68 seconds
Started May 28 02:55:32 PM PDT 24
Finished May 28 02:56:34 PM PDT 24
Peak memory 209052 kb
Host smart-fa5d8d98-dd23-45b8-884a-380cd16ad02d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396208669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.396208669
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2396572337
Short name T826
Test name
Test status
Simulation time 211537413 ps
CPU time 5.55 seconds
Started May 28 02:55:39 PM PDT 24
Finished May 28 02:55:58 PM PDT 24
Peak memory 209012 kb
Host smart-b46ce9b5-e22d-42ba-ab94-eab930b0e34a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396572337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2396572337
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.815549397
Short name T432
Test name
Test status
Simulation time 57034689 ps
CPU time 2.53 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 215664 kb
Host smart-021b9519-9bc3-4065-976d-9151aa9997fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815549397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.815549397
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.68871350
Short name T793
Test name
Test status
Simulation time 351123381 ps
CPU time 9.68 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:59 PM PDT 24
Peak memory 207928 kb
Host smart-504f93b1-b28c-4203-b579-230abcbd170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68871350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.68871350
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3353631483
Short name T809
Test name
Test status
Simulation time 270958093 ps
CPU time 2.78 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:50 PM PDT 24
Peak memory 222644 kb
Host smart-a5493b76-343d-43b4-82de-c4bcfcc1543f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353631483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3353631483
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.111536300
Short name T673
Test name
Test status
Simulation time 149421583 ps
CPU time 6.36 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 209388 kb
Host smart-8dbc4733-23cf-4ad3-845d-de59b1f2bd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111536300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.111536300
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2289387110
Short name T876
Test name
Test status
Simulation time 179863670 ps
CPU time 2.51 seconds
Started May 28 02:55:33 PM PDT 24
Finished May 28 02:55:50 PM PDT 24
Peak memory 210088 kb
Host smart-348c3355-ebec-4b64-88b3-12ebe27fad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289387110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2289387110
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3120468416
Short name T530
Test name
Test status
Simulation time 15262727 ps
CPU time 0.9 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:51 PM PDT 24
Peak memory 206180 kb
Host smart-19a455dd-9f6f-43a4-8cc7-b643c58095b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120468416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3120468416
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.251224482
Short name T851
Test name
Test status
Simulation time 234624194 ps
CPU time 2.9 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 208668 kb
Host smart-d307f447-2eee-46f3-a6c9-144c56e0648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251224482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.251224482
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1138146148
Short name T342
Test name
Test status
Simulation time 375925279 ps
CPU time 9.46 seconds
Started May 28 02:55:56 PM PDT 24
Finished May 28 02:56:16 PM PDT 24
Peak memory 214616 kb
Host smart-efe1d4b8-8e70-48d9-a17a-0d9f65ca40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138146148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1138146148
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1473567813
Short name T93
Test name
Test status
Simulation time 180860490 ps
CPU time 4.5 seconds
Started May 28 02:55:34 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 222120 kb
Host smart-1a6ec1d9-b5c0-4d91-aa12-0a25ca45deb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473567813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1473567813
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1811193477
Short name T110
Test name
Test status
Simulation time 48823570 ps
CPU time 3.23 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 215200 kb
Host smart-5961b288-0467-4dab-a259-3c1090ba0d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811193477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1811193477
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4188550933
Short name T785
Test name
Test status
Simulation time 291708642 ps
CPU time 5.52 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 210328 kb
Host smart-002514d6-cdfe-43c8-b9c7-d98c998b9492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188550933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4188550933
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1815559716
Short name T575
Test name
Test status
Simulation time 102051374 ps
CPU time 3.54 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 207736 kb
Host smart-ff7433fa-ff7a-4f73-9851-eb12c3cb0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815559716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1815559716
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.132061839
Short name T509
Test name
Test status
Simulation time 5703039877 ps
CPU time 39.05 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:56:29 PM PDT 24
Peak memory 209120 kb
Host smart-94b01a75-efa0-4a5b-bb77-f5cd8eecbe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132061839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.132061839
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3519120994
Short name T307
Test name
Test status
Simulation time 91287072 ps
CPU time 2.87 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 207088 kb
Host smart-f7bb927c-2067-4ee0-883a-4ea2e73f6ef2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519120994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3519120994
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.863915704
Short name T208
Test name
Test status
Simulation time 379842986 ps
CPU time 6.18 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:55:56 PM PDT 24
Peak memory 208108 kb
Host smart-dfdd6914-6e70-492d-a00a-0128f7da30aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863915704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.863915704
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2122777569
Short name T341
Test name
Test status
Simulation time 4060005243 ps
CPU time 37.81 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:56:28 PM PDT 24
Peak memory 208740 kb
Host smart-296d8591-cae6-43c8-a562-7a0efd3a3d46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122777569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2122777569
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1987547163
Short name T462
Test name
Test status
Simulation time 924196956 ps
CPU time 4.14 seconds
Started May 28 02:55:37 PM PDT 24
Finished May 28 02:55:55 PM PDT 24
Peak memory 218328 kb
Host smart-cc99e287-ac18-4897-8f84-8689a42e78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987547163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1987547163
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.86824512
Short name T910
Test name
Test status
Simulation time 190180147 ps
CPU time 4.26 seconds
Started May 28 02:55:35 PM PDT 24
Finished May 28 02:55:53 PM PDT 24
Peak memory 208368 kb
Host smart-4a504116-367e-46a3-b76d-0eae47e053d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86824512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.86824512
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4260834456
Short name T835
Test name
Test status
Simulation time 1703401812 ps
CPU time 65.38 seconds
Started May 28 02:55:36 PM PDT 24
Finished May 28 02:56:55 PM PDT 24
Peak memory 214444 kb
Host smart-2dc80f2e-0710-47f6-8cb2-055e6869f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260834456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4260834456
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.870703880
Short name T176
Test name
Test status
Simulation time 238675687 ps
CPU time 1.75 seconds
Started May 28 02:55:38 PM PDT 24
Finished May 28 02:55:54 PM PDT 24
Peak memory 209908 kb
Host smart-0b06cd55-7998-40ba-bc55-8f23c3af1e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870703880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.870703880
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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