Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11187

1

T1

1

T2

126

T3

3

auto[Attestation]

7751

1

T1

3

T2

108

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2699	1			T1	2		T2	33		T11	5
auto[Aes]	3478	1			T2	40		T4	4		T11	5
auto[Kmac]	3451	1			T2	34		T4	3		T11	5
auto[Otbn]	3328	1			T1	2		T2	42		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7722	1			T1	4		T2	91		T3	8
auto[OpGenId]	5982	1			T2	85		T4	2		T11	11
auto[OpGenSwOut]	6069	1			T1	1		T2	89		T4	4
auto[OpGenHwOut]	6887	1			T1	3		T2	60		T3	8
auto[OpDisable]	124	1			T2	6		T23	1		T52	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10681

1

T1

8

T2

143

T3

8

auto[OpDoneFail]

16103

1

T2

188

T3

8

T4

7

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6468	1			T1	1		T2	80		T3	1
auto[StInit]	3687	1			T1	1		T2	41		T3	2
auto[StCreatorRootKey]	3198	1			T1	5		T2	43		T3	2
auto[StOwnerIntKey]	2789	1			T1	1		T2	35		T3	2
auto[StOwnerKey]	2509	1			T2	39		T3	2		T11	3
auto[StDisabled]	8133	1			T2	93		T3	7		T11	12

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	344	1			T2	4		T23	4		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T2	2		T23	2		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T2	1		T12	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T2	1		T35	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	72	1			T2	2		T212	1		T213	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	229	1			T2	5		T23	9		T52	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	328	1			T2	5		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T2	1		T4	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	86	1			T2	3		T23	1		T52	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	80	1			T11	1		T17	1		T23	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T2	1		T57	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	250	1			T2	5		T11	1		T23	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	337	1			T2	6		T11	1		T12	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	94	1			T2	1		T4	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T5	2		T62	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T2	2		T23	2		T132	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T2	1		T23	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	246	1			T2	3		T12	1		T23	9
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T2	3		T11	2		T12	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T2	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	70	1			T2	1		T4	1		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T2	1		T23	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	70	1			T2	3		T11	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	207	1			T2	4		T23	2		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T2	1		T23	3		T217	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T11	2		T23	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T1	1		T23	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T2	1		T12	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T2	1		T23	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	211	1			T2	3		T12	2		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	82	1			T2	3		T23	3		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T2	3		T215	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T2	1		T16	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T12	1		T16	1		T23	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T2	1		T218	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	245	1			T2	2		T12	2		T23	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	75	1			T2	1		T23	1		T217	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	98	1			T2	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T2	3		T23	3		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T2	3		T35	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	67	1			T2	2		T12	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	210	1			T2	1		T12	1		T23	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T2	3		T23	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	114	1			T2	2		T38	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T35	3		T38	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T16	1		T57	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	66	1			T23	1		T57	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	205	1			T2	1		T11	2		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	255	1			T2	1		T11	2		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	85	1			T23	1		T57	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	54	1			T12	1		T23	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T2	1		T11	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T23	1		T65	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	187	1			T23	6		T218	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	457	1			T2	2		T12	1		T23	6
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	126	1			T2	1		T15	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	99	1			T4	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	83	1			T2	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T2	1		T11	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	281	1			T2	1		T15	4		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	518	1			T2	3		T4	2		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	116	1			T13	1		T14	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T12	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T2	1		T11	2		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	460	1			T2	5		T12	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T3	1		T23	3		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T1	1		T2	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T3	1		T17	2		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T2	2		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	274	1			T2	5		T3	1		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T23	1		T217	2		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	71	1			T2	3		T52	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T1	1		T2	3		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T2	3		T16	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T23	1		T131	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	180	1			T2	1		T23	2		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T2	2		T23	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T39	1		T65	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	100	1			T2	1		T23	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	99	1			T2	1		T11	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T2	1		T23	2		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	290	1			T2	3		T23	4		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T217	1		T5	3		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T2	1		T17	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T2	1		T16	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T57	1		T38	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	95	1			T145	1		T222	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T2	2		T13	2		T14	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T2	1		T23	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T4	1		T12	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T110	1		T38	1		T215	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T2	1		T3	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	308	1			T2	5		T3	3		T23	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	218	1			T2	4		T12	1		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	691	1			T2	11		T23	16		T52	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	217	1			T2	4		T11	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	697	1			T2	11		T4	2		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T2	3		T23	3		T132	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	688	1			T2	10		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	190	1			T2	4		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	645	1			T2	9		T11	2		T12	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	194	1			T1	1		T2	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	414	1			T2	4		T11	2		T12	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	224	1			T2	1		T12	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	453	1			T2	9		T12	2		T23	9
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	232	1			T2	7		T12	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	400	1			T2	4		T12	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	213	1			T16	1		T35	3		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	399	1			T2	6		T11	2		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	152	1			T2	1		T12	1		T23	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	544	1			T2	1		T11	3		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	253	1			T2	3		T4	2		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	883	1			T2	4		T12	1		T15	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	249	1			T2	1		T12	1		T13	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	926	1			T2	5		T4	2		T11	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T1	1		T2	5		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	846	1			T2	10		T3	2		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T1	1		T2	6		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	322	1			T2	4		T23	3		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	262	1			T2	1		T23	4		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	489	1			T2	7		T11	1		T23	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T2	1		T16	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	475	1			T2	3		T13	2		T14	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	259	1			T1	1		T2	2		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	494	1			T2	6		T3	3		T4	1