Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33196

1

T1

9

T2

375

T3

21

auto[1]

320

1

T12

6

T130

16

T132

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33206	1			T1	9		T2	375		T3	21
auto[134217728:268435455]	10	1			T145	1		T316	1		T269	1
auto[268435456:402653183]	9	1			T130	2		T145	1		T274	1
auto[402653184:536870911]	9	1			T130	1		T274	2		T399	2
auto[536870912:671088639]	7	1			T359	1		T137	1		T384	1
auto[671088640:805306367]	13	1			T130	1		T135	1		T325	1
auto[805306368:939524095]	10	1			T130	1		T276	2		T269	1
auto[939524096:1073741823]	7	1			T135	1		T370	1		T400	1
auto[1073741824:1207959551]	15	1			T12	1		T130	1		T145	1
auto[1207959552:1342177279]	9	1			T130	1		T145	1		T276	1
auto[1342177280:1476395007]	9	1			T145	1		T276	1		T401	1
auto[1476395008:1610612735]	13	1			T130	1		T325	1		T83	1
auto[1610612736:1744830463]	11	1			T130	1		T132	1		T145	1
auto[1744830464:1879048191]	16	1			T12	1		T130	1		T132	1
auto[1879048192:2013265919]	12	1			T130	1		T276	1		T325	1
auto[2013265920:2147483647]	11	1			T132	1		T136	1		T83	1
auto[2147483648:2281701375]	12	1			T83	1		T354	2		T370	1
auto[2281701376:2415919103]	13	1			T12	1		T132	2		T274	1
auto[2415919104:2550136831]	8	1			T130	1		T325	1		T272	2
auto[2550136832:2684354559]	9	1			T274	1		T402	1		T272	2
auto[2684354560:2818572287]	6	1			T130	1		T136	1		T402	2
auto[2818572288:2952790015]	11	1			T135	1		T370	1		T308	1
auto[2952790016:3087007743]	9	1			T359	1		T354	1		T401	1
auto[3087007744:3221225471]	13	1			T276	1		T136	1		T83	1
auto[3221225472:3355443199]	7	1			T12	1		T135	1		T136	1
auto[3355443200:3489660927]	10	1			T135	1		T276	1		T325	2
auto[3489660928:3623878655]	12	1			T12	1		T325	2		T274	1
auto[3623878656:3758096383]	8	1			T276	1		T359	2		T136	1
auto[3758096384:3892314111]	12	1			T130	1		T132	1		T276	2
auto[3892314112:4026531839]	5	1			T12	1		T130	1		T354	1
auto[4026531840:4160749567]	7	1			T145	1		T135	1		T279	1
auto[4160749568:4294967295]	7	1			T130	1		T137	1		T274	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33196	1			T1	9		T2	375		T3	21
auto[0:134217727]	auto[1]	10	1			T145	2		T276	2		T137	1
auto[134217728:268435455]	auto[1]	10	1			T145	1		T316	1		T269	1
auto[268435456:402653183]	auto[1]	9	1			T130	2		T145	1		T274	1
auto[402653184:536870911]	auto[1]	9	1			T130	1		T274	2		T399	2
auto[536870912:671088639]	auto[1]	7	1			T359	1		T137	1		T384	1
auto[671088640:805306367]	auto[1]	13	1			T130	1		T135	1		T325	1
auto[805306368:939524095]	auto[1]	10	1			T130	1		T276	2		T269	1
auto[939524096:1073741823]	auto[1]	7	1			T135	1		T370	1		T400	1
auto[1073741824:1207959551]	auto[1]	15	1			T12	1		T130	1		T145	1
auto[1207959552:1342177279]	auto[1]	9	1			T130	1		T145	1		T276	1
auto[1342177280:1476395007]	auto[1]	9	1			T145	1		T276	1		T401	1
auto[1476395008:1610612735]	auto[1]	13	1			T130	1		T325	1		T83	1
auto[1610612736:1744830463]	auto[1]	11	1			T130	1		T132	1		T145	1
auto[1744830464:1879048191]	auto[1]	16	1			T12	1		T130	1		T132	1
auto[1879048192:2013265919]	auto[1]	12	1			T130	1		T276	1		T325	1
auto[2013265920:2147483647]	auto[1]	11	1			T132	1		T136	1		T83	1
auto[2147483648:2281701375]	auto[1]	12	1			T83	1		T354	2		T370	1
auto[2281701376:2415919103]	auto[1]	13	1			T12	1		T132	2		T274	1
auto[2415919104:2550136831]	auto[1]	8	1			T130	1		T325	1		T272	2
auto[2550136832:2684354559]	auto[1]	9	1			T274	1		T402	1		T272	2
auto[2684354560:2818572287]	auto[1]	6	1			T130	1		T136	1		T402	2
auto[2818572288:2952790015]	auto[1]	11	1			T135	1		T370	1		T308	1
auto[2952790016:3087007743]	auto[1]	9	1			T359	1		T354	1		T401	1
auto[3087007744:3221225471]	auto[1]	13	1			T276	1		T136	1		T83	1
auto[3221225472:3355443199]	auto[1]	7	1			T12	1		T135	1		T136	1
auto[3355443200:3489660927]	auto[1]	10	1			T135	1		T276	1		T325	2
auto[3489660928:3623878655]	auto[1]	12	1			T12	1		T325	2		T274	1
auto[3623878656:3758096383]	auto[1]	8	1			T276	1		T359	2		T136	1
auto[3758096384:3892314111]	auto[1]	12	1			T130	1		T132	1		T276	2
auto[3892314112:4026531839]	auto[1]	5	1			T12	1		T130	1		T354	1
auto[4026531840:4160749567]	auto[1]	7	1			T145	1		T135	1		T279	1
auto[4160749568:4294967295]	auto[1]	7	1			T130	1		T137	1		T274	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1622

1

T1

1

T2

31

T4

2

auto[1]

1783

1

T2

20

T11

2

T12

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T11	1		T16	1		T23	1
auto[134217728:268435455]	115	1			T2	2		T23	1		T130	1
auto[268435456:402653183]	107	1			T2	4		T23	1		T65	1
auto[402653184:536870911]	109	1			T2	2		T12	1		T52	1
auto[536870912:671088639]	111	1			T17	1		T23	4		T52	1
auto[671088640:805306367]	118	1			T2	4		T12	1		T35	1
auto[805306368:939524095]	109	1			T2	2		T12	1		T23	2
auto[939524096:1073741823]	94	1			T2	2		T23	2		T131	1
auto[1073741824:1207959551]	114	1			T2	2		T12	1		T23	2
auto[1207959552:1342177279]	100	1			T2	2		T23	1		T145	1
auto[1342177280:1476395007]	90	1			T2	1		T23	2		T218	1
auto[1476395008:1610612735]	101	1			T2	2		T52	1		T218	1
auto[1610612736:1744830463]	100	1			T2	1		T4	1		T52	1
auto[1744830464:1879048191]	98	1			T12	1		T23	1		T37	1
auto[1879048192:2013265919]	116	1			T2	2		T16	1		T35	1
auto[2013265920:2147483647]	116	1			T1	1		T2	3		T11	1
auto[2147483648:2281701375]	119	1			T23	2		T57	1		T131	1
auto[2281701376:2415919103]	103	1			T2	2		T50	1		T62	1
auto[2415919104:2550136831]	113	1			T2	1		T4	1		T11	1
auto[2550136832:2684354559]	118	1			T2	1		T35	2		T23	1
auto[2684354560:2818572287]	105	1			T2	1		T23	2		T36	1
auto[2818572288:2952790015]	108	1			T2	1		T11	1		T23	2
auto[2952790016:3087007743]	96	1			T130	1		T50	1		T254	1
auto[3087007744:3221225471]	96	1			T23	2		T36	1		T132	1
auto[3221225472:3355443199]	98	1			T2	4		T23	2		T52	1
auto[3355443200:3489660927]	97	1			T2	2		T11	1		T23	2
auto[3489660928:3623878655]	115	1			T2	3		T23	1		T110	1
auto[3623878656:3758096383]	114	1			T2	1		T23	1		T57	1
auto[3758096384:3892314111]	113	1			T2	1		T11	1		T23	1
auto[3892314112:4026531839]	109	1			T2	1		T11	1		T12	1
auto[4026531840:4160749567]	106	1			T2	2		T57	1		T130	1
auto[4160749568:4294967295]	100	1			T2	2		T12	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T11	1		T57	1		T255	1
auto[0:134217727]	auto[1]	54	1			T16	1		T23	1		T5	1
auto[134217728:268435455]	auto[0]	61	1			T23	1		T145	1		T217	1
auto[134217728:268435455]	auto[1]	54	1			T2	2		T130	1		T51	1
auto[268435456:402653183]	auto[0]	51	1			T2	3		T217	1		T219	1
auto[268435456:402653183]	auto[1]	56	1			T2	1		T23	1		T65	1
auto[402653184:536870911]	auto[0]	59	1			T2	1		T12	1		T52	1
auto[402653184:536870911]	auto[1]	50	1			T2	1		T219	2		T5	1
auto[536870912:671088639]	auto[0]	50	1			T23	2		T52	1		T221	1
auto[536870912:671088639]	auto[1]	61	1			T17	1		T23	2		T5	2
auto[671088640:805306367]	auto[0]	50	1			T2	2		T35	1		T23	1
auto[671088640:805306367]	auto[1]	68	1			T2	2		T12	1		T23	1
auto[805306368:939524095]	auto[0]	42	1			T2	1		T12	1		T110	1
auto[805306368:939524095]	auto[1]	67	1			T2	1		T23	2		T130	1
auto[939524096:1073741823]	auto[0]	47	1			T2	1		T23	2		T131	1
auto[939524096:1073741823]	auto[1]	47	1			T2	1		T132	1		T50	1
auto[1073741824:1207959551]	auto[0]	50	1			T2	1		T12	1		T23	2
auto[1073741824:1207959551]	auto[1]	64	1			T2	1		T50	1		T219	1
auto[1207959552:1342177279]	auto[0]	41	1			T2	1		T135	2		T264	1
auto[1207959552:1342177279]	auto[1]	59	1			T2	1		T23	1		T145	1
auto[1342177280:1476395007]	auto[0]	34	1			T23	1		T5	1		T62	1
auto[1342177280:1476395007]	auto[1]	56	1			T2	1		T23	1		T218	1
auto[1476395008:1610612735]	auto[0]	50	1			T2	1		T52	1		T218	1
auto[1476395008:1610612735]	auto[1]	51	1			T2	1		T145	1		T5	2
auto[1610612736:1744830463]	auto[0]	54	1			T2	1		T4	1		T335	1
auto[1610612736:1744830463]	auto[1]	46	1			T52	1		T5	1		T68	1
auto[1744830464:1879048191]	auto[0]	34	1			T12	1		T37	1		T5	1
auto[1744830464:1879048191]	auto[1]	64	1			T23	1		T217	1		T219	1
auto[1879048192:2013265919]	auto[0]	60	1			T2	2		T35	1		T57	1
auto[1879048192:2013265919]	auto[1]	56	1			T16	1		T23	1		T24	1
auto[2013265920:2147483647]	auto[0]	61	1			T1	1		T2	1		T57	1
auto[2013265920:2147483647]	auto[1]	55	1			T2	2		T11	1		T23	2
auto[2147483648:2281701375]	auto[0]	59	1			T23	1		T40	1		T217	1
auto[2147483648:2281701375]	auto[1]	60	1			T23	1		T57	1		T131	1
auto[2281701376:2415919103]	auto[0]	50	1			T2	2		T6	1		T123	1
auto[2281701376:2415919103]	auto[1]	53	1			T50	1		T62	1		T135	2
auto[2415919104:2550136831]	auto[0]	62	1			T2	1		T4	1		T11	1
auto[2415919104:2550136831]	auto[1]	51	1			T23	2		T5	1		T317	1
auto[2550136832:2684354559]	auto[0]	60	1			T2	1		T35	2		T52	1
auto[2550136832:2684354559]	auto[1]	58	1			T23	1		T36	1		T130	1
auto[2684354560:2818572287]	auto[0]	56	1			T2	1		T36	1		T5	1
auto[2684354560:2818572287]	auto[1]	49	1			T23	2		T65	1		T68	1
auto[2818572288:2952790015]	auto[0]	53	1			T2	1		T11	1		T23	1
auto[2818572288:2952790015]	auto[1]	55	1			T23	1		T132	1		T218	1
auto[2952790016:3087007743]	auto[0]	36	1			T255	1		T64	1		T306	2
auto[2952790016:3087007743]	auto[1]	60	1			T130	1		T50	1		T254	1
auto[3087007744:3221225471]	auto[0]	44	1			T23	1		T36	1		T53	1
auto[3087007744:3221225471]	auto[1]	52	1			T23	1		T132	1		T5	1
auto[3221225472:3355443199]	auto[0]	46	1			T2	2		T23	1		T37	1
auto[3221225472:3355443199]	auto[1]	52	1			T2	2		T23	1		T52	1
auto[3355443200:3489660927]	auto[0]	52	1			T2	2		T11	1		T132	1
auto[3355443200:3489660927]	auto[1]	45	1			T23	2		T40	1		T254	1
auto[3489660928:3623878655]	auto[0]	58	1			T2	1		T23	1		T62	1
auto[3489660928:3623878655]	auto[1]	57	1			T2	2		T110	1		T62	2
auto[3623878656:3758096383]	auto[0]	59	1			T2	1		T23	1		T36	1
auto[3623878656:3758096383]	auto[1]	55	1			T57	1		T5	1		T62	1
auto[3758096384:3892314111]	auto[0]	49	1			T5	1		T68	1		T264	2
auto[3758096384:3892314111]	auto[1]	64	1			T2	1		T11	1		T23	1
auto[3892314112:4026531839]	auto[0]	53	1			T2	1		T11	1		T12	1
auto[3892314112:4026531839]	auto[1]	56	1			T23	1		T52	1		T57	1
auto[4026531840:4160749567]	auto[0]	48	1			T2	2		T130	1		T62	1
auto[4026531840:4160749567]	auto[1]	58	1			T57	1		T217	1		T62	1
auto[4160749568:4294967295]	auto[0]	50	1			T2	1		T12	1		T50	1
auto[4160749568:4294967295]	auto[1]	50	1			T2	1		T145	1		T5	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1594

1

T2

25

T4

2

T11

6

auto[1]

1811

1

T1

1

T2

26

T11

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T2	3		T12	2		T131	1
auto[134217728:268435455]	108	1			T2	1		T12	1		T23	4
auto[268435456:402653183]	89	1			T2	2		T17	1		T23	1
auto[402653184:536870911]	93	1			T2	1		T11	2		T23	1
auto[536870912:671088639]	95	1			T2	2		T23	2		T57	1
auto[671088640:805306367]	106	1			T2	3		T132	2		T65	1
auto[805306368:939524095]	115	1			T2	2		T4	1		T23	1
auto[939524096:1073741823]	126	1			T57	2		T130	1		T131	1
auto[1073741824:1207959551]	105	1			T2	2		T11	1		T16	1
auto[1207959552:1342177279]	115	1			T23	1		T110	1		T145	1
auto[1342177280:1476395007]	109	1			T2	2		T11	1		T23	1
auto[1476395008:1610612735]	95	1			T2	3		T23	2		T52	1
auto[1610612736:1744830463]	103	1			T11	1		T23	1		T36	1
auto[1744830464:1879048191]	92	1			T2	3		T12	1		T23	1
auto[1879048192:2013265919]	113	1			T2	2		T12	1		T35	1
auto[2013265920:2147483647]	120	1			T2	1		T4	1		T23	1
auto[2147483648:2281701375]	129	1			T2	3		T23	2		T52	1
auto[2281701376:2415919103]	103	1			T2	3		T52	1		T57	1
auto[2415919104:2550136831]	88	1			T23	1		T57	1		T221	1
auto[2550136832:2684354559]	113	1			T23	1		T52	1		T36	1
auto[2684354560:2818572287]	85	1			T23	1		T50	1		T217	1
auto[2818572288:2952790015]	122	1			T1	1		T11	1		T12	1
auto[2952790016:3087007743]	111	1			T2	1		T35	1		T23	1
auto[3087007744:3221225471]	120	1			T2	3		T35	1		T23	1
auto[3221225472:3355443199]	98	1			T2	1		T16	1		T23	1
auto[3355443200:3489660927]	106	1			T2	3		T23	3		T52	1
auto[3489660928:3623878655]	111	1			T2	1		T12	1		T23	1
auto[3623878656:3758096383]	128	1			T2	1		T23	3		T218	1
auto[3758096384:3892314111]	105	1			T2	4		T23	2		T218	1
auto[3892314112:4026531839]	101	1			T2	1		T23	2		T130	1
auto[4026531840:4160749567]	95	1			T2	1		T35	1		T23	1
auto[4160749568:4294967295]	92	1			T2	2		T11	1		T131	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T12	2		T62	1		T403	1
auto[0:134217727]	auto[1]	59	1			T2	3		T131	1		T217	1
auto[134217728:268435455]	auto[0]	52	1			T12	1		T23	2		T5	1
auto[134217728:268435455]	auto[1]	56	1			T2	1		T23	2		T52	1
auto[268435456:402653183]	auto[0]	42	1			T5	1		T62	1		T275	1
auto[268435456:402653183]	auto[1]	47	1			T2	2		T17	1		T23	1
auto[402653184:536870911]	auto[0]	42	1			T2	1		T11	2		T65	1
auto[402653184:536870911]	auto[1]	51	1			T23	1		T130	1		T65	1
auto[536870912:671088639]	auto[0]	43	1			T2	1		T23	1		T5	1
auto[536870912:671088639]	auto[1]	52	1			T2	1		T23	1		T57	1
auto[671088640:805306367]	auto[0]	45	1			T2	2		T5	1		T62	2
auto[671088640:805306367]	auto[1]	61	1			T2	1		T132	2		T65	1
auto[805306368:939524095]	auto[0]	61	1			T2	1		T4	1		T23	1
auto[805306368:939524095]	auto[1]	54	1			T2	1		T335	2		T72	1
auto[939524096:1073741823]	auto[0]	56	1			T57	1		T130	1		T37	1
auto[939524096:1073741823]	auto[1]	70	1			T57	1		T131	1		T145	1
auto[1073741824:1207959551]	auto[0]	48	1			T2	1		T11	1		T62	2
auto[1073741824:1207959551]	auto[1]	57	1			T2	1		T16	1		T23	2
auto[1207959552:1342177279]	auto[0]	49	1			T53	1		T313	1		T404	1
auto[1207959552:1342177279]	auto[1]	66	1			T23	1		T110	1		T145	1
auto[1342177280:1476395007]	auto[0]	46	1			T2	1		T11	1		T254	1
auto[1342177280:1476395007]	auto[1]	63	1			T2	1		T23	1		T57	1
auto[1476395008:1610612735]	auto[0]	43	1			T2	2		T132	1		T37	1
auto[1476395008:1610612735]	auto[1]	52	1			T2	1		T23	2		T52	1
auto[1610612736:1744830463]	auto[0]	50	1			T11	1		T50	2		T92	1
auto[1610612736:1744830463]	auto[1]	53	1			T23	1		T36	1		T219	1
auto[1744830464:1879048191]	auto[0]	40	1			T2	1		T12	1		T23	1
auto[1744830464:1879048191]	auto[1]	52	1			T2	2		T5	1		T335	3
auto[1879048192:2013265919]	auto[0]	48	1			T2	1		T12	1		T35	1
auto[1879048192:2013265919]	auto[1]	65	1			T2	1		T36	1		T145	1
auto[2013265920:2147483647]	auto[0]	56	1			T2	1		T4	1		T23	1
auto[2013265920:2147483647]	auto[1]	64	1			T145	1		T254	1		T51	1
auto[2147483648:2281701375]	auto[0]	66	1			T2	1		T23	2		T132	1
auto[2147483648:2281701375]	auto[1]	63	1			T2	2		T52	1		T254	1
auto[2281701376:2415919103]	auto[0]	54	1			T2	1		T57	1		T217	1
auto[2281701376:2415919103]	auto[1]	49	1			T2	2		T52	1		T5	1
auto[2415919104:2550136831]	auto[0]	38	1			T23	1		T57	1		T62	2
auto[2415919104:2550136831]	auto[1]	50	1			T221	1		T5	1		T62	1
auto[2550136832:2684354559]	auto[0]	58	1			T52	1		T36	1		T131	1
auto[2550136832:2684354559]	auto[1]	55	1			T23	1		T40	1		T5	1
auto[2684354560:2818572287]	auto[0]	53	1			T5	1		T62	1		T264	1
auto[2684354560:2818572287]	auto[1]	32	1			T23	1		T50	1		T217	1
auto[2818572288:2952790015]	auto[0]	51	1			T11	1		T62	1		T58	1
auto[2818572288:2952790015]	auto[1]	71	1			T1	1		T12	1		T23	3
auto[2952790016:3087007743]	auto[0]	59	1			T35	1		T253	1		T217	1
auto[2952790016:3087007743]	auto[1]	52	1			T2	1		T23	1		T359	1
auto[3087007744:3221225471]	auto[0]	67	1			T2	2		T35	1		T23	1
auto[3087007744:3221225471]	auto[1]	53	1			T2	1		T5	1		T53	1
auto[3221225472:3355443199]	auto[0]	46	1			T2	1		T23	1		T57	1
auto[3221225472:3355443199]	auto[1]	52	1			T16	1		T218	1		T145	1
auto[3355443200:3489660927]	auto[0]	45	1			T23	1		T52	1		T5	1
auto[3355443200:3489660927]	auto[1]	61	1			T2	3		T23	2		T50	1
auto[3489660928:3623878655]	auto[0]	50	1			T2	1		T12	1		T52	1
auto[3489660928:3623878655]	auto[1]	61	1			T23	1		T62	5		T335	1
auto[3623878656:3758096383]	auto[0]	53	1			T23	2		T217	1		T62	2
auto[3623878656:3758096383]	auto[1]	75	1			T2	1		T23	1		T218	1
auto[3758096384:3892314111]	auto[0]	51	1			T2	3		T23	1		T218	1
auto[3758096384:3892314111]	auto[1]	54	1			T2	1		T23	1		T50	1
auto[3892314112:4026531839]	auto[0]	44	1			T2	1		T23	1		T53	1
auto[3892314112:4026531839]	auto[1]	57	1			T23	1		T130	1		T132	1
auto[4026531840:4160749567]	auto[0]	49	1			T2	1		T35	1		T37	1
auto[4026531840:4160749567]	auto[1]	46	1			T23	1		T130	1		T65	1
auto[4160749568:4294967295]	auto[0]	34	1			T2	2		T6	1		T28	1
auto[4160749568:4294967295]	auto[1]	58	1			T11	1		T131	1		T219	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1601

1

T1

1

T2

28

T4

2

auto[1]

1804

1

T2

23

T12

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	1		T11	2		T23	1
auto[134217728:268435455]	130	1			T2	1		T35	1		T23	1
auto[268435456:402653183]	100	1			T2	2		T11	1		T23	1
auto[402653184:536870911]	107	1			T2	2		T4	1		T23	4
auto[536870912:671088639]	102	1			T2	1		T35	1		T23	2
auto[671088640:805306367]	110	1			T11	1		T12	1		T23	1
auto[805306368:939524095]	97	1			T2	2		T12	1		T52	1
auto[939524096:1073741823]	110	1			T2	2		T12	1		T23	1
auto[1073741824:1207959551]	96	1			T2	1		T12	1		T23	2
auto[1207959552:1342177279]	113	1			T2	3		T16	1		T23	2
auto[1342177280:1476395007]	107	1			T2	3		T4	1		T23	1
auto[1476395008:1610612735]	92	1			T2	1		T17	1		T130	1
auto[1610612736:1744830463]	124	1			T2	2		T11	1		T23	1
auto[1744830464:1879048191]	106	1			T2	4		T35	1		T40	1
auto[1879048192:2013265919]	102	1			T2	1		T23	1		T52	1
auto[2013265920:2147483647]	101	1			T2	3		T12	1		T23	1
auto[2147483648:2281701375]	101	1			T2	3		T130	1		T40	1
auto[2281701376:2415919103]	107	1			T2	3		T23	1		T5	2
auto[2415919104:2550136831]	100	1			T2	3		T23	1		T36	1
auto[2550136832:2684354559]	93	1			T11	1		T23	2		T52	1
auto[2684354560:2818572287]	104	1			T23	1		T36	1		T132	1
auto[2818572288:2952790015]	100	1			T2	2		T16	1		T23	2
auto[2952790016:3087007743]	117	1			T23	2		T57	1		T218	1
auto[3087007744:3221225471]	108	1			T2	1		T23	1		T5	1
auto[3221225472:3355443199]	107	1			T36	1		T218	1		T37	1
auto[3355443200:3489660927]	111	1			T2	1		T23	3		T50	1
auto[3489660928:3623878655]	118	1			T1	1		T12	1		T217	1
auto[3623878656:3758096383]	98	1			T2	2		T12	1		T23	4
auto[3758096384:3892314111]	103	1			T2	4		T35	1		T23	2
auto[3892314112:4026531839]	114	1			T2	1		T23	2		T52	1
auto[4026531840:4160749567]	116	1			T2	2		T23	1		T52	1
auto[4160749568:4294967295]	102	1			T11	1		T23	1		T132	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T2	1		T11	2		T23	1
auto[0:134217727]	auto[1]	56	1			T51	3		T100	1		T349	1
auto[134217728:268435455]	auto[0]	66	1			T2	1		T23	1		T276	1
auto[134217728:268435455]	auto[1]	64	1			T35	1		T52	1		T57	1
auto[268435456:402653183]	auto[0]	46	1			T2	1		T11	1		T51	1
auto[268435456:402653183]	auto[1]	54	1			T2	1		T23	1		T36	1
auto[402653184:536870911]	auto[0]	50	1			T4	1		T23	2		T5	3
auto[402653184:536870911]	auto[1]	57	1			T2	2		T23	2		T57	1
auto[536870912:671088639]	auto[0]	47	1			T2	1		T35	1		T23	1
auto[536870912:671088639]	auto[1]	55	1			T23	1		T57	1		T145	1
auto[671088640:805306367]	auto[0]	52	1			T11	1		T12	1		T62	1
auto[671088640:805306367]	auto[1]	58	1			T23	1		T5	1		T53	1
auto[805306368:939524095]	auto[0]	39	1			T2	1		T24	1		T403	1
auto[805306368:939524095]	auto[1]	58	1			T2	1		T12	1		T52	1
auto[939524096:1073741823]	auto[0]	53	1			T12	1		T37	1		T62	1
auto[939524096:1073741823]	auto[1]	57	1			T2	2		T23	1		T130	1
auto[1073741824:1207959551]	auto[0]	48	1			T2	1		T12	1		T99	1
auto[1073741824:1207959551]	auto[1]	48	1			T23	2		T132	1		T62	1
auto[1207959552:1342177279]	auto[0]	55	1			T2	2		T23	2		T52	1
auto[1207959552:1342177279]	auto[1]	58	1			T2	1		T16	1		T132	1
auto[1342177280:1476395007]	auto[0]	46	1			T2	1		T4	1		T131	1
auto[1342177280:1476395007]	auto[1]	61	1			T2	2		T23	1		T5	1
auto[1476395008:1610612735]	auto[0]	39	1			T2	1		T62	2		T275	1
auto[1476395008:1610612735]	auto[1]	53	1			T17	1		T130	1		T131	1
auto[1610612736:1744830463]	auto[0]	59	1			T2	2		T11	1		T52	1
auto[1610612736:1744830463]	auto[1]	65	1			T23	1		T221	1		T217	1
auto[1744830464:1879048191]	auto[0]	47	1			T2	1		T35	1		T40	1
auto[1744830464:1879048191]	auto[1]	59	1			T2	3		T50	2		T5	3
auto[1879048192:2013265919]	auto[0]	48	1			T52	1		T217	1		T219	1
auto[1879048192:2013265919]	auto[1]	54	1			T2	1		T23	1		T131	1
auto[2013265920:2147483647]	auto[0]	51	1			T2	1		T23	1		T36	1
auto[2013265920:2147483647]	auto[1]	50	1			T2	2		T12	1		T360	1
auto[2147483648:2281701375]	auto[0]	55	1			T2	3		T40	1		T5	1
auto[2147483648:2281701375]	auto[1]	46	1			T130	1		T254	1		T5	1
auto[2281701376:2415919103]	auto[0]	47	1			T2	3		T6	1		T51	1
auto[2281701376:2415919103]	auto[1]	60	1			T23	1		T5	2		T335	1
auto[2415919104:2550136831]	auto[0]	41	1			T2	1		T23	1		T36	1
auto[2415919104:2550136831]	auto[1]	59	1			T2	2		T65	1		T253	1
auto[2550136832:2684354559]	auto[0]	43	1			T11	1		T57	1		T254	1
auto[2550136832:2684354559]	auto[1]	50	1			T23	2		T52	1		T132	1
auto[2684354560:2818572287]	auto[0]	49	1			T36	1		T132	1		T37	1
auto[2684354560:2818572287]	auto[1]	55	1			T23	1		T329	1		T359	1
auto[2818572288:2952790015]	auto[0]	50	1			T2	2		T23	1		T5	1
auto[2818572288:2952790015]	auto[1]	50	1			T16	1		T23	1		T110	1
auto[2952790016:3087007743]	auto[0]	50	1			T23	1		T218	1		T5	1
auto[2952790016:3087007743]	auto[1]	67	1			T23	1		T57	1		T5	2
auto[3087007744:3221225471]	auto[0]	47	1			T23	1		T135	1		T275	1
auto[3087007744:3221225471]	auto[1]	61	1			T2	1		T5	1		T276	1
auto[3221225472:3355443199]	auto[0]	50	1			T36	1		T37	1		T5	1
auto[3221225472:3355443199]	auto[1]	57	1			T218	1		T145	1		T62	1
auto[3355443200:3489660927]	auto[0]	55	1			T2	1		T5	2		T53	2
auto[3355443200:3489660927]	auto[1]	56	1			T23	3		T50	1		T254	1
auto[3489660928:3623878655]	auto[0]	57	1			T1	1		T12	1		T62	1
auto[3489660928:3623878655]	auto[1]	61	1			T217	1		T219	1		T374	1
auto[3623878656:3758096383]	auto[0]	40	1			T12	1		T23	1		T50	1
auto[3623878656:3758096383]	auto[1]	58	1			T2	2		T23	3		T65	1
auto[3758096384:3892314111]	auto[0]	56	1			T2	2		T35	1		T23	2
auto[3758096384:3892314111]	auto[1]	47	1			T2	2		T57	1		T254	1
auto[3892314112:4026531839]	auto[0]	52	1			T23	2		T110	1		T62	1
auto[3892314112:4026531839]	auto[1]	62	1			T2	1		T52	1		T40	1
auto[4026531840:4160749567]	auto[0]	58	1			T2	2		T264	1		T123	1
auto[4026531840:4160749567]	auto[1]	58	1			T23	1		T52	1		T218	1
auto[4160749568:4294967295]	auto[0]	52	1			T11	1		T132	1		T40	1
auto[4160749568:4294967295]	auto[1]	50	1			T23	1		T5	1		T335	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1626

1

T2

28

T4

2

T11

5

auto[1]

1778

1

T1

1

T2

23

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	1		T52	1		T130	1
auto[134217728:268435455]	134	1			T2	2		T11	1		T35	1
auto[268435456:402653183]	122	1			T2	2		T23	1		T57	1
auto[402653184:536870911]	90	1			T110	1		T130	1		T132	1
auto[536870912:671088639]	105	1			T2	3		T23	1		T40	1
auto[671088640:805306367]	117	1			T1	1		T2	2		T11	1
auto[805306368:939524095]	120	1			T2	4		T23	2		T130	1
auto[939524096:1073741823]	109	1			T23	2		T57	2		T36	1
auto[1073741824:1207959551]	104	1			T2	2		T52	1		T65	1
auto[1207959552:1342177279]	101	1			T2	1		T16	1		T65	1
auto[1342177280:1476395007]	104	1			T2	2		T11	1		T23	3
auto[1476395008:1610612735]	93	1			T23	3		T52	1		T110	1
auto[1610612736:1744830463]	89	1			T2	1		T11	1		T12	1
auto[1744830464:1879048191]	96	1			T23	2		T57	1		T36	1
auto[1879048192:2013265919]	118	1			T2	4		T35	2		T36	1
auto[2013265920:2147483647]	102	1			T2	3		T12	1		T23	1
auto[2147483648:2281701375]	97	1			T2	1		T23	1		T52	2
auto[2281701376:2415919103]	106	1			T2	2		T35	1		T23	1
auto[2415919104:2550136831]	108	1			T2	3		T23	1		T5	3
auto[2550136832:2684354559]	104	1			T2	1		T23	1		T52	1
auto[2684354560:2818572287]	103	1			T2	1		T37	1		T217	2
auto[2818572288:2952790015]	111	1			T2	4		T11	1		T16	1
auto[2952790016:3087007743]	92	1			T52	1		T130	1		T217	1
auto[3087007744:3221225471]	111	1			T2	1		T23	2		T36	1
auto[3221225472:3355443199]	102	1			T23	1		T132	1		T37	1
auto[3355443200:3489660927]	102	1			T2	3		T4	1		T12	1
auto[3489660928:3623878655]	119	1			T2	1		T11	1		T23	1
auto[3623878656:3758096383]	105	1			T23	3		T253	1		T145	1
auto[3758096384:3892314111]	118	1			T4	1		T12	1		T23	1
auto[3892314112:4026531839]	100	1			T2	1		T12	1		T23	2
auto[4026531840:4160749567]	105	1			T2	3		T11	1		T12	2
auto[4160749568:4294967295]	108	1			T2	3		T23	3		T5	1