Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4540

1

T1

2

T2

82

T4

2

auto[1]

2268

1

T2

20

T4

2

T11

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	232	1			T2	6		T12	2		T35	2
auto[134217728:268435455]	218	1			T2	6		T11	2		T23	2
auto[268435456:402653183]	204	1			T2	4		T12	2		T23	2
auto[402653184:536870911]	218	1			T2	4		T11	2		T23	4
auto[536870912:671088639]	208	1			T2	2		T23	2		T52	4
auto[671088640:805306367]	210	1			T2	2		T23	4		T52	2
auto[805306368:939524095]	190	1			T2	4		T36	2		T219	2
auto[939524096:1073741823]	218	1			T2	2		T16	2		T23	6
auto[1073741824:1207959551]	236	1			T2	2		T11	4		T23	4
auto[1207959552:1342177279]	208	1			T2	6		T23	2		T218	2
auto[1342177280:1476395007]	214	1			T2	2		T23	4		T110	2
auto[1476395008:1610612735]	204	1			T16	2		T52	4		T145	2
auto[1610612736:1744830463]	188	1			T57	2		T130	2		T96	2
auto[1744830464:1879048191]	248	1			T2	6		T12	2		T35	2
auto[1879048192:2013265919]	218	1			T2	4		T23	4		T57	2
auto[2013265920:2147483647]	216	1			T2	2		T23	2		T110	2
auto[2147483648:2281701375]	222	1			T2	4		T24	2		T36	2
auto[2281701376:2415919103]	218	1			T4	2		T23	4		T37	2
auto[2415919104:2550136831]	192	1			T2	2		T23	4		T36	2
auto[2550136832:2684354559]	182	1			T2	6		T52	2		T65	2
auto[2684354560:2818572287]	198	1			T4	2		T12	2		T23	2
auto[2818572288:2952790015]	186	1			T36	2		T132	2		T254	2
auto[2952790016:3087007743]	198	1			T2	6		T35	2		T23	6
auto[3087007744:3221225471]	214	1			T2	4		T23	6		T57	2
auto[3221225472:3355443199]	208	1			T2	6		T12	2		T40	2
auto[3355443200:3489660927]	236	1			T2	2		T11	2		T12	2
auto[3489660928:3623878655]	222	1			T23	2		T57	2		T132	2
auto[3623878656:3758096383]	230	1			T2	6		T37	2		T253	2
auto[3758096384:3892314111]	234	1			T2	2		T12	2		T35	2
auto[3892314112:4026531839]	220	1			T1	2		T2	4		T23	2
auto[4026531840:4160749567]	214	1			T2	2		T11	2		T130	2
auto[4160749568:4294967295]	204	1			T2	6		T11	2		T23	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	154	1			T2	6		T12	2		T35	2
auto[0:134217727]	auto[1]	78	1			T23	2		T36	2		T5	2
auto[134217728:268435455]	auto[0]	150	1			T2	6		T11	2		T23	2
auto[134217728:268435455]	auto[1]	68	1			T52	2		T62	2		T275	2
auto[268435456:402653183]	auto[0]	128	1			T2	4		T12	2		T23	2
auto[268435456:402653183]	auto[1]	76	1			T218	2		T5	2		T51	2
auto[402653184:536870911]	auto[0]	144	1			T2	4		T11	2		T23	2
auto[402653184:536870911]	auto[1]	74	1			T23	2		T221	2		T5	2
auto[536870912:671088639]	auto[0]	138	1			T52	4		T130	2		T132	2
auto[536870912:671088639]	auto[1]	70	1			T2	2		T23	2		T5	2
auto[671088640:805306367]	auto[0]	124	1			T2	2		T23	4		T52	2
auto[671088640:805306367]	auto[1]	86	1			T50	2		T217	2		T62	2
auto[805306368:939524095]	auto[0]	140	1			T2	4		T36	2		T219	2
auto[805306368:939524095]	auto[1]	50	1			T404	2		T98	2		T7	2
auto[939524096:1073741823]	auto[0]	134	1			T23	4		T130	2		T254	2
auto[939524096:1073741823]	auto[1]	84	1			T2	2		T16	2		T23	2
auto[1073741824:1207959551]	auto[0]	160	1			T11	4		T23	2		T131	2
auto[1073741824:1207959551]	auto[1]	76	1			T2	2		T23	2		T5	2
auto[1207959552:1342177279]	auto[0]	144	1			T2	2		T218	2		T62	2
auto[1207959552:1342177279]	auto[1]	64	1			T2	4		T23	2		T254	2
auto[1342177280:1476395007]	auto[0]	172	1			T2	2		T23	4		T110	2
auto[1342177280:1476395007]	auto[1]	42	1			T374	2		T321	2		T73	2
auto[1476395008:1610612735]	auto[0]	114	1			T52	2		T145	2		T53	2
auto[1476395008:1610612735]	auto[1]	90	1			T16	2		T52	2		T53	2
auto[1610612736:1744830463]	auto[0]	128	1			T359	2		T255	2		T60	2
auto[1610612736:1744830463]	auto[1]	60	1			T57	2		T130	2		T96	2
auto[1744830464:1879048191]	auto[0]	186	1			T2	6		T35	2		T23	6
auto[1744830464:1879048191]	auto[1]	62	1			T12	2		T65	2		T5	2
auto[1879048192:2013265919]	auto[0]	142	1			T2	4		T23	2		T57	2
auto[1879048192:2013265919]	auto[1]	76	1			T23	2		T217	2		T92	2
auto[2013265920:2147483647]	auto[0]	152	1			T2	2		T23	2		T110	2
auto[2013265920:2147483647]	auto[1]	64	1			T223	2		T125	4		T302	2
auto[2147483648:2281701375]	auto[0]	136	1			T2	4		T36	2		T37	2
auto[2147483648:2281701375]	auto[1]	86	1			T24	2		T218	2		T335	2
auto[2281701376:2415919103]	auto[0]	138	1			T4	2		T37	2		T253	2
auto[2281701376:2415919103]	auto[1]	80	1			T23	4		T5	2		T96	2
auto[2415919104:2550136831]	auto[0]	128	1			T23	2		T50	2		T219	2
auto[2415919104:2550136831]	auto[1]	64	1			T2	2		T23	2		T36	2
auto[2550136832:2684354559]	auto[0]	98	1			T2	4		T52	2		T65	2
auto[2550136832:2684354559]	auto[1]	84	1			T2	2		T403	2		T392	2
auto[2684354560:2818572287]	auto[0]	134	1			T12	2		T130	2		T37	2
auto[2684354560:2818572287]	auto[1]	64	1			T4	2		T23	2		T36	2
auto[2818572288:2952790015]	auto[0]	120	1			T36	2		T132	2		T254	2
auto[2818572288:2952790015]	auto[1]	66	1			T5	2		T62	2		T403	2
auto[2952790016:3087007743]	auto[0]	126	1			T2	6		T35	2		T23	6
auto[2952790016:3087007743]	auto[1]	72	1			T52	2		T62	2		T92	2
auto[3087007744:3221225471]	auto[0]	136	1			T2	4		T23	2		T57	2
auto[3087007744:3221225471]	auto[1]	78	1			T23	4		T62	2		T359	2
auto[3221225472:3355443199]	auto[0]	158	1			T2	4		T12	2		T40	2
auto[3221225472:3355443199]	auto[1]	50	1			T2	2		T41	2		T258	2
auto[3355443200:3489660927]	auto[0]	160	1			T2	2		T12	2		T23	2
auto[3355443200:3489660927]	auto[1]	76	1			T11	2		T23	2		T57	2
auto[3489660928:3623878655]	auto[0]	144	1			T57	2		T132	2		T5	2
auto[3489660928:3623878655]	auto[1]	78	1			T23	2		T217	2		T5	2
auto[3623878656:3758096383]	auto[0]	142	1			T2	4		T37	2		T217	2
auto[3623878656:3758096383]	auto[1]	88	1			T2	2		T253	2		T356	2
auto[3758096384:3892314111]	auto[0]	164	1			T2	2		T12	2		T35	2
auto[3758096384:3892314111]	auto[1]	70	1			T23	2		T5	2		T62	4
auto[3892314112:4026531839]	auto[0]	144	1			T1	2		T2	4		T145	2
auto[3892314112:4026531839]	auto[1]	76	1			T23	2		T403	2		T51	2
auto[4026531840:4160749567]	auto[0]	154	1			T2	2		T11	2		T130	2
auto[4026531840:4160749567]	auto[1]	60	1			T53	2		T320	2		T125	4
auto[4160749568:4294967295]	auto[0]	148	1			T2	4		T11	2		T23	2
auto[4160749568:4294967295]	auto[1]	56	1			T2	2		T52	2		T68	2