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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3005 1 T1 1 T2 42 T4 2
auto[1] 296 1 T12 4 T130 15 T132 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 116 1 T11 1 T23 2 T130 1
auto[134217728:268435455] 100 1 T2 3 T36 1 T145 1
auto[268435456:402653183] 114 1 T2 3 T11 1 T12 1
auto[402653184:536870911] 105 1 T2 3 T35 1 T23 1
auto[536870912:671088639] 102 1 T12 1 T23 2 T52 1
auto[671088640:805306367] 116 1 T2 3 T65 1 T5 1
auto[805306368:939524095] 97 1 T2 1 T23 2 T50 1
auto[939524096:1073741823] 90 1 T12 2 T52 1 T218 2
auto[1073741824:1207959551] 99 1 T52 2 T57 2 T130 1
auto[1207959552:1342177279] 106 1 T2 1 T23 2 T132 1
auto[1342177280:1476395007] 92 1 T4 1 T12 1 T23 1
auto[1476395008:1610612735] 98 1 T23 1 T36 1 T132 2
auto[1610612736:1744830463] 102 1 T36 1 T130 1 T217 1
auto[1744830464:1879048191] 111 1 T2 1 T12 1 T35 1
auto[1879048192:2013265919] 109 1 T35 1 T57 1 T110 1
auto[2013265920:2147483647] 94 1 T2 1 T11 2 T23 1
auto[2147483648:2281701375] 132 1 T2 2 T23 3 T52 1
auto[2281701376:2415919103] 89 1 T4 1 T23 1 T50 1
auto[2415919104:2550136831] 94 1 T1 1 T2 1 T23 3
auto[2550136832:2684354559] 96 1 T2 1 T23 1 T57 1
auto[2684354560:2818572287] 113 1 T2 2 T23 2 T36 1
auto[2818572288:2952790015] 114 1 T2 1 T12 1 T16 1
auto[2952790016:3087007743] 89 1 T2 3 T12 1 T23 1
auto[3087007744:3221225471] 103 1 T2 1 T23 1 T50 1
auto[3221225472:3355443199] 101 1 T2 3 T23 1 T130 2
auto[3355443200:3489660927] 121 1 T2 2 T11 1 T23 2
auto[3489660928:3623878655] 92 1 T2 2 T12 2 T50 1
auto[3623878656:3758096383] 112 1 T17 1 T23 1 T52 1
auto[3758096384:3892314111] 99 1 T2 2 T11 1 T130 2
auto[3892314112:4026531839] 92 1 T11 1 T23 1 T130 1
auto[4026531840:4160749567] 114 1 T2 3 T16 1 T52 2
auto[4160749568:4294967295] 89 1 T2 3 T12 1 T23 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 102 1 T11 1 T23 2 T145 2
auto[0:134217727] auto[1] 14 1 T130 1 T135 1 T359 1
auto[134217728:268435455] auto[0] 91 1 T2 3 T36 1 T145 1
auto[134217728:268435455] auto[1] 9 1 T325 1 T354 1 T303 1
auto[268435456:402653183] auto[0] 102 1 T2 3 T11 1 T23 1
auto[268435456:402653183] auto[1] 12 1 T12 1 T145 1 T137 1
auto[402653184:536870911] auto[0] 97 1 T2 3 T35 1 T23 1
auto[402653184:536870911] auto[1] 8 1 T276 1 T251 1 T252 1
auto[536870912:671088639] auto[0] 94 1 T12 1 T23 2 T52 1
auto[536870912:671088639] auto[1] 8 1 T130 1 T316 1 T415 1
auto[671088640:805306367] auto[0] 104 1 T2 3 T65 1 T5 1
auto[671088640:805306367] auto[1] 12 1 T276 2 T354 1 T370 2
auto[805306368:939524095] auto[0] 86 1 T2 1 T23 2 T50 1
auto[805306368:939524095] auto[1] 11 1 T370 2 T406 1 T402 1
auto[939524096:1073741823] auto[0] 79 1 T12 2 T52 1 T218 2
auto[939524096:1073741823] auto[1] 11 1 T359 1 T354 2 T402 3
auto[1073741824:1207959551] auto[0] 86 1 T52 2 T57 2 T254 1
auto[1073741824:1207959551] auto[1] 13 1 T130 1 T135 1 T137 1
auto[1207959552:1342177279] auto[0] 95 1 T2 1 T23 2 T132 1
auto[1207959552:1342177279] auto[1] 11 1 T276 1 T325 1 T137 1
auto[1342177280:1476395007] auto[0] 80 1 T4 1 T12 1 T23 1
auto[1342177280:1476395007] auto[1] 12 1 T130 3 T145 1 T276 1
auto[1476395008:1610612735] auto[0] 91 1 T23 1 T36 1 T132 2
auto[1476395008:1610612735] auto[1] 7 1 T136 1 T137 1 T384 1
auto[1610612736:1744830463] auto[0] 97 1 T36 1 T217 1 T254 1
auto[1610612736:1744830463] auto[1] 5 1 T130 1 T269 1 T415 1
auto[1744830464:1879048191] auto[0] 106 1 T2 1 T35 1 T23 2
auto[1744830464:1879048191] auto[1] 5 1 T12 1 T276 1 T252 1
auto[1879048192:2013265919] auto[0] 102 1 T35 1 T57 1 T110 1
auto[1879048192:2013265919] auto[1] 7 1 T276 1 T406 1 T316 1
auto[2013265920:2147483647] auto[0] 90 1 T2 1 T11 2 T23 1
auto[2013265920:2147483647] auto[1] 4 1 T276 2 T414 1 T324 1
auto[2147483648:2281701375] auto[0] 122 1 T2 2 T23 3 T52 1
auto[2147483648:2281701375] auto[1] 10 1 T276 1 T402 1 T272 1
auto[2281701376:2415919103] auto[0] 79 1 T4 1 T23 1 T50 1
auto[2281701376:2415919103] auto[1] 10 1 T136 1 T83 2 T354 1
auto[2415919104:2550136831] auto[0] 81 1 T1 1 T2 1 T23 3
auto[2415919104:2550136831] auto[1] 13 1 T130 1 T325 1 T370 1
auto[2550136832:2684354559] auto[0] 91 1 T2 1 T23 1 T57 1
auto[2550136832:2684354559] auto[1] 5 1 T325 1 T269 1 T279 1
auto[2684354560:2818572287] auto[0] 103 1 T2 2 T23 2 T36 1
auto[2684354560:2818572287] auto[1] 10 1 T130 2 T136 1 T83 1
auto[2818572288:2952790015] auto[0] 102 1 T2 1 T12 1 T16 1
auto[2818572288:2952790015] auto[1] 12 1 T130 1 T83 1 T137 1
auto[2952790016:3087007743] auto[0] 79 1 T2 3 T12 1 T23 1
auto[2952790016:3087007743] auto[1] 10 1 T135 1 T276 1 T303 1
auto[3087007744:3221225471] auto[0] 94 1 T2 1 T23 1 T50 1
auto[3087007744:3221225471] auto[1] 9 1 T276 1 T359 1 T274 1
auto[3221225472:3355443199] auto[0] 91 1 T2 3 T23 1 T130 1
auto[3221225472:3355443199] auto[1] 10 1 T130 1 T359 1 T274 1
auto[3355443200:3489660927] auto[0] 109 1 T2 2 T11 1 T23 2
auto[3355443200:3489660927] auto[1] 12 1 T145 1 T83 1 T316 1
auto[3489660928:3623878655] auto[0] 84 1 T2 2 T12 1 T50 1
auto[3489660928:3623878655] auto[1] 8 1 T12 1 T136 1 T325 1
auto[3623878656:3758096383] auto[0] 107 1 T17 1 T23 1 T52 1
auto[3623878656:3758096383] auto[1] 5 1 T132 1 T316 2 T410 1
auto[3758096384:3892314111] auto[0] 88 1 T2 2 T11 1 T5 1
auto[3758096384:3892314111] auto[1] 11 1 T130 2 T145 2 T406 1
auto[3892314112:4026531839] auto[0] 85 1 T11 1 T23 1 T5 1
auto[3892314112:4026531839] auto[1] 7 1 T130 1 T308 1 T316 1
auto[4026531840:4160749567] auto[0] 107 1 T2 3 T16 1 T52 2
auto[4026531840:4160749567] auto[1] 7 1 T354 2 T406 1 T316 1
auto[4160749568:4294967295] auto[0] 81 1 T2 3 T23 2 T40 2
auto[4160749568:4294967295] auto[1] 8 1 T12 1 T136 1 T303 1

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