Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3005

1

T1

1

T2

42

T4

2

auto[1]

278

1

T12

1

T130

9

T132

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T2	2		T52	1		T65	1
auto[134217728:268435455]	103	1			T2	2		T11	1		T23	2
auto[268435456:402653183]	110	1			T2	1		T12	1		T16	1
auto[402653184:536870911]	93	1			T2	1		T12	1		T23	3
auto[536870912:671088639]	95	1			T2	4		T50	1		T65	1
auto[671088640:805306367]	97	1			T35	1		T23	2		T57	1
auto[805306368:939524095]	108	1			T2	1		T57	1		T217	1
auto[939524096:1073741823]	109	1			T23	1		T132	1		T218	1
auto[1073741824:1207959551]	104	1			T1	1		T2	1		T52	1
auto[1207959552:1342177279]	101	1			T2	1		T23	3		T37	1
auto[1342177280:1476395007]	96	1			T23	2		T130	1		T62	1
auto[1476395008:1610612735]	97	1			T2	1		T12	1		T23	4
auto[1610612736:1744830463]	106	1			T2	3		T52	1		T57	1
auto[1744830464:1879048191]	108	1			T2	2		T23	2		T130	1
auto[1879048192:2013265919]	93	1			T2	3		T23	1		T65	1
auto[2013265920:2147483647]	112	1			T2	3		T12	1		T130	1
auto[2147483648:2281701375]	116	1			T2	1		T36	1		T130	1
auto[2281701376:2415919103]	111	1			T2	1		T11	1		T23	2
auto[2415919104:2550136831]	96	1			T2	1		T11	1		T23	2
auto[2550136832:2684354559]	102	1			T4	1		T23	1		T52	1
auto[2684354560:2818572287]	99	1			T2	2		T12	1		T23	1
auto[2818572288:2952790015]	112	1			T2	1		T23	1		T132	1
auto[2952790016:3087007743]	88	1			T11	1		T57	1		T37	1
auto[3087007744:3221225471]	99	1			T2	1		T40	1		T50	1
auto[3221225472:3355443199]	97	1			T2	1		T12	1		T16	1
auto[3355443200:3489660927]	102	1			T130	3		T131	1		T5	3
auto[3489660928:3623878655]	92	1			T2	1		T12	1		T17	1
auto[3623878656:3758096383]	109	1			T2	2		T11	1		T35	1
auto[3758096384:3892314111]	130	1			T2	1		T4	1		T23	3
auto[3892314112:4026531839]	104	1			T2	3		T23	1		T130	1
auto[4026531840:4160749567]	92	1			T11	1		T36	1		T130	1
auto[4160749568:4294967295]	92	1			T2	2		T11	1		T12	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	99	1			T2	2		T52	1		T65	1
auto[0:134217727]	auto[1]	11	1			T276	1		T402	1		T272	1
auto[134217728:268435455]	auto[0]	91	1			T2	2		T11	1		T23	2
auto[134217728:268435455]	auto[1]	12	1			T135	1		T83	1		T354	1
auto[268435456:402653183]	auto[0]	100	1			T2	1		T16	1		T23	1
auto[268435456:402653183]	auto[1]	10	1			T12	1		T132	1		T136	1
auto[402653184:536870911]	auto[0]	85	1			T2	1		T12	1		T23	3
auto[402653184:536870911]	auto[1]	8	1			T359	1		T370	1		T269	1
auto[536870912:671088639]	auto[0]	88	1			T2	4		T50	1		T65	1
auto[536870912:671088639]	auto[1]	7	1			T145	1		T359	1		T251	1
auto[671088640:805306367]	auto[0]	83	1			T35	1		T23	2		T57	1
auto[671088640:805306367]	auto[1]	14	1			T130	1		T370	2		T271	3
auto[805306368:939524095]	auto[0]	100	1			T2	1		T57	1		T217	1
auto[805306368:939524095]	auto[1]	8	1			T276	1		T402	1		T316	1
auto[939524096:1073741823]	auto[0]	102	1			T23	1		T132	1		T218	1
auto[939524096:1073741823]	auto[1]	7	1			T137	1		T402	1		T279	1
auto[1073741824:1207959551]	auto[0]	98	1			T1	1		T2	1		T52	1
auto[1073741824:1207959551]	auto[1]	6	1			T130	1		T137	1		T324	1
auto[1207959552:1342177279]	auto[0]	92	1			T2	1		T23	3		T37	1
auto[1207959552:1342177279]	auto[1]	9	1			T325	1		T83	1		T272	2
auto[1342177280:1476395007]	auto[0]	89	1			T23	2		T62	1		T58	1
auto[1342177280:1476395007]	auto[1]	7	1			T130	1		T274	1		T271	2
auto[1476395008:1610612735]	auto[0]	89	1			T2	1		T12	1		T23	4
auto[1476395008:1610612735]	auto[1]	8	1			T145	1		T135	1		T325	1
auto[1610612736:1744830463]	auto[0]	101	1			T2	3		T52	1		T57	1
auto[1610612736:1744830463]	auto[1]	5	1			T370	1		T406	1		T308	1
auto[1744830464:1879048191]	auto[0]	98	1			T2	2		T23	2		T254	1
auto[1744830464:1879048191]	auto[1]	10	1			T130	1		T137	2		T402	1
auto[1879048192:2013265919]	auto[0]	88	1			T2	3		T23	1		T65	1
auto[1879048192:2013265919]	auto[1]	5	1			T83	1		T384	1		T339	1
auto[2013265920:2147483647]	auto[0]	101	1			T2	3		T12	1		T132	1
auto[2013265920:2147483647]	auto[1]	11	1			T130	1		T276	1		T325	1
auto[2147483648:2281701375]	auto[0]	106	1			T2	1		T36	1		T5	3
auto[2147483648:2281701375]	auto[1]	10	1			T130	1		T132	1		T83	1
auto[2281701376:2415919103]	auto[0]	100	1			T2	1		T11	1		T23	2
auto[2281701376:2415919103]	auto[1]	11	1			T145	1		T136	2		T83	1
auto[2415919104:2550136831]	auto[0]	93	1			T2	1		T11	1		T23	2
auto[2415919104:2550136831]	auto[1]	3	1			T274	2		T416	1		-	-
auto[2550136832:2684354559]	auto[0]	96	1			T4	1		T23	1		T52	1
auto[2550136832:2684354559]	auto[1]	6	1			T406	1		T279	2		T410	1
auto[2684354560:2818572287]	auto[0]	93	1			T2	2		T12	1		T23	1
auto[2684354560:2818572287]	auto[1]	6	1			T135	1		T83	1		T406	1
auto[2818572288:2952790015]	auto[0]	101	1			T2	1		T23	1		T132	1
auto[2818572288:2952790015]	auto[1]	11	1			T137	1		T272	1		T308	1
auto[2952790016:3087007743]	auto[0]	80	1			T11	1		T57	1		T37	1
auto[2952790016:3087007743]	auto[1]	8	1			T137	1		T272	1		T316	1
auto[3087007744:3221225471]	auto[0]	93	1			T2	1		T40	1		T50	1
auto[3087007744:3221225471]	auto[1]	6	1			T135	2		T308	1		T399	1
auto[3221225472:3355443199]	auto[0]	90	1			T2	1		T12	1		T16	1
auto[3221225472:3355443199]	auto[1]	7	1			T135	1		T137	1		T370	1
auto[3355443200:3489660927]	auto[0]	96	1			T130	2		T131	1		T5	3
auto[3355443200:3489660927]	auto[1]	6	1			T130	1		T370	1		T406	1
auto[3489660928:3623878655]	auto[0]	83	1			T2	1		T12	1		T17	1
auto[3489660928:3623878655]	auto[1]	9	1			T83	2		T272	1		T271	1
auto[3623878656:3758096383]	auto[0]	98	1			T2	2		T11	1		T35	1
auto[3623878656:3758096383]	auto[1]	11	1			T83	2		T274	1		T303	1
auto[3758096384:3892314111]	auto[0]	115	1			T2	1		T4	1		T23	3
auto[3758096384:3892314111]	auto[1]	15	1			T130	1		T135	1		T384	2
auto[3892314112:4026531839]	auto[0]	90	1			T2	3		T23	1		T130	1
auto[3892314112:4026531839]	auto[1]	14	1			T132	1		T272	1		T308	1
auto[4026531840:4160749567]	auto[0]	81	1			T11	1		T36	1		T37	1
auto[4026531840:4160749567]	auto[1]	11	1			T130	1		T145	1		T274	3
auto[4160749568:4294967295]	auto[0]	86	1			T2	2		T11	1		T12	1
auto[4160749568:4294967295]	auto[1]	6	1			T276	1		T137	1		T402	1