Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.37 99.00 98.03 98.39 97.67 98.93 98.41 91.14


Total test records in report: 1081
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T1008 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1220603466 May 30 02:12:48 PM PDT 24 May 30 02:12:51 PM PDT 24 454626125 ps
T1009 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.539324880 May 30 02:13:47 PM PDT 24 May 30 02:13:51 PM PDT 24 131037003 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1621069882 May 30 02:12:59 PM PDT 24 May 30 02:13:02 PM PDT 24 29140709 ps
T160 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.247110204 May 30 02:12:58 PM PDT 24 May 30 02:13:08 PM PDT 24 949982900 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.900837516 May 30 02:13:06 PM PDT 24 May 30 02:13:07 PM PDT 24 19622720 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3677871103 May 30 02:13:44 PM PDT 24 May 30 02:13:49 PM PDT 24 107255994 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1889038052 May 30 02:13:54 PM PDT 24 May 30 02:13:58 PM PDT 24 38951196 ps
T1014 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1739644642 May 30 02:13:59 PM PDT 24 May 30 02:14:01 PM PDT 24 31315861 ps
T1015 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.339008729 May 30 02:12:59 PM PDT 24 May 30 02:13:04 PM PDT 24 500350020 ps
T1016 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4251935036 May 30 02:13:57 PM PDT 24 May 30 02:14:00 PM PDT 24 51863836 ps
T1017 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.560149957 May 30 02:13:48 PM PDT 24 May 30 02:13:50 PM PDT 24 11604461 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1763648727 May 30 02:12:58 PM PDT 24 May 30 02:13:00 PM PDT 24 194447441 ps
T1019 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3078698533 May 30 02:12:47 PM PDT 24 May 30 02:12:56 PM PDT 24 180425137 ps
T1020 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4212883183 May 30 02:13:56 PM PDT 24 May 30 02:13:58 PM PDT 24 27159175 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4094155574 May 30 02:12:48 PM PDT 24 May 30 02:12:50 PM PDT 24 11839115 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2847669678 May 30 02:13:48 PM PDT 24 May 30 02:13:50 PM PDT 24 11486574 ps
T1023 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4113571597 May 30 02:13:58 PM PDT 24 May 30 02:14:00 PM PDT 24 14006849 ps
T1024 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2033282926 May 30 02:12:59 PM PDT 24 May 30 02:13:02 PM PDT 24 118126865 ps
T1025 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3338203138 May 30 02:13:57 PM PDT 24 May 30 02:13:59 PM PDT 24 14323841 ps
T1026 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3228548300 May 30 02:13:01 PM PDT 24 May 30 02:13:05 PM PDT 24 182792890 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1170824135 May 30 02:12:49 PM PDT 24 May 30 02:12:52 PM PDT 24 11654345 ps
T1028 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3713446956 May 30 02:13:49 PM PDT 24 May 30 02:13:54 PM PDT 24 200031782 ps
T1029 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.660329927 May 30 02:13:49 PM PDT 24 May 30 02:13:54 PM PDT 24 278665287 ps
T1030 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.284603148 May 30 02:13:47 PM PDT 24 May 30 02:13:50 PM PDT 24 103867510 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3111906702 May 30 02:13:57 PM PDT 24 May 30 02:14:00 PM PDT 24 78050072 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2266102739 May 30 02:12:58 PM PDT 24 May 30 02:13:01 PM PDT 24 28699307 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.347252203 May 30 02:13:06 PM PDT 24 May 30 02:13:08 PM PDT 24 29920929 ps
T1034 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1935089044 May 30 02:13:01 PM PDT 24 May 30 02:13:05 PM PDT 24 291944748 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2449472307 May 30 02:12:48 PM PDT 24 May 30 02:12:51 PM PDT 24 80843240 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3629263119 May 30 02:13:48 PM PDT 24 May 30 02:13:51 PM PDT 24 35897093 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1407186442 May 30 02:12:49 PM PDT 24 May 30 02:12:53 PM PDT 24 84773837 ps
T1038 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3376866344 May 30 02:13:56 PM PDT 24 May 30 02:13:59 PM PDT 24 27670954 ps
T1039 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3457157179 May 30 02:12:56 PM PDT 24 May 30 02:13:16 PM PDT 24 2153846390 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1333311859 May 30 02:13:48 PM PDT 24 May 30 02:13:52 PM PDT 24 171188197 ps
T1041 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1220217304 May 30 02:13:56 PM PDT 24 May 30 02:13:58 PM PDT 24 39520988 ps
T1042 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.339663610 May 30 02:13:00 PM PDT 24 May 30 02:13:05 PM PDT 24 1237986084 ps
T163 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.317607378 May 30 02:12:50 PM PDT 24 May 30 02:12:57 PM PDT 24 416221249 ps
T154 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.459226505 May 30 02:13:49 PM PDT 24 May 30 02:13:57 PM PDT 24 230536103 ps
T161 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.139255931 May 30 02:12:46 PM PDT 24 May 30 02:12:53 PM PDT 24 695508918 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3963031430 May 30 02:12:48 PM PDT 24 May 30 02:12:53 PM PDT 24 522622584 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.338767004 May 30 02:12:47 PM PDT 24 May 30 02:12:51 PM PDT 24 189762146 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2281040794 May 30 02:13:00 PM PDT 24 May 30 02:13:08 PM PDT 24 1672980948 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2011822458 May 30 02:13:47 PM PDT 24 May 30 02:13:49 PM PDT 24 37252401 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4156390551 May 30 02:13:01 PM PDT 24 May 30 02:13:07 PM PDT 24 83318959 ps
T1048 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3783410274 May 30 02:12:45 PM PDT 24 May 30 02:12:52 PM PDT 24 1611255899 ps
T1049 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4213274919 May 30 02:13:48 PM PDT 24 May 30 02:13:51 PM PDT 24 31981484 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3979568751 May 30 02:12:59 PM PDT 24 May 30 02:13:03 PM PDT 24 321815731 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1759390280 May 30 02:12:59 PM PDT 24 May 30 02:13:05 PM PDT 24 119904050 ps
T1052 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1518255797 May 30 02:13:48 PM PDT 24 May 30 02:13:51 PM PDT 24 11248748 ps
T1053 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.770913617 May 30 02:13:46 PM PDT 24 May 30 02:13:49 PM PDT 24 202028668 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2682137545 May 30 02:13:02 PM PDT 24 May 30 02:13:04 PM PDT 24 49023064 ps
T1055 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2516856434 May 30 02:13:53 PM PDT 24 May 30 02:13:55 PM PDT 24 54265071 ps
T1056 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2267587772 May 30 02:12:48 PM PDT 24 May 30 02:12:52 PM PDT 24 619989705 ps
T1057 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2559028985 May 30 02:12:46 PM PDT 24 May 30 02:12:50 PM PDT 24 367276457 ps
T1058 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2578039787 May 30 02:13:00 PM PDT 24 May 30 02:13:03 PM PDT 24 101578394 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2383714522 May 30 02:13:48 PM PDT 24 May 30 02:13:52 PM PDT 24 51414323 ps
T1060 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2481599981 May 30 02:12:47 PM PDT 24 May 30 02:12:51 PM PDT 24 112154789 ps
T1061 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4069585260 May 30 02:13:56 PM PDT 24 May 30 02:13:58 PM PDT 24 43097057 ps
T1062 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.845542513 May 30 02:13:57 PM PDT 24 May 30 02:13:59 PM PDT 24 130886049 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2019597621 May 30 02:13:56 PM PDT 24 May 30 02:13:59 PM PDT 24 109036501 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.423069441 May 30 02:13:47 PM PDT 24 May 30 02:13:49 PM PDT 24 38039345 ps
T153 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1340113006 May 30 02:13:05 PM PDT 24 May 30 02:13:16 PM PDT 24 1560277029 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.550607700 May 30 02:12:48 PM PDT 24 May 30 02:12:50 PM PDT 24 22103862 ps
T168 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.686927442 May 30 02:13:05 PM PDT 24 May 30 02:13:13 PM PDT 24 291514194 ps
T1066 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1488819805 May 30 02:13:56 PM PDT 24 May 30 02:13:58 PM PDT 24 9142122 ps
T169 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2574589104 May 30 02:13:47 PM PDT 24 May 30 02:13:53 PM PDT 24 189807758 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2046596974 May 30 02:13:00 PM PDT 24 May 30 02:13:06 PM PDT 24 109205972 ps
T1068 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1691179750 May 30 02:13:46 PM PDT 24 May 30 02:13:54 PM PDT 24 298324020 ps
T1069 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2475208584 May 30 02:12:59 PM PDT 24 May 30 02:13:03 PM PDT 24 27602281 ps
T1070 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3702989938 May 30 02:13:47 PM PDT 24 May 30 02:13:51 PM PDT 24 38716416 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2119223439 May 30 02:13:46 PM PDT 24 May 30 02:13:54 PM PDT 24 153925675 ps
T1072 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4159877210 May 30 02:12:52 PM PDT 24 May 30 02:12:53 PM PDT 24 11940515 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3099630851 May 30 02:13:56 PM PDT 24 May 30 02:14:03 PM PDT 24 83806870 ps
T1074 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3402574168 May 30 02:12:46 PM PDT 24 May 30 02:13:13 PM PDT 24 889241932 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3029884905 May 30 02:13:02 PM PDT 24 May 30 02:13:18 PM PDT 24 1126716381 ps
T1076 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2650017520 May 30 02:12:59 PM PDT 24 May 30 02:13:03 PM PDT 24 208568958 ps
T1077 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2602336813 May 30 02:12:50 PM PDT 24 May 30 02:13:07 PM PDT 24 516944707 ps
T1078 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2014258361 May 30 02:13:47 PM PDT 24 May 30 02:13:49 PM PDT 24 13937236 ps
T1079 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4124831277 May 30 02:13:46 PM PDT 24 May 30 02:13:50 PM PDT 24 140903877 ps
T1080 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1893392302 May 30 02:13:06 PM PDT 24 May 30 02:13:07 PM PDT 24 13804037 ps
T1081 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2204566016 May 30 02:12:44 PM PDT 24 May 30 02:12:49 PM PDT 24 493656710 ps

Test location /workspace/coverage/default/23.keymgr_stress_all.3202536037
Short name T2
Test name
Test status
Simulation time 2867074611 ps
CPU time 50.45 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:38:27 PM PDT 24
Peak memory 215664 kb
Host smart-5ed49cd8-a570-4aaa-b3d6-3d9195482fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202536037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3202536037
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1479364177
Short name T5
Test name
Test status
Simulation time 2173294979 ps
CPU time 45.07 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 216404 kb
Host smart-87888410-1f1c-4471-a060-6c1444c3e3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479364177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1479364177
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.500350777
Short name T57
Test name
Test status
Simulation time 692303887 ps
CPU time 11.39 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 222644 kb
Host smart-e5065978-91a5-45bf-909e-f324c1f1668a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500350777 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.500350777
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3175028530
Short name T8
Test name
Test status
Simulation time 304070767 ps
CPU time 9.77 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:40 PM PDT 24
Peak memory 230384 kb
Host smart-897c9968-5536-4a99-962c-de35ffd03848
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175028530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3175028530
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2346338935
Short name T114
Test name
Test status
Simulation time 259735661 ps
CPU time 5.96 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:56 PM PDT 24
Peak memory 214112 kb
Host smart-f1f68373-edeb-436c-a003-b8c3cf2edf92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346338935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2346338935
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3101963091
Short name T23
Test name
Test status
Simulation time 4484664930 ps
CPU time 43.57 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:37:18 PM PDT 24
Peak memory 222644 kb
Host smart-edd1b22c-48e5-47b2-b190-ae42e574e0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101963091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3101963091
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2503766213
Short name T130
Test name
Test status
Simulation time 1181586008 ps
CPU time 15.99 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:46 PM PDT 24
Peak memory 215164 kb
Host smart-7ce902bc-7d15-42d9-b72a-b4351ee54a99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503766213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2503766213
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2210758467
Short name T53
Test name
Test status
Simulation time 90717914 ps
CPU time 2.73 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 214300 kb
Host smart-d04aa8a9-ca9d-4224-b264-933ee26536c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210758467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2210758467
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.304811542
Short name T6
Test name
Test status
Simulation time 915246612 ps
CPU time 4.79 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 209860 kb
Host smart-56e564ac-c726-4abe-a40b-69dc9be7c1ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304811542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.304811542
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.20729898
Short name T12
Test name
Test status
Simulation time 117465553 ps
CPU time 4.67 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 222440 kb
Host smart-80615ee6-d2a5-49b1-b50c-0ec44fdf9499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20729898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.20729898
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.296550254
Short name T62
Test name
Test status
Simulation time 4105036470 ps
CPU time 44.27 seconds
Started May 30 03:37:13 PM PDT 24
Finished May 30 03:37:59 PM PDT 24
Peak memory 222608 kb
Host smart-b4ab2bc6-767d-4637-b99b-870c6c8dad0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296550254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.296550254
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1270504099
Short name T113
Test name
Test status
Simulation time 434830299 ps
CPU time 13.2 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:12 PM PDT 24
Peak memory 214192 kb
Host smart-96f34719-158a-41d0-a69f-35f0eaef7941
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270504099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1270504099
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.690605481
Short name T279
Test name
Test status
Simulation time 151914441 ps
CPU time 8.41 seconds
Started May 30 03:37:10 PM PDT 24
Finished May 30 03:37:20 PM PDT 24
Peak memory 214268 kb
Host smart-3de714c3-3588-417a-a077-ff99322c23c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690605481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.690605481
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1257068233
Short name T22
Test name
Test status
Simulation time 44739043 ps
CPU time 2.87 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 222488 kb
Host smart-063f1a7f-427c-4b4f-971a-9c2950d7fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257068233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1257068233
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1563033790
Short name T18
Test name
Test status
Simulation time 165273308 ps
CPU time 3 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 209852 kb
Host smart-ca19ae68-3d32-4072-a6e7-08ff40fc1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563033790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1563033790
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.403718365
Short name T51
Test name
Test status
Simulation time 1393760436 ps
CPU time 49.82 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:38:08 PM PDT 24
Peak memory 222408 kb
Host smart-06857bd3-2f63-4bdf-adf4-f908bc76ab1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403718365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.403718365
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.885111315
Short name T272
Test name
Test status
Simulation time 2018816239 ps
CPU time 62.3 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 215636 kb
Host smart-699d1f3f-74d8-4501-a219-d2d69ddd2abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885111315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.885111315
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2391909917
Short name T316
Test name
Test status
Simulation time 156649880 ps
CPU time 8.81 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 214340 kb
Host smart-1dfc1fde-3cc7-41c3-9333-9c8ad30ea43a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391909917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2391909917
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1304048498
Short name T45
Test name
Test status
Simulation time 54989217 ps
CPU time 1.68 seconds
Started May 30 03:36:17 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 208600 kb
Host smart-76282c89-4085-4607-b67f-a79b572094bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304048498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1304048498
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2961983814
Short name T73
Test name
Test status
Simulation time 3905553389 ps
CPU time 85.23 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 216296 kb
Host smart-24d8fbc5-9bd5-444b-a0b5-237afd403004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961983814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2961983814
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3488238167
Short name T400
Test name
Test status
Simulation time 10462568691 ps
CPU time 48.03 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 222644 kb
Host smart-7799983a-bf2c-406a-be34-4f25e7294bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488238167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3488238167
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2646803977
Short name T125
Test name
Test status
Simulation time 2246693323 ps
CPU time 35.08 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:38:02 PM PDT 24
Peak memory 223400 kb
Host smart-213c6d0e-8a2b-4577-a4a6-c7fb123fb244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646803977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2646803977
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2919345579
Short name T227
Test name
Test status
Simulation time 514662656 ps
CPU time 11.77 seconds
Started May 30 03:37:14 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 214296 kb
Host smart-1a5b37ef-02a6-4cfc-8ad3-b9c9d145263a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919345579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2919345579
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3719378597
Short name T19
Test name
Test status
Simulation time 108279520 ps
CPU time 5.32 seconds
Started May 30 03:38:20 PM PDT 24
Finished May 30 03:38:27 PM PDT 24
Peak memory 219712 kb
Host smart-6e150452-3e4a-40e4-9ab1-159783e885b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719378597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3719378597
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1173491332
Short name T170
Test name
Test status
Simulation time 170399335 ps
CPU time 5.24 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 222588 kb
Host smart-3eaf06a9-160f-4582-b2da-7cd343889af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173491332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1173491332
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1784964545
Short name T276
Test name
Test status
Simulation time 412003083 ps
CPU time 22.4 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 215544 kb
Host smart-d95c7969-e963-438d-8040-f251346b9b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784964545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1784964545
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2425201898
Short name T27
Test name
Test status
Simulation time 40549772 ps
CPU time 2.58 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 217096 kb
Host smart-3b8759fd-52dd-4ced-90bb-e210fc7e7f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425201898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2425201898
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3523675612
Short name T64
Test name
Test status
Simulation time 2758997845 ps
CPU time 13.71 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 215676 kb
Host smart-6112c2f3-6e98-4775-b03e-71d73734cbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523675612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3523675612
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.71474594
Short name T20
Test name
Test status
Simulation time 216965683 ps
CPU time 1.79 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 220720 kb
Host smart-381d2b6f-324e-4f2c-a7c6-cf40cc278354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71474594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.71474594
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3203163395
Short name T151
Test name
Test status
Simulation time 1008154664 ps
CPU time 7.46 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:05 PM PDT 24
Peak memory 205884 kb
Host smart-c1078912-d49c-4b0b-b7d4-cb99e920a9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203163395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3203163395
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4038554517
Short name T271
Test name
Test status
Simulation time 98326167 ps
CPU time 6.13 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:29 PM PDT 24
Peak memory 215284 kb
Host smart-488e2387-e105-4ca4-bb59-f050db95d14d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038554517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4038554517
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3119012961
Short name T55
Test name
Test status
Simulation time 7790794822 ps
CPU time 218.93 seconds
Started May 30 03:37:06 PM PDT 24
Finished May 30 03:40:47 PM PDT 24
Peak memory 222576 kb
Host smart-ba241452-3376-4882-9582-16ba15af6ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119012961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3119012961
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3629838258
Short name T440
Test name
Test status
Simulation time 11259313 ps
CPU time 0.71 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 205924 kb
Host smart-0f7d8c72-9285-479a-97e1-89a48bbb6040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629838258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3629838258
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.834376017
Short name T336
Test name
Test status
Simulation time 1549060994 ps
CPU time 36.87 seconds
Started May 30 03:37:44 PM PDT 24
Finished May 30 03:38:22 PM PDT 24
Peak memory 222168 kb
Host smart-36595a1d-9655-499d-9a30-252e19909f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834376017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.834376017
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4007953122
Short name T416
Test name
Test status
Simulation time 143965894 ps
CPU time 4.78 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 214568 kb
Host smart-dbe486c3-1ae9-444f-ae2e-3fe6c41c0ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007953122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4007953122
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3029372680
Short name T1
Test name
Test status
Simulation time 396241556 ps
CPU time 18.46 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 209296 kb
Host smart-060fe3b6-9117-4224-a071-44babc50d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029372680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3029372680
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2035700258
Short name T121
Test name
Test status
Simulation time 161450771 ps
CPU time 3.66 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 214188 kb
Host smart-4fc61ef5-cc89-408b-b39e-677a4ac9077f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035700258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2035700258
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1224502954
Short name T263
Test name
Test status
Simulation time 1005055000 ps
CPU time 3.42 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:27 PM PDT 24
Peak memory 206160 kb
Host smart-fdfbe069-0256-43bf-8653-a83720dcccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224502954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1224502954
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.771430219
Short name T94
Test name
Test status
Simulation time 297973965 ps
CPU time 3.06 seconds
Started May 30 03:38:55 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 214324 kb
Host smart-014f7d30-79a2-42b9-b41f-ccd35f52f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771430219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.771430219
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1450637769
Short name T145
Test name
Test status
Simulation time 192273468 ps
CPU time 3.66 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:20 PM PDT 24
Peak memory 214348 kb
Host smart-c77c5764-b8a6-4788-8906-b6e01ada67a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450637769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1450637769
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1915747794
Short name T243
Test name
Test status
Simulation time 15159667701 ps
CPU time 88.51 seconds
Started May 30 03:37:25 PM PDT 24
Finished May 30 03:38:57 PM PDT 24
Peak memory 221548 kb
Host smart-98bcecfc-1c0d-4891-b2aa-666593c4fb93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915747794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1915747794
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1332559597
Short name T359
Test name
Test status
Simulation time 65265286 ps
CPU time 4.48 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 214612 kb
Host smart-2f5f27a0-2ad0-4500-82ac-4e698b5e5f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332559597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1332559597
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.473966387
Short name T68
Test name
Test status
Simulation time 1653711666 ps
CPU time 6.73 seconds
Started May 30 03:38:00 PM PDT 24
Finished May 30 03:38:08 PM PDT 24
Peak memory 222672 kb
Host smart-5c54868e-82f8-4cd5-b7f3-efaf5b79f29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473966387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.473966387
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3574907126
Short name T246
Test name
Test status
Simulation time 1319990683 ps
CPU time 17.86 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:33 PM PDT 24
Peak memory 215628 kb
Host smart-e5b80c77-ea68-4de9-8f0b-b5dadfb06901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574907126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3574907126
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4160011809
Short name T186
Test name
Test status
Simulation time 2510613099 ps
CPU time 54.52 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:39:05 PM PDT 24
Peak memory 220752 kb
Host smart-ccf8c2c3-7faf-4e50-bd87-70ad5b818d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160011809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4160011809
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2417483240
Short name T158
Test name
Test status
Simulation time 260964767 ps
CPU time 9.97 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:10 PM PDT 24
Peak memory 213880 kb
Host smart-ca3516c5-75b9-43e1-b6cb-ef954695ff96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417483240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2417483240
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.247110204
Short name T160
Test name
Test status
Simulation time 949982900 ps
CPU time 9.23 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:08 PM PDT 24
Peak memory 213964 kb
Host smart-2c430f86-4820-4fd5-a0e5-19f1429daf89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247110204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
247110204
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1431284213
Short name T320
Test name
Test status
Simulation time 136776826 ps
CPU time 2.74 seconds
Started May 30 03:36:17 PM PDT 24
Finished May 30 03:36:22 PM PDT 24
Peak memory 214228 kb
Host smart-43a9b1a5-3b96-4fc0-97b4-362c006d3f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431284213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1431284213
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1593999914
Short name T237
Test name
Test status
Simulation time 10283582349 ps
CPU time 67.56 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 222604 kb
Host smart-5acf0a7a-61cc-49a0-a21d-391d1271fc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593999914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1593999914
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3255180287
Short name T164
Test name
Test status
Simulation time 114229916 ps
CPU time 4.09 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 210188 kb
Host smart-1dbbf491-4e06-461c-9d85-ed23ce7e2dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255180287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3255180287
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.317607378
Short name T163
Test name
Test status
Simulation time 416221249 ps
CPU time 6.01 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:12:57 PM PDT 24
Peak memory 213904 kb
Host smart-b8c845fa-beda-4486-b6f2-5fe68f19d213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317607378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
317607378
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.149617211
Short name T9
Test name
Test status
Simulation time 2780663022 ps
CPU time 20.04 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 239048 kb
Host smart-ed6d440b-a96e-4397-975b-144794ae532f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149617211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.149617211
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.627368791
Short name T173
Test name
Test status
Simulation time 215233196 ps
CPU time 2.75 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 215684 kb
Host smart-486bb8f1-03d7-4690-90c7-46e1df080a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627368791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.627368791
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3441654408
Short name T201
Test name
Test status
Simulation time 82539620 ps
CPU time 3.3 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 210180 kb
Host smart-27ce54c1-a12c-49f0-a665-d180977de151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441654408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3441654408
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2912541665
Short name T342
Test name
Test status
Simulation time 247642367 ps
CPU time 4.21 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:23 PM PDT 24
Peak memory 208916 kb
Host smart-66c5289f-4851-4eed-b974-09a1fbf60e68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912541665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2912541665
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2808270014
Short name T99
Test name
Test status
Simulation time 114488094 ps
CPU time 3.31 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 220860 kb
Host smart-073710b1-2910-4ad4-b050-ebb41968d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808270014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2808270014
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1984037416
Short name T406
Test name
Test status
Simulation time 478233327 ps
CPU time 13.64 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:38:03 PM PDT 24
Peak memory 215312 kb
Host smart-b5d51d8b-df7d-4bf9-be74-defc483fac3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984037416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1984037416
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.675231586
Short name T324
Test name
Test status
Simulation time 267000668 ps
CPU time 8.06 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:08 PM PDT 24
Peak memory 214572 kb
Host smart-d0f4a8d6-4edf-4edb-83fa-2dd738e5de70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675231586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.675231586
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.540705745
Short name T79
Test name
Test status
Simulation time 2916988886 ps
CPU time 40.37 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 216212 kb
Host smart-d4899bb0-3bd4-4402-8e9a-da8331268c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540705745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.540705745
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3095723363
Short name T269
Test name
Test status
Simulation time 138456129 ps
CPU time 7.85 seconds
Started May 30 03:38:32 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 215672 kb
Host smart-dda77e02-6ec1-4649-b009-c1a1b29f94b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095723363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3095723363
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1362556684
Short name T383
Test name
Test status
Simulation time 76325321 ps
CPU time 4 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 222428 kb
Host smart-6cce6f2c-f42a-4c19-b984-40f28ab97acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362556684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1362556684
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1293022225
Short name T138
Test name
Test status
Simulation time 788547392 ps
CPU time 24.46 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:58 PM PDT 24
Peak memory 222484 kb
Host smart-dadb7cfe-ec7b-4e40-b397-108538025f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293022225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1293022225
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1569319129
Short name T123
Test name
Test status
Simulation time 914513681 ps
CPU time 20.98 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:56 PM PDT 24
Peak memory 220268 kb
Host smart-3483cdd5-6f3b-4ff6-87c5-d3a028a1a4a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569319129 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1569319129
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2165382266
Short name T351
Test name
Test status
Simulation time 8642104174 ps
CPU time 198.37 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 218892 kb
Host smart-4b98fb31-b53b-4de3-91a7-3d2d249f231a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165382266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2165382266
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.686927442
Short name T168
Test name
Test status
Simulation time 291514194 ps
CPU time 7.18 seconds
Started May 30 02:13:05 PM PDT 24
Finished May 30 02:13:13 PM PDT 24
Peak memory 213880 kb
Host smart-ddc429fa-2d26-46a4-a7b3-78fe1e9b2ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686927442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
686927442
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3901107627
Short name T139
Test name
Test status
Simulation time 563798999 ps
CPU time 2.1 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 217224 kb
Host smart-1e7a09b8-2cec-4ed0-9e54-67bfdda9ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901107627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3901107627
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3227897654
Short name T172
Test name
Test status
Simulation time 148353213 ps
CPU time 1.94 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 222632 kb
Host smart-391f68cc-e720-4a63-b695-c293fc1b3b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227897654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3227897654
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4268605111
Short name T96
Test name
Test status
Simulation time 86795900 ps
CPU time 1.6 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:17 PM PDT 24
Peak memory 214324 kb
Host smart-ed64b0b7-16e2-4e4d-a7c6-85dfb100aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268605111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4268605111
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4154496338
Short name T88
Test name
Test status
Simulation time 1158542354 ps
CPU time 30.15 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:54 PM PDT 24
Peak memory 216364 kb
Host smart-7bdec63f-d8a9-4bc4-b785-77568035112c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154496338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4154496338
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2742405575
Short name T284
Test name
Test status
Simulation time 69198798 ps
CPU time 3.32 seconds
Started May 30 03:36:22 PM PDT 24
Finished May 30 03:36:29 PM PDT 24
Peak memory 214348 kb
Host smart-cae3c02f-3c3e-4c14-82f1-4a0caec85f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742405575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2742405575
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1369160407
Short name T900
Test name
Test status
Simulation time 112268643 ps
CPU time 4.27 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 214340 kb
Host smart-757e5a58-6015-4626-ac20-9e5419f8ec96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369160407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1369160407
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.20644404
Short name T248
Test name
Test status
Simulation time 70927653 ps
CPU time 2.59 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 214392 kb
Host smart-66a6771b-b1b9-4ad2-945e-c5796606bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20644404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.20644404
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1471255284
Short name T561
Test name
Test status
Simulation time 1239736537 ps
CPU time 9.18 seconds
Started May 30 03:37:39 PM PDT 24
Finished May 30 03:37:51 PM PDT 24
Peak memory 208476 kb
Host smart-01942576-d067-4dd2-96fe-1eef7a0b8391
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471255284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1471255284
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.172115212
Short name T308
Test name
Test status
Simulation time 62973711 ps
CPU time 4.4 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 214348 kb
Host smart-c083a252-9e59-42cf-a6c2-acdcbe20e252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172115212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.172115212
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3587566366
Short name T330
Test name
Test status
Simulation time 4605289835 ps
CPU time 21.43 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:19 PM PDT 24
Peak memory 222768 kb
Host smart-ccea5aba-9e45-4c09-94b8-d3b799a25324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587566366 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3587566366
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.459226505
Short name T154
Test name
Test status
Simulation time 230536103 ps
CPU time 6.95 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:57 PM PDT 24
Peak memory 215304 kb
Host smart-47b30fe4-4f07-4df7-9083-37edc75e3be7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459226505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.459226505
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2574589104
Short name T169
Test name
Test status
Simulation time 189807758 ps
CPU time 5.36 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 213908 kb
Host smart-073e33bf-1386-4881-ad27-ba6f941a07e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574589104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2574589104
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1152647377
Short name T167
Test name
Test status
Simulation time 1281999896 ps
CPU time 3.64 seconds
Started May 30 02:12:56 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 205580 kb
Host smart-b223d40b-2199-4aa8-9243-357e3ab120c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152647377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1152647377
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3172130166
Short name T818
Test name
Test status
Simulation time 216936971 ps
CPU time 3.95 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:29 PM PDT 24
Peak memory 209048 kb
Host smart-b864a5eb-19d0-4c8f-ab49-ad0c9a21481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172130166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3172130166
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4150087484
Short name T31
Test name
Test status
Simulation time 517887426 ps
CPU time 5.12 seconds
Started May 30 03:37:29 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 210140 kb
Host smart-93ae993e-57a9-4fc7-8a5f-9acebd70969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150087484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4150087484
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2582117133
Short name T49
Test name
Test status
Simulation time 229681806 ps
CPU time 5.65 seconds
Started May 30 03:36:27 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 237416 kb
Host smart-9d747416-d001-4340-aa31-47a1481015b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582117133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2582117133
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3228627381
Short name T171
Test name
Test status
Simulation time 739979968 ps
CPU time 4.13 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:34 PM PDT 24
Peak memory 218288 kb
Host smart-4819849a-7ceb-4444-8418-056d25c3cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228627381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3228627381
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3892280172
Short name T35
Test name
Test status
Simulation time 138321446 ps
CPU time 4.15 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:51 PM PDT 24
Peak memory 218632 kb
Host smart-9abaec10-f8de-4186-94f4-52f6ea3933f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892280172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3892280172
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3509010028
Short name T580
Test name
Test status
Simulation time 1672225802 ps
CPU time 7.48 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:29 PM PDT 24
Peak memory 214276 kb
Host smart-46a08af2-cdb3-4c00-b4ce-600d689b8bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509010028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3509010028
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3551545594
Short name T442
Test name
Test status
Simulation time 34711408 ps
CPU time 2.47 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206972 kb
Host smart-9300f575-c327-4206-b7f4-b8c3b7465f9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551545594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3551545594
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.453336008
Short name T134
Test name
Test status
Simulation time 738526768 ps
CPU time 19.42 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 220848 kb
Host smart-6025a84c-a743-4830-bda3-1970809f1f51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453336008 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.453336008
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.954215741
Short name T39
Test name
Test status
Simulation time 286689638 ps
CPU time 7.18 seconds
Started May 30 03:37:05 PM PDT 24
Finished May 30 03:37:14 PM PDT 24
Peak memory 210496 kb
Host smart-10d788b4-0b74-4a36-aec8-9576118b56bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954215741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.954215741
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2212690534
Short name T405
Test name
Test status
Simulation time 832031521 ps
CPU time 2.76 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:21 PM PDT 24
Peak memory 218540 kb
Host smart-0a4e4863-1954-404a-8975-2c969c7aa739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212690534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2212690534
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.704632717
Short name T155
Test name
Test status
Simulation time 146597193 ps
CPU time 1.79 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 209836 kb
Host smart-c33f44d9-be31-4e12-ae98-353f641ccfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704632717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.704632717
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3115942319
Short name T321
Test name
Test status
Simulation time 41542754 ps
CPU time 2.74 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 206224 kb
Host smart-2ff9c90a-510d-41c8-bb5c-420a78f986b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115942319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3115942319
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3483883208
Short name T36
Test name
Test status
Simulation time 185563646 ps
CPU time 2.83 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 214264 kb
Host smart-f7226ab2-1fb5-4be1-a12d-03d01b143d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483883208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3483883208
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.613221593
Short name T303
Test name
Test status
Simulation time 51696521 ps
CPU time 3.42 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214332 kb
Host smart-66d1c1c7-776a-4e38-a36d-41b2a062a45b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613221593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.613221593
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3370102321
Short name T252
Test name
Test status
Simulation time 67289581 ps
CPU time 4.67 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 214104 kb
Host smart-f746ad02-69e7-4fe4-b569-860a927c0a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370102321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3370102321
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.182350225
Short name T363
Test name
Test status
Simulation time 148025780 ps
CPU time 3.01 seconds
Started May 30 03:37:57 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 214224 kb
Host smart-09a21853-1bd8-48fe-b8e2-0cd865cb2fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182350225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.182350225
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.4258840644
Short name T83
Test name
Test status
Simulation time 665659361 ps
CPU time 6.22 seconds
Started May 30 03:38:20 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 222512 kb
Host smart-8b1db09e-748a-4fd4-88bb-2551bc56e028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258840644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.4258840644
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.849895375
Short name T41
Test name
Test status
Simulation time 117408170 ps
CPU time 2.25 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 220512 kb
Host smart-ab133761-ae50-4497-b5eb-64694f795b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849895375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.849895375
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3403762287
Short name T367
Test name
Test status
Simulation time 185975994 ps
CPU time 2.84 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:38:35 PM PDT 24
Peak memory 214336 kb
Host smart-65338eb0-c605-490b-b66e-468ead0658cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403762287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3403762287
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1581802253
Short name T323
Test name
Test status
Simulation time 9941235782 ps
CPU time 48.96 seconds
Started May 30 03:38:41 PM PDT 24
Finished May 30 03:39:31 PM PDT 24
Peak memory 218924 kb
Host smart-e6764636-74d8-4efd-9ae1-a847827e80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581802253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1581802253
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_random.1236001701
Short name T218
Test name
Test status
Simulation time 4702292608 ps
CPU time 17.65 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:39:05 PM PDT 24
Peak memory 219700 kb
Host smart-ded150f5-9163-4592-9ee2-fe0e1647cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236001701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1236001701
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3078698533
Short name T1019
Test name
Test status
Simulation time 180425137 ps
CPU time 8.48 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:56 PM PDT 24
Peak memory 205528 kb
Host smart-b7349b9f-81c6-4799-a23d-154ee9aee219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078698533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
078698533
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.483041526
Short name T926
Test name
Test status
Simulation time 441021290 ps
CPU time 12.7 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 205748 kb
Host smart-df07e74f-1c0c-45ee-a456-2c3053ce54a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483041526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.483041526
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1903995837
Short name T176
Test name
Test status
Simulation time 35947067 ps
CPU time 1.52 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 205700 kb
Host smart-04b1ebf0-b0d4-4c9d-8d93-e9e184265421
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903995837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
903995837
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1206436140
Short name T992
Test name
Test status
Simulation time 53942084 ps
CPU time 2.2 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 219132 kb
Host smart-c945dbc2-ad36-4415-b77c-c8fbb99a00f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206436140 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1206436140
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2827201990
Short name T142
Test name
Test status
Simulation time 37606651 ps
CPU time 0.92 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 205500 kb
Host smart-d6da1434-e75a-4f60-a366-d7a9a9997646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827201990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2827201990
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2452641955
Short name T954
Test name
Test status
Simulation time 26386818 ps
CPU time 0.82 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 205392 kb
Host smart-21977697-0ca5-453d-aaa3-9be53e39f779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452641955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2452641955
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1407186442
Short name T1037
Test name
Test status
Simulation time 84773837 ps
CPU time 2.54 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 205688 kb
Host smart-d723671f-3d5d-4719-8935-45e3bf174b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407186442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1407186442
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2267587772
Short name T1056
Test name
Test status
Simulation time 619989705 ps
CPU time 2.86 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 214184 kb
Host smart-ce18953e-f831-47f8-a5d6-6c200ba88e1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267587772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2267587772
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4040332781
Short name T937
Test name
Test status
Simulation time 379985505 ps
CPU time 5.23 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 214300 kb
Host smart-4434fa0d-6a63-4a70-b50f-d760b6737764
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040332781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4040332781
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3963031430
Short name T1043
Test name
Test status
Simulation time 522622584 ps
CPU time 3.58 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 216968 kb
Host smart-894ad729-e337-4a94-9443-2f7d31a3cde0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963031430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3963031430
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2602336813
Short name T1077
Test name
Test status
Simulation time 516944707 ps
CPU time 16.12 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:13:07 PM PDT 24
Peak memory 205512 kb
Host smart-b8612b9e-2323-43b9-b456-e79a993bb9b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602336813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
602336813
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3783410274
Short name T1048
Test name
Test status
Simulation time 1611255899 ps
CPU time 6.39 seconds
Started May 30 02:12:45 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 205624 kb
Host smart-c949ed1a-e23e-44ff-9505-27fa478d69ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783410274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
783410274
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2995869541
Short name T985
Test name
Test status
Simulation time 18940040 ps
CPU time 1.25 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 205760 kb
Host smart-9107122b-14fd-4470-b948-ee84635754cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995869541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
995869541
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.582304631
Short name T963
Test name
Test status
Simulation time 632530698 ps
CPU time 1.47 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 213868 kb
Host smart-0b182a7a-e5c2-445b-bf8b-77acdaee9063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582304631 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.582304631
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4094155574
Short name T1021
Test name
Test status
Simulation time 11839115 ps
CPU time 1.07 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 205640 kb
Host smart-5d761cc9-fb81-4d44-9cd2-af4cafc1389a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094155574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4094155574
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.550607700
Short name T1065
Test name
Test status
Simulation time 22103862 ps
CPU time 0.84 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 205248 kb
Host smart-07d9ed55-117c-429c-8a01-a1fd087ed122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550607700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.550607700
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.338767004
Short name T1044
Test name
Test status
Simulation time 189762146 ps
CPU time 2.17 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 205576 kb
Host smart-a8bc6571-408f-4aff-bd1f-285ceeb8601d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338767004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.338767004
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1220603466
Short name T1008
Test name
Test status
Simulation time 454626125 ps
CPU time 1.77 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 214268 kb
Host smart-26da2bbf-6d87-4f9d-8c7f-38084d0dff7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220603466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1220603466
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4105936629
Short name T971
Test name
Test status
Simulation time 2544102174 ps
CPU time 14.67 seconds
Started May 30 02:12:45 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 214316 kb
Host smart-e2613516-843d-4504-b50d-7fc374db11f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105936629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4105936629
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2204566016
Short name T1081
Test name
Test status
Simulation time 493656710 ps
CPU time 3.48 seconds
Started May 30 02:12:44 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 213824 kb
Host smart-375eadd8-3691-469b-9572-0011cccc3007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204566016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2204566016
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.641496820
Short name T147
Test name
Test status
Simulation time 81022967 ps
CPU time 2.55 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 205744 kb
Host smart-77745c22-6915-481c-b704-668ac73c2ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641496820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
641496820
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2324181341
Short name T944
Test name
Test status
Simulation time 55809477 ps
CPU time 1.59 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 213880 kb
Host smart-3d051dd9-f135-4dcc-bac5-fed2d884a4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324181341 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2324181341
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2033282926
Short name T1024
Test name
Test status
Simulation time 118126865 ps
CPU time 1 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 205448 kb
Host smart-8fa97430-bb25-4ebd-bbe2-96ee66747fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033282926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2033282926
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1640688844
Short name T979
Test name
Test status
Simulation time 33487903 ps
CPU time 0.71 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:12:58 PM PDT 24
Peak memory 205344 kb
Host smart-984defb7-c2a8-481d-a0fe-7cac15a94251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640688844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1640688844
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3979568751
Short name T1050
Test name
Test status
Simulation time 321815731 ps
CPU time 2.33 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 205612 kb
Host smart-e7843a24-b641-4ed8-bc02-cae26b91eca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979568751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3979568751
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3616729704
Short name T119
Test name
Test status
Simulation time 314293602 ps
CPU time 5.35 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:08 PM PDT 24
Peak memory 214404 kb
Host smart-82cd14b3-33af-4aa2-97b1-ffc2a126883e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616729704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3616729704
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3228548300
Short name T1026
Test name
Test status
Simulation time 182792890 ps
CPU time 1.97 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 213896 kb
Host smart-123afa7d-b417-4a23-b73f-333c1d6d8aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228548300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3228548300
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3629263119
Short name T1036
Test name
Test status
Simulation time 35897093 ps
CPU time 1.82 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 214128 kb
Host smart-cd7301bf-0342-4361-903b-c45b9c769516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629263119 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3629263119
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2431362315
Short name T964
Test name
Test status
Simulation time 43564365 ps
CPU time 1.12 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205544 kb
Host smart-49dfc869-1594-4942-93b6-f493caf5b2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431362315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2431362315
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2011822458
Short name T1046
Test name
Test status
Simulation time 37252401 ps
CPU time 0.74 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205376 kb
Host smart-e2e04604-460a-41bc-9a1a-16bc877ba590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011822458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2011822458
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3677871103
Short name T1012
Test name
Test status
Simulation time 107255994 ps
CPU time 3.85 seconds
Started May 30 02:13:44 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205600 kb
Host smart-8143a309-fa6f-4da4-914b-97e058bee4b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677871103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3677871103
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2985664756
Short name T117
Test name
Test status
Simulation time 1480359151 ps
CPU time 2.91 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 214216 kb
Host smart-1eb06507-5077-4ef6-8544-525f6ec89936
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985664756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2985664756
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4015944115
Short name T966
Test name
Test status
Simulation time 383687500 ps
CPU time 6.78 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:57 PM PDT 24
Peak memory 220480 kb
Host smart-869788d3-bfcf-4494-9f02-d122d4014989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015944115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4015944115
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3702989938
Short name T1070
Test name
Test status
Simulation time 38716416 ps
CPU time 2.69 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 213928 kb
Host smart-df36c52c-3e89-4a92-a0b1-a09928fc02fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702989938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3702989938
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.801417729
Short name T387
Test name
Test status
Simulation time 143571420 ps
CPU time 2.92 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 213848 kb
Host smart-b80a4389-c175-4931-81e4-55d2d56c8df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801417729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.801417729
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.503026594
Short name T924
Test name
Test status
Simulation time 19647152 ps
CPU time 1.3 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 213736 kb
Host smart-e62b3578-600d-4389-a729-91dad803ab06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503026594 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.503026594
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1344994786
Short name T152
Test name
Test status
Simulation time 11945467 ps
CPU time 1.06 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205616 kb
Host smart-3a7c95bd-cd4d-4167-b8b0-4703c456bd59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344994786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1344994786
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2847669678
Short name T1022
Test name
Test status
Simulation time 11486574 ps
CPU time 0.72 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 205372 kb
Host smart-bf8ade88-b18b-4070-9319-f93b5f85186d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847669678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2847669678
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.660329927
Short name T1029
Test name
Test status
Simulation time 278665287 ps
CPU time 3.22 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 205548 kb
Host smart-cbbceeba-9563-496b-a207-e750ac96ed48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660329927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.660329927
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2031293607
Short name T967
Test name
Test status
Simulation time 480251377 ps
CPU time 4.78 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 214172 kb
Host smart-32b1b839-2082-4e28-bd60-cfce10c8a1bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031293607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2031293607
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2119223439
Short name T1071
Test name
Test status
Simulation time 153925675 ps
CPU time 6.81 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 214116 kb
Host smart-dca3634a-591c-464a-9e74-ba3e03445a6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119223439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2119223439
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.284603148
Short name T1030
Test name
Test status
Simulation time 103867510 ps
CPU time 1.58 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 213848 kb
Host smart-8f34e2f4-6ee6-49db-a6cc-943370d4649e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284603148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.284603148
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2400209911
Short name T923
Test name
Test status
Simulation time 114625179 ps
CPU time 1.51 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:52 PM PDT 24
Peak memory 213992 kb
Host smart-7d25d31d-6b73-41c4-a2bf-f780864dd5db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400209911 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2400209911
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2062727330
Short name T140
Test name
Test status
Simulation time 24148945 ps
CPU time 1.04 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205736 kb
Host smart-62ee2ed9-26b6-4bbe-a40b-efc549c08a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062727330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2062727330
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2363421672
Short name T1005
Test name
Test status
Simulation time 16348244 ps
CPU time 0.73 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:48 PM PDT 24
Peak memory 205380 kb
Host smart-64c95092-ba1f-4589-b5f6-7a216de50a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363421672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2363421672
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2374256420
Short name T956
Test name
Test status
Simulation time 450513451 ps
CPU time 4.15 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 205680 kb
Host smart-47b3c2fe-d50a-4c9d-ae4d-197116272cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374256420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2374256420
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3713446956
Short name T1028
Test name
Test status
Simulation time 200031782 ps
CPU time 3.22 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 214192 kb
Host smart-97a85cca-5958-4d33-b8d2-4683459c423e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713446956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3713446956
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.135955193
Short name T1004
Test name
Test status
Simulation time 419103336 ps
CPU time 3.82 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 214268 kb
Host smart-d8d55a3f-01a9-414e-aaf7-ebd67bb06dee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135955193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.135955193
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1356953920
Short name T920
Test name
Test status
Simulation time 735773736 ps
CPU time 3.47 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 213992 kb
Host smart-de1d9193-fa6d-45a2-bc11-774946ae2c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356953920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1356953920
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2383714522
Short name T1059
Test name
Test status
Simulation time 51414323 ps
CPU time 1.76 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:52 PM PDT 24
Peak memory 213920 kb
Host smart-a5d65f00-2a84-4c62-8784-8f98a57197e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383714522 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2383714522
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4008040389
Short name T962
Test name
Test status
Simulation time 51625679 ps
CPU time 1.41 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205788 kb
Host smart-d5053c80-28dc-4e88-b335-bb0288b85972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008040389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4008040389
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2054128975
Short name T1001
Test name
Test status
Simulation time 57581201 ps
CPU time 0.72 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205312 kb
Host smart-cc3827d5-8909-4ab4-a166-ef92f71df2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054128975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2054128975
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2006984483
Short name T976
Test name
Test status
Simulation time 317099457 ps
CPU time 1.47 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 205688 kb
Host smart-50dbe778-800e-4d9c-afef-8fb0424fc841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006984483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2006984483
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.770913617
Short name T1053
Test name
Test status
Simulation time 202028668 ps
CPU time 1.42 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 214280 kb
Host smart-667a5fb7-5ec6-42cb-8cec-dbd5a4ec49e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770913617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.770913617
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1691179750
Short name T1068
Test name
Test status
Simulation time 298324020 ps
CPU time 7.23 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 214284 kb
Host smart-703691db-1050-42dd-992b-6600beebf812
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691179750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1691179750
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2889830418
Short name T993
Test name
Test status
Simulation time 72744220 ps
CPU time 3.09 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 213884 kb
Host smart-ecb9c2a2-4af7-4527-a21b-b57508b1c1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889830418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2889830418
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1209607576
Short name T150
Test name
Test status
Simulation time 449056282 ps
CPU time 3.18 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:52 PM PDT 24
Peak memory 213888 kb
Host smart-292f6b3b-333f-460b-b364-e90d30bf9dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209607576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1209607576
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.297856027
Short name T928
Test name
Test status
Simulation time 29948170 ps
CPU time 1.76 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 213904 kb
Host smart-3db7ade8-eb7b-4bff-8020-4c7a0903a432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297856027 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.297856027
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4284518400
Short name T143
Test name
Test status
Simulation time 19015066 ps
CPU time 0.99 seconds
Started May 30 02:13:45 PM PDT 24
Finished May 30 02:13:47 PM PDT 24
Peak memory 205384 kb
Host smart-e22934af-dfa2-4b8b-a79d-45dea3237e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284518400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4284518400
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2014258361
Short name T1078
Test name
Test status
Simulation time 13937236 ps
CPU time 0.88 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 205500 kb
Host smart-7b18048f-5e57-4168-ac52-87185c9c7245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014258361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2014258361
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3863807610
Short name T946
Test name
Test status
Simulation time 379647483 ps
CPU time 3.93 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 205676 kb
Host smart-0dcfd5eb-a2b8-4aed-a2c5-fba2800cfb4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863807610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3863807610
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.539324880
Short name T1009
Test name
Test status
Simulation time 131037003 ps
CPU time 2.52 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 214216 kb
Host smart-8829e1c4-62b8-4711-910c-74f830951bed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539324880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.539324880
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2467469185
Short name T1003
Test name
Test status
Simulation time 1691418697 ps
CPU time 12.17 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 214192 kb
Host smart-35d8580d-e6c6-495d-8d23-9459b3b8d2c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467469185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2467469185
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4092314606
Short name T200
Test name
Test status
Simulation time 140300812 ps
CPU time 3.38 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:52 PM PDT 24
Peak memory 213840 kb
Host smart-ae8ca088-2b7c-40b5-b16e-bae08b6c8821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092314606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4092314606
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2007309859
Short name T157
Test name
Test status
Simulation time 202279321 ps
CPU time 3.21 seconds
Started May 30 02:13:42 PM PDT 24
Finished May 30 02:13:45 PM PDT 24
Peak memory 213928 kb
Host smart-406220c1-136b-4707-a335-4028ce4923d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007309859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2007309859
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1333311859
Short name T1040
Test name
Test status
Simulation time 171188197 ps
CPU time 1.92 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:52 PM PDT 24
Peak memory 213948 kb
Host smart-5cc9bece-ef73-4677-8138-2fb4333039be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333311859 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1333311859
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4177706508
Short name T1007
Test name
Test status
Simulation time 10179731 ps
CPU time 0.87 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 205520 kb
Host smart-c0a4069e-dabc-4d6d-80e9-7e02897c377b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177706508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4177706508
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1518255797
Short name T1052
Test name
Test status
Simulation time 11248748 ps
CPU time 0.77 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 205296 kb
Host smart-5b446b39-9568-4ee8-8415-42490065b264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518255797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1518255797
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4124831277
Short name T1079
Test name
Test status
Simulation time 140903877 ps
CPU time 2.11 seconds
Started May 30 02:13:46 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 205712 kb
Host smart-52073c56-e026-4451-b7b5-77e70214cc8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124831277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4124831277
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3109431848
Short name T969
Test name
Test status
Simulation time 535679519 ps
CPU time 3.86 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:54 PM PDT 24
Peak memory 214252 kb
Host smart-b5d261b1-bf55-437d-a210-b4b93c00709c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109431848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3109431848
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3619383346
Short name T120
Test name
Test status
Simulation time 76913739 ps
CPU time 3.43 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 214168 kb
Host smart-af29cbda-2e09-4109-8156-6148e9c4a7d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619383346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3619383346
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4121387478
Short name T961
Test name
Test status
Simulation time 25666767 ps
CPU time 1.69 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 213984 kb
Host smart-2c173c52-9be4-4cdb-b340-ae21847bc66d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121387478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4121387478
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2743746668
Short name T156
Test name
Test status
Simulation time 252537105 ps
CPU time 2.89 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 205756 kb
Host smart-ca2f3ae7-6ca4-46de-bd4d-cddd238c0f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743746668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2743746668
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3460225237
Short name T950
Test name
Test status
Simulation time 97948668 ps
CPU time 1.59 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 213944 kb
Host smart-8a3f6735-307c-4254-b3b4-668d79f7427e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460225237 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3460225237
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4213274919
Short name T1049
Test name
Test status
Simulation time 31981484 ps
CPU time 1.26 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 205768 kb
Host smart-0e6d4976-2be0-4c8a-98da-8fda1fc00c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213274919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4213274919
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.560149957
Short name T1017
Test name
Test status
Simulation time 11604461 ps
CPU time 0.84 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 205316 kb
Host smart-c47bb781-32a7-400b-8fa7-91a0b37933f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560149957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.560149957
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1022348944
Short name T141
Test name
Test status
Simulation time 92534073 ps
CPU time 2.6 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 205664 kb
Host smart-b15fb6f3-5cb1-49f4-b6a6-96878e40b78f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022348944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1022348944
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2200448784
Short name T990
Test name
Test status
Simulation time 369920225 ps
CPU time 1.8 seconds
Started May 30 02:13:48 PM PDT 24
Finished May 30 02:13:51 PM PDT 24
Peak memory 214232 kb
Host smart-f30dcef8-3b15-454a-a263-02565ec6134f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200448784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2200448784
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.423069441
Short name T1064
Test name
Test status
Simulation time 38039345 ps
CPU time 1.36 seconds
Started May 30 02:13:47 PM PDT 24
Finished May 30 02:13:49 PM PDT 24
Peak memory 213984 kb
Host smart-c6491410-a4d0-42f8-a10d-5a41fdc19b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423069441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.423069441
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4002480461
Short name T166
Test name
Test status
Simulation time 809125932 ps
CPU time 8.4 seconds
Started May 30 02:13:49 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 213900 kb
Host smart-1a71db22-3500-478f-992c-ee307453d888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002480461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4002480461
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1218562254
Short name T947
Test name
Test status
Simulation time 44215869 ps
CPU time 1.06 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205624 kb
Host smart-c1f850c0-dbcb-4c90-a7b5-63b97f256a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218562254 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1218562254
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1866297086
Short name T144
Test name
Test status
Simulation time 20049289 ps
CPU time 1.21 seconds
Started May 30 02:13:54 PM PDT 24
Finished May 30 02:13:56 PM PDT 24
Peak memory 205580 kb
Host smart-fd00b5d1-9ac2-4958-a6dc-17a232e786f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866297086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1866297086
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2978215172
Short name T931
Test name
Test status
Simulation time 20938447 ps
CPU time 0.78 seconds
Started May 30 02:13:59 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205320 kb
Host smart-2e5178da-249c-4538-ae9f-8400f94d760c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978215172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2978215172
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1790531674
Short name T939
Test name
Test status
Simulation time 280353560 ps
CPU time 4.93 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:03 PM PDT 24
Peak memory 205748 kb
Host smart-f713ef29-88cd-46c6-b181-470637b17f17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790531674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1790531674
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3483799560
Short name T986
Test name
Test status
Simulation time 273967953 ps
CPU time 3.33 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 214148 kb
Host smart-5aacb316-c5e1-489c-98de-306e25cd6f18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483799560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3483799560
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2863964559
Short name T948
Test name
Test status
Simulation time 214697495 ps
CPU time 8.85 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:07 PM PDT 24
Peak memory 220192 kb
Host smart-8b449dbe-1171-4f2a-9973-08e83a922943
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863964559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2863964559
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3059453374
Short name T995
Test name
Test status
Simulation time 172317839 ps
CPU time 3.92 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:14:03 PM PDT 24
Peak memory 213800 kb
Host smart-ac694fcd-f079-40df-b6e2-98b972d6f7eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059453374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3059453374
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3376866344
Short name T1038
Test name
Test status
Simulation time 27670954 ps
CPU time 1.04 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205736 kb
Host smart-7278a1e4-c68a-45e4-a0b3-b4a37e56f8f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376866344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3376866344
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.242810843
Short name T980
Test name
Test status
Simulation time 378825059 ps
CPU time 1.14 seconds
Started May 30 02:13:58 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205628 kb
Host smart-08eb5d74-0994-462f-8172-82414b672f50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242810843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.242810843
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2142669463
Short name T918
Test name
Test status
Simulation time 13153308 ps
CPU time 0.71 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205364 kb
Host smart-da496b5c-17f4-49b7-ba02-32d326afceb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142669463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2142669463
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2019597621
Short name T1063
Test name
Test status
Simulation time 109036501 ps
CPU time 2.26 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205672 kb
Host smart-9cb2e70a-0dd0-4644-ad95-144a8d2b09a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019597621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2019597621
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3111906702
Short name T1031
Test name
Test status
Simulation time 78050072 ps
CPU time 1.51 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 214224 kb
Host smart-3f4f0515-23a9-4b79-8f71-5f3c4837cfc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111906702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3111906702
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3099630851
Short name T1073
Test name
Test status
Simulation time 83806870 ps
CPU time 4.75 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:03 PM PDT 24
Peak memory 214228 kb
Host smart-65490e7a-bd81-47a1-893b-7430ec911f5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099630851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3099630851
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1889038052
Short name T1013
Test name
Test status
Simulation time 38951196 ps
CPU time 2.89 seconds
Started May 30 02:13:54 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 213872 kb
Host smart-57b05647-ca1f-422c-ade2-8390567c4155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889038052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1889038052
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2523083781
Short name T162
Test name
Test status
Simulation time 152448506 ps
CPU time 6.17 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:14:04 PM PDT 24
Peak memory 205720 kb
Host smart-4e037d99-42b0-48f1-8e31-9158cba5bdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523083781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2523083781
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2229662367
Short name T943
Test name
Test status
Simulation time 520941482 ps
CPU time 10.59 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 205668 kb
Host smart-13c3b824-dd28-4538-87ff-7029e941ab01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229662367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
229662367
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3402574168
Short name T1074
Test name
Test status
Simulation time 889241932 ps
CPU time 24.86 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:13:13 PM PDT 24
Peak memory 205732 kb
Host smart-0c476de5-c600-43a3-bb0b-8deed3b9196a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402574168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
402574168
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2080503827
Short name T983
Test name
Test status
Simulation time 77934445 ps
CPU time 1.47 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 205652 kb
Host smart-6a97f3d2-367d-422d-bac9-70b48183919e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080503827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
080503827
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3262432775
Short name T975
Test name
Test status
Simulation time 16230435 ps
CPU time 1.25 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 213928 kb
Host smart-0d0ee42c-a172-4c16-bf82-21e727ed4974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262432775 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3262432775
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2449472307
Short name T1035
Test name
Test status
Simulation time 80843240 ps
CPU time 1.15 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 205640 kb
Host smart-8c50c52f-5c04-4ae6-b86f-d4dbff548168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449472307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2449472307
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3752514536
Short name T942
Test name
Test status
Simulation time 18555009 ps
CPU time 0.8 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 205344 kb
Host smart-2006e3e7-0662-4b2a-8ced-e9e1c404f1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752514536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3752514536
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2481599981
Short name T1060
Test name
Test status
Simulation time 112154789 ps
CPU time 1.99 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 205748 kb
Host smart-5c483c27-4fd4-43e6-869e-a5fc68012eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481599981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2481599981
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.550560232
Short name T122
Test name
Test status
Simulation time 88970150 ps
CPU time 1.96 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 214188 kb
Host smart-0a7e1b4f-74da-4aa4-8a8b-6c326a43f757
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550560232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.550560232
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3693579690
Short name T999
Test name
Test status
Simulation time 216060949 ps
CPU time 4.64 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:54 PM PDT 24
Peak memory 214212 kb
Host smart-9198aa6d-bfe6-4f67-a20a-168cc23be924
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693579690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3693579690
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4120186896
Short name T922
Test name
Test status
Simulation time 213853346 ps
CPU time 2.35 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 213912 kb
Host smart-6d5f8ec6-024f-4d7c-87c6-275a5c2a77fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120186896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4120186896
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3604706692
Short name T159
Test name
Test status
Simulation time 194394453 ps
CPU time 3.13 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:12:54 PM PDT 24
Peak memory 213848 kb
Host smart-d5cbee84-cd17-4e45-8bab-672e55ebde02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604706692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3604706692
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2127399642
Short name T960
Test name
Test status
Simulation time 23327932 ps
CPU time 0.71 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205288 kb
Host smart-a37262b7-1d95-499b-bc4a-ca49a37c3cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127399642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2127399642
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4013860326
Short name T989
Test name
Test status
Simulation time 9771025 ps
CPU time 0.72 seconds
Started May 30 02:13:59 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205280 kb
Host smart-55ce7a0e-3dc3-4f75-9ac4-8952d0ea9199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013860326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4013860326
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1473466260
Short name T998
Test name
Test status
Simulation time 95949758 ps
CPU time 0.8 seconds
Started May 30 02:13:58 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 205344 kb
Host smart-24266c67-a0b8-4e7c-a858-77f3e41deafa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473466260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1473466260
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2343421049
Short name T933
Test name
Test status
Simulation time 15173221 ps
CPU time 0.92 seconds
Started May 30 02:13:58 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205568 kb
Host smart-a4f79392-29c3-4888-af80-d1028c100842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343421049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2343421049
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2050500203
Short name T919
Test name
Test status
Simulation time 22743950 ps
CPU time 0.71 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205388 kb
Host smart-6d0ff2ce-556d-4d0c-997c-e21487575d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050500203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2050500203
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2446803026
Short name T938
Test name
Test status
Simulation time 32778471 ps
CPU time 0.87 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 204736 kb
Host smart-d0828f63-70d4-4da9-9cfc-97274298e845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446803026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2446803026
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2589267235
Short name T940
Test name
Test status
Simulation time 44539144 ps
CPU time 0.82 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205296 kb
Host smart-04139288-e02b-436b-b4db-e61ec1fd8d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589267235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2589267235
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2135102217
Short name T996
Test name
Test status
Simulation time 13246033 ps
CPU time 0.88 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205384 kb
Host smart-7d054b86-1d60-4da3-ab32-6ef5bbe23fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135102217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2135102217
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3747579810
Short name T982
Test name
Test status
Simulation time 38710395 ps
CPU time 0.74 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 204764 kb
Host smart-b1605eb4-e0be-4d87-818c-f723c3f4c5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747579810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3747579810
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4113571597
Short name T1023
Test name
Test status
Simulation time 14006849 ps
CPU time 0.89 seconds
Started May 30 02:13:58 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 205388 kb
Host smart-8e5f199c-3eec-4890-84ff-3f4c80f4967d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113571597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4113571597
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3626755954
Short name T146
Test name
Test status
Simulation time 543335543 ps
CPU time 14.04 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 205740 kb
Host smart-8706f5bf-755e-4bae-9054-6649e9ae6170
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626755954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
626755954
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3388253149
Short name T952
Test name
Test status
Simulation time 5116009824 ps
CPU time 30.25 seconds
Started May 30 02:12:52 PM PDT 24
Finished May 30 02:13:24 PM PDT 24
Peak memory 205668 kb
Host smart-54078687-2b14-4715-a2c6-ea31f3d3ba60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388253149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
388253149
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2873394392
Short name T968
Test name
Test status
Simulation time 49870302 ps
CPU time 1 seconds
Started May 30 02:12:52 PM PDT 24
Finished May 30 02:12:54 PM PDT 24
Peak memory 205656 kb
Host smart-a0b501ac-db9a-4511-b27e-891dc31c5836
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873394392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
873394392
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1621069882
Short name T1010
Test name
Test status
Simulation time 29140709 ps
CPU time 1.2 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 205656 kb
Host smart-f7546781-3799-4121-a508-ce1752cbe661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621069882 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1621069882
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1170824135
Short name T1027
Test name
Test status
Simulation time 11654345 ps
CPU time 0.91 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 205520 kb
Host smart-0978f2ea-62bc-4c58-a2df-3aecb53497ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170824135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1170824135
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4159877210
Short name T1072
Test name
Test status
Simulation time 11940515 ps
CPU time 0.71 seconds
Started May 30 02:12:52 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 205272 kb
Host smart-ee725612-065a-402d-a8e0-de7d2d6a9d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159877210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4159877210
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2606642886
Short name T987
Test name
Test status
Simulation time 34512720 ps
CPU time 1.96 seconds
Started May 30 02:12:52 PM PDT 24
Finished May 30 02:12:55 PM PDT 24
Peak memory 205652 kb
Host smart-984f0d92-5362-48a9-af80-8da9a37a1301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606642886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2606642886
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3382961049
Short name T974
Test name
Test status
Simulation time 71527049 ps
CPU time 2.11 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 214136 kb
Host smart-ea0b3de9-9bdd-47b1-bb3e-31445f66380e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382961049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3382961049
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3577378816
Short name T116
Test name
Test status
Simulation time 186956895 ps
CPU time 3.51 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 214260 kb
Host smart-afb67577-f987-477c-8473-820475f48aeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577378816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3577378816
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2559028985
Short name T1057
Test name
Test status
Simulation time 367276457 ps
CPU time 2.76 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 213892 kb
Host smart-cee12820-7520-4171-be6c-402522f767cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559028985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2559028985
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.139255931
Short name T161
Test name
Test status
Simulation time 695508918 ps
CPU time 5.69 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 213752 kb
Host smart-934e33a6-30de-480c-9d28-02cbf0f41381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139255931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
139255931
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4069585260
Short name T1061
Test name
Test status
Simulation time 43097057 ps
CPU time 0.82 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205348 kb
Host smart-b4c9727e-917b-44e0-ba30-2cb09247c972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069585260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4069585260
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1739644642
Short name T1014
Test name
Test status
Simulation time 31315861 ps
CPU time 0.72 seconds
Started May 30 02:13:59 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205312 kb
Host smart-1bfe7220-d1b6-409a-827b-ed37a06ade77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739644642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1739644642
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1220217304
Short name T1041
Test name
Test status
Simulation time 39520988 ps
CPU time 0.7 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205216 kb
Host smart-eb22cbf7-0e35-49e6-aa2c-a098e7e7125b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220217304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1220217304
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3380816118
Short name T949
Test name
Test status
Simulation time 12890771 ps
CPU time 0.86 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205216 kb
Host smart-d940ac5a-fc99-412f-8bb2-14218b947146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380816118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3380816118
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2706753009
Short name T951
Test name
Test status
Simulation time 10825611 ps
CPU time 0.73 seconds
Started May 30 02:13:59 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205388 kb
Host smart-c95084d8-1fd3-4b3b-8b6f-f1a083ab224d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706753009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2706753009
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2929148277
Short name T984
Test name
Test status
Simulation time 50710384 ps
CPU time 0.72 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205368 kb
Host smart-18f46893-2808-4ac3-84ea-8ef9df582f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929148277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2929148277
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.845542513
Short name T1062
Test name
Test status
Simulation time 130886049 ps
CPU time 0.68 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205376 kb
Host smart-f6b5ff6d-a014-4a86-9956-fac86514ab1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845542513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.845542513
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4251935036
Short name T1016
Test name
Test status
Simulation time 51863836 ps
CPU time 0.81 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 205292 kb
Host smart-b02c5393-5bfc-4c79-8d40-670835147052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251935036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4251935036
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4234924998
Short name T925
Test name
Test status
Simulation time 8736112 ps
CPU time 0.74 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205344 kb
Host smart-b997933d-b4d4-4fa7-bce9-67f409689f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234924998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4234924998
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4212883183
Short name T1020
Test name
Test status
Simulation time 27159175 ps
CPU time 0.86 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205424 kb
Host smart-6fc7f561-3da4-4a5b-b7f5-2c1f09479445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212883183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.4212883183
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3457157179
Short name T1039
Test name
Test status
Simulation time 2153846390 ps
CPU time 18.22 seconds
Started May 30 02:12:56 PM PDT 24
Finished May 30 02:13:16 PM PDT 24
Peak memory 205684 kb
Host smart-e0141e94-1c7c-4686-89d7-5f560e6d38d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457157179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
457157179
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3029884905
Short name T1075
Test name
Test status
Simulation time 1126716381 ps
CPU time 15.01 seconds
Started May 30 02:13:02 PM PDT 24
Finished May 30 02:13:18 PM PDT 24
Peak memory 205712 kb
Host smart-1bb76655-e760-4318-b91e-46774b13cfb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029884905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
029884905
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2482833395
Short name T185
Test name
Test status
Simulation time 19182199 ps
CPU time 1.12 seconds
Started May 30 02:13:06 PM PDT 24
Finished May 30 02:13:08 PM PDT 24
Peak memory 205604 kb
Host smart-6acc3c53-98eb-4ed4-9fd1-d5b91582108e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482833395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
482833395
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3289632311
Short name T991
Test name
Test status
Simulation time 90196606 ps
CPU time 1.53 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 214032 kb
Host smart-7e251510-9e36-4c3c-8a5d-a368107f814a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289632311 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3289632311
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2266102739
Short name T1032
Test name
Test status
Simulation time 28699307 ps
CPU time 1.44 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 205644 kb
Host smart-842154f2-89a3-4ed8-a3b4-6f731e3b768d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266102739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2266102739
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1144722124
Short name T973
Test name
Test status
Simulation time 179880302 ps
CPU time 0.71 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 205292 kb
Host smart-0b46916b-ffe1-4339-81b0-179ca1f1d842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144722124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1144722124
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.122758952
Short name T977
Test name
Test status
Simulation time 148554592 ps
CPU time 3.78 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 205664 kb
Host smart-585ac224-8199-45bc-ad35-5074964022e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122758952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.122758952
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2046596974
Short name T1067
Test name
Test status
Simulation time 109205972 ps
CPU time 3.42 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:06 PM PDT 24
Peak memory 214156 kb
Host smart-3709dfe0-7354-4a34-908c-511abfea1a94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046596974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2046596974
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.390136001
Short name T934
Test name
Test status
Simulation time 109252352 ps
CPU time 1.86 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 213920 kb
Host smart-1f7ab8cd-308c-4863-9d2c-c558bcad1078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390136001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.390136001
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3015619487
Short name T930
Test name
Test status
Simulation time 20117120 ps
CPU time 0.77 seconds
Started May 30 02:13:34 PM PDT 24
Finished May 30 02:13:35 PM PDT 24
Peak memory 205376 kb
Host smart-5cc969a6-7a36-485a-883c-c9fc28c1ce3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015619487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3015619487
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3036101517
Short name T927
Test name
Test status
Simulation time 27166388 ps
CPU time 0.88 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:57 PM PDT 24
Peak memory 205452 kb
Host smart-b7bbd8f0-a352-43eb-bcf6-02fbeeab220b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036101517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3036101517
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2516856434
Short name T1055
Test name
Test status
Simulation time 54265071 ps
CPU time 0.89 seconds
Started May 30 02:13:53 PM PDT 24
Finished May 30 02:13:55 PM PDT 24
Peak memory 205300 kb
Host smart-aaa945c6-8b54-4171-adba-fc0188a1bd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516856434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2516856434
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.873756086
Short name T981
Test name
Test status
Simulation time 14330400 ps
CPU time 0.75 seconds
Started May 30 02:13:58 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 205392 kb
Host smart-ce7fc53c-e05b-47dc-80cd-298b7ed63937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873756086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.873756086
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1488819805
Short name T1066
Test name
Test status
Simulation time 9142122 ps
CPU time 0.83 seconds
Started May 30 02:13:56 PM PDT 24
Finished May 30 02:13:58 PM PDT 24
Peak memory 205348 kb
Host smart-f0b404a9-eecb-4d96-a0c2-cc3a60d9e75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488819805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1488819805
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3338203138
Short name T1025
Test name
Test status
Simulation time 14323841 ps
CPU time 0.85 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:13:59 PM PDT 24
Peak memory 205288 kb
Host smart-9a6b7d35-0b9b-469e-8bf4-51f8f556c892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338203138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3338203138
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.659162703
Short name T932
Test name
Test status
Simulation time 10341347 ps
CPU time 0.7 seconds
Started May 30 02:13:57 PM PDT 24
Finished May 30 02:14:00 PM PDT 24
Peak memory 205220 kb
Host smart-969616d7-2662-41d6-ad30-cf13eb31e5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659162703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.659162703
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3481341366
Short name T1006
Test name
Test status
Simulation time 14136230 ps
CPU time 0.73 seconds
Started May 30 02:13:59 PM PDT 24
Finished May 30 02:14:01 PM PDT 24
Peak memory 205388 kb
Host smart-6f1a9063-8799-4b38-b1b4-cde8794b06bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481341366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3481341366
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1433053980
Short name T941
Test name
Test status
Simulation time 10374164 ps
CPU time 0.74 seconds
Started May 30 02:14:05 PM PDT 24
Finished May 30 02:14:06 PM PDT 24
Peak memory 205384 kb
Host smart-01e6dde4-7cab-4a9d-8304-ff535dfbf929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433053980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1433053980
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3731931331
Short name T959
Test name
Test status
Simulation time 42040504 ps
CPU time 0.8 seconds
Started May 30 02:14:01 PM PDT 24
Finished May 30 02:14:02 PM PDT 24
Peak memory 205384 kb
Host smart-9cd13ca2-4d31-4bf6-8323-404c4640047d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731931331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3731931331
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3836979315
Short name T391
Test name
Test status
Simulation time 70442727 ps
CPU time 1.39 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 213972 kb
Host smart-0ab052c8-c469-466c-8a8f-f42f711f7611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836979315 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3836979315
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3623522846
Short name T935
Test name
Test status
Simulation time 13691187 ps
CPU time 1.11 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 205640 kb
Host smart-520a6702-5934-4bb4-8e07-90207716a18b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623522846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3623522846
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3800292296
Short name T957
Test name
Test status
Simulation time 8848894 ps
CPU time 0.73 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:12:59 PM PDT 24
Peak memory 205368 kb
Host smart-e8db90af-8320-4197-a0c3-0fa2e2e8eeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800292296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3800292296
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2530211406
Short name T958
Test name
Test status
Simulation time 74430079 ps
CPU time 2.2 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 205700 kb
Host smart-4cb7db73-2a68-43f5-8cde-b783113bba54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530211406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2530211406
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1240814464
Short name T997
Test name
Test status
Simulation time 362665983 ps
CPU time 2.16 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 214324 kb
Host smart-dd65f851-237a-401a-8fc5-387a13cc5fa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240814464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1240814464
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1323000909
Short name T112
Test name
Test status
Simulation time 303215927 ps
CPU time 3.61 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 219808 kb
Host smart-484ff89d-7692-45a4-a7e4-968d76777835
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323000909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1323000909
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1759390280
Short name T1051
Test name
Test status
Simulation time 119904050 ps
CPU time 4.61 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 213848 kb
Host smart-32e30d47-9448-491e-8436-c8ca051706e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759390280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1759390280
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1694160280
Short name T988
Test name
Test status
Simulation time 182150286 ps
CPU time 1.75 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 213984 kb
Host smart-81214c57-e5d6-43db-af97-30cf10372633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694160280 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1694160280
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1763648727
Short name T1018
Test name
Test status
Simulation time 194447441 ps
CPU time 1.2 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 205624 kb
Host smart-b220a0e3-efd8-4132-9b29-8b741312301e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763648727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1763648727
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3580449493
Short name T921
Test name
Test status
Simulation time 32818024 ps
CPU time 0.71 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 205312 kb
Host smart-fadf850f-df26-42b6-93c2-d8cf8515a519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580449493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3580449493
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1297594993
Short name T994
Test name
Test status
Simulation time 545455506 ps
CPU time 2.9 seconds
Started May 30 02:13:02 PM PDT 24
Finished May 30 02:13:06 PM PDT 24
Peak memory 205784 kb
Host smart-e5e5cd14-7aed-48d5-aa8d-135e1759217e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297594993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1297594993
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.339008729
Short name T1015
Test name
Test status
Simulation time 500350020 ps
CPU time 4.23 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 214196 kb
Host smart-a6c5e1a6-a755-4ab9-bfe1-c95006065671
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339008729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.339008729
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2281040794
Short name T1045
Test name
Test status
Simulation time 1672980948 ps
CPU time 6.52 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:08 PM PDT 24
Peak memory 214240 kb
Host smart-abdc0500-7c9c-47b9-b5e9-bfee45ed5da4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281040794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2281040794
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.339663610
Short name T1042
Test name
Test status
Simulation time 1237986084 ps
CPU time 3.41 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 217016 kb
Host smart-deb83768-dead-4149-aefa-c7633b4cf8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339663610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.339663610
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2650017520
Short name T1076
Test name
Test status
Simulation time 208568958 ps
CPU time 2.68 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 205728 kb
Host smart-c96dff94-9f6a-4a73-9aa3-cfd3e110d95c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650017520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2650017520
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2167370932
Short name T978
Test name
Test status
Simulation time 48471064 ps
CPU time 2.08 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 213852 kb
Host smart-267353f0-4fd8-4aaf-9e71-41f713da7f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167370932 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2167370932
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1005727905
Short name T936
Test name
Test status
Simulation time 53507126 ps
CPU time 0.94 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:12:59 PM PDT 24
Peak memory 205428 kb
Host smart-3fd748ce-5d91-41e1-9f56-0868d75f0701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005727905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1005727905
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2897240001
Short name T970
Test name
Test status
Simulation time 13509345 ps
CPU time 0.85 seconds
Started May 30 02:13:03 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 205372 kb
Host smart-55e77a21-8a60-4dc7-83b9-becbfaa4fe7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897240001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2897240001
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3736388826
Short name T1000
Test name
Test status
Simulation time 343842000 ps
CPU time 1.92 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 205708 kb
Host smart-0a16b6c9-8eb9-40d6-b5c7-58090d29ca37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736388826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3736388826
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3182988083
Short name T115
Test name
Test status
Simulation time 728340836 ps
CPU time 2.97 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 214216 kb
Host smart-57ba9f65-357f-4566-a091-80785274ebad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182988083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3182988083
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3524878990
Short name T118
Test name
Test status
Simulation time 1547542796 ps
CPU time 8.56 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:10 PM PDT 24
Peak memory 214212 kb
Host smart-f51ea37a-e13e-4c51-b6a4-569045720969
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524878990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3524878990
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1158784483
Short name T175
Test name
Test status
Simulation time 401101544 ps
CPU time 2.65 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 216992 kb
Host smart-5f2307c4-088c-4a37-b860-b00360dd21d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158784483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1158784483
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4117278463
Short name T965
Test name
Test status
Simulation time 291041121 ps
CPU time 3.52 seconds
Started May 30 02:12:57 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 213892 kb
Host smart-d63b617e-fc6e-4091-8158-d4201d5cb3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117278463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4117278463
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2373619192
Short name T955
Test name
Test status
Simulation time 181080565 ps
CPU time 1.71 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 213948 kb
Host smart-b1711bbd-6c01-4654-8497-d108b1936679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373619192 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2373619192
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.900837516
Short name T1011
Test name
Test status
Simulation time 19622720 ps
CPU time 0.98 seconds
Started May 30 02:13:06 PM PDT 24
Finished May 30 02:13:07 PM PDT 24
Peak memory 205428 kb
Host smart-e2d7853d-e310-4edc-870a-80b1efc84c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900837516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.900837516
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2682137545
Short name T1054
Test name
Test status
Simulation time 49023064 ps
CPU time 0.86 seconds
Started May 30 02:13:02 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 205328 kb
Host smart-8b9d7d81-86dd-4c34-89b3-df66b83e161f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682137545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2682137545
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2738481618
Short name T953
Test name
Test status
Simulation time 259357870 ps
CPU time 1.39 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 205656 kb
Host smart-4ce2d616-2c00-4444-a645-12f04e9a347a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738481618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2738481618
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2007204719
Short name T972
Test name
Test status
Simulation time 105554556 ps
CPU time 2.65 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 214284 kb
Host smart-b4b1626d-9ffd-47a6-a1c7-fd8f29383241
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007204719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2007204719
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1345731004
Short name T1002
Test name
Test status
Simulation time 373783289 ps
CPU time 3.67 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:06 PM PDT 24
Peak memory 220224 kb
Host smart-d9025721-b283-4a40-b2ab-8ab5a62be594
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345731004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1345731004
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1114435184
Short name T929
Test name
Test status
Simulation time 255591827 ps
CPU time 3.54 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:04 PM PDT 24
Peak memory 213888 kb
Host smart-bcd396e5-ef6f-4000-92de-b0cd2518e3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114435184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1114435184
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.347252203
Short name T1033
Test name
Test status
Simulation time 29920929 ps
CPU time 2.08 seconds
Started May 30 02:13:06 PM PDT 24
Finished May 30 02:13:08 PM PDT 24
Peak memory 213940 kb
Host smart-65404080-d0e2-4193-a0bb-551f83b538f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347252203 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.347252203
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2578039787
Short name T1058
Test name
Test status
Simulation time 101578394 ps
CPU time 1.19 seconds
Started May 30 02:13:00 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 205692 kb
Host smart-5ad32640-a9f7-48dd-94a8-2652d988caea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578039787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2578039787
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1893392302
Short name T1080
Test name
Test status
Simulation time 13804037 ps
CPU time 0.71 seconds
Started May 30 02:13:06 PM PDT 24
Finished May 30 02:13:07 PM PDT 24
Peak memory 205372 kb
Host smart-7b542693-7c3a-4aee-9647-f0ce76595679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893392302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1893392302
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1488789146
Short name T945
Test name
Test status
Simulation time 31933196 ps
CPU time 2 seconds
Started May 30 02:12:58 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 205612 kb
Host smart-7669b404-6d04-4d58-8316-680a044a3688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488789146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1488789146
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1935089044
Short name T1034
Test name
Test status
Simulation time 291944748 ps
CPU time 2.22 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:05 PM PDT 24
Peak memory 214360 kb
Host smart-50f60c7a-cab9-4045-8db6-bc9200ff752c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935089044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1935089044
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4156390551
Short name T1047
Test name
Test status
Simulation time 83318959 ps
CPU time 4.86 seconds
Started May 30 02:13:01 PM PDT 24
Finished May 30 02:13:07 PM PDT 24
Peak memory 220120 kb
Host smart-5755cca8-5bb9-40bb-beb6-86e1ee4d94d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156390551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4156390551
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2475208584
Short name T1069
Test name
Test status
Simulation time 27602281 ps
CPU time 1.79 seconds
Started May 30 02:12:59 PM PDT 24
Finished May 30 02:13:03 PM PDT 24
Peak memory 215324 kb
Host smart-8a64bceb-a699-425a-875d-2f6b2c5bccd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475208584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2475208584
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1340113006
Short name T153
Test name
Test status
Simulation time 1560277029 ps
CPU time 10.67 seconds
Started May 30 02:13:05 PM PDT 24
Finished May 30 02:13:16 PM PDT 24
Peak memory 213804 kb
Host smart-12e9725d-2aa2-4826-869b-eecf7222579c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340113006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1340113006
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4264488895
Short name T809
Test name
Test status
Simulation time 11635420 ps
CPU time 0.75 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:15 PM PDT 24
Peak memory 205920 kb
Host smart-180c6e90-7fff-4116-8186-eed4accaeb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264488895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4264488895
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.179840736
Short name T409
Test name
Test status
Simulation time 593598086 ps
CPU time 12.57 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:31 PM PDT 24
Peak memory 214380 kb
Host smart-498feaac-a59a-46c6-946d-5060ed94d3fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179840736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.179840736
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1621328259
Short name T78
Test name
Test status
Simulation time 1975548497 ps
CPU time 14.94 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 218472 kb
Host smart-e9f54ba0-3570-41aa-9a7a-0b84e5497e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621328259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1621328259
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.425958448
Short name T538
Test name
Test status
Simulation time 28372087 ps
CPU time 1.58 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:19 PM PDT 24
Peak memory 206192 kb
Host smart-7b169f91-66b5-42db-8879-b0675a7c944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425958448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.425958448
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2257874021
Short name T355
Test name
Test status
Simulation time 680004556 ps
CPU time 8.7 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:24 PM PDT 24
Peak memory 208768 kb
Host smart-ee0a906e-0018-43b1-8aaa-349d49daed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257874021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2257874021
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3164131999
Short name T10
Test name
Test status
Simulation time 247773553 ps
CPU time 5.54 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 237464 kb
Host smart-d6bd7116-9c1a-47d2-8a48-933cfd2a73c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164131999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3164131999
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2987404039
Short name T734
Test name
Test status
Simulation time 93176798 ps
CPU time 2.92 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:20 PM PDT 24
Peak memory 208620 kb
Host smart-6aaa3ef6-abb0-4842-b058-b544714614f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987404039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2987404039
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4216519259
Short name T752
Test name
Test status
Simulation time 2677141847 ps
CPU time 22.41 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:40 PM PDT 24
Peak memory 209072 kb
Host smart-7fc66e29-f593-410f-b1e8-8aea5659ba56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216519259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4216519259
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.444080694
Short name T480
Test name
Test status
Simulation time 244181597 ps
CPU time 2.91 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 206892 kb
Host smart-0990f120-305d-4ac7-a9df-2c60029f7762
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444080694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.444080694
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.926244020
Short name T789
Test name
Test status
Simulation time 257733308 ps
CPU time 3.08 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 218328 kb
Host smart-407bb9e7-cd65-4f4e-93c3-b991164c64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926244020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.926244020
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3626074236
Short name T179
Test name
Test status
Simulation time 108189335 ps
CPU time 2.52 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:19 PM PDT 24
Peak memory 208672 kb
Host smart-5b8f70f6-2b59-4e2c-807d-6d0bb29291ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626074236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3626074236
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1947247964
Short name T128
Test name
Test status
Simulation time 2447519922 ps
CPU time 10.69 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:27 PM PDT 24
Peak memory 222644 kb
Host smart-456f831f-5873-49a7-8e0d-48649413f8d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947247964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1947247964
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3599833302
Short name T863
Test name
Test status
Simulation time 157513703 ps
CPU time 6.82 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 210024 kb
Host smart-51d6a678-f2ef-40d7-835f-feeba32f5885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599833302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3599833302
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3624030386
Short name T645
Test name
Test status
Simulation time 10667507 ps
CPU time 0.82 seconds
Started May 30 03:36:17 PM PDT 24
Finished May 30 03:36:20 PM PDT 24
Peak memory 205980 kb
Host smart-a6ee1919-b83f-4ea7-b59a-0f35f77c85dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624030386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3624030386
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3717198075
Short name T44
Test name
Test status
Simulation time 46183363 ps
CPU time 2.96 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:24 PM PDT 24
Peak memory 221132 kb
Host smart-7f4f7d5d-bc6d-4d12-9bf2-0285fa7475c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717198075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3717198075
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1742159543
Short name T345
Test name
Test status
Simulation time 1067668920 ps
CPU time 14.39 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 214284 kb
Host smart-5aed6c6b-f541-42cf-972e-1fbdd18cb34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742159543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1742159543
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1184277097
Short name T620
Test name
Test status
Simulation time 37162699 ps
CPU time 2.61 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 222436 kb
Host smart-bc453d85-39a2-473c-a29b-81f2a3daa17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184277097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1184277097
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.544767803
Short name T665
Test name
Test status
Simulation time 165635287 ps
CPU time 3.52 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 208688 kb
Host smart-5058204d-1c89-4f34-9201-7f6332f547d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544767803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.544767803
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.724524350
Short name T668
Test name
Test status
Simulation time 555545288 ps
CPU time 4.82 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:23 PM PDT 24
Peak memory 207600 kb
Host smart-2b10ee6f-63a1-40d9-a943-da5b77ae8abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724524350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.724524350
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2708784241
Short name T804
Test name
Test status
Simulation time 162794773 ps
CPU time 3.07 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:20 PM PDT 24
Peak memory 206872 kb
Host smart-ead3cb66-55a5-4117-8cc4-1da4f8d93588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708784241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2708784241
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2145671797
Short name T353
Test name
Test status
Simulation time 82656991 ps
CPU time 2.86 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206964 kb
Host smart-ed618243-a295-44fe-9bab-3249652d99ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145671797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2145671797
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.144969051
Short name T312
Test name
Test status
Simulation time 227969631 ps
CPU time 3.01 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 208620 kb
Host smart-6068b981-447d-4c22-8dfd-0f94f7367303
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144969051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.144969051
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3151016414
Short name T468
Test name
Test status
Simulation time 46028362 ps
CPU time 2.65 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:23 PM PDT 24
Peak memory 208604 kb
Host smart-63c9e92f-dcab-42a0-861a-dc697dbd4eb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151016414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3151016414
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3501201249
Short name T618
Test name
Test status
Simulation time 414954897 ps
CPU time 3.85 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 218320 kb
Host smart-6e57ed60-ab37-4167-81e0-f33f9c5fa678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501201249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3501201249
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1143155218
Short name T426
Test name
Test status
Simulation time 38671912 ps
CPU time 2.31 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:19 PM PDT 24
Peak memory 208384 kb
Host smart-059f5c2b-cfb7-4caf-8f99-5f6231a6727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143155218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1143155218
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1508740342
Short name T835
Test name
Test status
Simulation time 704568142 ps
CPU time 4.47 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 209972 kb
Host smart-ec0c3340-5889-45cb-b980-1dbd7222cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508740342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1508740342
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4105469139
Short name T867
Test name
Test status
Simulation time 140707225 ps
CPU time 2.66 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 209772 kb
Host smart-0a915d79-6e1a-4b81-9d6e-334e57a17914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105469139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4105469139
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1500400680
Short name T741
Test name
Test status
Simulation time 43743984 ps
CPU time 0.76 seconds
Started May 30 03:37:04 PM PDT 24
Finished May 30 03:37:07 PM PDT 24
Peak memory 205972 kb
Host smart-2daef0d7-64f3-4571-a495-aded614a73d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500400680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1500400680
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.232750550
Short name T419
Test name
Test status
Simulation time 94586115 ps
CPU time 5.35 seconds
Started May 30 03:36:43 PM PDT 24
Finished May 30 03:36:50 PM PDT 24
Peak memory 222468 kb
Host smart-bc4961c9-0ef0-4a35-85f5-65b801b26f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232750550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.232750550
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1414586329
Short name T834
Test name
Test status
Simulation time 1198761505 ps
CPU time 13.07 seconds
Started May 30 03:36:42 PM PDT 24
Finished May 30 03:36:56 PM PDT 24
Peak memory 218544 kb
Host smart-5c1fb763-207b-49a1-9ba5-e9ed9c97a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414586329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1414586329
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.932533115
Short name T530
Test name
Test status
Simulation time 167611072 ps
CPU time 2.93 seconds
Started May 30 03:36:42 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 209212 kb
Host smart-ab17a998-f79b-459c-a44b-33f43ad9bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932533115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.932533115
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.740863180
Short name T101
Test name
Test status
Simulation time 208955236 ps
CPU time 3.55 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 209032 kb
Host smart-264d2cb8-db1d-4d93-a057-b06765609a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740863180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.740863180
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3665383172
Short name T283
Test name
Test status
Simulation time 110021009 ps
CPU time 1.96 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 214264 kb
Host smart-3e6a3a31-ac21-49e1-b24c-3f83b05fedc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665383172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3665383172
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.229710139
Short name T541
Test name
Test status
Simulation time 683965231 ps
CPU time 5.32 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 220536 kb
Host smart-16787e4a-ef6a-4898-ae74-0262c9bcdb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229710139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.229710139
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.952398725
Short name T766
Test name
Test status
Simulation time 1113871533 ps
CPU time 6.85 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 207192 kb
Host smart-70093799-1d24-47d5-a621-f2a753b8b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952398725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.952398725
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2192047467
Short name T648
Test name
Test status
Simulation time 291066252 ps
CPU time 7.75 seconds
Started May 30 03:36:37 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 208132 kb
Host smart-fb2ecd32-c699-47b7-9310-7a1c97fdd64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192047467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2192047467
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3921989961
Short name T555
Test name
Test status
Simulation time 109932436 ps
CPU time 3.7 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:39 PM PDT 24
Peak memory 208748 kb
Host smart-dd0ae102-d1c9-4bba-a84e-5d68d82fe36b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921989961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3921989961
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4211326441
Short name T849
Test name
Test status
Simulation time 460852855 ps
CPU time 3.52 seconds
Started May 30 03:36:42 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 208000 kb
Host smart-22f08869-9bf2-47b1-9b71-60dd1435746f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211326441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4211326441
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.557326505
Short name T791
Test name
Test status
Simulation time 25515593 ps
CPU time 1.95 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 208664 kb
Host smart-372da4ed-c447-40f5-b355-baa7b8f81187
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557326505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.557326505
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.542452651
Short name T714
Test name
Test status
Simulation time 156701492 ps
CPU time 2.29 seconds
Started May 30 03:37:09 PM PDT 24
Finished May 30 03:37:13 PM PDT 24
Peak memory 207248 kb
Host smart-410c4dc0-1271-4790-a6d1-17312d0cd7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542452651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.542452651
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1908454748
Short name T461
Test name
Test status
Simulation time 362454476 ps
CPU time 2.92 seconds
Started May 30 03:36:43 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 207116 kb
Host smart-c3eabb98-f627-4757-9692-790161456e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908454748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1908454748
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3277142468
Short name T615
Test name
Test status
Simulation time 831393842 ps
CPU time 6.12 seconds
Started May 30 03:36:42 PM PDT 24
Finished May 30 03:36:50 PM PDT 24
Peak memory 206884 kb
Host smart-e1019ef0-bad7-4fc5-a4c7-32b7136ee8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277142468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3277142468
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1153233108
Short name T488
Test name
Test status
Simulation time 69867586 ps
CPU time 0.88 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:18 PM PDT 24
Peak memory 205924 kb
Host smart-1af6a17a-2fd8-4b5e-b624-825ad46f35ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153233108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1153233108
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3444971241
Short name T71
Test name
Test status
Simulation time 221299614 ps
CPU time 3.23 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 208680 kb
Host smart-900f2e5f-8ceb-42e8-a947-12ac50712450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444971241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3444971241
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3690269958
Short name T91
Test name
Test status
Simulation time 120683314 ps
CPU time 2.45 seconds
Started May 30 03:37:14 PM PDT 24
Finished May 30 03:37:17 PM PDT 24
Peak memory 208112 kb
Host smart-71f80194-b7c6-4dca-8717-904ab4044bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690269958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3690269958
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.332374478
Short name T755
Test name
Test status
Simulation time 4247295522 ps
CPU time 37.58 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:57 PM PDT 24
Peak memory 214420 kb
Host smart-680345bf-812a-431b-a906-7167f293fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332374478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.332374478
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2759942392
Short name T289
Test name
Test status
Simulation time 232220886 ps
CPU time 2.85 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:21 PM PDT 24
Peak memory 216908 kb
Host smart-2d6ab0ea-8683-40d5-8933-76a86776af88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759942392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2759942392
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1601176041
Short name T564
Test name
Test status
Simulation time 2193048618 ps
CPU time 7.25 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 215384 kb
Host smart-10a5850b-47e8-45d9-a329-3c5481936b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601176041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1601176041
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.368754247
Short name T605
Test name
Test status
Simulation time 66127611 ps
CPU time 4.19 seconds
Started May 30 03:37:11 PM PDT 24
Finished May 30 03:37:16 PM PDT 24
Peak memory 214364 kb
Host smart-b66481e3-2d29-4e15-a143-d0071b5fa05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368754247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.368754247
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2263667092
Short name T872
Test name
Test status
Simulation time 249656298 ps
CPU time 5.5 seconds
Started May 30 03:37:04 PM PDT 24
Finished May 30 03:37:12 PM PDT 24
Peak memory 208500 kb
Host smart-44d7961f-8159-425a-a9aa-63b698277f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263667092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2263667092
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3416215401
Short name T798
Test name
Test status
Simulation time 38893474 ps
CPU time 2.83 seconds
Started May 30 03:37:13 PM PDT 24
Finished May 30 03:37:17 PM PDT 24
Peak memory 208988 kb
Host smart-5ee64d19-1607-4753-938e-60dedb64e4d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416215401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3416215401
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3849015976
Short name T546
Test name
Test status
Simulation time 5345180178 ps
CPU time 21.81 seconds
Started May 30 03:37:07 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 208996 kb
Host smart-3c0aa748-2b9b-4fdc-9421-be9f3ac038dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849015976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3849015976
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.833001940
Short name T501
Test name
Test status
Simulation time 73417408 ps
CPU time 2.92 seconds
Started May 30 03:37:09 PM PDT 24
Finished May 30 03:37:14 PM PDT 24
Peak memory 207536 kb
Host smart-6be7a56e-a366-4794-9393-8f3078661584
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833001940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.833001940
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3690727966
Short name T253
Test name
Test status
Simulation time 120231342 ps
CPU time 3.26 seconds
Started May 30 03:37:14 PM PDT 24
Finished May 30 03:37:19 PM PDT 24
Peak memory 209800 kb
Host smart-bcb44f5b-14c5-476f-ae2b-4f326c0645a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690727966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3690727966
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3048204736
Short name T505
Test name
Test status
Simulation time 738994920 ps
CPU time 4.68 seconds
Started May 30 03:37:06 PM PDT 24
Finished May 30 03:37:13 PM PDT 24
Peak memory 208380 kb
Host smart-2ab48af2-667c-459d-bdf6-f796ed99bab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048204736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3048204736
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2301721740
Short name T299
Test name
Test status
Simulation time 681784232 ps
CPU time 19.56 seconds
Started May 30 03:37:14 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 222568 kb
Host smart-3f2fbccd-75ed-4904-8eed-35b87e10ac3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301721740 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2301721740
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2725346225
Short name T639
Test name
Test status
Simulation time 596156521 ps
CPU time 5.42 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 208180 kb
Host smart-89b16000-98ce-448a-b125-685ee0360b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725346225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2725346225
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2634694466
Short name T773
Test name
Test status
Simulation time 14444027 ps
CPU time 0.78 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:20 PM PDT 24
Peak memory 205652 kb
Host smart-349a356e-515a-4825-bb86-27f396deef60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634694466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2634694466
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3199210027
Short name T339
Test name
Test status
Simulation time 264359848 ps
CPU time 4.3 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 215172 kb
Host smart-a903ce2c-1ae0-4d1e-ab02-27e91c0fc58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199210027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3199210027
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1302083905
Short name T282
Test name
Test status
Simulation time 222180787 ps
CPU time 5.95 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 218396 kb
Host smart-bdb31a61-ce0f-49d1-a0aa-8800ab6c43eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302083905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1302083905
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1467504358
Short name T654
Test name
Test status
Simulation time 280353972 ps
CPU time 2.98 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 214376 kb
Host smart-77951375-7a49-47f1-91d6-28bdc3ea6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467504358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1467504358
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.264780295
Short name T58
Test name
Test status
Simulation time 47001908 ps
CPU time 2.8 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:21 PM PDT 24
Peak memory 214300 kb
Host smart-b4ed49f2-d1f6-4141-92e5-0dd82832e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264780295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.264780295
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.674622302
Short name T239
Test name
Test status
Simulation time 258199647 ps
CPU time 3.25 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 222508 kb
Host smart-49aaacac-9263-4def-ad02-fc2cbc12f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674622302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.674622302
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.443096931
Short name T412
Test name
Test status
Simulation time 1139854305 ps
CPU time 8.28 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 208980 kb
Host smart-57f13133-fe28-4caf-b484-0e7c072d881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443096931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.443096931
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.232348765
Short name T703
Test name
Test status
Simulation time 147864373 ps
CPU time 2.74 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:20 PM PDT 24
Peak memory 208636 kb
Host smart-eed652ba-2476-470e-b132-bf479e582ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232348765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.232348765
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.144670797
Short name T592
Test name
Test status
Simulation time 341957294 ps
CPU time 3.13 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 206748 kb
Host smart-fa776d8a-418d-4f29-b8b2-169a76beae6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144670797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.144670797
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.695123443
Short name T689
Test name
Test status
Simulation time 37555321 ps
CPU time 2.44 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 206688 kb
Host smart-2e41f723-40e0-4433-9d30-691539985668
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695123443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.695123443
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2198258007
Short name T706
Test name
Test status
Simulation time 82238473 ps
CPU time 2.03 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:19 PM PDT 24
Peak memory 215508 kb
Host smart-dc78c099-7b5f-4052-9722-28f88e52fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198258007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2198258007
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1496015710
Short name T887
Test name
Test status
Simulation time 25925338 ps
CPU time 1.67 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:19 PM PDT 24
Peak memory 206868 kb
Host smart-8a60b7e7-40b8-4ec0-823c-dd43b92e3d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496015710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1496015710
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.441645256
Short name T782
Test name
Test status
Simulation time 579215218 ps
CPU time 5.4 seconds
Started May 30 03:37:14 PM PDT 24
Finished May 30 03:37:21 PM PDT 24
Peak memory 210192 kb
Host smart-6c4a43ef-765a-461d-bc17-f044fd2f5260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441645256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.441645256
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1907247986
Short name T617
Test name
Test status
Simulation time 10313165 ps
CPU time 0.87 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:23 PM PDT 24
Peak memory 205980 kb
Host smart-2938c59a-687a-4444-b9a6-83d994914197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907247986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1907247986
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3669867811
Short name T137
Test name
Test status
Simulation time 458799414 ps
CPU time 10.76 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 214392 kb
Host smart-5f749a16-1035-40ab-8c66-b9d802280eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669867811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3669867811
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1640593965
Short name T28
Test name
Test status
Simulation time 147888935 ps
CPU time 2.81 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 218444 kb
Host smart-a3eb7fbc-ae9d-4a52-81d5-125ea0bbbf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640593965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1640593965
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4066151540
Short name T288
Test name
Test status
Simulation time 61057529 ps
CPU time 3.24 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 214432 kb
Host smart-5277d1b2-f177-42b2-9f2f-fb849b3752f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066151540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4066151540
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3426500492
Short name T264
Test name
Test status
Simulation time 98901049 ps
CPU time 4.32 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 214216 kb
Host smart-d16306c7-a9a6-4ef7-8acf-ad811fa52ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426500492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3426500492
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1462285480
Short name T50
Test name
Test status
Simulation time 475845300 ps
CPU time 3.67 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 219776 kb
Host smart-a0897a36-6bec-4b32-be5a-4321a6b5049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462285480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1462285480
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1734311918
Short name T557
Test name
Test status
Simulation time 619887495 ps
CPU time 5.24 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 209752 kb
Host smart-da4439ef-01cc-4d66-988a-53fd1419b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734311918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1734311918
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3054823673
Short name T347
Test name
Test status
Simulation time 987620470 ps
CPU time 6.02 seconds
Started May 30 03:37:15 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 208980 kb
Host smart-a17f6986-54e2-4b38-99f5-c87f34d72c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054823673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3054823673
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3178685554
Short name T447
Test name
Test status
Simulation time 45458468 ps
CPU time 2.25 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:21 PM PDT 24
Peak memory 208800 kb
Host smart-49c1307b-a873-42fd-a301-0566865a653b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178685554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3178685554
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4253088236
Short name T579
Test name
Test status
Simulation time 61396711 ps
CPU time 2.41 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:22 PM PDT 24
Peak memory 206976 kb
Host smart-2a5d2597-e809-40df-be16-996a6d22a9b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253088236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4253088236
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1659305132
Short name T458
Test name
Test status
Simulation time 89385219 ps
CPU time 4.03 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:23 PM PDT 24
Peak memory 208712 kb
Host smart-7ce24cb5-aa97-454a-8702-93957de8b4a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659305132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1659305132
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3792943913
Short name T352
Test name
Test status
Simulation time 38940994 ps
CPU time 1.92 seconds
Started May 30 03:37:25 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 207908 kb
Host smart-cd5e7c39-8b77-4906-b52a-fdde80d51e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792943913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3792943913
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2860738530
Short name T881
Test name
Test status
Simulation time 3036832030 ps
CPU time 29.12 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 208048 kb
Host smart-47640e0c-7546-4e04-b9f6-f21f286a8be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860738530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2860738530
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1442691675
Short name T895
Test name
Test status
Simulation time 1445534747 ps
CPU time 18.02 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:40 PM PDT 24
Peak memory 216568 kb
Host smart-792c0fcc-d681-429d-8136-3d535727da8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442691675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1442691675
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3223063722
Short name T255
Test name
Test status
Simulation time 226918922 ps
CPU time 8.52 seconds
Started May 30 03:37:16 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 207420 kb
Host smart-5675bcce-df1c-4abf-9cff-3a70d2cb9889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223063722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3223063722
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.948355601
Short name T669
Test name
Test status
Simulation time 11498733 ps
CPU time 0.72 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:23 PM PDT 24
Peak memory 205956 kb
Host smart-3a576da7-d536-431a-aae5-44235803cb68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948355601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.948355601
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1811464092
Short name T370
Test name
Test status
Simulation time 117289385 ps
CPU time 4.22 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:31 PM PDT 24
Peak memory 214324 kb
Host smart-47e83e1a-d8a7-4554-b712-60731a6da14d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811464092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1811464092
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2486476692
Short name T273
Test name
Test status
Simulation time 89904777 ps
CPU time 3.01 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:31 PM PDT 24
Peak memory 208916 kb
Host smart-cd29468e-058b-49c6-82e7-7af33ee6c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486476692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2486476692
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.24081249
Short name T21
Test name
Test status
Simulation time 185906274 ps
CPU time 6.89 seconds
Started May 30 03:37:17 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 221576 kb
Host smart-56ac04b7-9e60-48e8-9e35-e647dbaa1bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24081249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.24081249
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.649214650
Short name T240
Test name
Test status
Simulation time 334333912 ps
CPU time 3.86 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:29 PM PDT 24
Peak memory 222500 kb
Host smart-4d5d5963-35f8-4032-aac2-e2a6985c7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649214650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.649214650
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2821074827
Short name T317
Test name
Test status
Simulation time 970326978 ps
CPU time 6.95 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 214324 kb
Host smart-26fcfdda-7a6d-4344-ac9c-77ff5a2c3717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821074827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2821074827
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3043222272
Short name T604
Test name
Test status
Simulation time 28054136 ps
CPU time 2.08 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:29 PM PDT 24
Peak memory 208448 kb
Host smart-ec5c2aad-d858-4c74-9309-35fadef41632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043222272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3043222272
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2129124779
Short name T844
Test name
Test status
Simulation time 123300240 ps
CPU time 3.97 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 208568 kb
Host smart-263bed92-6d14-4b32-b818-a76107ec39dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129124779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2129124779
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1517439816
Short name T542
Test name
Test status
Simulation time 953076725 ps
CPU time 3.23 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 206820 kb
Host smart-ec7712df-a05e-4dcf-bb3e-84bc07600c6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517439816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1517439816
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1705356693
Short name T800
Test name
Test status
Simulation time 728853248 ps
CPU time 6.53 seconds
Started May 30 03:37:18 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 208052 kb
Host smart-ca05c53a-0bde-4c10-8510-ff3e8abfcf05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705356693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1705356693
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.720919227
Short name T545
Test name
Test status
Simulation time 4217073960 ps
CPU time 13.62 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 216496 kb
Host smart-0c9b0215-7466-4340-9c55-3404df6687fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720919227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.720919227
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.221085002
Short name T866
Test name
Test status
Simulation time 72712283 ps
CPU time 1.79 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:23 PM PDT 24
Peak memory 206824 kb
Host smart-c316b42a-a839-43e3-8d3d-0abf11be70e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221085002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.221085002
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3547599918
Short name T223
Test name
Test status
Simulation time 6490447716 ps
CPU time 30.06 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:52 PM PDT 24
Peak memory 222592 kb
Host smart-517e63b4-043c-4000-821a-164210889233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547599918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3547599918
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.164253294
Short name T880
Test name
Test status
Simulation time 786554988 ps
CPU time 5.49 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 218452 kb
Host smart-6b2ef2e4-d29c-4635-9447-97e1e969a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164253294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.164253294
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3537062680
Short name T633
Test name
Test status
Simulation time 33561640 ps
CPU time 1.34 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 208552 kb
Host smart-c18426a9-feba-4618-9e63-e9ee8f19f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537062680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3537062680
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.383841946
Short name T769
Test name
Test status
Simulation time 48809624 ps
CPU time 0.88 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 205960 kb
Host smart-51808107-ca0f-44a6-8bfd-e3ee94eefe4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383841946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.383841946
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2701116406
Short name T832
Test name
Test status
Simulation time 2379992048 ps
CPU time 4.54 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 207788 kb
Host smart-ed99c554-f9e6-43a5-8714-b1ea5e756e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701116406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2701116406
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3760891800
Short name T398
Test name
Test status
Simulation time 43359808 ps
CPU time 3.14 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 214408 kb
Host smart-b27d3996-4b1e-4462-bdd8-4a4f90a2de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760891800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3760891800
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.265332529
Short name T286
Test name
Test status
Simulation time 51267478 ps
CPU time 2.24 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 214268 kb
Host smart-ff5188e7-c5b9-443b-bcbc-c17d2a9e4c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265332529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.265332529
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4248792523
Short name T479
Test name
Test status
Simulation time 35037693 ps
CPU time 2.24 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 214460 kb
Host smart-e0a45e7d-48a2-48d7-b2bd-7651b1706e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248792523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4248792523
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1078742751
Short name T131
Test name
Test status
Simulation time 132400171 ps
CPU time 2.69 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 208172 kb
Host smart-c65f2739-7e3d-48c9-ada1-2ec14f763545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078742751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1078742751
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2114997648
Short name T841
Test name
Test status
Simulation time 306156490 ps
CPU time 3.27 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:31 PM PDT 24
Peak memory 208252 kb
Host smart-72664f0c-431a-47cf-9afb-cedb9e7225fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114997648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2114997648
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1549044323
Short name T729
Test name
Test status
Simulation time 216883354 ps
CPU time 2.27 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 206896 kb
Host smart-9cc1643c-5de4-4600-9d88-380f796bd740
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549044323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1549044323
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1458107508
Short name T432
Test name
Test status
Simulation time 330068178 ps
CPU time 2.66 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 206948 kb
Host smart-c6bde280-4387-4f56-be62-6523efc706c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458107508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1458107508
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2854622912
Short name T311
Test name
Test status
Simulation time 155534629 ps
CPU time 3.35 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 208844 kb
Host smart-11541319-ff98-46d0-9677-cf72e9bb97c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854622912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2854622912
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.4137769771
Short name T652
Test name
Test status
Simulation time 22786012 ps
CPU time 1.89 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 208180 kb
Host smart-16b14be2-2660-46b4-80cb-45973deb3484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137769771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.4137769771
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.761044105
Short name T198
Test name
Test status
Simulation time 262191152 ps
CPU time 3.91 seconds
Started May 30 03:37:19 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 207792 kb
Host smart-07f24f14-456e-4544-95d3-1affee667ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761044105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.761044105
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1170434730
Short name T905
Test name
Test status
Simulation time 2032765008 ps
CPU time 13.76 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 220196 kb
Host smart-cf1f66d7-4fbf-4e24-a974-87d6bc6b6dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170434730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1170434730
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2561850463
Short name T202
Test name
Test status
Simulation time 1891508129 ps
CPU time 13.84 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 219676 kb
Host smart-8d170a7c-5585-4ecd-93a0-36fda45cac2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561850463 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2561850463
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3127359750
Short name T891
Test name
Test status
Simulation time 1797823240 ps
CPU time 40.91 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:38:05 PM PDT 24
Peak memory 214296 kb
Host smart-e701b655-ee58-4cbd-bc6f-4a3ac11892f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127359750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3127359750
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3152661673
Short name T525
Test name
Test status
Simulation time 14909797 ps
CPU time 0.8 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 205960 kb
Host smart-f921c246-3ce8-4c7c-b1d6-b34da2502e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152661673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3152661673
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.612028600
Short name T208
Test name
Test status
Simulation time 52101613 ps
CPU time 3.56 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 215680 kb
Host smart-0b7628cd-bb0b-4374-aa9e-075008728b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612028600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.612028600
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3135274817
Short name T736
Test name
Test status
Simulation time 194025486 ps
CPU time 3.49 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 220460 kb
Host smart-ff4b9158-b5d4-4b99-b9aa-7c77d71db1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135274817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3135274817
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2830821427
Short name T177
Test name
Test status
Simulation time 1323050986 ps
CPU time 3.96 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 214368 kb
Host smart-f21f055d-7c01-450e-8ea4-f86cb775f007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830821427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2830821427
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2503307034
Short name T61
Test name
Test status
Simulation time 198839747 ps
CPU time 2.54 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:25 PM PDT 24
Peak memory 214308 kb
Host smart-2eeef035-a663-4586-b191-b42174d322d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503307034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2503307034
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.582262827
Short name T533
Test name
Test status
Simulation time 1638486794 ps
CPU time 31.87 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:58 PM PDT 24
Peak memory 208232 kb
Host smart-dcc7fc51-5aa1-4f8a-8e13-d76d446b8e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582262827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.582262827
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2627965878
Short name T649
Test name
Test status
Simulation time 121825272 ps
CPU time 1.94 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:24 PM PDT 24
Peak memory 207448 kb
Host smart-ef0f8043-25a4-4ac0-b81c-eb04ab09b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627965878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2627965878
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3936107444
Short name T371
Test name
Test status
Simulation time 221544075 ps
CPU time 3.94 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 208328 kb
Host smart-96ef65f6-5e47-44b8-a8f8-d2a8faa2debc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936107444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3936107444
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3665542441
Short name T626
Test name
Test status
Simulation time 79469285 ps
CPU time 2.75 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 207380 kb
Host smart-6560f882-c2a8-4526-b5b9-63aa609b15e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665542441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3665542441
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2870920589
Short name T768
Test name
Test status
Simulation time 98082949 ps
CPU time 4.36 seconds
Started May 30 03:37:20 PM PDT 24
Finished May 30 03:37:27 PM PDT 24
Peak memory 209180 kb
Host smart-253b0b3d-97b9-46e5-889a-0f5f65588c1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870920589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2870920589
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3714909937
Short name T569
Test name
Test status
Simulation time 1256781543 ps
CPU time 13.7 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 209264 kb
Host smart-40c11c37-6e36-447c-8993-bcccfb6511cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714909937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3714909937
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3273283443
Short name T699
Test name
Test status
Simulation time 190148105 ps
CPU time 2.68 seconds
Started May 30 03:37:21 PM PDT 24
Finished May 30 03:37:26 PM PDT 24
Peak memory 206852 kb
Host smart-f55f5344-9ee2-4bf4-9e92-8904ed9f33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273283443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3273283443
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2645712328
Short name T189
Test name
Test status
Simulation time 21962481208 ps
CPU time 153.31 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 222632 kb
Host smart-2e7f41e0-820f-4ad4-9d2f-afd6e1b8ec49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645712328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2645712328
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.454148214
Short name T640
Test name
Test status
Simulation time 141879907 ps
CPU time 4.14 seconds
Started May 30 03:37:22 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 218228 kb
Host smart-2d174549-7810-4529-a647-4ad42060e3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454148214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.454148214
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3339557906
Short name T126
Test name
Test status
Simulation time 62218335 ps
CPU time 1.83 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:28 PM PDT 24
Peak memory 209876 kb
Host smart-3c349e53-91a5-4a87-a89f-6e080bbc60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339557906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3339557906
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3862167909
Short name T884
Test name
Test status
Simulation time 17571377 ps
CPU time 0.79 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 205964 kb
Host smart-17ff8dc9-a400-4bc4-8636-1e7c3731fd0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862167909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3862167909
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.717779666
Short name T475
Test name
Test status
Simulation time 195558508 ps
CPU time 2.45 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 216984 kb
Host smart-5a507498-68ed-4b18-8139-4f13aa6c8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717779666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.717779666
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1853052884
Short name T80
Test name
Test status
Simulation time 811866222 ps
CPU time 12.24 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 208240 kb
Host smart-f4936aec-9d97-4226-b475-d8376ed390ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853052884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1853052884
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2330811232
Short name T249
Test name
Test status
Simulation time 2439909277 ps
CPU time 25.9 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:57 PM PDT 24
Peak memory 220180 kb
Host smart-813acc9a-988c-4d25-9a33-a5ea6ba39ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330811232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2330811232
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3975818843
Short name T217
Test name
Test status
Simulation time 257918406 ps
CPU time 5.74 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 222400 kb
Host smart-156c4628-bfb6-4376-848f-d3da49587ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975818843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3975818843
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3136150482
Short name T635
Test name
Test status
Simulation time 91576797 ps
CPU time 4.08 seconds
Started May 30 03:37:25 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 210176 kb
Host smart-e6bdfd25-4fe8-4912-a3d7-1bdcd7bbbd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136150482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3136150482
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3410260563
Short name T520
Test name
Test status
Simulation time 259645092 ps
CPU time 6.84 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214412 kb
Host smart-c88729f2-c103-4524-9057-80e05b73d13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410260563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3410260563
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1549101568
Short name T771
Test name
Test status
Simulation time 27027995 ps
CPU time 1.85 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 206848 kb
Host smart-05682db9-464b-4d9b-9673-473e4509d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549101568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1549101568
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1672598342
Short name T446
Test name
Test status
Simulation time 121858742 ps
CPU time 2.46 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 206940 kb
Host smart-6c0fa353-fbe8-483d-9c4d-e6e3ee29fa89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672598342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1672598342
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2087315371
Short name T787
Test name
Test status
Simulation time 210686573 ps
CPU time 2.66 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 206968 kb
Host smart-3a8914ef-a352-4de4-9800-eea1a9d1fb00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087315371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2087315371
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2238175390
Short name T206
Test name
Test status
Simulation time 203632520 ps
CPU time 2.97 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:33 PM PDT 24
Peak memory 206900 kb
Host smart-40ab756c-2c9b-427d-92b7-aaba0faa2506
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238175390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2238175390
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3646330318
Short name T528
Test name
Test status
Simulation time 49288185 ps
CPU time 2.63 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:29 PM PDT 24
Peak memory 207592 kb
Host smart-cc0b0642-7427-4409-a8e1-cee535a854a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646330318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3646330318
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3538926111
Short name T393
Test name
Test status
Simulation time 126283065 ps
CPU time 3.08 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 208172 kb
Host smart-ed46c63b-ef13-42f1-bff2-5fe0828ad58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538926111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3538926111
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1419241008
Short name T219
Test name
Test status
Simulation time 210305417 ps
CPU time 5.89 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 207764 kb
Host smart-afd0c16f-70bb-4d09-81dc-8a568af91290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419241008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1419241008
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1864936636
Short name T899
Test name
Test status
Simulation time 1934233798 ps
CPU time 9.37 seconds
Started May 30 03:37:23 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 210876 kb
Host smart-f6f9b8ea-7984-4bda-a66b-6f13a1f755f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864936636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1864936636
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1811150198
Short name T676
Test name
Test status
Simulation time 15454845 ps
CPU time 0.74 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 205936 kb
Host smart-a126e492-f73d-4131-b04e-33aaa03676c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811150198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1811150198
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1530483765
Short name T25
Test name
Test status
Simulation time 136316534 ps
CPU time 2.33 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 216240 kb
Host smart-743b63ae-9d97-414e-90b3-8487d9ec53f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530483765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1530483765
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1491113574
Short name T742
Test name
Test status
Simulation time 555277200 ps
CPU time 6.1 seconds
Started May 30 03:37:25 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 208652 kb
Host smart-0e2940e5-5886-444b-9bef-666bce4be1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491113574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1491113574
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3597534918
Short name T250
Test name
Test status
Simulation time 797712353 ps
CPU time 6.28 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 214328 kb
Host smart-f146a4fd-7c6c-4674-83b6-9e67734830ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597534918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3597534918
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4234482721
Short name T679
Test name
Test status
Simulation time 66211714 ps
CPU time 3.43 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214256 kb
Host smart-cb81cbcc-96fd-4e0a-8c19-1d3b18e13afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234482721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4234482721
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1559801555
Short name T233
Test name
Test status
Simulation time 235177129 ps
CPU time 3.4 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 215748 kb
Host smart-4bb1fe43-59fd-4272-9c00-5edebba0b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559801555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1559801555
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1126125167
Short name T294
Test name
Test status
Simulation time 105929634 ps
CPU time 3.97 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 209796 kb
Host smart-4f028c26-aa8a-400f-944b-fc5c65a33101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126125167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1126125167
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3878955233
Short name T193
Test name
Test status
Simulation time 193973665 ps
CPU time 2.53 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 206796 kb
Host smart-8a307145-d94e-455a-bae5-66f9c149270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878955233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3878955233
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3301539585
Short name T322
Test name
Test status
Simulation time 1021609737 ps
CPU time 3.38 seconds
Started May 30 03:37:24 PM PDT 24
Finished May 30 03:37:30 PM PDT 24
Peak memory 208636 kb
Host smart-777c1782-e70d-4219-887a-e00ff33d1d27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301539585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3301539585
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.819716308
Short name T222
Test name
Test status
Simulation time 301727659 ps
CPU time 4.98 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 208508 kb
Host smart-9202d288-4c6d-44d2-8513-36c4e637dd4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819716308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.819716308
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.538318206
Short name T3
Test name
Test status
Simulation time 108580525 ps
CPU time 3.09 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 206896 kb
Host smart-da434673-a5b1-48f8-a322-fec6dab677ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538318206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.538318206
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1043076408
Short name T882
Test name
Test status
Simulation time 272877660 ps
CPU time 3.96 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 208808 kb
Host smart-1c0d5b5c-9ec3-4bd2-bcd4-5117d218b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043076408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1043076408
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1076987943
Short name T861
Test name
Test status
Simulation time 120624127 ps
CPU time 3.31 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:33 PM PDT 24
Peak memory 208884 kb
Host smart-6dac8c24-bae2-424a-a52f-cc8494849889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076987943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1076987943
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3902768043
Short name T333
Test name
Test status
Simulation time 4271559728 ps
CPU time 40.29 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:38:10 PM PDT 24
Peak memory 214536 kb
Host smart-8e18b61a-a988-44e2-a248-d8e80b5f8373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902768043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3902768043
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.446560980
Short name T67
Test name
Test status
Simulation time 330774009 ps
CPU time 3.6 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 210340 kb
Host smart-2d8ead9b-95a4-41ef-ad3a-0602fc386984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446560980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.446560980
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.229741011
Short name T473
Test name
Test status
Simulation time 73188243 ps
CPU time 0.84 seconds
Started May 30 03:37:29 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 205940 kb
Host smart-beb36b33-621f-4531-964e-3833cb3a377c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229741011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.229741011
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.664275713
Short name T305
Test name
Test status
Simulation time 92145588 ps
CPU time 2.53 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 210672 kb
Host smart-8202d94f-44cf-40b7-8065-9524807c4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664275713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.664275713
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1700147243
Short name T307
Test name
Test status
Simulation time 35861314 ps
CPU time 2.4 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214328 kb
Host smart-fee34651-8d38-483d-ae33-2a2c171b9a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700147243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1700147243
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1629063313
Short name T585
Test name
Test status
Simulation time 412370575 ps
CPU time 2.49 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 222408 kb
Host smart-335376b1-0ba6-4d80-8792-29b6f7a1a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629063313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1629063313
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1066976249
Short name T595
Test name
Test status
Simulation time 269137212 ps
CPU time 2.95 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214304 kb
Host smart-afb7d047-bbac-412f-8c82-c121fd6488c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066976249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1066976249
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2700019314
Short name T265
Test name
Test status
Simulation time 152827362 ps
CPU time 2.72 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 218268 kb
Host smart-70eb70c3-5382-4849-acb9-cc14dde6d284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700019314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2700019314
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.548519716
Short name T586
Test name
Test status
Simulation time 6677936178 ps
CPU time 57.82 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 208124 kb
Host smart-f190834a-5b23-44f0-8fbe-15aa73cdc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548519716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.548519716
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2295483644
Short name T436
Test name
Test status
Simulation time 96477889 ps
CPU time 4.04 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 208684 kb
Host smart-0fdabd97-7912-4a1b-a760-05b72d69b47d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295483644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2295483644
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.360552240
Short name T738
Test name
Test status
Simulation time 64984710 ps
CPU time 2.45 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 206780 kb
Host smart-5e4709a1-e1b7-4300-bddb-e1c5efe5b8f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360552240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.360552240
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.239196065
Short name T817
Test name
Test status
Simulation time 213250547 ps
CPU time 2.6 seconds
Started May 30 03:37:26 PM PDT 24
Finished May 30 03:37:32 PM PDT 24
Peak memory 208852 kb
Host smart-8016ac1d-cdff-488a-a91e-187c26328c24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239196065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.239196065
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2742439492
Short name T593
Test name
Test status
Simulation time 361707070 ps
CPU time 2.77 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 209920 kb
Host smart-24e833bd-8382-4ae8-9ea8-c7eac4ef2767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742439492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2742439492
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.472538170
Short name T687
Test name
Test status
Simulation time 101381525 ps
CPU time 3.04 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 208200 kb
Host smart-cdac8564-ca86-4142-8fd9-d59be825ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472538170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.472538170
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1973806838
Short name T572
Test name
Test status
Simulation time 66459775 ps
CPU time 3.91 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 209488 kb
Host smart-9a85c292-b0f8-41ee-98d7-c4f45b535c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973806838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1973806838
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.894662258
Short name T790
Test name
Test status
Simulation time 310445034 ps
CPU time 10.33 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 210724 kb
Host smart-bdbb1a28-9113-4368-be7a-e6da509b29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894662258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.894662258
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3701756130
Short name T234
Test name
Test status
Simulation time 222552437 ps
CPU time 3.25 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 218144 kb
Host smart-d8f33216-4f73-4f5f-85cd-d33b4b803809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701756130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3701756130
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3334742558
Short name T642
Test name
Test status
Simulation time 664146997 ps
CPU time 2.95 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:27 PM PDT 24
Peak memory 210488 kb
Host smart-51e709f2-a8f4-4696-ad32-035fb805200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334742558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3334742558
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1921376351
Short name T381
Test name
Test status
Simulation time 287089974 ps
CPU time 6.77 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 222464 kb
Host smart-5368b01a-e45d-4945-9fd6-85ade7268b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921376351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1921376351
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3838269768
Short name T803
Test name
Test status
Simulation time 167189039 ps
CPU time 2.59 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 215460 kb
Host smart-1e7f5bd1-792d-436d-b8cd-b9104c288fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838269768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3838269768
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.901651666
Short name T499
Test name
Test status
Simulation time 793524614 ps
CPU time 4.01 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 209712 kb
Host smart-eded5d64-c923-4d76-8a82-4aa5d6a64b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901651666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.901651666
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.655806396
Short name T48
Test name
Test status
Simulation time 795731160 ps
CPU time 10.13 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:33 PM PDT 24
Peak memory 237576 kb
Host smart-0a4d8760-9b0f-4ba4-8baf-b3043c3595cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655806396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.655806396
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.711188875
Short name T89
Test name
Test status
Simulation time 97236839 ps
CPU time 1.91 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:23 PM PDT 24
Peak memory 206896 kb
Host smart-ce145e9e-a57d-40db-bd22-dcf29e5aae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711188875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.711188875
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2732704671
Short name T199
Test name
Test status
Simulation time 132059685 ps
CPU time 4.37 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:27 PM PDT 24
Peak memory 206968 kb
Host smart-6fad7604-40f4-4206-a43a-9e2aeb1c2af1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732704671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2732704671
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2974461362
Short name T429
Test name
Test status
Simulation time 160265797 ps
CPU time 5.54 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 208448 kb
Host smart-d734d6e4-0193-4fa7-83e0-3b4590fb075a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974461362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2974461362
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3509726580
Short name T531
Test name
Test status
Simulation time 184245166 ps
CPU time 2.64 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 206872 kb
Host smart-6d54a9d5-f97b-4864-a209-ca4457b45521
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509726580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3509726580
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2608387822
Short name T536
Test name
Test status
Simulation time 139253572 ps
CPU time 2.73 seconds
Started May 30 03:36:22 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 208816 kb
Host smart-bfa45077-008f-459b-9af9-f1cd3f94aa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608387822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2608387822
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3932283300
Short name T757
Test name
Test status
Simulation time 3732928440 ps
CPU time 15.89 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 207788 kb
Host smart-e898f284-ec4d-47e8-86ce-ce0ddffb574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932283300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3932283300
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2000462694
Short name T722
Test name
Test status
Simulation time 266908085 ps
CPU time 13.29 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 216120 kb
Host smart-0062e37a-f423-4e1a-9d4c-71f89e001c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000462694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2000462694
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.31855111
Short name T785
Test name
Test status
Simulation time 205363163 ps
CPU time 8.41 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 219416 kb
Host smart-50e0de15-ab0e-448b-b994-120571a9cc0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31855111 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.31855111
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.332328801
Short name T329
Test name
Test status
Simulation time 101811886 ps
CPU time 4.46 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:27 PM PDT 24
Peak memory 214528 kb
Host smart-283dc0f6-ad96-4efc-86a5-c402e3db2169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332328801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.332328801
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.973428369
Short name T892
Test name
Test status
Simulation time 54374552 ps
CPU time 3.3 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 210232 kb
Host smart-6244c012-0741-440c-8a78-a65ba40a6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973428369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.973428369
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1914932942
Short name T680
Test name
Test status
Simulation time 15036063 ps
CPU time 0.85 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 205960 kb
Host smart-7707d059-a368-4584-8baf-596bd9a1b954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914932942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1914932942
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3228387051
Short name T728
Test name
Test status
Simulation time 45988963 ps
CPU time 2.85 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214584 kb
Host smart-598d1cc9-1cc5-42d0-8e32-0f5fd3284516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228387051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3228387051
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2203413810
Short name T319
Test name
Test status
Simulation time 498165615 ps
CPU time 2.74 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 208284 kb
Host smart-ea051d60-fe07-4841-bd26-10d1f3dc78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203413810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2203413810
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2349227148
Short name T346
Test name
Test status
Simulation time 63127801 ps
CPU time 3.27 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214332 kb
Host smart-fd9a9a4a-926c-49e7-a5e0-0417f855e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349227148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2349227148
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3656024617
Short name T92
Test name
Test status
Simulation time 139693290 ps
CPU time 2.99 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 214244 kb
Host smart-1db9b88b-f2de-4846-81a5-d58acd8a4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656024617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3656024617
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1606568075
Short name T514
Test name
Test status
Simulation time 320358394 ps
CPU time 3.24 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 209760 kb
Host smart-a0d87fbf-0b87-4b51-ac74-7faac096c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606568075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1606568075
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1312558037
Short name T690
Test name
Test status
Simulation time 164796653 ps
CPU time 5.96 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:41 PM PDT 24
Peak memory 218456 kb
Host smart-867c3a6b-0943-402d-a60f-936a96a4b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312558037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1312558037
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.744062627
Short name T483
Test name
Test status
Simulation time 423844983 ps
CPU time 2.96 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:40 PM PDT 24
Peak memory 206700 kb
Host smart-ae0a9c02-d9f5-4829-9b00-8a6e36753cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744062627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.744062627
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2710549386
Short name T878
Test name
Test status
Simulation time 31816690 ps
CPU time 2.41 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 208888 kb
Host smart-8c5dffb0-02e0-4832-b73f-7f1e197e537f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710549386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2710549386
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3816619445
Short name T655
Test name
Test status
Simulation time 128265198 ps
CPU time 4.82 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 206932 kb
Host smart-33112156-1556-45b4-ba68-b66c2e86fa97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816619445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3816619445
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4222841685
Short name T911
Test name
Test status
Simulation time 99670157 ps
CPU time 3.49 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 208896 kb
Host smart-3546c664-e9d0-465e-b8f8-12f2d812718d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222841685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4222841685
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2995866327
Short name T210
Test name
Test status
Simulation time 80998131 ps
CPU time 2.81 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 208876 kb
Host smart-89d7c157-0a9a-4d35-8301-652b195060f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995866327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2995866327
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3671443655
Short name T614
Test name
Test status
Simulation time 498326781 ps
CPU time 2.55 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:35 PM PDT 24
Peak memory 206840 kb
Host smart-1308dc31-5031-4cfd-82f2-f3912ef17265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671443655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3671443655
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2738656602
Short name T129
Test name
Test status
Simulation time 3273119061 ps
CPU time 38.44 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:38:13 PM PDT 24
Peak memory 223292 kb
Host smart-2d73c26f-4614-4bef-ba66-974de5caa814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738656602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2738656602
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1302563088
Short name T718
Test name
Test status
Simulation time 77215977 ps
CPU time 4.15 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:36 PM PDT 24
Peak memory 207660 kb
Host smart-c7678fca-2ed5-449b-bda4-f81c90305895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302563088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1302563088
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1681144705
Short name T494
Test name
Test status
Simulation time 92647499 ps
CPU time 2.47 seconds
Started May 30 03:37:31 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 210448 kb
Host smart-dc2aded4-16d8-4871-8c4c-187e2df5bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681144705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1681144705
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4207119970
Short name T472
Test name
Test status
Simulation time 285273223 ps
CPU time 1.07 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 206140 kb
Host smart-dd93606c-0af4-4924-9bb7-563ae7f35b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207119970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4207119970
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1791288981
Short name T417
Test name
Test status
Simulation time 963782799 ps
CPU time 25.92 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:38:05 PM PDT 24
Peak memory 214276 kb
Host smart-9338dba0-c10a-48cb-9d0a-823806bff152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791288981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1791288981
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.188194049
Short name T774
Test name
Test status
Simulation time 115727396 ps
CPU time 2.9 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:40 PM PDT 24
Peak memory 219144 kb
Host smart-74e3f6d5-500c-4fd6-b6c0-12c508cc1847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188194049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.188194049
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3519459540
Short name T673
Test name
Test status
Simulation time 186142950 ps
CPU time 2.11 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 209440 kb
Host smart-5fc2bd78-6eb5-417d-b618-80f466b2bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519459540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3519459540
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4195623911
Short name T100
Test name
Test status
Simulation time 520469146 ps
CPU time 2.82 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 213476 kb
Host smart-65cd3e04-9485-4096-a5ff-030913ead817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195623911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4195623911
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1678436270
Short name T671
Test name
Test status
Simulation time 167651188 ps
CPU time 4.66 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 216756 kb
Host smart-8d9495ef-5700-4ba9-a6f3-422e22dd53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678436270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1678436270
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1380874122
Short name T828
Test name
Test status
Simulation time 213073048 ps
CPU time 5.1 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 210868 kb
Host smart-7b96e630-0672-4120-977e-2a0bac96c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380874122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1380874122
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3830992033
Short name T883
Test name
Test status
Simulation time 3831083924 ps
CPU time 26.58 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 209592 kb
Host smart-d4f52958-b715-4b14-bb63-bef445165592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830992033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3830992033
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3258672642
Short name T731
Test name
Test status
Simulation time 75331914 ps
CPU time 1.8 seconds
Started May 30 03:37:28 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 207372 kb
Host smart-92510b09-03f1-4a5c-abbc-b7fba8c6be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258672642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3258672642
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4222980151
Short name T524
Test name
Test status
Simulation time 44883299 ps
CPU time 2.48 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 208812 kb
Host smart-70b3f40f-57ad-4998-afd2-b52070dd367b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222980151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4222980151
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1348480145
Short name T664
Test name
Test status
Simulation time 195708896 ps
CPU time 2.61 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 207388 kb
Host smart-b81329c3-3a57-47b5-9d59-6f2a72aa8a38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348480145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1348480145
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.609103568
Short name T685
Test name
Test status
Simulation time 83957678 ps
CPU time 3.11 seconds
Started May 30 03:37:29 PM PDT 24
Finished May 30 03:37:37 PM PDT 24
Peak memory 208600 kb
Host smart-4c18e8b3-6d99-4101-8324-131f27986f34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609103568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.609103568
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1805436759
Short name T683
Test name
Test status
Simulation time 138295402 ps
CPU time 4.9 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:45 PM PDT 24
Peak memory 214268 kb
Host smart-dae7e087-408e-4fe4-8895-f4413cb85738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805436759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1805436759
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2581656179
Short name T611
Test name
Test status
Simulation time 108370596 ps
CPU time 2.75 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 206888 kb
Host smart-d42ff3ae-0a0e-419e-915f-3738196f1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581656179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2581656179
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1810037009
Short name T56
Test name
Test status
Simulation time 615828702 ps
CPU time 20.39 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:38:02 PM PDT 24
Peak memory 216084 kb
Host smart-6691b1fe-04fe-4796-87a0-e5624fb71640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810037009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1810037009
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1271113936
Short name T293
Test name
Test status
Simulation time 152681137 ps
CPU time 7.5 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 222644 kb
Host smart-59766cb9-f289-4fdb-9bc6-f6ff83a60774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271113936 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1271113936
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2066315419
Short name T763
Test name
Test status
Simulation time 447198598 ps
CPU time 5.21 seconds
Started May 30 03:37:33 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 222452 kb
Host smart-784dcc9d-0d70-4848-b1e3-d9ce9ae4c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066315419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2066315419
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1761469451
Short name T63
Test name
Test status
Simulation time 56327885 ps
CPU time 2.02 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 210252 kb
Host smart-31a80c6b-ad8a-4246-82c6-5cdb5789f667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761469451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1761469451
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3563597425
Short name T724
Test name
Test status
Simulation time 57100895 ps
CPU time 0.9 seconds
Started May 30 03:37:43 PM PDT 24
Finished May 30 03:37:45 PM PDT 24
Peak memory 205868 kb
Host smart-76d23a8e-d778-463d-bed7-42377f2d1b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563597425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3563597425
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.311101855
Short name T411
Test name
Test status
Simulation time 666470691 ps
CPU time 4.47 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:45 PM PDT 24
Peak memory 215416 kb
Host smart-c24b6435-673c-4b35-95bf-113406a7a566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311101855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.311101855
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1973294087
Short name T33
Test name
Test status
Simulation time 53339998 ps
CPU time 3.39 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:41 PM PDT 24
Peak memory 217192 kb
Host smart-dc8dd635-9fdf-44a7-9f57-42c18d5a9a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973294087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1973294087
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.749930315
Short name T641
Test name
Test status
Simulation time 107053975 ps
CPU time 3.45 seconds
Started May 30 03:37:27 PM PDT 24
Finished May 30 03:37:34 PM PDT 24
Peak memory 208348 kb
Host smart-1f44c88c-56ea-46bd-9f75-156b1191a7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749930315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.749930315
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2692256062
Short name T379
Test name
Test status
Simulation time 51912439 ps
CPU time 3.32 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 222436 kb
Host smart-a1ea5276-2c59-4bec-9ae2-c1161329b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692256062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2692256062
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1809984820
Short name T69
Test name
Test status
Simulation time 47782324 ps
CPU time 3.1 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 209344 kb
Host smart-962a7e6c-deab-41eb-ac5e-263f14671d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809984820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1809984820
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1695166549
Short name T280
Test name
Test status
Simulation time 43106419 ps
CPU time 3.08 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 209324 kb
Host smart-a6a0d7c0-1721-40a6-89a6-db9aff1e8e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695166549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1695166549
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1945946858
Short name T337
Test name
Test status
Simulation time 36719453 ps
CPU time 1.7 seconds
Started May 30 03:37:32 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 207236 kb
Host smart-c51551c9-8710-4f2e-8a52-5ca7e194e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945946858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1945946858
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.169437944
Short name T877
Test name
Test status
Simulation time 4193884711 ps
CPU time 65.82 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:38:46 PM PDT 24
Peak memory 208616 kb
Host smart-f9f360b9-a634-4cb2-a672-fc3f7b8b26b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169437944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.169437944
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3927704987
Short name T14
Test name
Test status
Simulation time 43084980 ps
CPU time 2.36 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 206960 kb
Host smart-9e28a719-c65c-412c-aa2f-49e851a51bfd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927704987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3927704987
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.719444676
Short name T612
Test name
Test status
Simulation time 872806346 ps
CPU time 28.21 seconds
Started May 30 03:37:33 PM PDT 24
Finished May 30 03:38:06 PM PDT 24
Peak memory 209124 kb
Host smart-5999776e-82ed-41c2-9958-89038ee62654
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719444676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.719444676
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3955582409
Short name T695
Test name
Test status
Simulation time 7542491747 ps
CPU time 30.99 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:38:11 PM PDT 24
Peak memory 209072 kb
Host smart-70084f3e-10e9-45dc-8c17-bf31983f8067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955582409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3955582409
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2372875593
Short name T820
Test name
Test status
Simulation time 6376480863 ps
CPU time 50.55 seconds
Started May 30 03:37:37 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 208984 kb
Host smart-960dd18c-6881-4e8d-9c56-076e527bffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372875593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2372875593
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3763215122
Short name T670
Test name
Test status
Simulation time 202025249 ps
CPU time 3.11 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 208896 kb
Host smart-017a1c70-2ece-4b91-b59f-eabdf79b39cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763215122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3763215122
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.932867292
Short name T701
Test name
Test status
Simulation time 130673950 ps
CPU time 5.52 seconds
Started May 30 03:37:36 PM PDT 24
Finished May 30 03:37:46 PM PDT 24
Peak memory 208840 kb
Host smart-dd7c4a0b-ccb5-4cfe-941d-c5a80fd1df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932867292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.932867292
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3182899899
Short name T726
Test name
Test status
Simulation time 94824115 ps
CPU time 2.73 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 210460 kb
Host smart-9d0db761-252d-4779-ab71-4d55cb2f83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182899899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3182899899
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1460683191
Short name T825
Test name
Test status
Simulation time 34040612 ps
CPU time 0.74 seconds
Started May 30 03:37:33 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 205916 kb
Host smart-21b620c2-cc4a-467a-b5a8-32da2ad74978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460683191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1460683191
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1065334051
Short name T399
Test name
Test status
Simulation time 215991322 ps
CPU time 11.92 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:56 PM PDT 24
Peak memory 215036 kb
Host smart-558a697d-3857-462d-a1d5-df89d12a6d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065334051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1065334051
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.4142053571
Short name T510
Test name
Test status
Simulation time 245443836 ps
CPU time 2.96 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 208744 kb
Host smart-19ec5ecb-0e95-46a2-bd1a-be30d31800a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142053571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.4142053571
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2699973694
Short name T81
Test name
Test status
Simulation time 135549465 ps
CPU time 4.11 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 208524 kb
Host smart-a1b53038-5396-41a0-8a3b-3f2d788181dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699973694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2699973694
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.746948395
Short name T98
Test name
Test status
Simulation time 262246689 ps
CPU time 3.31 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 214368 kb
Host smart-bbbfa4a3-b757-400f-9107-06c1fd65ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746948395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.746948395
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3340133393
Short name T365
Test name
Test status
Simulation time 398359171 ps
CPU time 4.34 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:49 PM PDT 24
Peak memory 214320 kb
Host smart-9f95f84f-a372-4189-90ed-4a3034260354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340133393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3340133393
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1120366126
Short name T242
Test name
Test status
Simulation time 394600868 ps
CPU time 4.07 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 219232 kb
Host smart-cce93c85-74e8-4161-a962-94f3a63f5d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120366126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1120366126
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2066840674
Short name T540
Test name
Test status
Simulation time 528389157 ps
CPU time 13.68 seconds
Started May 30 03:37:43 PM PDT 24
Finished May 30 03:37:58 PM PDT 24
Peak memory 209100 kb
Host smart-d2456638-1a34-4745-92d7-1ab95808d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066840674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2066840674
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4121683904
Short name T837
Test name
Test status
Simulation time 418262595 ps
CPU time 2.91 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 206904 kb
Host smart-b67a5a1a-550f-4e1f-8e78-6533f2742c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121683904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4121683904
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2746685540
Short name T750
Test name
Test status
Simulation time 342011210 ps
CPU time 3.53 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 208712 kb
Host smart-6416baec-3bf9-43fa-83b4-5f3b5fb4052d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746685540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2746685540
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3266422703
Short name T853
Test name
Test status
Simulation time 3676064660 ps
CPU time 24.44 seconds
Started May 30 03:37:41 PM PDT 24
Finished May 30 03:38:08 PM PDT 24
Peak memory 208400 kb
Host smart-a5d0f64e-49f7-41af-a592-a89002799b7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266422703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3266422703
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4193505804
Short name T455
Test name
Test status
Simulation time 436881505 ps
CPU time 3.12 seconds
Started May 30 03:37:34 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 206852 kb
Host smart-cee17b81-d365-47fd-aea6-417e5296d046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193505804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4193505804
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1919153991
Short name T912
Test name
Test status
Simulation time 109277151 ps
CPU time 4.25 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 209784 kb
Host smart-60b069e6-056f-4ae0-936e-ee87768622a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919153991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1919153991
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3029884143
Short name T656
Test name
Test status
Simulation time 70983229 ps
CPU time 2.38 seconds
Started May 30 03:37:43 PM PDT 24
Finished May 30 03:37:47 PM PDT 24
Peak memory 206672 kb
Host smart-e77983fc-28b3-4407-80e1-1dfada485456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029884143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3029884143
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4041901136
Short name T477
Test name
Test status
Simulation time 742805379 ps
CPU time 5.19 seconds
Started May 30 03:37:35 PM PDT 24
Finished May 30 03:37:45 PM PDT 24
Peak memory 207788 kb
Host smart-b09c6e96-c080-4419-a86c-eb0ea2f98dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041901136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4041901136
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3272242396
Short name T503
Test name
Test status
Simulation time 389668697 ps
CPU time 3.07 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 210904 kb
Host smart-a15d3740-00c5-4307-95dd-c3a0242679e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272242396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3272242396
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.678387963
Short name T601
Test name
Test status
Simulation time 29642936 ps
CPU time 0.87 seconds
Started May 30 03:37:39 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 205916 kb
Host smart-7d878563-295c-4ca5-9796-211c5bdae423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678387963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.678387963
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.379203153
Short name T415
Test name
Test status
Simulation time 2019027925 ps
CPU time 105.45 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 214296 kb
Host smart-bfa07e00-f052-4131-a7fb-e694b3ee504e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379203153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.379203153
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.351146237
Short name T602
Test name
Test status
Simulation time 121402995 ps
CPU time 4.31 seconds
Started May 30 03:37:41 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 218224 kb
Host smart-86085c65-20e7-4ebc-a12c-3e79ae47b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351146237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.351146237
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2589632219
Short name T178
Test name
Test status
Simulation time 27279820 ps
CPU time 1.25 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:37:43 PM PDT 24
Peak memory 207648 kb
Host smart-749a7cdb-63f0-4a4b-9053-89fb5b962add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589632219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2589632219
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3348850575
Short name T59
Test name
Test status
Simulation time 261213668 ps
CPU time 3.37 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:39 PM PDT 24
Peak memory 217048 kb
Host smart-948157b3-f096-42ce-a930-0720cc4e81aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348850575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3348850575
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2637103566
Short name T778
Test name
Test status
Simulation time 400326252 ps
CPU time 3.37 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 214352 kb
Host smart-535cc498-e134-4656-996c-7e25cf9bec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637103566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2637103566
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2237377989
Short name T534
Test name
Test status
Simulation time 118724237 ps
CPU time 5.4 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:37:47 PM PDT 24
Peak memory 207724 kb
Host smart-7863aa6d-a0b6-477d-a6d0-17e6215d23b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237377989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2237377989
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1209004164
Short name T596
Test name
Test status
Simulation time 7261833913 ps
CPU time 16.56 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 208012 kb
Host smart-f6732744-b96a-4388-a846-21f34de9b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209004164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1209004164
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2689894804
Short name T562
Test name
Test status
Simulation time 58992187 ps
CPU time 2.76 seconds
Started May 30 03:37:30 PM PDT 24
Finished May 30 03:37:38 PM PDT 24
Peak memory 208688 kb
Host smart-11f0cfa2-6cfe-4f4c-a5c0-7f773981a015
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689894804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2689894804
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.784306609
Short name T893
Test name
Test status
Simulation time 226804400 ps
CPU time 3.85 seconds
Started May 30 03:37:33 PM PDT 24
Finished May 30 03:37:42 PM PDT 24
Peak memory 206876 kb
Host smart-31b9b0d0-7613-4d70-9c3e-b2eacd18f619
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784306609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.784306609
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.524550747
Short name T575
Test name
Test status
Simulation time 105797109 ps
CPU time 2.73 seconds
Started May 30 03:37:38 PM PDT 24
Finished May 30 03:37:44 PM PDT 24
Peak memory 208388 kb
Host smart-63ed6c69-c19a-4101-ab52-e17cb6053eba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524550747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.524550747
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.306826382
Short name T854
Test name
Test status
Simulation time 270636049 ps
CPU time 3.52 seconds
Started May 30 03:37:41 PM PDT 24
Finished May 30 03:37:47 PM PDT 24
Peak memory 209952 kb
Host smart-9d6e96e7-6bc4-40cb-806e-e0b427b009df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306826382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.306826382
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4294549310
Short name T213
Test name
Test status
Simulation time 326342432 ps
CPU time 8.21 seconds
Started May 30 03:37:40 PM PDT 24
Finished May 30 03:37:51 PM PDT 24
Peak memory 208528 kb
Host smart-6bb3e6c9-2bb1-46db-a219-f6bcd493447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294549310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4294549310
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.554004127
Short name T205
Test name
Test status
Simulation time 162740391 ps
CPU time 6.84 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:51 PM PDT 24
Peak memory 217760 kb
Host smart-28f9ddf0-0b9c-4bda-b11a-7010791614b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554004127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.554004127
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2944932197
Short name T165
Test name
Test status
Simulation time 110472082 ps
CPU time 2.25 seconds
Started May 30 03:37:47 PM PDT 24
Finished May 30 03:37:50 PM PDT 24
Peak memory 210068 kb
Host smart-8ecd4b92-9274-4472-8f05-03c6c824ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944932197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2944932197
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.657765981
Short name T424
Test name
Test status
Simulation time 17194251 ps
CPU time 0.77 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:00 PM PDT 24
Peak memory 205940 kb
Host smart-3473ea7f-9b37-417b-865a-2e9d6a4e227c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657765981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.657765981
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1613623076
Short name T551
Test name
Test status
Simulation time 63024953 ps
CPU time 1.7 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:02 PM PDT 24
Peak memory 208692 kb
Host smart-6eb8f14e-ae5e-47c2-9703-0900690d0af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613623076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1613623076
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3590185452
Short name T500
Test name
Test status
Simulation time 24032398 ps
CPU time 1.68 seconds
Started May 30 03:37:52 PM PDT 24
Finished May 30 03:37:55 PM PDT 24
Peak memory 209904 kb
Host smart-b8ff5860-aef7-4c36-9901-33442c91426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590185452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3590185452
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.544749342
Short name T873
Test name
Test status
Simulation time 262162212 ps
CPU time 2.63 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:37:52 PM PDT 24
Peak memory 214292 kb
Host smart-92ef51fd-0075-4ef0-b42d-97a1a42553fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544749342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.544749342
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2821922119
Short name T748
Test name
Test status
Simulation time 97301457 ps
CPU time 2.28 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:37:52 PM PDT 24
Peak memory 220660 kb
Host smart-2fe319df-f6fb-4ae3-8eff-609cac38b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821922119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2821922119
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4015651824
Short name T261
Test name
Test status
Simulation time 159083039 ps
CPU time 3.77 seconds
Started May 30 03:37:47 PM PDT 24
Finished May 30 03:37:52 PM PDT 24
Peak memory 210164 kb
Host smart-fb33e89d-db44-49de-b7d4-a91f19fbe523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015651824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4015651824
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1694563359
Short name T897
Test name
Test status
Simulation time 1337559534 ps
CPU time 9.75 seconds
Started May 30 03:37:39 PM PDT 24
Finished May 30 03:37:51 PM PDT 24
Peak memory 208996 kb
Host smart-11793be9-f8bb-46d5-98cb-b6226ba9b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694563359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1694563359
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3274215900
Short name T328
Test name
Test status
Simulation time 203410254 ps
CPU time 2.82 seconds
Started May 30 03:37:43 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 208368 kb
Host smart-bf9a1adc-bcb5-42cd-b1c3-556c35cdd520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274215900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3274215900
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2920123418
Short name T858
Test name
Test status
Simulation time 106989889 ps
CPU time 4.39 seconds
Started May 30 03:37:47 PM PDT 24
Finished May 30 03:37:52 PM PDT 24
Peak memory 206920 kb
Host smart-f457aeee-8bf9-48d0-96ca-43395f1d1c3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920123418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2920123418
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1843333664
Short name T868
Test name
Test status
Simulation time 715152066 ps
CPU time 3.99 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:48 PM PDT 24
Peak memory 208908 kb
Host smart-a9bc46b8-a316-47c9-807f-f908c7b252b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843333664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1843333664
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.128514959
Short name T110
Test name
Test status
Simulation time 294906695 ps
CPU time 6.81 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:37:56 PM PDT 24
Peak memory 210272 kb
Host smart-064471b6-92a7-4b55-8f69-c15472a4cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128514959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.128514959
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2953829407
Short name T484
Test name
Test status
Simulation time 335475348 ps
CPU time 3.43 seconds
Started May 30 03:37:42 PM PDT 24
Finished May 30 03:37:47 PM PDT 24
Peak memory 208704 kb
Host smart-bc33e59a-ed76-4690-bc53-40af0d1a5584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953829407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2953829407
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.856630658
Short name T870
Test name
Test status
Simulation time 1595685214 ps
CPU time 35.85 seconds
Started May 30 03:37:49 PM PDT 24
Finished May 30 03:38:26 PM PDT 24
Peak memory 221948 kb
Host smart-73ea76ec-1c0b-46e7-9f40-4eebc830e57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856630658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.856630658
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2402121565
Short name T831
Test name
Test status
Simulation time 394065914 ps
CPU time 6.89 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:37:56 PM PDT 24
Peak memory 208592 kb
Host smart-c5f5aa84-eccb-40fa-829f-a9cd62b70e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402121565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2402121565
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.570455896
Short name T717
Test name
Test status
Simulation time 847597296 ps
CPU time 2.46 seconds
Started May 30 03:37:51 PM PDT 24
Finished May 30 03:37:55 PM PDT 24
Peak memory 210500 kb
Host smart-6f37bca1-5ef3-4703-ab0b-6484092dd4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570455896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.570455896
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.613968380
Short name T730
Test name
Test status
Simulation time 43989246 ps
CPU time 1.08 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:02 PM PDT 24
Peak memory 206104 kb
Host smart-10cd4dfd-85b8-4f09-a223-0af97bf5a78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613968380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.613968380
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3479826740
Short name T251
Test name
Test status
Simulation time 35644223 ps
CPU time 2.7 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 214344 kb
Host smart-76feb961-e6ca-48fc-90cc-14f3e162f055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479826740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3479826740
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2562684649
Short name T70
Test name
Test status
Simulation time 140371785 ps
CPU time 3.34 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 219704 kb
Host smart-910dbbef-46e3-4a53-8745-1fa5b0140b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562684649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2562684649
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.449399854
Short name T594
Test name
Test status
Simulation time 62080209 ps
CPU time 1.89 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:03 PM PDT 24
Peak memory 207600 kb
Host smart-498901a8-f9b0-41da-9029-65ccf6f4a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449399854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.449399854
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.51282059
Short name T204
Test name
Test status
Simulation time 402368179 ps
CPU time 1.83 seconds
Started May 30 03:37:56 PM PDT 24
Finished May 30 03:37:59 PM PDT 24
Peak memory 214452 kb
Host smart-e091b05e-8cdd-4dbb-aecd-b05b3315c242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51282059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.51282059
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3176327198
Short name T708
Test name
Test status
Simulation time 79450539 ps
CPU time 3.57 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:03 PM PDT 24
Peak memory 218676 kb
Host smart-202d6ccc-b062-4ba4-ac18-eae856eaecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176327198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3176327198
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1346128541
Short name T862
Test name
Test status
Simulation time 3174058826 ps
CPU time 8.95 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:08 PM PDT 24
Peak memory 218132 kb
Host smart-bb9a8c55-9794-430a-9a64-2385735c4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346128541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1346128541
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2456153928
Short name T760
Test name
Test status
Simulation time 2271326546 ps
CPU time 17.06 seconds
Started May 30 03:37:48 PM PDT 24
Finished May 30 03:38:06 PM PDT 24
Peak memory 208940 kb
Host smart-d6113890-937b-4897-9a86-0bca7d2fbef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456153928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2456153928
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.470027527
Short name T694
Test name
Test status
Simulation time 68960674 ps
CPU time 3.45 seconds
Started May 30 03:37:50 PM PDT 24
Finished May 30 03:37:54 PM PDT 24
Peak memory 208936 kb
Host smart-388b37cc-01d4-484a-8836-75ccbc49128d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470027527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.470027527
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1475221520
Short name T739
Test name
Test status
Simulation time 98089409 ps
CPU time 4.42 seconds
Started May 30 03:37:53 PM PDT 24
Finished May 30 03:37:59 PM PDT 24
Peak memory 209048 kb
Host smart-7611421f-4881-4389-8acb-115ffe82d893
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475221520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1475221520
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3427167990
Short name T357
Test name
Test status
Simulation time 121500591 ps
CPU time 3.33 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:03 PM PDT 24
Peak memory 206980 kb
Host smart-af7b8768-9720-4641-8802-7bbb35d23ccf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427167990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3427167990
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4074020611
Short name T221
Test name
Test status
Simulation time 88681728 ps
CPU time 3 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:02 PM PDT 24
Peak memory 215824 kb
Host smart-3f0c6f00-121d-4664-98b0-1a40469e054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074020611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4074020611
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2966091755
Short name T697
Test name
Test status
Simulation time 3073038039 ps
CPU time 41.73 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:41 PM PDT 24
Peak memory 208272 kb
Host smart-e14164b8-4a1a-4d80-bd32-f94ef14a2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966091755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2966091755
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3240205936
Short name T823
Test name
Test status
Simulation time 1765600891 ps
CPU time 18.57 seconds
Started May 30 03:37:56 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 222516 kb
Host smart-5cb93e53-3b3d-490c-99ec-e46821263a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240205936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3240205936
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3875668265
Short name T244
Test name
Test status
Simulation time 2732233162 ps
CPU time 15.91 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:17 PM PDT 24
Peak memory 222668 kb
Host smart-780114e2-67d7-47ac-8136-614a5f7a5457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875668265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3875668265
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.36755668
Short name T450
Test name
Test status
Simulation time 2133128040 ps
CPU time 20.57 seconds
Started May 30 03:37:57 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 214368 kb
Host smart-46157585-d3a0-455e-b019-3cd61e0ae150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36755668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.36755668
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4205623456
Short name T386
Test name
Test status
Simulation time 165960151 ps
CPU time 2.01 seconds
Started May 30 03:38:02 PM PDT 24
Finished May 30 03:38:05 PM PDT 24
Peak memory 210236 kb
Host smart-daab2faa-dd0f-47d3-bdbc-af68129e31e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205623456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4205623456
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1430068021
Short name T502
Test name
Test status
Simulation time 11396865 ps
CPU time 0.84 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 205936 kb
Host smart-d8198364-7e8f-4a96-a950-d39438c71344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430068021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1430068021
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1331872876
Short name T526
Test name
Test status
Simulation time 162853780 ps
CPU time 3.64 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 208064 kb
Host smart-3e92db40-f35f-4a1d-a474-80517df172af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331872876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1331872876
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1567759376
Short name T751
Test name
Test status
Simulation time 64541776 ps
CPU time 2.83 seconds
Started May 30 03:37:57 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 214340 kb
Host smart-67267721-ea57-4060-8b6b-8610a19c18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567759376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1567759376
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4136640214
Short name T380
Test name
Test status
Simulation time 152604646 ps
CPU time 3.75 seconds
Started May 30 03:37:56 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 214280 kb
Host smart-d8661e8a-accd-4be2-8f69-2a01940de504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136640214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4136640214
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1143985438
Short name T7
Test name
Test status
Simulation time 437835549 ps
CPU time 3.4 seconds
Started May 30 03:38:00 PM PDT 24
Finished May 30 03:38:05 PM PDT 24
Peak memory 220588 kb
Host smart-b01c121f-6263-4c52-a6cc-562b24d87dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143985438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1143985438
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1114036929
Short name T509
Test name
Test status
Simulation time 365961662 ps
CPU time 9.57 seconds
Started May 30 03:37:56 PM PDT 24
Finished May 30 03:38:07 PM PDT 24
Peak memory 214340 kb
Host smart-5f17f8c6-ce48-4896-8107-be9ef4ec4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114036929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1114036929
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2535225215
Short name T587
Test name
Test status
Simulation time 196228218 ps
CPU time 3.15 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 208712 kb
Host smart-ff142cee-97c7-4a58-85df-0d4c1088b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535225215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2535225215
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.368571027
Short name T829
Test name
Test status
Simulation time 113065048 ps
CPU time 3.18 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:05 PM PDT 24
Peak memory 207124 kb
Host smart-3e7f48e1-85c0-42cd-b53f-2c8395dbaff3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368571027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.368571027
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1474011292
Short name T839
Test name
Test status
Simulation time 3849338510 ps
CPU time 37.24 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 208376 kb
Host smart-5709ec6b-681c-4041-9738-66d763b4ed60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474011292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1474011292
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4078275046
Short name T616
Test name
Test status
Simulation time 20225400 ps
CPU time 1.76 seconds
Started May 30 03:37:57 PM PDT 24
Finished May 30 03:38:01 PM PDT 24
Peak memory 206996 kb
Host smart-a89d61fc-4ca8-4c73-868e-9afd47c222fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078275046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4078275046
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2123127212
Short name T721
Test name
Test status
Simulation time 38925925 ps
CPU time 1.99 seconds
Started May 30 03:38:00 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 208312 kb
Host smart-9feff5fc-f8f6-4bf6-8834-4353e75517e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123127212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2123127212
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3597794377
Short name T675
Test name
Test status
Simulation time 3849015448 ps
CPU time 23.36 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:24 PM PDT 24
Peak memory 208384 kb
Host smart-cebab645-2718-4b9d-b10a-a0578badf157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597794377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3597794377
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4248575009
Short name T187
Test name
Test status
Simulation time 3263884930 ps
CPU time 41.76 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 215488 kb
Host smart-c8265af9-182b-4b69-b87f-40383a52ceeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248575009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4248575009
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3249445481
Short name T377
Test name
Test status
Simulation time 259236032 ps
CPU time 15.11 seconds
Started May 30 03:38:04 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 222604 kb
Host smart-c0ff296e-e6a9-4879-b047-abe0e599e8ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249445481 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3249445481
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3636031451
Short name T344
Test name
Test status
Simulation time 488951172 ps
CPU time 3.81 seconds
Started May 30 03:37:58 PM PDT 24
Finished May 30 03:38:03 PM PDT 24
Peak memory 207248 kb
Host smart-4a05f21b-4878-49e8-9ca7-f50730a78b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636031451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3636031451
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3234322754
Short name T560
Test name
Test status
Simulation time 54502583 ps
CPU time 2.37 seconds
Started May 30 03:37:59 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 209900 kb
Host smart-48b3fc43-5b4a-4c30-b87c-39ff98ce54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234322754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3234322754
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3929710216
Short name T857
Test name
Test status
Simulation time 11807852 ps
CPU time 0.74 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 205932 kb
Host smart-3f8c7042-ca9e-425d-b1ef-3f50de11fcc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929710216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3929710216
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1613874358
Short name T634
Test name
Test status
Simulation time 274075942 ps
CPU time 2.4 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:38:12 PM PDT 24
Peak memory 209664 kb
Host smart-beff3836-0d63-41a1-b7eb-a01ed7453ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613874358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1613874358
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.38103710
Short name T780
Test name
Test status
Simulation time 1750379454 ps
CPU time 4.64 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:17 PM PDT 24
Peak memory 214344 kb
Host smart-20fc8d77-3e99-4802-801a-c9e545d13082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38103710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.38103710
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.200808259
Short name T806
Test name
Test status
Simulation time 103897499 ps
CPU time 4.6 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 214336 kb
Host smart-a376fe08-d3bb-4d73-bf24-d8db454d53ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200808259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.200808259
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.906435854
Short name T285
Test name
Test status
Simulation time 75180757 ps
CPU time 3.59 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 214204 kb
Host smart-963ef5ae-aa8d-4b93-833d-0b7f73eb343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906435854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.906435854
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1131269518
Short name T886
Test name
Test status
Simulation time 904388482 ps
CPU time 7.37 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:23 PM PDT 24
Peak memory 218324 kb
Host smart-ca5fa566-63f1-4b14-b79a-d2f259a7ea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131269518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1131269518
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.78269385
Short name T637
Test name
Test status
Simulation time 61521510 ps
CPU time 3.71 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 207348 kb
Host smart-f98af545-9ccd-4c63-8d0f-3fefc91489c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78269385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.78269385
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2173451186
Short name T747
Test name
Test status
Simulation time 2329475222 ps
CPU time 25.83 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 208364 kb
Host smart-7c222a69-97a6-4731-a2a1-9d6b7c72c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173451186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2173451186
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3891768650
Short name T712
Test name
Test status
Simulation time 672134766 ps
CPU time 5.91 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 207968 kb
Host smart-4f79b305-5494-42c5-9297-c573d9d4f0c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891768650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3891768650
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.88457808
Short name T277
Test name
Test status
Simulation time 75194277 ps
CPU time 3.34 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:38:13 PM PDT 24
Peak memory 208688 kb
Host smart-e0b64867-bf0f-48e7-9027-8ada1258a4f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88457808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.88457808
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2863416153
Short name T395
Test name
Test status
Simulation time 80206707 ps
CPU time 2.9 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:14 PM PDT 24
Peak memory 208856 kb
Host smart-4818d4fb-a05e-4a35-af9a-e48c5d8a6756
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863416153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2863416153
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2077098457
Short name T469
Test name
Test status
Simulation time 129053402 ps
CPU time 3.07 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:38:14 PM PDT 24
Peak memory 210040 kb
Host smart-af260561-c3d0-4bd0-81b1-e3602ff3cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077098457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2077098457
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.508041548
Short name T481
Test name
Test status
Simulation time 59258462 ps
CPU time 2.11 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:13 PM PDT 24
Peak memory 208500 kb
Host smart-090f0b15-1a42-4216-b979-da0a2b4407af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508041548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.508041548
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3452943894
Short name T686
Test name
Test status
Simulation time 278315124 ps
CPU time 3.44 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 207532 kb
Host smart-2259b484-33b4-48a5-8369-e170523e5295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452943894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3452943894
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1576833950
Short name T133
Test name
Test status
Simulation time 946590519 ps
CPU time 6.26 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:22 PM PDT 24
Peak memory 210872 kb
Host smart-d9310973-73da-4a43-a721-3096c8de1d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576833950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1576833950
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4030330199
Short name T425
Test name
Test status
Simulation time 26124338 ps
CPU time 1.01 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:12 PM PDT 24
Peak memory 206104 kb
Host smart-d4466de0-b38c-4da9-85e2-cff80b2c728d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030330199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4030330199
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1517002673
Short name T42
Test name
Test status
Simulation time 186155423 ps
CPU time 4.54 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 209768 kb
Host smart-3ffae4b9-d33e-4ae7-82de-2f04038de878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517002673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1517002673
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1040532599
Short name T672
Test name
Test status
Simulation time 682356715 ps
CPU time 3.61 seconds
Started May 30 03:38:08 PM PDT 24
Finished May 30 03:38:13 PM PDT 24
Peak memory 218504 kb
Host smart-b003152f-d83d-4e90-923f-c1a42f0cf03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040532599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1040532599
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.19316385
Short name T657
Test name
Test status
Simulation time 11282887341 ps
CPU time 77.22 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 214488 kb
Host smart-3435b7e3-d0ad-4efe-8861-d5cda6b1bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19316385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.19316385
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3411901995
Short name T860
Test name
Test status
Simulation time 58274110 ps
CPU time 3.31 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 221536 kb
Host smart-81c342e4-9cb8-4f91-abec-3dd56e7cf6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411901995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3411901995
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3011672926
Short name T241
Test name
Test status
Simulation time 1684291126 ps
CPU time 3.86 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 222412 kb
Host smart-9559d617-a7b5-444d-9dd0-b006c322b001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011672926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3011672926
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.556890589
Short name T275
Test name
Test status
Simulation time 263776859 ps
CPU time 7.45 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:22 PM PDT 24
Peak memory 208276 kb
Host smart-419efbdc-2374-4d91-8a5b-fa5bf615b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556890589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.556890589
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.532916352
Short name T459
Test name
Test status
Simulation time 470671471 ps
CPU time 6.55 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 206748 kb
Host smart-601f6818-4b7e-4c30-9548-2a2c187f2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532916352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.532916352
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.63444186
Short name T522
Test name
Test status
Simulation time 254020402 ps
CPU time 3.06 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 208536 kb
Host smart-5e2136b7-f646-467a-a5b4-02f1f50a426d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63444186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.63444186
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.549109725
Short name T749
Test name
Test status
Simulation time 120162293 ps
CPU time 3.05 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:14 PM PDT 24
Peak memory 208084 kb
Host smart-e0ccfde1-c91f-43fa-a7ca-aa81bf1172cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549109725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.549109725
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.287681856
Short name T833
Test name
Test status
Simulation time 100240338 ps
CPU time 2.68 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 208096 kb
Host smart-af07a42f-5b96-4d53-87e6-b58178760a20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287681856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.287681856
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3070756634
Short name T643
Test name
Test status
Simulation time 48958455 ps
CPU time 2.58 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 210112 kb
Host smart-1d884b6a-b6a1-4489-8e4a-d9cbaeea6f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070756634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3070756634
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.479706784
Short name T855
Test name
Test status
Simulation time 49187004 ps
CPU time 1.92 seconds
Started May 30 03:38:08 PM PDT 24
Finished May 30 03:38:11 PM PDT 24
Peak memory 208228 kb
Host smart-e6589b3d-9545-41db-abfa-a0ed0433f391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479706784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.479706784
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3664406333
Short name T340
Test name
Test status
Simulation time 60120505 ps
CPU time 3.86 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 208292 kb
Host smart-cc2438d4-7b69-451e-adc8-b5e2a6da8e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664406333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3664406333
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.6696050
Short name T843
Test name
Test status
Simulation time 233336399 ps
CPU time 17.15 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 222624 kb
Host smart-3dcfabae-7b85-4388-9a7c-6a89d7f52c07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6696050 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.6696050
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4206223746
Short name T875
Test name
Test status
Simulation time 1277658633 ps
CPU time 17.8 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 208828 kb
Host smart-4709e8ef-0e81-4595-be8f-e2d196f5302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206223746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4206223746
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1113522080
Short name T709
Test name
Test status
Simulation time 258647506 ps
CPU time 4.46 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 209964 kb
Host smart-27834415-d2fc-4a94-af80-e6d86ad33f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113522080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1113522080
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.216609169
Short name T527
Test name
Test status
Simulation time 66977182 ps
CPU time 0.96 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:25 PM PDT 24
Peak memory 206120 kb
Host smart-beefdc40-9c35-488f-b777-3123c88cbe53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216609169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.216609169
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4044028281
Short name T354
Test name
Test status
Simulation time 141040605 ps
CPU time 4.87 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 214948 kb
Host smart-14ef36db-9a45-4f57-89d2-4fb5c66eb94a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044028281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4044028281
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1202519683
Short name T765
Test name
Test status
Simulation time 102298429 ps
CPU time 3.98 seconds
Started May 30 03:36:24 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 210640 kb
Host smart-068bc914-9878-4cb5-8938-2eb4da7a70c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202519683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1202519683
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.101895778
Short name T758
Test name
Test status
Simulation time 48422439 ps
CPU time 1.94 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 207792 kb
Host smart-baf43b5c-437b-43ad-84be-4022bfc6d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101895778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.101895778
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4170452597
Short name T549
Test name
Test status
Simulation time 34130057 ps
CPU time 2.13 seconds
Started May 30 03:36:24 PM PDT 24
Finished May 30 03:36:29 PM PDT 24
Peak memory 214348 kb
Host smart-d9e16758-d003-4793-81e7-b6c254cb374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170452597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4170452597
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.976467672
Short name T287
Test name
Test status
Simulation time 82571297 ps
CPU time 2.67 seconds
Started May 30 03:36:22 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 214332 kb
Host smart-7749bb51-8a57-4fa0-a28c-50e8b1ff32f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976467672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.976467672
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3228440257
Short name T373
Test name
Test status
Simulation time 178599714 ps
CPU time 4.4 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 209800 kb
Host smart-9ee436a0-fe24-48e3-b7b6-efe35f61df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228440257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3228440257
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1818543823
Short name T598
Test name
Test status
Simulation time 125760517 ps
CPU time 4.07 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 218468 kb
Host smart-a675bf60-db55-4ba4-acf0-8aec1da4132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818543823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1818543823
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1780878781
Short name T735
Test name
Test status
Simulation time 171244409 ps
CPU time 2.41 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:24 PM PDT 24
Peak memory 206940 kb
Host smart-817b5702-6d94-4c0f-b3b8-30b40471fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780878781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1780878781
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4266778822
Short name T372
Test name
Test status
Simulation time 2097541914 ps
CPU time 7.33 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:31 PM PDT 24
Peak memory 209064 kb
Host smart-0cdba350-9b01-424f-9b7d-810429778d7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266778822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4266778822
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2136861805
Short name T659
Test name
Test status
Simulation time 380440186 ps
CPU time 6.1 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:27 PM PDT 24
Peak memory 208576 kb
Host smart-0d05fa98-031c-4fbc-aeb2-6c7b20706f70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136861805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2136861805
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.472839526
Short name T485
Test name
Test status
Simulation time 136063553 ps
CPU time 3.99 seconds
Started May 30 03:36:22 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 208356 kb
Host smart-105de471-05bc-4833-8208-acde2a9566a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472839526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.472839526
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.895013245
Short name T17
Test name
Test status
Simulation time 67952911 ps
CPU time 3.08 seconds
Started May 30 03:36:26 PM PDT 24
Finished May 30 03:36:31 PM PDT 24
Peak memory 208284 kb
Host smart-af8bbf51-7285-49a8-a151-187de93ee916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895013245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.895013245
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1841506309
Short name T420
Test name
Test status
Simulation time 167154201 ps
CPU time 4.74 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:29 PM PDT 24
Peak memory 206780 kb
Host smart-2bdf4d1a-1871-41b8-92b5-c647bf57d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841506309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1841506309
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1185188612
Short name T660
Test name
Test status
Simulation time 772380424 ps
CPU time 15.44 seconds
Started May 30 03:36:26 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 222168 kb
Host smart-fbb315ba-713d-4789-9e78-5f97c5af8822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185188612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1185188612
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3845590580
Short name T631
Test name
Test status
Simulation time 2460759706 ps
CPU time 44.23 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:37:12 PM PDT 24
Peak memory 214420 kb
Host smart-944af6aa-1ac3-46cb-881f-1f24ebe74b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845590580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3845590580
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.839918229
Short name T385
Test name
Test status
Simulation time 826934014 ps
CPU time 4.17 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 210424 kb
Host smart-4ef2031c-4038-4dc6-a763-b4896f304777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839918229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.839918229
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2735538327
Short name T816
Test name
Test status
Simulation time 18900450 ps
CPU time 0.78 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 205896 kb
Host smart-e7b370ff-a088-47f6-b11d-f9e000c3bdd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735538327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2735538327
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.560953410
Short name T781
Test name
Test status
Simulation time 37645182 ps
CPU time 3.12 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 214320 kb
Host smart-03975352-f9ca-4907-9100-761d83240eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560953410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.560953410
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4174876643
Short name T196
Test name
Test status
Simulation time 1077741273 ps
CPU time 17.15 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 220764 kb
Host smart-58571369-c9ed-49dc-bb60-de6b2888865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174876643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4174876643
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.582607238
Short name T262
Test name
Test status
Simulation time 107729052 ps
CPU time 4.48 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:17 PM PDT 24
Peak memory 214344 kb
Host smart-02e96df9-8432-4532-8364-0c13287445d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582607238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.582607238
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4106559923
Short name T85
Test name
Test status
Simulation time 277369738 ps
CPU time 3.26 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:38:14 PM PDT 24
Peak memory 214384 kb
Host smart-0a75c981-e9d9-4a56-a49e-68dcf03c681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106559923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4106559923
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1122347942
Short name T194
Test name
Test status
Simulation time 77650916 ps
CPU time 2.99 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:19 PM PDT 24
Peak memory 222376 kb
Host smart-004267e9-eba1-426c-8302-12378f9d9de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122347942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1122347942
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2762994449
Short name T16
Test name
Test status
Simulation time 73628361 ps
CPU time 3.57 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 209660 kb
Host smart-865fcbe5-798c-4c2d-b827-1b36332b4a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762994449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2762994449
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.213321059
Short name T467
Test name
Test status
Simulation time 877156512 ps
CPU time 6.88 seconds
Started May 30 03:38:08 PM PDT 24
Finished May 30 03:38:16 PM PDT 24
Peak memory 214316 kb
Host smart-bf6957ef-ddf4-4af3-911e-76519729dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213321059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.213321059
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3029950172
Short name T517
Test name
Test status
Simulation time 7207612931 ps
CPU time 16.31 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 208164 kb
Host smart-5cad4866-4865-4de5-af50-208db27f32d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029950172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3029950172
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2947778348
Short name T577
Test name
Test status
Simulation time 546527610 ps
CPU time 6.55 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:21 PM PDT 24
Peak memory 208880 kb
Host smart-0d39913b-fd57-49b9-8522-57c63918adb0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947778348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2947778348
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2357593345
Short name T448
Test name
Test status
Simulation time 315768188 ps
CPU time 2.94 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 206916 kb
Host smart-482c0ca5-566f-4d8d-ac87-0d6c9ddb5d02
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357593345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2357593345
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2090394686
Short name T349
Test name
Test status
Simulation time 292287762 ps
CPU time 3.07 seconds
Started May 30 03:38:08 PM PDT 24
Finished May 30 03:38:12 PM PDT 24
Peak memory 209852 kb
Host smart-c1fec790-3b89-411b-a209-ce9e149092cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090394686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2090394686
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.423951573
Short name T662
Test name
Test status
Simulation time 133913303 ps
CPU time 3.01 seconds
Started May 30 03:38:08 PM PDT 24
Finished May 30 03:38:12 PM PDT 24
Peak memory 208296 kb
Host smart-b1430e9c-9bd8-49eb-a599-39acbd1e3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423951573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.423951573
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2993069773
Short name T245
Test name
Test status
Simulation time 901170903 ps
CPU time 37.02 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:52 PM PDT 24
Peak memory 221324 kb
Host smart-7ff4885c-1a67-4376-9249-ec82b7bc8f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993069773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2993069773
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.104070155
Short name T812
Test name
Test status
Simulation time 2121460494 ps
CPU time 23.75 seconds
Started May 30 03:38:09 PM PDT 24
Finished May 30 03:38:34 PM PDT 24
Peak memory 222584 kb
Host smart-36515141-716c-4a3b-ad2b-d0c64223c2cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104070155 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.104070155
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.185867684
Short name T350
Test name
Test status
Simulation time 112117756 ps
CPU time 3.17 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 207004 kb
Host smart-c4003ee3-3602-4151-bc10-d07c64be4a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185867684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.185867684
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3192239634
Short name T516
Test name
Test status
Simulation time 506243787 ps
CPU time 3.7 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 209856 kb
Host smart-73038085-6b67-4efe-a75e-cb78a5ba4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192239634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3192239634
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2946452842
Short name T627
Test name
Test status
Simulation time 153678249 ps
CPU time 0.77 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 205976 kb
Host smart-a67a4daa-cd22-43bb-aeda-79dd50b4b036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946452842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2946452842
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.107346678
Short name T77
Test name
Test status
Simulation time 203921178 ps
CPU time 2.25 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 207428 kb
Host smart-dea36011-03ab-4763-b644-4c55f3469e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107346678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.107346678
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2926392671
Short name T744
Test name
Test status
Simulation time 31229671 ps
CPU time 1.98 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 215400 kb
Host smart-8f6edd63-7913-4054-b3a0-4727a6bcabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926392671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2926392671
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2072272472
Short name T291
Test name
Test status
Simulation time 87752457 ps
CPU time 4.12 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 214436 kb
Host smart-000e7cf0-13fe-4ffb-9656-4b2025bb6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072272472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2072272472
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.320300440
Short name T238
Test name
Test status
Simulation time 55139651 ps
CPU time 2.34 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:17 PM PDT 24
Peak memory 207892 kb
Host smart-66df62ef-aa21-4cc9-b7ac-794ee0f19651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320300440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.320300440
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2354286047
Short name T302
Test name
Test status
Simulation time 343546273 ps
CPU time 3.89 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:15 PM PDT 24
Peak memory 210008 kb
Host smart-961d0f63-58f4-4d7f-999a-62a849249a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354286047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2354286047
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1973387906
Short name T678
Test name
Test status
Simulation time 236196481 ps
CPU time 6.55 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 208740 kb
Host smart-3802ebb1-22cd-451e-b966-f31996c63f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973387906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1973387906
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4242396528
Short name T304
Test name
Test status
Simulation time 36137004 ps
CPU time 1.84 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:17 PM PDT 24
Peak memory 206880 kb
Host smart-bbada13b-ecaf-406d-9bca-3b34ee216da5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242396528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4242396528
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1005051460
Short name T451
Test name
Test status
Simulation time 186458665 ps
CPU time 5.1 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:20 PM PDT 24
Peak memory 208148 kb
Host smart-3dfacc91-7ab8-4191-9562-38fcaccfb44b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005051460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1005051460
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3268953058
Short name T430
Test name
Test status
Simulation time 841267844 ps
CPU time 9.55 seconds
Started May 30 03:38:11 PM PDT 24
Finished May 30 03:38:23 PM PDT 24
Peak memory 207252 kb
Host smart-c3ee8287-cf53-4186-ad33-c44d6a10f511
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268953058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3268953058
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1098333166
Short name T879
Test name
Test status
Simulation time 122292222 ps
CPU time 2.69 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 208232 kb
Host smart-782147cb-ba4f-457d-8544-d5af9a2bd5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098333166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1098333166
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2933219193
Short name T606
Test name
Test status
Simulation time 29215898 ps
CPU time 2.03 seconds
Started May 30 03:38:10 PM PDT 24
Finished May 30 03:38:14 PM PDT 24
Peak memory 206696 kb
Host smart-213b138b-2e08-4f1a-b38f-024bfa426cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933219193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2933219193
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2409196180
Short name T226
Test name
Test status
Simulation time 2373926613 ps
CPU time 31.36 seconds
Started May 30 03:38:12 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 222632 kb
Host smart-b2781fd1-1bb2-4f3e-b2d9-c80234d57c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409196180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2409196180
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.247911150
Short name T537
Test name
Test status
Simulation time 2202393867 ps
CPU time 18.3 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 222572 kb
Host smart-658d3ec8-ccc9-45b9-b201-a400ee6ca929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247911150 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.247911150
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3577485435
Short name T478
Test name
Test status
Simulation time 1432525241 ps
CPU time 6.02 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:21 PM PDT 24
Peak memory 207460 kb
Host smart-9a5a0a3f-3cba-494e-955d-edc5246d5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577485435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3577485435
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.998414851
Short name T811
Test name
Test status
Simulation time 259995912 ps
CPU time 2.1 seconds
Started May 30 03:38:13 PM PDT 24
Finished May 30 03:38:18 PM PDT 24
Peak memory 210128 kb
Host smart-0dacf6d6-01d0-4759-b71e-32a1e4e5cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998414851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.998414851
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2822519809
Short name T613
Test name
Test status
Simulation time 25858814 ps
CPU time 0.78 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:27 PM PDT 24
Peak memory 205788 kb
Host smart-7c26f854-9060-4d73-a276-f0222f47146f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822519809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2822519809
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.61774069
Short name T407
Test name
Test status
Simulation time 28529992 ps
CPU time 2.33 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:25 PM PDT 24
Peak memory 214284 kb
Host smart-29e720a5-1c74-4a82-a64f-16bac5e0db3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61774069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.61774069
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4138975796
Short name T840
Test name
Test status
Simulation time 102647928 ps
CPU time 2.47 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 209000 kb
Host smart-fe8b946c-f5d0-4bd2-85f2-41d61f74be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138975796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4138975796
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1348975348
Short name T258
Test name
Test status
Simulation time 397110110 ps
CPU time 4.73 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 210484 kb
Host smart-16691daa-e2f0-44fd-b7c4-0b0d676a43be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348975348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1348975348
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3649664522
Short name T314
Test name
Test status
Simulation time 513923827 ps
CPU time 9.88 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 209912 kb
Host smart-8aa62b27-92e5-421f-a4f0-2719b2a65caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649664522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3649664522
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1223497152
Short name T181
Test name
Test status
Simulation time 31152422 ps
CPU time 2.25 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:24 PM PDT 24
Peak memory 206792 kb
Host smart-31d5b1a7-e35f-4bb5-9655-35fe68fa32fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223497152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1223497152
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.267544971
Short name T195
Test name
Test status
Simulation time 456243381 ps
CPU time 2.68 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 206800 kb
Host smart-e3d255ca-2500-4775-a09a-d89893112024
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267544971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.267544971
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2301885622
Short name T859
Test name
Test status
Simulation time 60357223 ps
CPU time 2.26 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:24 PM PDT 24
Peak memory 206848 kb
Host smart-5ae0aa20-9f93-4a39-b5ea-e5f3a94f0b49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301885622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2301885622
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1452223427
Short name T646
Test name
Test status
Simulation time 60718694 ps
CPU time 3.3 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 207080 kb
Host smart-ef08f1cc-c3eb-4d2a-bf5a-fca95daafaff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452223427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1452223427
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.185455804
Short name T298
Test name
Test status
Simulation time 131783462 ps
CPU time 2.34 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 208516 kb
Host smart-45fe549f-665d-47c5-ad56-51478e2072d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185455804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.185455804
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3912558235
Short name T851
Test name
Test status
Simulation time 24924155 ps
CPU time 1.98 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 208832 kb
Host smart-8b5b8951-3467-4fea-8711-0c5795fa70e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912558235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3912558235
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2482066707
Short name T836
Test name
Test status
Simulation time 1277167926 ps
CPU time 33.64 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 215956 kb
Host smart-9933eff9-83ec-4711-b336-2b1acc20b437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482066707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2482066707
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1022241980
Short name T876
Test name
Test status
Simulation time 686908488 ps
CPU time 4.55 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 214316 kb
Host smart-a9eb3d37-f6ad-43b2-9b75-3585795bfe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022241980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1022241980
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1810963299
Short name T224
Test name
Test status
Simulation time 134180781 ps
CPU time 3.26 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 210960 kb
Host smart-87cc5729-8784-4987-940a-25d010cbf33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810963299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1810963299
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3957985943
Short name T107
Test name
Test status
Simulation time 47651651 ps
CPU time 0.77 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:23 PM PDT 24
Peak memory 205988 kb
Host smart-2cb611eb-efc6-4e23-be74-a9cb73a3a829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957985943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3957985943
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1942690627
Short name T725
Test name
Test status
Simulation time 150623999 ps
CPU time 2.67 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 217564 kb
Host smart-a4553721-3b8b-495d-85c7-5693890bcb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942690627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1942690627
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3157486331
Short name T203
Test name
Test status
Simulation time 91971807 ps
CPU time 1.86 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 208184 kb
Host smart-e6cfd06a-960a-4fb8-8653-0f932b482ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157486331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3157486331
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3701962557
Short name T917
Test name
Test status
Simulation time 78642459 ps
CPU time 3.76 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 217436 kb
Host smart-878c1bfa-7f39-4bd9-829c-e496b5daba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701962557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3701962557
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2137726641
Short name T40
Test name
Test status
Simulation time 106283395 ps
CPU time 3.18 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 222440 kb
Host smart-ee531733-3032-4dc7-9999-e5544f192af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137726641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2137726641
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4022550126
Short name T54
Test name
Test status
Simulation time 241311736 ps
CPU time 2.4 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 214172 kb
Host smart-fbadce04-81c7-497b-8f78-e654f46d2d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022550126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4022550126
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3279356587
Short name T565
Test name
Test status
Simulation time 378737591 ps
CPU time 2.98 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 207272 kb
Host smart-543bd1ef-c306-4087-b8b9-76e4d8762223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279356587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3279356587
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1541430185
Short name T702
Test name
Test status
Simulation time 195808714 ps
CPU time 2.83 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 206520 kb
Host smart-ccfddc1f-7201-4131-9802-9634d2d6b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541430185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1541430185
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3556403818
Short name T466
Test name
Test status
Simulation time 110903495 ps
CPU time 3.23 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 208784 kb
Host smart-b3814956-ac5b-4bb6-aba1-afe5a8cd41ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556403818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3556403818
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2455780730
Short name T553
Test name
Test status
Simulation time 215066231 ps
CPU time 5.46 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:27 PM PDT 24
Peak memory 208132 kb
Host smart-a3464b71-fbe8-4f10-ae80-6f5fadbcf9a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455780730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2455780730
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2526979037
Short name T584
Test name
Test status
Simulation time 211901647 ps
CPU time 2.6 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 207472 kb
Host smart-b889f349-5225-4416-b720-001f749da8f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526979037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2526979037
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.103076342
Short name T885
Test name
Test status
Simulation time 70614895 ps
CPU time 3.15 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 215788 kb
Host smart-53a2417b-72aa-4711-8a3e-84de108e7eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103076342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.103076342
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.4229536673
Short name T511
Test name
Test status
Simulation time 336897244 ps
CPU time 3.05 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 206860 kb
Host smart-e69a470c-1f57-4bba-ae2c-69437884b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229536673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4229536673
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1182712841
Short name T824
Test name
Test status
Simulation time 9020607947 ps
CPU time 53.37 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 222544 kb
Host smart-f04504dc-f5f6-4a61-ae80-289b09ecf43f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182712841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1182712841
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.243134855
Short name T127
Test name
Test status
Simulation time 113114166 ps
CPU time 7.14 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 219612 kb
Host smart-5330ed75-b937-4933-9b71-1c5937547359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243134855 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.243134855
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3699830381
Short name T394
Test name
Test status
Simulation time 321116110 ps
CPU time 4.54 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 206944 kb
Host smart-8c54ed6a-7295-4de0-aa78-39fb66776145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699830381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3699830381
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.489177189
Short name T225
Test name
Test status
Simulation time 163860451 ps
CPU time 2.5 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 209924 kb
Host smart-22064227-375c-41ff-8b92-aaf49d0654aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489177189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.489177189
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.701988649
Short name T108
Test name
Test status
Simulation time 20585400 ps
CPU time 1.07 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 206188 kb
Host smart-e48e345e-7722-47d0-9a1e-cde837ea5380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701988649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.701988649
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2894284675
Short name T743
Test name
Test status
Simulation time 225569160 ps
CPU time 6.65 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 215912 kb
Host smart-fb5e1c33-5108-4b78-97db-a2410c53eca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894284675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2894284675
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.628745661
Short name T776
Test name
Test status
Simulation time 444730251 ps
CPU time 4.88 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 221588 kb
Host smart-f9816338-b8e4-4470-8951-3cdbc9339d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628745661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.628745661
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4158716215
Short name T700
Test name
Test status
Simulation time 300666562 ps
CPU time 3.49 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 218236 kb
Host smart-d5fb1936-aae4-461a-9423-1807b92078cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158716215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4158716215
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2888994163
Short name T182
Test name
Test status
Simulation time 971614591 ps
CPU time 6.16 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 214264 kb
Host smart-8d94587a-1bb3-49ea-b272-986ab9a4814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888994163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2888994163
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2572021420
Short name T710
Test name
Test status
Simulation time 75102844 ps
CPU time 2.01 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 214292 kb
Host smart-73e520fd-4a37-410f-a273-01b35ca58ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572021420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2572021420
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3283407653
Short name T583
Test name
Test status
Simulation time 150452802 ps
CPU time 2.68 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:26 PM PDT 24
Peak memory 222536 kb
Host smart-8521cf17-830b-483a-ac31-081a4a4914f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283407653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3283407653
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3949108854
Short name T805
Test name
Test status
Simulation time 1949265743 ps
CPU time 64.41 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:39:31 PM PDT 24
Peak memory 209036 kb
Host smart-f496de8d-e2e6-422d-81c0-966fcfffe426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949108854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3949108854
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3021638973
Short name T692
Test name
Test status
Simulation time 135681217 ps
CPU time 3.01 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 208388 kb
Host smart-a37a78b2-9a3f-4f46-aae5-286a0a19698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021638973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3021638973
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1894948039
Short name T470
Test name
Test status
Simulation time 68393937 ps
CPU time 2.68 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 208600 kb
Host smart-dae25f0c-df11-4d8b-afdf-852c2dae6bbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894948039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1894948039
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2356468346
Short name T802
Test name
Test status
Simulation time 72227442 ps
CPU time 2.5 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 207372 kb
Host smart-86a0d8d2-5499-4c68-b219-42cc8597fead
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356468346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2356468346
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1484470524
Short name T588
Test name
Test status
Simulation time 6956236525 ps
CPU time 23.59 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 208852 kb
Host smart-f9c2196b-19ba-43c2-8c03-2caa9bb3f07a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484470524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1484470524
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3082829422
Short name T215
Test name
Test status
Simulation time 135203830 ps
CPU time 2.66 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 207580 kb
Host smart-a0e6b9a1-4987-4b48-bf11-c320b3729605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082829422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3082829422
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2381097233
Short name T444
Test name
Test status
Simulation time 181931515 ps
CPU time 4.37 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 207020 kb
Host smart-a3fbd42a-f279-42b7-bbed-a3cdb1747a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381097233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2381097233
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2280227628
Short name T236
Test name
Test status
Simulation time 434233543 ps
CPU time 17.11 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 215860 kb
Host smart-20903121-10c0-4307-820e-1a5b58951cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280227628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2280227628
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4041560127
Short name T392
Test name
Test status
Simulation time 278297731 ps
CPU time 4.83 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 208576 kb
Host smart-e65b9f1d-809c-49d8-9a7a-0dc8d8d237cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041560127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4041560127
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4210225662
Short name T148
Test name
Test status
Simulation time 62947700 ps
CPU time 2.03 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 209976 kb
Host smart-4aa7601b-65b9-4ad8-ad4a-3b86704a6010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210225662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4210225662
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3253332624
Short name T783
Test name
Test status
Simulation time 9661578 ps
CPU time 0.82 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 205952 kb
Host smart-b7046298-6ee6-42de-a58f-be2d07c1b680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253332624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3253332624
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2266829511
Short name T402
Test name
Test status
Simulation time 1668869877 ps
CPU time 8.66 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:35 PM PDT 24
Peak memory 214604 kb
Host smart-853ad5b2-92cb-42ea-95dc-b8ca799440ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266829511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2266829511
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.566969225
Short name T632
Test name
Test status
Simulation time 210529723 ps
CPU time 1.65 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 209112 kb
Host smart-485804f4-322b-4ecd-b0b6-1e157324c367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566969225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.566969225
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1583002705
Short name T456
Test name
Test status
Simulation time 87339047 ps
CPU time 2.37 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 214324 kb
Host smart-0b82b6a9-ffa7-4b5e-8602-dffc5f476ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583002705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1583002705
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3365381336
Short name T37
Test name
Test status
Simulation time 560162930 ps
CPU time 2.94 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 214232 kb
Host smart-1abdb220-76c0-4a09-8252-b7e7d1d74905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365381336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3365381336
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3561207982
Short name T691
Test name
Test status
Simulation time 473649751 ps
CPU time 4.95 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 222384 kb
Host smart-5260b9a9-9e42-48c3-ac7c-aa34c3bfe074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561207982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3561207982
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3102853100
Short name T309
Test name
Test status
Simulation time 164494544 ps
CPU time 3.22 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 214372 kb
Host smart-96bffb65-2ff5-4788-b96b-24d09bd5130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102853100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3102853100
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3460062119
Short name T270
Test name
Test status
Simulation time 259223596 ps
CPU time 3.53 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 208600 kb
Host smart-ea2ad535-a0e6-4003-967d-163d3811e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460062119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3460062119
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.335565463
Short name T281
Test name
Test status
Simulation time 267127937 ps
CPU time 7.29 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 208024 kb
Host smart-8c592706-4c15-4ec9-9bdd-3137a67c3ffe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335565463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.335565463
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.403762991
Short name T490
Test name
Test status
Simulation time 140641230 ps
CPU time 4.63 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 208692 kb
Host smart-a68c5654-7b5f-45f6-b5b8-2b41a7ca8d08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403762991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.403762991
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2189830223
Short name T278
Test name
Test status
Simulation time 437791092 ps
CPU time 5.55 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:35 PM PDT 24
Peak memory 208792 kb
Host smart-6c0d15f5-e95e-4c57-859a-7f62b1432876
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189830223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2189830223
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4126108010
Short name T808
Test name
Test status
Simulation time 64116759 ps
CPU time 2.65 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:26 PM PDT 24
Peak memory 218460 kb
Host smart-6a88c1fe-85ba-4c56-8060-4d243c3f89c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126108010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4126108010
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.359242270
Short name T216
Test name
Test status
Simulation time 766956987 ps
CPU time 8.37 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 207044 kb
Host smart-591aede6-b1ad-4610-b66d-4a031d66bf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359242270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.359242270
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3803937279
Short name T82
Test name
Test status
Simulation time 5434093442 ps
CPU time 86.06 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:39:51 PM PDT 24
Peak memory 217640 kb
Host smart-08f0191a-5ceb-4c3b-b33c-a9d538a629da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803937279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3803937279
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2703193352
Short name T184
Test name
Test status
Simulation time 903693303 ps
CPU time 17.76 seconds
Started May 30 03:38:22 PM PDT 24
Finished May 30 03:38:41 PM PDT 24
Peak memory 222716 kb
Host smart-0ecacc5d-eee6-4a14-94e9-1d29be626ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703193352 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2703193352
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3912871505
Short name T723
Test name
Test status
Simulation time 755887761 ps
CPU time 3.84 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 207784 kb
Host smart-5786cca0-ac41-45ba-80bf-d29173ca62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912871505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3912871505
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.944949998
Short name T454
Test name
Test status
Simulation time 57102520 ps
CPU time 2.06 seconds
Started May 30 03:38:19 PM PDT 24
Finished May 30 03:38:23 PM PDT 24
Peak memory 209700 kb
Host smart-1591ce68-603d-4f56-a2ad-c1e36ec7de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944949998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.944949998
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3766520261
Short name T754
Test name
Test status
Simulation time 38393315 ps
CPU time 0.84 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:38:34 PM PDT 24
Peak memory 205980 kb
Host smart-bd61b9ab-d2cb-4497-94ca-c9195622831c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766520261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3766520261
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.327787030
Short name T65
Test name
Test status
Simulation time 128080520 ps
CPU time 3.61 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 218332 kb
Host smart-9d925516-5231-4f41-8b4c-86d459e1e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327787030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.327787030
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.786939770
Short name T496
Test name
Test status
Simulation time 321153716 ps
CPU time 2.63 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 214348 kb
Host smart-216c4cd7-c0d0-4f5d-a056-04838d24daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786939770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.786939770
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2544534465
Short name T888
Test name
Test status
Simulation time 52262618 ps
CPU time 2.65 seconds
Started May 30 03:38:26 PM PDT 24
Finished May 30 03:38:32 PM PDT 24
Peak memory 216944 kb
Host smart-71c0d3b4-792d-49e0-a039-acfb77364101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544534465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2544534465
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1980720674
Short name T368
Test name
Test status
Simulation time 87801197 ps
CPU time 3.83 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 222504 kb
Host smart-415936ef-0c0f-45b8-a58c-3e4cfcb9a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980720674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1980720674
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.977111534
Short name T403
Test name
Test status
Simulation time 8947657902 ps
CPU time 86.41 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:39:52 PM PDT 24
Peak memory 208136 kb
Host smart-bd58760b-6346-46ca-8c09-99434f84ff98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977111534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.977111534
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2788438415
Short name T535
Test name
Test status
Simulation time 461750093 ps
CPU time 4.14 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 206832 kb
Host smart-97e23cee-68f5-435c-a8fa-2a56ebbaefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788438415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2788438415
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.139368625
Short name T292
Test name
Test status
Simulation time 470298302 ps
CPU time 4.25 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:35 PM PDT 24
Peak memory 208972 kb
Host smart-5b6a2c0c-ea52-4e2a-8f57-cf9858bfd2f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139368625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.139368625
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.34958734
Short name T894
Test name
Test status
Simulation time 367807229 ps
CPU time 2.64 seconds
Started May 30 03:38:23 PM PDT 24
Finished May 30 03:38:28 PM PDT 24
Peak memory 208616 kb
Host smart-1129b8bb-47f9-41c8-947f-9314050039d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.34958734
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2038036381
Short name T581
Test name
Test status
Simulation time 1139827227 ps
CPU time 6.41 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 208036 kb
Host smart-ca29ba97-ce93-471d-9b8f-8a303ac06518
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038036381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2038036381
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2144843290
Short name T865
Test name
Test status
Simulation time 205227848 ps
CPU time 2.67 seconds
Started May 30 03:38:28 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 209132 kb
Host smart-5666c29d-3943-4960-9f52-b07b742b555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144843290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2144843290
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1444437519
Short name T504
Test name
Test status
Simulation time 483957180 ps
CPU time 11.08 seconds
Started May 30 03:38:21 PM PDT 24
Finished May 30 03:38:33 PM PDT 24
Peak memory 208404 kb
Host smart-8972f45e-83bf-4d9f-985c-2199c488d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444437519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1444437519
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4137304990
Short name T775
Test name
Test status
Simulation time 35085125495 ps
CPU time 133.96 seconds
Started May 30 03:38:24 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 222136 kb
Host smart-a9825b4b-2ac6-46d4-90a5-8ec1558ddd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137304990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4137304990
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3675960591
Short name T915
Test name
Test status
Simulation time 4042359230 ps
CPU time 7.91 seconds
Started May 30 03:38:27 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 208084 kb
Host smart-bf9e24bf-b3ed-4c28-b3c1-f0f5d8a8dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675960591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3675960591
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1109077602
Short name T149
Test name
Test status
Simulation time 102631622 ps
CPU time 3.74 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 210244 kb
Host smart-9e6dc96c-01eb-4692-b2cf-f5c2446526b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109077602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1109077602
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1512215259
Short name T106
Test name
Test status
Simulation time 83842983 ps
CPU time 0.88 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:38:34 PM PDT 24
Peak memory 205956 kb
Host smart-57a7b38c-6141-40a6-a927-40c9c27f129f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512215259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1512215259
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.122713594
Short name T414
Test name
Test status
Simulation time 359947775 ps
CPU time 10.35 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 215048 kb
Host smart-1a60cb7c-65d4-475c-ae6a-f5c301a05d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122713594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.122713594
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2652323022
Short name T813
Test name
Test status
Simulation time 69285695 ps
CPU time 2.08 seconds
Started May 30 03:38:34 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 208312 kb
Host smart-97d04365-ced9-4b23-a0d6-3ab66807abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652323022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2652323022
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.285728925
Short name T799
Test name
Test status
Simulation time 107116833 ps
CPU time 2.86 seconds
Started May 30 03:38:40 PM PDT 24
Finished May 30 03:38:44 PM PDT 24
Peak memory 214296 kb
Host smart-3311095c-e59b-40a4-8424-77049bc59fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285728925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.285728925
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.894612997
Short name T801
Test name
Test status
Simulation time 102975455 ps
CPU time 2.1 seconds
Started May 30 03:38:37 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 214732 kb
Host smart-e1addc46-8cf7-433b-aa6e-090ab5ff770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894612997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.894612997
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3180154417
Short name T207
Test name
Test status
Simulation time 362896217 ps
CPU time 4.16 seconds
Started May 30 03:38:34 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 207596 kb
Host smart-973b1696-16fb-4dc5-9cf9-a1d02a03d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180154417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3180154417
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4111681089
Short name T759
Test name
Test status
Simulation time 1046353952 ps
CPU time 28.92 seconds
Started May 30 03:38:31 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 208112 kb
Host smart-f8d7f920-6206-4c11-b0a2-062a45093971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111681089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4111681089
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4045834433
Short name T471
Test name
Test status
Simulation time 39324162 ps
CPU time 1.72 seconds
Started May 30 03:38:41 PM PDT 24
Finished May 30 03:38:44 PM PDT 24
Peak memory 207020 kb
Host smart-bfc0107f-0061-49be-ac46-59b0e5c02401
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045834433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4045834433
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.538592732
Short name T220
Test name
Test status
Simulation time 83609007 ps
CPU time 3.5 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:31 PM PDT 24
Peak memory 208396 kb
Host smart-ccaada52-1ef4-45ac-9bb4-902a2c15893d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538592732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.538592732
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2124070709
Short name T267
Test name
Test status
Simulation time 157984022 ps
CPU time 3.77 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 208908 kb
Host smart-38afdc00-4fa2-40c2-ba09-5aea63cfabb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124070709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2124070709
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1616653248
Short name T571
Test name
Test status
Simulation time 46959445 ps
CPU time 2.71 seconds
Started May 30 03:38:33 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 209428 kb
Host smart-711d3de5-3c94-417f-a4eb-d12069ccdc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616653248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1616653248
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.211793390
Short name T521
Test name
Test status
Simulation time 45524108 ps
CPU time 2.43 seconds
Started May 30 03:38:25 PM PDT 24
Finished May 30 03:38:30 PM PDT 24
Peak memory 206852 kb
Host smart-f25d3525-2d40-44bd-b733-378cb7d539ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211793390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.211793390
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3712067688
Short name T696
Test name
Test status
Simulation time 564829615 ps
CPU time 4.18 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 209440 kb
Host smart-99ba373d-f41e-4f64-8553-29ba642b8ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712067688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3712067688
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3428887786
Short name T822
Test name
Test status
Simulation time 127722090 ps
CPU time 1.77 seconds
Started May 30 03:38:37 PM PDT 24
Finished May 30 03:38:41 PM PDT 24
Peak memory 209772 kb
Host smart-5b749a81-6a7b-46db-a2f2-dc31424a00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428887786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3428887786
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1039465305
Short name T661
Test name
Test status
Simulation time 22327564 ps
CPU time 0.82 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 205916 kb
Host smart-5dff18f0-7c9b-48df-ad1f-db856ca93180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039465305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1039465305
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3481042878
Short name T401
Test name
Test status
Simulation time 47174883 ps
CPU time 3.17 seconds
Started May 30 03:38:33 PM PDT 24
Finished May 30 03:38:38 PM PDT 24
Peak memory 214424 kb
Host smart-84c1e87c-583b-4fb5-b3c4-22261db91415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481042878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3481042878
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.513374871
Short name T34
Test name
Test status
Simulation time 234177190 ps
CPU time 2.74 seconds
Started May 30 03:38:31 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 210964 kb
Host smart-607d7787-0a40-41cd-b313-447eaa4d33b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513374871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.513374871
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3310627083
Short name T318
Test name
Test status
Simulation time 73985364 ps
CPU time 1.47 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 207472 kb
Host smart-c337e02a-5f1f-4721-ac09-c1abe09f1601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310627083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3310627083
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1887075636
Short name T103
Test name
Test status
Simulation time 343323888 ps
CPU time 5.06 seconds
Started May 30 03:38:29 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 214296 kb
Host smart-5bf20903-fe08-45d3-8f72-9cc4611a6fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887075636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1887075636
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2588765741
Short name T47
Test name
Test status
Simulation time 109615501 ps
CPU time 3.58 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:38:41 PM PDT 24
Peak memory 214284 kb
Host smart-6de8bf4f-b43f-48a8-b17d-48c2f74e2407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588765741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2588765741
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1700747875
Short name T745
Test name
Test status
Simulation time 223370706 ps
CPU time 4.79 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 219908 kb
Host smart-f21b74ac-5bd4-422f-8780-dc2e7f13527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700747875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1700747875
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1195544807
Short name T628
Test name
Test status
Simulation time 233442015 ps
CPU time 4.88 seconds
Started May 30 03:38:37 PM PDT 24
Finished May 30 03:38:44 PM PDT 24
Peak memory 218396 kb
Host smart-df9a58a9-a25b-43d1-a6e4-0811653c4d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195544807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1195544807
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3244509681
Short name T558
Test name
Test status
Simulation time 151169611 ps
CPU time 2.78 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 208952 kb
Host smart-5e3515cb-4e4d-4c57-964e-d05749df3b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244509681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3244509681
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1646513076
Short name T209
Test name
Test status
Simulation time 84983073 ps
CPU time 4.02 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 209092 kb
Host smart-640e2e5a-07b3-432c-8ce4-67b243732728
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646513076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1646513076
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1191415590
Short name T297
Test name
Test status
Simulation time 197129595 ps
CPU time 2.65 seconds
Started May 30 03:38:31 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 208976 kb
Host smart-83e55373-d449-4619-8685-46f8de9c73a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191415590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1191415590
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3572806710
Short name T621
Test name
Test status
Simulation time 863444080 ps
CPU time 2.68 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 206880 kb
Host smart-ef644bd2-0f48-41b1-965a-f05d741810cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572806710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3572806710
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.493116230
Short name T315
Test name
Test status
Simulation time 5569906555 ps
CPU time 23.99 seconds
Started May 30 03:38:37 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 208740 kb
Host smart-fc5b42ce-88d3-4529-9bfa-72caebc66eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493116230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.493116230
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.27979573
Short name T211
Test name
Test status
Simulation time 1641328714 ps
CPU time 8.97 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:38:46 PM PDT 24
Peak memory 208584 kb
Host smart-7ec785c1-4ffe-45c6-9668-6e804bacc63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27979573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.27979573
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4236142357
Short name T607
Test name
Test status
Simulation time 871627021 ps
CPU time 5.49 seconds
Started May 30 03:38:42 PM PDT 24
Finished May 30 03:38:48 PM PDT 24
Peak memory 210812 kb
Host smart-c6745fcb-d2ad-450b-b7a3-1fd7822c8622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236142357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4236142357
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.256374529
Short name T576
Test name
Test status
Simulation time 68466647 ps
CPU time 0.87 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 205948 kb
Host smart-65278be6-7623-40c6-b8d2-f0f7e7c98204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256374529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.256374529
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2335196878
Short name T737
Test name
Test status
Simulation time 71938980 ps
CPU time 2.59 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 207920 kb
Host smart-c8b43632-553c-4803-b71e-942e72a8649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335196878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2335196878
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.651639206
Short name T382
Test name
Test status
Simulation time 83555405 ps
CPU time 2.81 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 214360 kb
Host smart-544c3aeb-cd3d-4442-a58b-558212944739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651639206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.651639206
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4242297686
Short name T306
Test name
Test status
Simulation time 454800240 ps
CPU time 5.83 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 222424 kb
Host smart-f590913c-2efa-41b5-b3e8-f34b0c0d6a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242297686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4242297686
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.68472760
Short name T60
Test name
Test status
Simulation time 55824281 ps
CPU time 2.17 seconds
Started May 30 03:38:37 PM PDT 24
Finished May 30 03:38:41 PM PDT 24
Peak memory 214352 kb
Host smart-dcc6905a-0646-41e6-b2b4-a36cdf3b1cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68472760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.68472760
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2763712207
Short name T374
Test name
Test status
Simulation time 349489426 ps
CPU time 7.47 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:38:45 PM PDT 24
Peak memory 210436 kb
Host smart-5134a47e-1362-478a-879c-a828a6a0f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763712207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2763712207
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3531442104
Short name T327
Test name
Test status
Simulation time 63901793 ps
CPU time 2.37 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 206804 kb
Host smart-cc4799d4-7dc6-4f19-a94b-7f682ac24d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531442104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3531442104
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1668234764
Short name T197
Test name
Test status
Simulation time 13834334871 ps
CPU time 37.49 seconds
Started May 30 03:38:29 PM PDT 24
Finished May 30 03:39:09 PM PDT 24
Peak memory 209024 kb
Host smart-eaa9d655-6d9c-4700-aa5e-00d538b529ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668234764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1668234764
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1964873605
Short name T334
Test name
Test status
Simulation time 102424939 ps
CPU time 4.6 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:44 PM PDT 24
Peak memory 208756 kb
Host smart-1b127309-b0a1-454f-8b94-011569e42f8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964873605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1964873605
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2569110127
Short name T544
Test name
Test status
Simulation time 227200625 ps
CPU time 6.64 seconds
Started May 30 03:38:31 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 208800 kb
Host smart-d84b7d4c-8bcf-4156-8829-a2d3c57810f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569110127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2569110127
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1783182114
Short name T518
Test name
Test status
Simulation time 306870835 ps
CPU time 2.01 seconds
Started May 30 03:38:32 PM PDT 24
Finished May 30 03:38:36 PM PDT 24
Peak memory 215416 kb
Host smart-4418a569-fec7-4cb8-8c1e-4499d8404c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783182114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1783182114
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2382489538
Short name T821
Test name
Test status
Simulation time 374801776 ps
CPU time 2.81 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 208548 kb
Host smart-4887c3b2-2ed9-4242-9980-d40fcb8f0ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382489538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2382489538
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3742739093
Short name T889
Test name
Test status
Simulation time 2636356226 ps
CPU time 21.02 seconds
Started May 30 03:38:40 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 216976 kb
Host smart-2137f03e-69fd-4960-8641-c47200f73a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742739093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3742739093
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2989123941
Short name T111
Test name
Test status
Simulation time 258354073 ps
CPU time 10.59 seconds
Started May 30 03:38:36 PM PDT 24
Finished May 30 03:38:48 PM PDT 24
Peak memory 222656 kb
Host smart-fe320a2f-8b72-41a3-a5a6-913953e3897a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989123941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2989123941
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.880298400
Short name T794
Test name
Test status
Simulation time 1188601522 ps
CPU time 5.52 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:42 PM PDT 24
Peak memory 214336 kb
Host smart-faf27476-ebcb-4684-8688-15a1d06633a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880298400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.880298400
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3012355045
Short name T901
Test name
Test status
Simulation time 259115935 ps
CPU time 3.93 seconds
Started May 30 03:38:30 PM PDT 24
Finished May 30 03:38:37 PM PDT 24
Peak memory 210576 kb
Host smart-1c05fdb8-51f5-4034-8bc9-6b83e72c7196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012355045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3012355045
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3274339990
Short name T449
Test name
Test status
Simulation time 59994450 ps
CPU time 0.79 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 205944 kb
Host smart-79d7bbaa-056b-4b7b-a7ff-e2195e300047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274339990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3274339990
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.507908751
Short name T410
Test name
Test status
Simulation time 2060710206 ps
CPU time 103.83 seconds
Started May 30 03:36:26 PM PDT 24
Finished May 30 03:38:12 PM PDT 24
Peak memory 215500 kb
Host smart-077f20c3-d217-4d1e-abb8-aa28be13cf39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507908751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.507908751
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.396799196
Short name T24
Test name
Test status
Simulation time 274874198 ps
CPU time 2.97 seconds
Started May 30 03:36:26 PM PDT 24
Finished May 30 03:36:31 PM PDT 24
Peak memory 222512 kb
Host smart-2f00d854-a686-49f6-bed1-354d6e1a0383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396799196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.396799196
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3358373019
Short name T362
Test name
Test status
Simulation time 31768116 ps
CPU time 1.97 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 208012 kb
Host smart-0778665e-8118-42ad-b06e-727fdde50911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358373019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3358373019
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2108110255
Short name T740
Test name
Test status
Simulation time 232180194 ps
CPU time 5.2 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:33 PM PDT 24
Peak memory 214328 kb
Host smart-970f87e6-48c4-478e-9863-33e08b96a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108110255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2108110255
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.606118745
Short name T464
Test name
Test status
Simulation time 72684341 ps
CPU time 2.46 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:29 PM PDT 24
Peak memory 206432 kb
Host smart-a03cd0d6-3bf4-4f60-b2cd-3c6e7fbaa3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606118745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.606118745
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3719172377
Short name T376
Test name
Test status
Simulation time 99834227 ps
CPU time 2.2 seconds
Started May 30 03:36:21 PM PDT 24
Finished May 30 03:36:26 PM PDT 24
Peak memory 208192 kb
Host smart-5b15525f-bd94-4a65-a6e5-66ca3599af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719172377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3719172377
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3621286856
Short name T338
Test name
Test status
Simulation time 38284308 ps
CPU time 2.78 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 208500 kb
Host smart-4223b693-023f-404c-8b74-43ef640c40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621286856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3621286856
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1260106262
Short name T341
Test name
Test status
Simulation time 337174558 ps
CPU time 3.44 seconds
Started May 30 03:36:26 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 208344 kb
Host smart-9b330fe2-5a47-4e28-8893-fd3322f121f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260106262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1260106262
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.661858381
Short name T295
Test name
Test status
Simulation time 86902944 ps
CPU time 4.14 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 208592 kb
Host smart-c3fc6480-890b-4c19-9b6b-84ed7d4d08a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661858381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.661858381
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1722362359
Short name T437
Test name
Test status
Simulation time 64439149 ps
CPU time 3.03 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 208960 kb
Host smart-b770e25f-6b33-47f9-8d54-5e21bbba159a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722362359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1722362359
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1484591174
Short name T4
Test name
Test status
Simulation time 88788502 ps
CPU time 1.91 seconds
Started May 30 03:36:24 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 209656 kb
Host smart-0fc759bd-5685-48fc-b041-6208bee1ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484591174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1484591174
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2207940919
Short name T396
Test name
Test status
Simulation time 218731196 ps
CPU time 2.97 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:30 PM PDT 24
Peak memory 207032 kb
Host smart-ae75c040-c9a8-4145-8c72-2eae2c773310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207940919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2207940919
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.636126584
Short name T548
Test name
Test status
Simulation time 376335385 ps
CPU time 3.75 seconds
Started May 30 03:36:25 PM PDT 24
Finished May 30 03:36:31 PM PDT 24
Peak memory 209868 kb
Host smart-6659bd3a-b462-4bf3-88b1-1843906c0fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636126584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.636126584
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3681720490
Short name T369
Test name
Test status
Simulation time 3634004013 ps
CPU time 46.27 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:37:12 PM PDT 24
Peak memory 210224 kb
Host smart-16db8f25-1f69-4b6a-81e8-d01845c98694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681720490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3681720490
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2478881526
Short name T388
Test name
Test status
Simulation time 51158491 ps
CPU time 1.81 seconds
Started May 30 03:36:23 PM PDT 24
Finished May 30 03:36:28 PM PDT 24
Peak memory 209904 kb
Host smart-232acd63-21da-429c-8daf-500f21d56e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478881526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2478881526
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1479957178
Short name T86
Test name
Test status
Simulation time 16755079 ps
CPU time 0.95 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 205952 kb
Host smart-ea487fdb-3308-4dec-aa60-a53ac116bc48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479957178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1479957178
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3982286632
Short name T786
Test name
Test status
Simulation time 415874585 ps
CPU time 4.39 seconds
Started May 30 03:38:43 PM PDT 24
Finished May 30 03:38:48 PM PDT 24
Peak memory 220240 kb
Host smart-b8301dd7-b3e4-4f28-bdbc-9a0f18608a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982286632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3982286632
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3076776582
Short name T74
Test name
Test status
Simulation time 1807725455 ps
CPU time 17.06 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:58 PM PDT 24
Peak memory 208304 kb
Host smart-e9aad6c5-a1f5-4478-a6bc-085714f42e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076776582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3076776582
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3114310559
Short name T105
Test name
Test status
Simulation time 258032311 ps
CPU time 7.33 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:55 PM PDT 24
Peak memory 214332 kb
Host smart-41a92a0d-f663-4a07-8702-18e2f31a4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114310559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3114310559
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.366281677
Short name T847
Test name
Test status
Simulation time 284976284 ps
CPU time 2.57 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:48 PM PDT 24
Peak memory 214288 kb
Host smart-4980cf46-c2ab-4e5a-9954-bf99112eec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366281677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.366281677
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.748650179
Short name T761
Test name
Test status
Simulation time 500842964 ps
CPU time 4.58 seconds
Started May 30 03:38:47 PM PDT 24
Finished May 30 03:38:53 PM PDT 24
Peak memory 214312 kb
Host smart-16b0b838-bff6-4a23-bf1a-1fee4decfbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748650179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.748650179
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2575742009
Short name T715
Test name
Test status
Simulation time 495940043 ps
CPU time 15.59 seconds
Started May 30 03:38:39 PM PDT 24
Finished May 30 03:38:57 PM PDT 24
Peak memory 218620 kb
Host smart-1fd80867-b55d-4afa-90ea-574cff90b554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575742009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2575742009
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2836410920
Short name T797
Test name
Test status
Simulation time 63500734 ps
CPU time 2.37 seconds
Started May 30 03:38:34 PM PDT 24
Finished May 30 03:38:38 PM PDT 24
Peak memory 206796 kb
Host smart-d0cb45bd-85ff-4430-b42f-133d313f00e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836410920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2836410920
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.799646829
Short name T732
Test name
Test status
Simulation time 255403877 ps
CPU time 3.34 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:40 PM PDT 24
Peak memory 206892 kb
Host smart-1d0ebb05-864a-4073-ab59-6774dcc1ee7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799646829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.799646829
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1116060056
Short name T779
Test name
Test status
Simulation time 270745050 ps
CPU time 3.36 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:43 PM PDT 24
Peak memory 208912 kb
Host smart-f6e2bcb0-1879-4b6d-9d9b-081c15904c13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116060056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1116060056
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.540543676
Short name T358
Test name
Test status
Simulation time 1464267156 ps
CPU time 11.2 seconds
Started May 30 03:38:38 PM PDT 24
Finished May 30 03:38:51 PM PDT 24
Peak memory 208540 kb
Host smart-e71a2059-d092-49f3-9b6d-62500b9c3900
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540543676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.540543676
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2977329400
Short name T807
Test name
Test status
Simulation time 64093887 ps
CPU time 3.36 seconds
Started May 30 03:38:48 PM PDT 24
Finished May 30 03:38:53 PM PDT 24
Peak memory 209544 kb
Host smart-53dae29f-4a54-4142-ac9d-66d888867f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977329400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2977329400
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4184474171
Short name T212
Test name
Test status
Simulation time 35051750 ps
CPU time 2.22 seconds
Started May 30 03:38:35 PM PDT 24
Finished May 30 03:38:39 PM PDT 24
Peak memory 206688 kb
Host smart-55934d66-c8f7-448f-a085-6466b9fe5145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184474171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4184474171
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2211440086
Short name T190
Test name
Test status
Simulation time 1317256752 ps
CPU time 39.16 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 222508 kb
Host smart-713d6cc3-7606-459e-be1c-5b7c4cc485ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211440086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2211440086
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.803752443
Short name T11
Test name
Test status
Simulation time 116086216 ps
CPU time 4.08 seconds
Started May 30 03:38:47 PM PDT 24
Finished May 30 03:38:52 PM PDT 24
Peak memory 214356 kb
Host smart-e6f18ff7-bbeb-4cd2-81eb-823b1e2ffac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803752443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.803752443
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4027564304
Short name T705
Test name
Test status
Simulation time 67432830 ps
CPU time 2.42 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:49 PM PDT 24
Peak memory 209892 kb
Host smart-2a3626c4-f3bd-43b7-b6bb-28da4eb999cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027564304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4027564304
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.48460248
Short name T443
Test name
Test status
Simulation time 17906050 ps
CPU time 0.91 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 206120 kb
Host smart-cf095e9e-e353-428d-a4a1-a3136bbe3438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48460248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.48460248
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2186658706
Short name T418
Test name
Test status
Simulation time 384048660 ps
CPU time 6.72 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:53 PM PDT 24
Peak memory 215588 kb
Host smart-fbda7508-c018-4ec7-a392-c07beae9a0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186658706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2186658706
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2354999065
Short name T508
Test name
Test status
Simulation time 33093361 ps
CPU time 1.83 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:47 PM PDT 24
Peak memory 208188 kb
Host smart-9a743b01-ac91-40cf-867b-99bbea3273f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354999065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2354999065
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3909289200
Short name T650
Test name
Test status
Simulation time 312773060 ps
CPU time 2.77 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:49 PM PDT 24
Peak memory 214460 kb
Host smart-80fd47a0-8bfd-45e6-9d89-d537b3be382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909289200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3909289200
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3028265932
Short name T556
Test name
Test status
Simulation time 48255703 ps
CPU time 3.1 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:49 PM PDT 24
Peak memory 214264 kb
Host smart-6a8d1947-2716-4d66-a483-e56933f850d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028265932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3028265932
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3615075653
Short name T796
Test name
Test status
Simulation time 72910674 ps
CPU time 2.49 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:50 PM PDT 24
Peak memory 206620 kb
Host smart-2358a6ff-c0af-492d-b7f6-2c53dcb15817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615075653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3615075653
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1820909180
Short name T590
Test name
Test status
Simulation time 206444537 ps
CPU time 4.76 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:52 PM PDT 24
Peak memory 208000 kb
Host smart-4b16ba04-2a6e-4254-a5be-a9a42a83a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820909180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1820909180
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3625005836
Short name T681
Test name
Test status
Simulation time 340307250 ps
CPU time 5.15 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:51 PM PDT 24
Peak memory 208520 kb
Host smart-f14ea019-2aac-422a-8ce7-699d87e40eec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625005836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3625005836
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2977777893
Short name T497
Test name
Test status
Simulation time 81289283 ps
CPU time 2.91 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:48 PM PDT 24
Peak memory 208580 kb
Host smart-715add07-9f0f-44ea-a35b-8ac52d6780a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977777893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2977777893
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1175317821
Short name T733
Test name
Test status
Simulation time 202273215 ps
CPU time 3.01 seconds
Started May 30 03:38:44 PM PDT 24
Finished May 30 03:38:49 PM PDT 24
Peak memory 207472 kb
Host smart-e0c72dc5-aacd-468a-8001-ccecbf12cca4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175317821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1175317821
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1768110405
Short name T770
Test name
Test status
Simulation time 250402413 ps
CPU time 4.77 seconds
Started May 30 03:38:49 PM PDT 24
Finished May 30 03:38:55 PM PDT 24
Peak memory 208412 kb
Host smart-d41f73dc-ee97-41d9-83be-cd4be4b9e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768110405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1768110405
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3237878002
Short name T423
Test name
Test status
Simulation time 49426695 ps
CPU time 2.42 seconds
Started May 30 03:38:48 PM PDT 24
Finished May 30 03:38:52 PM PDT 24
Peak memory 206868 kb
Host smart-82ba2b1a-d0b1-4880-8594-6963904480c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237878002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3237878002
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2930110173
Short name T52
Test name
Test status
Simulation time 228802500 ps
CPU time 7.15 seconds
Started May 30 03:38:47 PM PDT 24
Finished May 30 03:38:55 PM PDT 24
Peak memory 222512 kb
Host smart-cc8df271-6c56-4c1f-8ecf-c15919b69a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930110173 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2930110173
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2439319612
Short name T907
Test name
Test status
Simulation time 584435176 ps
CPU time 6.72 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:54 PM PDT 24
Peak memory 208616 kb
Host smart-ab76064c-c693-47c4-807b-7c906285f187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439319612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2439319612
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1366731973
Short name T567
Test name
Test status
Simulation time 86354594 ps
CPU time 2.7 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:49 PM PDT 24
Peak memory 210804 kb
Host smart-72a0ea43-03cf-46bf-8a81-1c0652b1941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366731973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1366731973
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1811741125
Short name T574
Test name
Test status
Simulation time 19100358 ps
CPU time 0.83 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:57 PM PDT 24
Peak memory 205968 kb
Host smart-5f3235a8-2f8d-4a1d-b01d-65431108caa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811741125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1811741125
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2222779452
Short name T274
Test name
Test status
Simulation time 5539065146 ps
CPU time 78.28 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:40:15 PM PDT 24
Peak memory 214440 kb
Host smart-e8ee0b67-c1eb-4bd3-a989-2fe7629cea06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222779452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2222779452
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2300006329
Short name T29
Test name
Test status
Simulation time 184079793 ps
CPU time 2.83 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 214264 kb
Host smart-e2656901-218f-419a-a40f-f7129b497e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300006329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2300006329
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.88564303
Short name T630
Test name
Test status
Simulation time 151410600 ps
CPU time 2.88 seconds
Started May 30 03:38:53 PM PDT 24
Finished May 30 03:38:58 PM PDT 24
Peak memory 208056 kb
Host smart-4bbab8b2-9ac7-46ce-855b-e6ef7aa392cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88564303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.88564303
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1220422982
Short name T902
Test name
Test status
Simulation time 382019525 ps
CPU time 2.53 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:59 PM PDT 24
Peak memory 214376 kb
Host smart-8a0bd25c-5676-4990-86eb-a6ca26ce1a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220422982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1220422982
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.534288340
Short name T84
Test name
Test status
Simulation time 61035462 ps
CPU time 3.15 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 214260 kb
Host smart-5ffa5e87-0978-4d73-8002-22f1fe9a9f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534288340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.534288340
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.258385670
Short name T235
Test name
Test status
Simulation time 132680789 ps
CPU time 3.13 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 207464 kb
Host smart-36aaa284-39d9-4b8c-b891-c174ce2953ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258385670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.258385670
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.960965188
Short name T257
Test name
Test status
Simulation time 2054204844 ps
CPU time 13.53 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 209048 kb
Host smart-024f3668-d610-49c8-9ecc-a7e19b9bfcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960965188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.960965188
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.272457541
Short name T698
Test name
Test status
Simulation time 97780759 ps
CPU time 2.65 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:50 PM PDT 24
Peak memory 206776 kb
Host smart-ac896090-f96f-483e-ad1a-8a8c9ab78a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272457541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.272457541
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3348858457
Short name T623
Test name
Test status
Simulation time 191506039 ps
CPU time 2.78 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:50 PM PDT 24
Peak memory 207848 kb
Host smart-0f38443f-3e40-4868-8b63-83f4a27824c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348858457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3348858457
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.182683512
Short name T810
Test name
Test status
Simulation time 1073899715 ps
CPU time 8.18 seconds
Started May 30 03:38:45 PM PDT 24
Finished May 30 03:38:55 PM PDT 24
Peak memory 208692 kb
Host smart-28a8c865-54d8-44d2-bb9f-0aad7dbb35d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182683512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.182683512
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2683640227
Short name T570
Test name
Test status
Simulation time 132554785 ps
CPU time 4.25 seconds
Started May 30 03:38:50 PM PDT 24
Finished May 30 03:38:56 PM PDT 24
Peak memory 208532 kb
Host smart-79ce62d8-64f3-4b1c-a45e-da6319c0bc76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683640227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2683640227
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.318442537
Short name T629
Test name
Test status
Simulation time 1563305474 ps
CPU time 14.71 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 208956 kb
Host smart-8256d950-8c34-422f-9d7b-82e5c9301386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318442537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.318442537
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2177256931
Short name T422
Test name
Test status
Simulation time 68344566 ps
CPU time 2.54 seconds
Started May 30 03:38:46 PM PDT 24
Finished May 30 03:38:50 PM PDT 24
Peak memory 207328 kb
Host smart-da047c18-e83c-4f68-a4c2-dd6103ef471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177256931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2177256931
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2246649420
Short name T188
Test name
Test status
Simulation time 2239877904 ps
CPU time 45.69 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:42 PM PDT 24
Peak memory 221892 kb
Host smart-c804b505-5a7c-4277-8d3a-14c88ed75480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246649420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2246649420
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1011499378
Short name T174
Test name
Test status
Simulation time 222076449 ps
CPU time 5.83 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 220460 kb
Host smart-594cdb2c-0002-4d7f-b89f-fd933b30a338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011499378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1011499378
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.334566968
Short name T842
Test name
Test status
Simulation time 122140857 ps
CPU time 5.55 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 207560 kb
Host smart-9ce267cc-a503-4588-8cb8-936e71fe1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334566968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.334566968
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1564899880
Short name T390
Test name
Test status
Simulation time 150959412 ps
CPU time 2 seconds
Started May 30 03:38:55 PM PDT 24
Finished May 30 03:38:59 PM PDT 24
Peak memory 209968 kb
Host smart-ddcb9787-c0da-415c-bd4b-29f8369e47e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564899880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1564899880
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2697592998
Short name T519
Test name
Test status
Simulation time 14753844 ps
CPU time 0.91 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:56 PM PDT 24
Peak memory 206060 kb
Host smart-98662feb-aa4d-43b5-b3bb-e5d5474b9764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697592998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2697592998
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.604082068
Short name T132
Test name
Test status
Simulation time 102354381 ps
CPU time 6.42 seconds
Started May 30 03:39:00 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 215252 kb
Host smart-a43bb13c-f189-455c-8154-02326a384206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604082068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.604082068
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3075358582
Short name T793
Test name
Test status
Simulation time 117201806 ps
CPU time 2.3 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 220508 kb
Host smart-7f42c129-c724-4159-80e1-cbb4a16ce3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075358582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3075358582
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1662162382
Short name T72
Test name
Test status
Simulation time 357575608 ps
CPU time 4.45 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 209324 kb
Host smart-3c9cf3ad-7be0-4a1d-a493-81b5eff26ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662162382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1662162382
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1680045955
Short name T364
Test name
Test status
Simulation time 87860691 ps
CPU time 3.88 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:59 PM PDT 24
Peak memory 214296 kb
Host smart-3ef027d7-07a4-4422-b81f-88fbb6d3cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680045955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1680045955
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.427644602
Short name T229
Test name
Test status
Simulation time 45533615 ps
CPU time 2.34 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 209692 kb
Host smart-8224daee-cf30-4ecb-bb99-1d5363c072c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427644602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.427644602
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.738874914
Short name T310
Test name
Test status
Simulation time 295327267 ps
CPU time 3.83 seconds
Started May 30 03:38:55 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 209084 kb
Host smart-69eda8a8-ad57-49b6-b6ec-19af840b3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738874914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.738874914
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.135656432
Short name T910
Test name
Test status
Simulation time 1422708322 ps
CPU time 37.72 seconds
Started May 30 03:38:53 PM PDT 24
Finished May 30 03:39:33 PM PDT 24
Peak memory 208276 kb
Host smart-67987d8c-e862-46ad-811d-56838c18a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135656432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.135656432
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2647115477
Short name T476
Test name
Test status
Simulation time 221260131 ps
CPU time 2.72 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:59 PM PDT 24
Peak memory 207036 kb
Host smart-b48f104b-f4fc-4c07-8811-74af27997892
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647115477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2647115477
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3474812962
Short name T445
Test name
Test status
Simulation time 279697490 ps
CPU time 4.07 seconds
Started May 30 03:39:00 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 208672 kb
Host smart-7d794bfd-039f-4a5d-821a-416b13f807e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474812962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3474812962
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1914103541
Short name T492
Test name
Test status
Simulation time 654041210 ps
CPU time 15.23 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:14 PM PDT 24
Peak memory 207900 kb
Host smart-fcf5c753-3cd2-482f-bd77-3042d067278d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914103541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1914103541
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1039788900
Short name T563
Test name
Test status
Simulation time 62319904 ps
CPU time 2.59 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 209092 kb
Host smart-adf21c9f-a9e8-4dd3-bc50-251117df7505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039788900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1039788900
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.570280395
Short name T453
Test name
Test status
Simulation time 121981406 ps
CPU time 3.02 seconds
Started May 30 03:38:53 PM PDT 24
Finished May 30 03:38:57 PM PDT 24
Peak memory 208320 kb
Host smart-61b2af33-e141-4762-8d02-9a54774fd48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570280395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.570280395
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.339347658
Short name T191
Test name
Test status
Simulation time 1037466469 ps
CPU time 37.4 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:33 PM PDT 24
Peak memory 222412 kb
Host smart-62b72e67-1478-40e8-874c-839492dedb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339347658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.339347658
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.488548749
Short name T348
Test name
Test status
Simulation time 196986536 ps
CPU time 4.11 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 214352 kb
Host smart-575e5272-8318-4c70-964f-6ecadb6a7620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488548749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.488548749
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.368635241
Short name T644
Test name
Test status
Simulation time 175082049 ps
CPU time 2.5 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 210040 kb
Host smart-b34c5bce-3ccb-43ac-a4f8-5369a5b99d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368635241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.368635241
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4218932942
Short name T707
Test name
Test status
Simulation time 11295763 ps
CPU time 0.82 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 206040 kb
Host smart-9bbac1da-d660-467a-8e4e-83b3cd33f7ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218932942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4218932942
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.375493950
Short name T325
Test name
Test status
Simulation time 1102585128 ps
CPU time 57.61 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 214992 kb
Host smart-487cb029-b261-4986-b69f-a99f4627af4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375493950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.375493950
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.779719100
Short name T720
Test name
Test status
Simulation time 174412723 ps
CPU time 1.65 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 217172 kb
Host smart-0ee3a2f7-c1d6-4e9f-ba5f-7266028148e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779719100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.779719100
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1078689190
Short name T756
Test name
Test status
Simulation time 39992129 ps
CPU time 2.2 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 208988 kb
Host smart-f543e24f-05dd-4b54-b365-4563ef910ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078689190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1078689190
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1460746350
Short name T102
Test name
Test status
Simulation time 292803213 ps
CPU time 3.89 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 209368 kb
Host smart-1d6137ef-6443-4643-a28a-ce0bca0427be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460746350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1460746350
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2836537387
Short name T711
Test name
Test status
Simulation time 766622666 ps
CPU time 6.07 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 222424 kb
Host smart-85eced80-723b-41cf-8e50-b8eee3689f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836537387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2836537387
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.252032418
Short name T792
Test name
Test status
Simulation time 94949730 ps
CPU time 5.02 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 210064 kb
Host smart-5c0f2302-e4a9-408b-9d62-b24efbbccf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252032418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.252032418
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4186799001
Short name T554
Test name
Test status
Simulation time 154701495 ps
CPU time 5.57 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 208492 kb
Host smart-d57c5d3a-45e0-4582-a4a8-5c380dc672d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186799001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4186799001
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.957730913
Short name T256
Test name
Test status
Simulation time 62000423 ps
CPU time 2.85 seconds
Started May 30 03:38:54 PM PDT 24
Finished May 30 03:38:59 PM PDT 24
Peak memory 206880 kb
Host smart-7c5dd2d2-decd-4002-9a7d-dce796ea9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957730913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.957730913
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3896025075
Short name T15
Test name
Test status
Simulation time 161172399 ps
CPU time 1.73 seconds
Started May 30 03:38:53 PM PDT 24
Finished May 30 03:38:57 PM PDT 24
Peak memory 206972 kb
Host smart-d84c4c07-789e-4b08-898d-448c57342f2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896025075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3896025075
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3203006749
Short name T914
Test name
Test status
Simulation time 95272027 ps
CPU time 4.34 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 208968 kb
Host smart-1f45fdf4-520d-435a-9370-c5b1497c640f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203006749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3203006749
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.980403974
Short name T326
Test name
Test status
Simulation time 179897792 ps
CPU time 4.98 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 208032 kb
Host smart-a4814dcf-2526-41f0-b781-b106f5e62677
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980403974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.980403974
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3665543116
Short name T290
Test name
Test status
Simulation time 8424967058 ps
CPU time 15.17 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 218812 kb
Host smart-3c3d4667-6ae6-4a59-83d5-a6b35c594d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665543116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3665543116
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.514323667
Short name T589
Test name
Test status
Simulation time 50633714 ps
CPU time 2.48 seconds
Started May 30 03:38:55 PM PDT 24
Finished May 30 03:39:00 PM PDT 24
Peak memory 206696 kb
Host smart-3ecc7ad8-7f3a-4979-b47d-b095e571393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514323667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.514323667
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1429093698
Short name T260
Test name
Test status
Simulation time 972140563 ps
CPU time 10.52 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 220540 kb
Host smart-76f5af45-ab4f-44b6-9ce1-11de061c93bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429093698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1429093698
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2692283304
Short name T848
Test name
Test status
Simulation time 3355508898 ps
CPU time 6.25 seconds
Started May 30 03:38:56 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 214384 kb
Host smart-2c1994dc-6514-4c24-9ff2-37d2944ee00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692283304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2692283304
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3587310386
Short name T838
Test name
Test status
Simulation time 95418502 ps
CPU time 1.7 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 214396 kb
Host smart-ae223937-ce86-42bb-9b4e-26bb8b495da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587310386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3587310386
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2323955416
Short name T784
Test name
Test status
Simulation time 35917238 ps
CPU time 0.74 seconds
Started May 30 03:39:02 PM PDT 24
Finished May 30 03:39:05 PM PDT 24
Peak memory 205924 kb
Host smart-8500fa8b-59b7-45e0-85c2-8094af0c8d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323955416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2323955416
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2237682529
Short name T727
Test name
Test status
Simulation time 526445993 ps
CPU time 4.74 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:05 PM PDT 24
Peak memory 214400 kb
Host smart-ee3865c7-feab-4192-bb97-563210a94566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237682529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2237682529
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.344891312
Short name T713
Test name
Test status
Simulation time 260058604 ps
CPU time 4.83 seconds
Started May 30 03:39:01 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 210144 kb
Host smart-e4823532-9327-4124-8f7a-a5d243a66dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344891312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.344891312
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1948594749
Short name T76
Test name
Test status
Simulation time 226005613 ps
CPU time 3.01 seconds
Started May 30 03:39:02 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 210676 kb
Host smart-dd6d7db3-7188-43f2-807a-d89623e64675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948594749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1948594749
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3556389350
Short name T515
Test name
Test status
Simulation time 91639817 ps
CPU time 3.58 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:02 PM PDT 24
Peak memory 222524 kb
Host smart-01ec6f1a-6acc-4cec-b14b-d5fc9d3bf171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556389350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3556389350
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3215709525
Short name T578
Test name
Test status
Simulation time 51654787 ps
CPU time 2.81 seconds
Started May 30 03:39:02 PM PDT 24
Finished May 30 03:39:07 PM PDT 24
Peak memory 221796 kb
Host smart-7cb8a3a2-baee-40ee-989b-b5d90a32162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215709525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3215709525
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3378777325
Short name T819
Test name
Test status
Simulation time 231021115 ps
CPU time 3.95 seconds
Started May 30 03:39:02 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 209944 kb
Host smart-e6eab1b0-a918-451c-9186-06d62cf1c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378777325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3378777325
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2752339907
Short name T313
Test name
Test status
Simulation time 1001626503 ps
CPU time 5.42 seconds
Started May 30 03:39:00 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 209272 kb
Host smart-78a53c3a-2575-479e-a402-b4f49855890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752339907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2752339907
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2076443857
Short name T513
Test name
Test status
Simulation time 956972974 ps
CPU time 3.81 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 208196 kb
Host smart-493cf1e5-6684-4440-a544-d8e0ee529e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076443857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2076443857
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3526724309
Short name T625
Test name
Test status
Simulation time 22263935 ps
CPU time 1.82 seconds
Started May 30 03:39:02 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 206852 kb
Host smart-943787a3-d76e-4c9f-ba6c-a010f2296d6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526724309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3526724309
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3569736924
Short name T762
Test name
Test status
Simulation time 194001431 ps
CPU time 3.7 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 206984 kb
Host smart-cb36c871-b87c-43d6-abbb-a75a4f0fe16e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569736924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3569736924
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4290609317
Short name T845
Test name
Test status
Simulation time 54697904 ps
CPU time 2.76 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 207052 kb
Host smart-5332ce2f-e07b-4d00-9556-26c8e5d4e9d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290609317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4290609317
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2393354524
Short name T906
Test name
Test status
Simulation time 238354737 ps
CPU time 2.74 seconds
Started May 30 03:39:01 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 214276 kb
Host smart-d534423d-fba6-4b75-89fa-f7807c70d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393354524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2393354524
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1791723996
Short name T214
Test name
Test status
Simulation time 179875364 ps
CPU time 5.08 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 206872 kb
Host smart-97ac5478-dc47-45a2-a62a-3aea4ad7af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791723996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1791723996
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3050017895
Short name T230
Test name
Test status
Simulation time 352255809 ps
CPU time 17.65 seconds
Started May 30 03:39:01 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 217080 kb
Host smart-aaf4ac1b-0099-4ed0-8433-c7dc124a47e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050017895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3050017895
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.4168918862
Short name T266
Test name
Test status
Simulation time 312644850 ps
CPU time 9.41 seconds
Started May 30 03:39:00 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 222520 kb
Host smart-b92fe52e-464b-4251-91cb-ce35db2a3d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168918862 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.4168918862
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4207728094
Short name T864
Test name
Test status
Simulation time 5746652528 ps
CPU time 56.43 seconds
Started May 30 03:38:57 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 220920 kb
Host smart-4e3aa148-a4b3-4651-8316-75d212a6a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207728094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4207728094
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4243625926
Short name T498
Test name
Test status
Simulation time 176438237 ps
CPU time 2.21 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 209940 kb
Host smart-d028d7c0-8935-4914-96a1-6b3595a9b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243625926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4243625926
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1922651218
Short name T506
Test name
Test status
Simulation time 13969213 ps
CPU time 0.79 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 205888 kb
Host smart-be71d9f0-b5bc-4713-a728-2fc695097bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922651218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1922651218
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1646313474
Short name T136
Test name
Test status
Simulation time 196784060 ps
CPU time 3.66 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 214352 kb
Host smart-bf83de46-0ece-4593-9dab-de8ee45094b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646313474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1646313474
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.379310577
Short name T30
Test name
Test status
Simulation time 505911489 ps
CPU time 5.92 seconds
Started May 30 03:39:10 PM PDT 24
Finished May 30 03:39:17 PM PDT 24
Peak memory 221464 kb
Host smart-77d65651-c24e-4fde-aa3a-23529d66a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379310577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.379310577
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3747084975
Short name T75
Test name
Test status
Simulation time 767365690 ps
CPU time 3.59 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 218684 kb
Host smart-f7969389-deb5-47f9-8294-bd7131394095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747084975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3747084975
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.429542011
Short name T247
Test name
Test status
Simulation time 1492637301 ps
CPU time 6.46 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:14 PM PDT 24
Peak memory 214288 kb
Host smart-0a4eb2fe-a7c3-4135-837b-c265e28d4aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429542011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.429542011
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4191369349
Short name T830
Test name
Test status
Simulation time 52904477 ps
CPU time 2.81 seconds
Started May 30 03:39:03 PM PDT 24
Finished May 30 03:39:08 PM PDT 24
Peak memory 214412 kb
Host smart-96826433-51a9-41d5-bd9d-966271be5552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191369349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4191369349
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2949579595
Short name T638
Test name
Test status
Simulation time 347046949 ps
CPU time 3.78 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 220148 kb
Host smart-8de144f8-d7dc-4b74-8a05-cc3f2f0f35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949579595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2949579595
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2971029576
Short name T495
Test name
Test status
Simulation time 376906927 ps
CPU time 4.65 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 209016 kb
Host smart-6c383a83-23ad-4979-a788-812eda9b52a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971029576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2971029576
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.464278314
Short name T777
Test name
Test status
Simulation time 114316283 ps
CPU time 3.83 seconds
Started May 30 03:38:59 PM PDT 24
Finished May 30 03:39:04 PM PDT 24
Peak memory 206964 kb
Host smart-d9147e6d-50f9-4a43-8ff0-688a169289ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464278314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.464278314
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1271437573
Short name T908
Test name
Test status
Simulation time 38152149 ps
CPU time 2.45 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 206824 kb
Host smart-8865f668-b243-43ba-abc3-9c4a02e855a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271437573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1271437573
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1372480320
Short name T566
Test name
Test status
Simulation time 95390160 ps
CPU time 2.78 seconds
Started May 30 03:38:58 PM PDT 24
Finished May 30 03:39:03 PM PDT 24
Peak memory 206948 kb
Host smart-b3b66307-3635-4759-af27-1b7d5bdb07a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372480320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1372480320
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1741397261
Short name T180
Test name
Test status
Simulation time 619154188 ps
CPU time 5.61 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 208568 kb
Host smart-2295cf74-a258-4d54-a378-c0d482e15ef2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741397261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1741397261
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2521430982
Short name T462
Test name
Test status
Simulation time 59718568 ps
CPU time 2 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:09 PM PDT 24
Peak memory 208760 kb
Host smart-c418e016-b821-4bc0-9b60-3012810df5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521430982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2521430982
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1759539878
Short name T438
Test name
Test status
Simulation time 434867226 ps
CPU time 4.54 seconds
Started May 30 03:38:55 PM PDT 24
Finished May 30 03:39:01 PM PDT 24
Peak memory 207772 kb
Host smart-0724ed6e-2ea0-4dc6-95d1-5456a73b18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759539878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1759539878
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.771051292
Short name T124
Test name
Test status
Simulation time 299094304 ps
CPU time 13.6 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 222652 kb
Host smart-37b5ef7b-4bb8-4a31-90cf-49d21473f204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771051292 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.771051292
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4114659991
Short name T795
Test name
Test status
Simulation time 3028608918 ps
CPU time 33.86 seconds
Started May 30 03:39:03 PM PDT 24
Finished May 30 03:39:39 PM PDT 24
Peak memory 209332 kb
Host smart-c1da6c6b-277c-4662-8d32-9186a4b443f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114659991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4114659991
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1547494222
Short name T192
Test name
Test status
Simulation time 177305110 ps
CPU time 2.22 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:11 PM PDT 24
Peak memory 209968 kb
Host smart-ff5989f2-906a-4e6b-ac64-e5a3b7811077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547494222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1547494222
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1522679180
Short name T547
Test name
Test status
Simulation time 11355305 ps
CPU time 0.72 seconds
Started May 30 03:39:08 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 205936 kb
Host smart-afc4ffe1-2ae8-442a-a557-3b4dcaf7d25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522679180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1522679180
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3299330287
Short name T764
Test name
Test status
Simulation time 63186499 ps
CPU time 3.63 seconds
Started May 30 03:39:09 PM PDT 24
Finished May 30 03:39:14 PM PDT 24
Peak memory 209828 kb
Host smart-2f4b2918-2eaf-413d-a15c-5e7213bda0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299330287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3299330287
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3258652224
Short name T591
Test name
Test status
Simulation time 159852444 ps
CPU time 3.76 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:11 PM PDT 24
Peak memory 214408 kb
Host smart-32c764bf-b089-43fe-858f-3dfe9e87e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258652224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3258652224
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1915771326
Short name T487
Test name
Test status
Simulation time 83397288 ps
CPU time 2.67 seconds
Started May 30 03:39:03 PM PDT 24
Finished May 30 03:39:07 PM PDT 24
Peak memory 214360 kb
Host smart-9eff2647-38ad-4aa7-8c44-30173f2ae3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915771326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1915771326
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1599884999
Short name T460
Test name
Test status
Simulation time 228316464 ps
CPU time 2.62 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 214248 kb
Host smart-a09d3345-dc7b-40ae-b52e-740e29ba7916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599884999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1599884999
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.441128702
Short name T232
Test name
Test status
Simulation time 487383746 ps
CPU time 2.96 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 214824 kb
Host smart-46e5ff22-1531-404c-b773-6b87e832e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441128702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.441128702
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1072274723
Short name T658
Test name
Test status
Simulation time 570407604 ps
CPU time 5.94 seconds
Started May 30 03:39:09 PM PDT 24
Finished May 30 03:39:16 PM PDT 24
Peak memory 209916 kb
Host smart-12457eb2-11c4-431c-9a04-2fc0a1376c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072274723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1072274723
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1604338391
Short name T663
Test name
Test status
Simulation time 62876694 ps
CPU time 3.1 seconds
Started May 30 03:39:09 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 208216 kb
Host smart-b1de7a5a-0e0b-4262-bc8e-e1090a41545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604338391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1604338391
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2761186874
Short name T397
Test name
Test status
Simulation time 130135778 ps
CPU time 2.12 seconds
Started May 30 03:39:10 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 207008 kb
Host smart-7efcef44-eac9-4ee7-817a-fdb30b38387b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761186874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2761186874
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2807517709
Short name T13
Test name
Test status
Simulation time 476524869 ps
CPU time 3.7 seconds
Started May 30 03:39:04 PM PDT 24
Finished May 30 03:39:11 PM PDT 24
Peak memory 208876 kb
Host smart-d30741f2-f307-4734-8d9f-5e6065fc77e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807517709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2807517709
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2461513834
Short name T493
Test name
Test status
Simulation time 278031969 ps
CPU time 3.37 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 206912 kb
Host smart-849089ef-dc52-4145-8460-51b879b444b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461513834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2461513834
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3889270518
Short name T869
Test name
Test status
Simulation time 896862549 ps
CPU time 14.03 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 218328 kb
Host smart-01c5703d-27c1-46be-ae91-9c24ec0ea7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889270518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3889270518
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.796551035
Short name T852
Test name
Test status
Simulation time 199490550 ps
CPU time 4.4 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 207824 kb
Host smart-003b4135-371b-4d6e-af0d-7d2a1bb6f064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796551035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.796551035
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3549437913
Short name T599
Test name
Test status
Simulation time 1289577258 ps
CPU time 32.3 seconds
Started May 30 03:39:10 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 215976 kb
Host smart-0d43b0eb-3953-499a-8d56-c49db7198976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549437913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3549437913
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2838253820
Short name T890
Test name
Test status
Simulation time 370028588 ps
CPU time 6.07 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:14 PM PDT 24
Peak memory 219724 kb
Host smart-4f1b6be5-c04a-4c5f-a378-b2cae2b71bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838253820 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2838253820
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2644567052
Short name T335
Test name
Test status
Simulation time 6334592939 ps
CPU time 50.64 seconds
Started May 30 03:39:09 PM PDT 24
Finished May 30 03:40:00 PM PDT 24
Peak memory 214440 kb
Host smart-5fb29bbb-1008-47ba-978a-4c01392fc61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644567052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2644567052
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.4191014735
Short name T608
Test name
Test status
Simulation time 210766188 ps
CPU time 2.36 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:11 PM PDT 24
Peak memory 209880 kb
Host smart-abbd1b68-61a6-4109-90d7-512e42dbf181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191014735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.4191014735
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2981559852
Short name T427
Test name
Test status
Simulation time 40470028 ps
CPU time 0.77 seconds
Started May 30 03:39:14 PM PDT 24
Finished May 30 03:39:16 PM PDT 24
Peak memory 205956 kb
Host smart-d0707344-e0b8-4593-9749-e488ee82435a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981559852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2981559852
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1401038569
Short name T135
Test name
Test status
Simulation time 257520850 ps
CPU time 4.31 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 215216 kb
Host smart-18453788-d74a-4a49-853b-5cb11dac0f11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401038569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1401038569
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1138287385
Short name T693
Test name
Test status
Simulation time 610499131 ps
CPU time 4.52 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 209376 kb
Host smart-69383b4d-e26a-4d0a-bb74-e1e42157a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138287385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1138287385
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.690002555
Short name T332
Test name
Test status
Simulation time 359853674 ps
CPU time 3.54 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 214296 kb
Host smart-e39f3709-a1e7-43f5-8012-e47d5487349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690002555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.690002555
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.932619635
Short name T95
Test name
Test status
Simulation time 875246167 ps
CPU time 4.46 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 209872 kb
Host smart-4557a039-66cc-4b57-8fdb-0d5ec01380aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932619635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.932619635
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1558292243
Short name T704
Test name
Test status
Simulation time 259355053 ps
CPU time 5.58 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 222452 kb
Host smart-44a7e6f1-c90c-43fd-bde9-7758d52d1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558292243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1558292243
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.293095981
Short name T532
Test name
Test status
Simulation time 126363327 ps
CPU time 4.61 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 214368 kb
Host smart-7483d08f-54b1-4a3b-9905-a18e568a37b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293095981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.293095981
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1712248459
Short name T523
Test name
Test status
Simulation time 393397491 ps
CPU time 5.04 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:12 PM PDT 24
Peak memory 208724 kb
Host smart-9d51f348-f277-4d3a-8ab6-154db00b415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712248459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1712248459
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3280182567
Short name T682
Test name
Test status
Simulation time 153981697 ps
CPU time 2.4 seconds
Started May 30 03:39:05 PM PDT 24
Finished May 30 03:39:10 PM PDT 24
Peak memory 207008 kb
Host smart-d3f1cd26-1571-4f2b-a1ae-186a14d7318d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280182567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3280182567
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2554416158
Short name T568
Test name
Test status
Simulation time 2221072148 ps
CPU time 16.52 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 208632 kb
Host smart-ba63d3dd-6e30-4cc5-bba5-37554299c5de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554416158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2554416158
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3955025782
Short name T428
Test name
Test status
Simulation time 3626931069 ps
CPU time 11.06 seconds
Started May 30 03:39:06 PM PDT 24
Finished May 30 03:39:19 PM PDT 24
Peak memory 207020 kb
Host smart-2e161345-3060-4e8b-997c-7e887ef3c61b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955025782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3955025782
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.266376420
Short name T603
Test name
Test status
Simulation time 34008029 ps
CPU time 2.11 seconds
Started May 30 03:39:14 PM PDT 24
Finished May 30 03:39:17 PM PDT 24
Peak memory 214356 kb
Host smart-0f901d3f-37f2-4bd0-ac66-94e29079b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266376420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.266376420
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3863601009
Short name T465
Test name
Test status
Simulation time 425126632 ps
CPU time 4.37 seconds
Started May 30 03:39:07 PM PDT 24
Finished May 30 03:39:13 PM PDT 24
Peak memory 207944 kb
Host smart-212937c5-9ca4-4b3f-ab74-e293f55f2ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863601009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3863601009
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.984704719
Short name T719
Test name
Test status
Simulation time 394534154 ps
CPU time 5 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:26 PM PDT 24
Peak memory 210288 kb
Host smart-6c2995f5-21eb-4e06-b6c1-ca127a45c84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984704719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.984704719
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.4013605823
Short name T360
Test name
Test status
Simulation time 312051947 ps
CPU time 3.18 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 208228 kb
Host smart-1a627c3b-0504-4639-901c-b17043769dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013605823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4013605823
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2105137432
Short name T38
Test name
Test status
Simulation time 759421861 ps
CPU time 4.09 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 209752 kb
Host smart-91a6e29c-c4b1-4faa-8ada-b81147722493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105137432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2105137432
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.227332593
Short name T421
Test name
Test status
Simulation time 56620479 ps
CPU time 0.8 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 205940 kb
Host smart-92db9464-4e87-4b12-b0e8-4163ae830001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227332593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.227332593
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2442193066
Short name T26
Test name
Test status
Simulation time 581461126 ps
CPU time 6.06 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 222792 kb
Host smart-8a522bde-8d5c-42d2-9895-f95f28fb92e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442193066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2442193066
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1476251005
Short name T871
Test name
Test status
Simulation time 158897656 ps
CPU time 3.54 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 214412 kb
Host smart-79e5f3f4-74cf-4c3d-a3e9-1d247c16c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476251005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1476251005
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3600599000
Short name T600
Test name
Test status
Simulation time 279789558 ps
CPU time 3.12 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 214352 kb
Host smart-450945a8-15f9-4559-b35f-528307408bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600599000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3600599000
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1653073067
Short name T898
Test name
Test status
Simulation time 458511951 ps
CPU time 2.9 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 214292 kb
Host smart-a3d2d6d5-a6db-4d4d-b9c7-f6859062240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653073067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1653073067
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.657452040
Short name T826
Test name
Test status
Simulation time 133547352 ps
CPU time 2.19 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 214908 kb
Host smart-12533461-bcf1-46c1-a81a-b78da50bf1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657452040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.657452040
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2896076247
Short name T677
Test name
Test status
Simulation time 1200988698 ps
CPU time 9.37 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:30 PM PDT 24
Peak memory 208136 kb
Host smart-5e0b6722-4c32-4d4b-bd21-90f43ef5c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896076247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2896076247
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.634093123
Short name T827
Test name
Test status
Simulation time 236953056 ps
CPU time 2.79 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:19 PM PDT 24
Peak memory 206976 kb
Host smart-bf919f06-45d2-41de-aea2-68b9f0d97d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634093123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.634093123
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.307167376
Short name T300
Test name
Test status
Simulation time 537376254 ps
CPU time 3.42 seconds
Started May 30 03:39:14 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 207032 kb
Host smart-3c990c0a-a35d-4af4-a4e1-59d04387ff18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307167376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.307167376
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.93628569
Short name T433
Test name
Test status
Simulation time 357319562 ps
CPU time 5.02 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:26 PM PDT 24
Peak memory 208444 kb
Host smart-07e98bf9-6963-42c8-8fe3-5e042f4dfe15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93628569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.93628569
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2927720264
Short name T439
Test name
Test status
Simulation time 1358915584 ps
CPU time 34.08 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:53 PM PDT 24
Peak memory 207924 kb
Host smart-d6ff5879-138d-41ba-8b25-87a299a31794
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927720264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2927720264
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1314338914
Short name T856
Test name
Test status
Simulation time 132682598 ps
CPU time 1.97 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 216060 kb
Host smart-93e602f4-cb25-44da-ba40-0ec673c8a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314338914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1314338914
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2113166516
Short name T610
Test name
Test status
Simulation time 1189598412 ps
CPU time 4.7 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 206132 kb
Host smart-1b194461-77a4-4438-bf06-908b96c335cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113166516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2113166516
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3940371483
Short name T772
Test name
Test status
Simulation time 528012771 ps
CPU time 13.04 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:33 PM PDT 24
Peak memory 216592 kb
Host smart-d941fa7e-3f5b-4839-8ef0-089b21195fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940371483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3940371483
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1871686145
Short name T746
Test name
Test status
Simulation time 663208555 ps
CPU time 12.72 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 220076 kb
Host smart-b0226515-582e-41a8-b90a-9231784d21c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871686145 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1871686145
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.734316093
Short name T463
Test name
Test status
Simulation time 68637174 ps
CPU time 2.95 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:19 PM PDT 24
Peak memory 207620 kb
Host smart-8e04a731-81f0-4d06-92fa-b722d3f596ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734316093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.734316093
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.91415493
Short name T609
Test name
Test status
Simulation time 84820964 ps
CPU time 1.57 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 209860 kb
Host smart-9f878ed0-ab8a-4a6c-9d68-b1c740452947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91415493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.91415493
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4017084887
Short name T474
Test name
Test status
Simulation time 18937831 ps
CPU time 0.8 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 205936 kb
Host smart-7c1fc0fb-3e81-48bc-a604-36f8dd417039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017084887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4017084887
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.439986235
Short name T408
Test name
Test status
Simulation time 199050635 ps
CPU time 10.82 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 215348 kb
Host smart-d1fa224e-4a91-4dc1-89cf-08d177216b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439986235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.439986235
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2823553502
Short name T43
Test name
Test status
Simulation time 148512278 ps
CPU time 3.4 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 208172 kb
Host smart-0a178c69-de32-46db-9fa0-5db4789ed89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823553502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2823553502
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4095688261
Short name T361
Test name
Test status
Simulation time 2716198251 ps
CPU time 11.11 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 208692 kb
Host smart-6ff16f6e-13c2-4d05-a31a-3080d8e5e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095688261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4095688261
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3818400374
Short name T93
Test name
Test status
Simulation time 102695152 ps
CPU time 1.94 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 214308 kb
Host smart-2ee2c72c-5e3b-400c-8f1b-f7220e304765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818400374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3818400374
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2764441534
Short name T231
Test name
Test status
Simulation time 128988366 ps
CPU time 3.97 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 215048 kb
Host smart-58315726-8cb6-443b-b727-47ef9d96faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764441534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2764441534
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.65172396
Short name T619
Test name
Test status
Simulation time 422264903 ps
CPU time 5.29 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 209876 kb
Host smart-c67a95f6-e8a4-446f-bdc5-a184e0d1be70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65172396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.65172396
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2762678146
Short name T109
Test name
Test status
Simulation time 78138886 ps
CPU time 3.63 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 206936 kb
Host smart-69d16c98-5976-4d9d-8247-d485009b0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762678146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2762678146
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1453480363
Short name T767
Test name
Test status
Simulation time 32256949 ps
CPU time 2.27 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 206992 kb
Host smart-b02976ce-9d25-4627-9f64-77ee7b2e24f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453480363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1453480363
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3936119805
Short name T489
Test name
Test status
Simulation time 96879851 ps
CPU time 3.26 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 206956 kb
Host smart-c860d038-128a-49a8-bddf-c1948dad2fda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936119805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3936119805
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4190137977
Short name T452
Test name
Test status
Simulation time 483187710 ps
CPU time 4.89 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 207052 kb
Host smart-4e7e0359-26a1-43a9-abce-a38852267b8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190137977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4190137977
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1404931425
Short name T716
Test name
Test status
Simulation time 109124469 ps
CPU time 1.72 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:33 PM PDT 24
Peak memory 207404 kb
Host smart-642f2574-6b63-428f-9e5c-25ad4aa80ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404931425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1404931425
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3570483290
Short name T512
Test name
Test status
Simulation time 39745910 ps
CPU time 1.61 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 206952 kb
Host smart-35433a9a-199a-4816-99ff-270595266927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570483290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3570483290
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1588017332
Short name T666
Test name
Test status
Simulation time 362537961 ps
CPU time 5 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 207660 kb
Host smart-b0a934ce-1f22-4ea3-853e-9f2134eb4edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588017332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1588017332
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4151966055
Short name T66
Test name
Test status
Simulation time 438441818 ps
CPU time 4.92 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 211068 kb
Host smart-5941c9ed-8d1c-4c3f-9df8-15ff75a72e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151966055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4151966055
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1197872860
Short name T647
Test name
Test status
Simulation time 43882371 ps
CPU time 0.83 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 205960 kb
Host smart-da4e512f-d166-4cb6-b887-47248d3fb69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197872860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1197872860
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.788374042
Short name T903
Test name
Test status
Simulation time 125226919 ps
CPU time 6.8 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:40 PM PDT 24
Peak memory 214320 kb
Host smart-c0157656-fad6-4b64-a17f-ec70dffc476b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788374042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.788374042
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3282803758
Short name T913
Test name
Test status
Simulation time 68822650 ps
CPU time 1.95 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 209392 kb
Host smart-0446b0db-0994-4593-8d81-477cb14649c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282803758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3282803758
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4219231305
Short name T482
Test name
Test status
Simulation time 114510226 ps
CPU time 1.94 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 214332 kb
Host smart-bf9a0e29-b838-4a9f-ba20-5d74cd68c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219231305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4219231305
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2174604250
Short name T87
Test name
Test status
Simulation time 548916595 ps
CPU time 2.34 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:32 PM PDT 24
Peak memory 209216 kb
Host smart-6ee41752-abff-4a0c-81d2-67da5f4624fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174604250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2174604250
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2325795127
Short name T636
Test name
Test status
Simulation time 452147087 ps
CPU time 4.42 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 214276 kb
Host smart-97579179-d968-4910-a083-2a3191f7e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325795127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2325795127
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1602805725
Short name T904
Test name
Test status
Simulation time 72727343 ps
CPU time 3.81 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 210220 kb
Host smart-22a34322-3252-4375-b1a7-4d21a2bf56f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602805725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1602805725
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.244425861
Short name T375
Test name
Test status
Simulation time 875184479 ps
CPU time 19.15 seconds
Started May 30 03:36:29 PM PDT 24
Finished May 30 03:36:50 PM PDT 24
Peak memory 209420 kb
Host smart-7597efde-c994-4061-8eb2-7e2ac6f79432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244425861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.244425861
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1072127664
Short name T550
Test name
Test status
Simulation time 193098284 ps
CPU time 2.85 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 206740 kb
Host smart-3f1ef3df-ea3c-43d2-beb2-4cc77a06bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072127664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1072127664
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.935526408
Short name T507
Test name
Test status
Simulation time 77584179 ps
CPU time 1.87 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 207560 kb
Host smart-7dbef4ba-b1f1-4e97-8869-7acf7900c1b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935526408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.935526408
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2293540662
Short name T301
Test name
Test status
Simulation time 71243856 ps
CPU time 1.68 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 206996 kb
Host smart-71e44d11-de53-48bf-bad4-f9e12724ad40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293540662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2293540662
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2416802361
Short name T573
Test name
Test status
Simulation time 1200388824 ps
CPU time 8.34 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 207152 kb
Host smart-a5a32b8b-b999-4203-98b0-6fa25a233b6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416802361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2416802361
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1460509365
Short name T552
Test name
Test status
Simulation time 132684418 ps
CPU time 2.18 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 207472 kb
Host smart-0003ce4a-4004-49bd-8bfc-5403bdfb8c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460509365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1460509365
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3304367262
Short name T486
Test name
Test status
Simulation time 18070229 ps
CPU time 1.62 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 206656 kb
Host smart-f7dbf6e3-e5d6-4e24-9835-0ace2e7a165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304367262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3304367262
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.698331121
Short name T404
Test name
Test status
Simulation time 414947332 ps
CPU time 6.36 seconds
Started May 30 03:36:30 PM PDT 24
Finished May 30 03:36:39 PM PDT 24
Peak memory 209372 kb
Host smart-ab4afdc5-7c7d-4675-bc04-2870c527c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698331121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.698331121
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2841069463
Short name T814
Test name
Test status
Simulation time 122023094 ps
CPU time 1.47 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 209856 kb
Host smart-ba6d8871-4433-455b-aabc-64d4e2afeb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841069463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2841069463
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2362616435
Short name T435
Test name
Test status
Simulation time 33014100 ps
CPU time 0.75 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:34 PM PDT 24
Peak memory 205948 kb
Host smart-48a2c010-75a9-4fd2-b03a-8586d3c1d210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362616435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2362616435
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3040480995
Short name T413
Test name
Test status
Simulation time 48639662 ps
CPU time 3.44 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 214352 kb
Host smart-9bf83394-a208-4299-9ce8-eaceee714971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040480995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3040480995
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2146995362
Short name T815
Test name
Test status
Simulation time 65611338 ps
CPU time 1.34 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:35 PM PDT 24
Peak memory 216080 kb
Host smart-204db09e-d6e4-46dd-9d4d-95a795dd0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146995362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2146995362
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2408680006
Short name T688
Test name
Test status
Simulation time 223753913 ps
CPU time 2.16 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 207940 kb
Host smart-a242d45d-12c4-48cf-91d2-b20beca3970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408680006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2408680006
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.448370097
Short name T104
Test name
Test status
Simulation time 194657447 ps
CPU time 6.46 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 214348 kb
Host smart-ba58ec09-af24-4210-b33b-4cc26d3e95a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448370097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.448370097
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.848860286
Short name T916
Test name
Test status
Simulation time 60076458 ps
CPU time 2.76 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 214288 kb
Host smart-80cc967e-799b-4847-8c71-5c8c7bd78d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848860286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.848860286
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1401577844
Short name T543
Test name
Test status
Simulation time 121560901 ps
CPU time 3.93 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 209192 kb
Host smart-bfd776f0-b303-4fa7-90e5-c2480ca09f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401577844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1401577844
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.857203113
Short name T183
Test name
Test status
Simulation time 391862388 ps
CPU time 5.78 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:39 PM PDT 24
Peak memory 208564 kb
Host smart-caca7ae1-e6f9-4917-be83-3ae593720fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857203113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.857203113
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4017152458
Short name T624
Test name
Test status
Simulation time 264346358 ps
CPU time 2.88 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 206888 kb
Host smart-1d1a17b2-ff46-4284-8641-3bc4bc764df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017152458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4017152458
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2439004250
Short name T259
Test name
Test status
Simulation time 58202642 ps
CPU time 2.86 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 206968 kb
Host smart-0145a50f-933f-4a08-bc9d-8a006064c572
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439004250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2439004250
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3012175833
Short name T597
Test name
Test status
Simulation time 125028318 ps
CPU time 2.44 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 206864 kb
Host smart-beadb67d-ef29-4ab7-b31f-af2f900dbbb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012175833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3012175833
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1899542369
Short name T457
Test name
Test status
Simulation time 1625911907 ps
CPU time 7.58 seconds
Started May 30 03:36:28 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 206976 kb
Host smart-9e2fb1b2-e6fb-4f67-aa4c-029ac3c382a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899542369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1899542369
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3485980274
Short name T559
Test name
Test status
Simulation time 64004844 ps
CPU time 1.61 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 207740 kb
Host smart-51d5875b-5603-45b2-a4f5-4fc68f7535af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485980274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3485980274
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2584730477
Short name T667
Test name
Test status
Simulation time 83905926 ps
CPU time 2.76 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 206160 kb
Host smart-fa326422-a50a-4269-97c3-f0dfe47030fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584730477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2584730477
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1080394692
Short name T684
Test name
Test status
Simulation time 233255718 ps
CPU time 12.47 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:48 PM PDT 24
Peak memory 216472 kb
Host smart-49cb6e0a-325b-441f-8963-a4af48897691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080394692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1080394692
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1583565817
Short name T491
Test name
Test status
Simulation time 867992637 ps
CPU time 4.43 seconds
Started May 30 03:36:31 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 214392 kb
Host smart-e49c4cf6-eb76-44d0-a8ac-53dd083e19b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583565817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1583565817
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3613796323
Short name T653
Test name
Test status
Simulation time 31915706 ps
CPU time 1.78 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:36 PM PDT 24
Peak memory 209564 kb
Host smart-ba848300-79f2-45b4-87e5-57f6ceb42157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613796323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3613796323
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3257396695
Short name T529
Test name
Test status
Simulation time 97060204 ps
CPU time 1.57 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 206088 kb
Host smart-414681ba-74a5-4a44-8ce2-c46d54b32a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257396695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3257396695
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1087175480
Short name T378
Test name
Test status
Simulation time 54631308 ps
CPU time 2.63 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 214364 kb
Host smart-14a8b525-3da2-4f6c-a92e-d8a233268030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087175480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1087175480
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2316660329
Short name T356
Test name
Test status
Simulation time 267185917 ps
CPU time 2.99 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 208744 kb
Host smart-fb74f02b-6d4f-4694-a85f-1bc21e8f1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316660329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2316660329
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3247345102
Short name T331
Test name
Test status
Simulation time 314000485 ps
CPU time 2.08 seconds
Started May 30 03:36:40 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 214316 kb
Host smart-c160f27c-f7e4-48a8-b96a-619bede1b072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247345102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3247345102
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.251394839
Short name T366
Test name
Test status
Simulation time 264538762 ps
CPU time 3.41 seconds
Started May 30 03:36:37 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 222496 kb
Host smart-9a7c3ea3-e3ed-4a46-9195-b7c16416e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251394839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.251394839
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.80557595
Short name T228
Test name
Test status
Simulation time 1022486734 ps
CPU time 3.46 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:39 PM PDT 24
Peak memory 220336 kb
Host smart-283b621f-4ec0-476c-b64d-0ec2d27fb4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80557595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.80557595
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2759712046
Short name T268
Test name
Test status
Simulation time 478020281 ps
CPU time 6.07 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 210496 kb
Host smart-0f414167-fe79-4511-9e5c-93ec5ffb100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759712046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2759712046
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2184467757
Short name T343
Test name
Test status
Simulation time 102726662 ps
CPU time 2.79 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:37 PM PDT 24
Peak memory 206976 kb
Host smart-f3d6b9ad-f669-4a35-af44-1614fb290da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184467757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2184467757
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2360141053
Short name T539
Test name
Test status
Simulation time 185554866 ps
CPU time 6.05 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:40 PM PDT 24
Peak memory 208452 kb
Host smart-b9cbc9bf-149b-49b3-a1e4-4f51f8db6f45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360141053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2360141053
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2224887741
Short name T753
Test name
Test status
Simulation time 27376693 ps
CPU time 2.07 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:38 PM PDT 24
Peak memory 208556 kb
Host smart-abcc05a0-5552-4f6d-be5e-b27ce55efbf6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224887741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2224887741
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3260103006
Short name T651
Test name
Test status
Simulation time 272133618 ps
CPU time 3.58 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:39 PM PDT 24
Peak memory 208708 kb
Host smart-8b9c16a3-1e3f-48a6-8f49-e0a8e393215a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260103006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3260103006
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3963356520
Short name T674
Test name
Test status
Simulation time 485730252 ps
CPU time 2.87 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 209368 kb
Host smart-d85663c0-c911-4ed5-b211-81da0d0f4f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963356520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3963356520
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3172098197
Short name T90
Test name
Test status
Simulation time 2918646629 ps
CPU time 7.9 seconds
Started May 30 03:36:32 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 208208 kb
Host smart-64bb63b6-2c80-4532-bfc4-0533a04511d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172098197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3172098197
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2442023716
Short name T254
Test name
Test status
Simulation time 553291188 ps
CPU time 6.38 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 218460 kb
Host smart-d570ff8a-6f22-4725-945e-3209df8ba0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442023716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2442023716
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3610913447
Short name T46
Test name
Test status
Simulation time 70275318 ps
CPU time 2.06 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 210096 kb
Host smart-804d5e96-80d2-47ac-acfb-0460190c9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610913447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3610913447
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3039219568
Short name T622
Test name
Test status
Simulation time 8575443 ps
CPU time 0.75 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:42 PM PDT 24
Peak memory 205888 kb
Host smart-3dbabc5f-37ad-475a-bc45-5d6a7ae1e5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039219568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3039219568
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3460652586
Short name T384
Test name
Test status
Simulation time 232479567 ps
CPU time 4.42 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:45 PM PDT 24
Peak memory 214368 kb
Host smart-4e04270b-fb46-41b7-9ab8-1b6a29569fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460652586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3460652586
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2554096413
Short name T32
Test name
Test status
Simulation time 279209461 ps
CPU time 2.62 seconds
Started May 30 03:36:40 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 216056 kb
Host smart-db3baba5-eba9-463d-b6dd-97eb86653de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554096413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2554096413
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1543327587
Short name T431
Test name
Test status
Simulation time 592987454 ps
CPU time 2.48 seconds
Started May 30 03:36:43 PM PDT 24
Finished May 30 03:36:47 PM PDT 24
Peak memory 207040 kb
Host smart-22d42b52-4de1-45c2-9568-409e947f7519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543327587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1543327587
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3871026602
Short name T97
Test name
Test status
Simulation time 445666629 ps
CPU time 5.43 seconds
Started May 30 03:36:34 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 222444 kb
Host smart-67fb0c36-7c3d-4690-91ab-35832cc32765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871026602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3871026602
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2980305556
Short name T909
Test name
Test status
Simulation time 240273071 ps
CPU time 3.56 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 209820 kb
Host smart-e1ec765b-d7ec-4f1f-9fb4-d80f7eb832bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980305556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2980305556
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.448771438
Short name T788
Test name
Test status
Simulation time 39028394 ps
CPU time 2.73 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 209372 kb
Host smart-f804e238-e1de-4278-9a44-55ed247db746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448771438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.448771438
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1842323600
Short name T441
Test name
Test status
Simulation time 621932013 ps
CPU time 16.81 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:58 PM PDT 24
Peak memory 208548 kb
Host smart-b018d961-caf9-45e9-8554-20315bfb78fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842323600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1842323600
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2136050404
Short name T846
Test name
Test status
Simulation time 21266263 ps
CPU time 1.87 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 206920 kb
Host smart-d4801554-5753-4b34-944c-d924565a405f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136050404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2136050404
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3316870516
Short name T582
Test name
Test status
Simulation time 68834193 ps
CPU time 3.4 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:44 PM PDT 24
Peak memory 208796 kb
Host smart-ea254ee6-204b-43ec-ae60-fb9f040f0856
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316870516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3316870516
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.170314559
Short name T296
Test name
Test status
Simulation time 123161705 ps
CPU time 2.46 seconds
Started May 30 03:36:38 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 208808 kb
Host smart-493c9b0a-ca73-49fc-88f9-2754548ea516
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170314559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.170314559
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.941185415
Short name T896
Test name
Test status
Simulation time 219002037 ps
CPU time 4.61 seconds
Started May 30 03:36:42 PM PDT 24
Finished May 30 03:36:48 PM PDT 24
Peak memory 218340 kb
Host smart-408ed18c-4969-4938-9edb-d7c85d4ee4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941185415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.941185415
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1686748191
Short name T434
Test name
Test status
Simulation time 72636777 ps
CPU time 2.07 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 206864 kb
Host smart-bcd6eafe-9c0a-44c5-9ff6-0b28e7613e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686748191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1686748191
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2712433598
Short name T874
Test name
Test status
Simulation time 4839100968 ps
CPU time 83.36 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:38:04 PM PDT 24
Peak memory 216012 kb
Host smart-0fa358b0-23ee-4e81-8cfb-c90f76f65ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712433598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2712433598
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3406852472
Short name T850
Test name
Test status
Simulation time 243128226 ps
CPU time 5.43 seconds
Started May 30 03:36:39 PM PDT 24
Finished May 30 03:36:46 PM PDT 24
Peak memory 207364 kb
Host smart-c18fa676-ff41-4e20-b839-ea90d778efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406852472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3406852472
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2784884458
Short name T389
Test name
Test status
Simulation time 327823026 ps
CPU time 7.87 seconds
Started May 30 03:36:33 PM PDT 24
Finished May 30 03:36:43 PM PDT 24
Peak memory 210744 kb
Host smart-a2c6fa1e-265d-49c6-b3ff-4bab31775eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784884458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2784884458
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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