Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4851

1

T2

4

T3

5

T4

9

auto[1]

561

1

T5

3

T35

4

T36

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4851

1

T2

4

T3

5

T4

9

auto[1]

561

1

T5

3

T35

4

T36

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4822

1

T2

4

T3

5

T4

9

auto[1]

590

1

T5

2

T17

1

T109

6

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4822

1

T2

4

T3

5

T4

9

auto[1]

590

1

T5

2

T17

1

T109

6

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	409	1			T2	1		T3	2		T5	1
auto[OpGenId]	1166	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	1178	1			T2	1		T3	3		T15	1
auto[OpGenHwOut]	2593	1			T2	1		T4	9		T5	3
auto[OpDisable]	66	1			T49	1		T50	1		T57	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	409	1			T2	1		T3	2		T5	1
auto[OpGenId]	1166	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	1178	1			T2	1		T3	3		T15	1
auto[OpGenHwOut]	2593	1			T2	1		T4	9		T5	3
auto[OpDisable]	66	1			T49	1		T50	1		T57	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4853

1

T2

1

T3

5

T4

5

auto[1]

559

1

T2

3

T4

4

T5

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4853

1

T2

1

T3

5

T4

5

auto[1]

559

1

T2

3

T4

4

T5

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5104

1

T2

4

T3

5

T4

9

auto[1]

308

1

T36

5

T109

5

T140

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1846	1			T2	1		T3	2		T4	4
auto[1]	718	1			T2	1		T4	1		T5	1
auto[2]	680	1			T2	1		T4	1		T5	1
auto[3]	750	1			T3	2		T4	1		T5	1
auto[4]	345	1			T2	1		T17	1		T35	1
auto[5]	320	1			T4	2		T16	1		T49	1
auto[6]	401	1			T3	1		T16	1		T34	1
auto[7]	352	1			T35	1		T36	1		T86	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1418	1			T2	1		T3	1		T4	2
clear_one[1]	718	1			T2	1		T4	1		T5	1
clear_one[2]	680	1			T2	1		T4	1		T5	1
clear_one[3]	750	1			T3	2		T4	1		T5	1
clear_none	1846	1			T2	1		T3	2		T4	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	976	1			T4	1		T16	2		T17	1
auto[StInit]	652	1			T4	1		T5	1		T15	1
auto[StCreatorRootKey]	577	1			T2	1		T4	1		T15	1
auto[StOwnerIntKey]	527	1			T2	1		T4	1		T35	1
auto[StOwnerKey]	493	1			T2	1		T4	1		T5	1
auto[StDisabled]	1904	1			T2	1		T4	4		T5	3
auto[StInvalid]	283	1			T3	5		T16	3		T37	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	976	1			T4	1		T16	2		T17	1
auto[StInit]	652	1			T4	1		T5	1		T15	1
auto[StCreatorRootKey]	577	1			T2	1		T4	1		T15	1
auto[StOwnerIntKey]	527	1			T2	1		T4	1		T35	1
auto[StOwnerKey]	493	1			T2	1		T4	1		T5	1
auto[StDisabled]	1904	1			T2	1		T4	4		T5	3
auto[StInvalid]	283	1			T3	5		T16	3		T37	1

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[1] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[1] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T224	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	161	1			T16	1		T49	1		T37	3
auto[0]	auto[StReset]	auto[OpGenSwOut]	159	1			T39	1		T26	3		T123	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	266	1			T4	1		T17	1		T35	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T5	1		T22	1		T23	1
auto[0]	auto[StInit]	auto[OpGenId]	103	1			T34	1		T50	1		T87	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	92	1			T15	1		T46	1		T58	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	183	1			T4	1		T36	2		T50	3
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	28	1			T57	1		T47	1		T225	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	56	1			T15	1		T56	1		T198	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	56	1			T56	1		T57	1		T58	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	77	1			T2	1		T4	1		T193	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	19	1			T36	1		T191	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T47	1		T67	1		T7	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	40	1			T26	1		T100	1		T47	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	62	1			T56	1		T47	2		T226	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T227	1		T75	1		T228	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	26	1			T56	2		T187	1		T69	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T229	1		T7	1		T68	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T4	1		T5	1		T100	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T36	2		T26	1		T56	1
auto[0]	auto[StDisabled]	auto[OpGenId]	60	1			T100	1		T56	1		T57	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T36	1		T56	2		T47	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T85	1		T56	1		T193	2
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T230	1		T7	1		T231	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T3	2		T83	2		T232	1
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T16	1		T52	1		T233	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T234	1		T235	1		T232	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T39	1		T80	1		T233	1
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T36	1		T39	1		T236	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	15	1			T58	1		T67	1		T7	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	39	1			T26	1		T128	1		T237	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T238	2		T146	1		T239	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T230	2		T117	1		T240	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T49	1		T51	1		T241	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T122	1		T47	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T243	1		T96	1		T53	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T17	1		T56	1		T59	3
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T50	1		T244	1		T203	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T122	1		T56	1		T73	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T59	1		T130	1		T245	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T50	1		T109	1		T56	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T57	1		T47	1		T158	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T122	1		T57	1		T246	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T2	1		T48	1		T200	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T50	1		T236	1		T242	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T50	1		T56	2		T47	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T86	1		T56	2		T101	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	35	1			T26	1		T56	1		T47	1
auto[1]	auto[StDisabled]	auto[OpGenId]	52	1			T5	1		T50	2		T26	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T56	2		T57	1		T247	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T4	1		T35	1		T50	1
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T57	1		T8	1		T9	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T248	1		T249	1		T250	1
auto[1]	auto[StInvalid]	auto[OpGenId]	17	1			T39	1		T233	1		T55	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T39	1		T251	1		T252	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T55	1		T235	1		T248	1
auto[2]	auto[StReset]	auto[OpGenId]	28	1			T39	1		T124	1		T51	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	19	1			T36	1		T39	1		T26	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	29	1			T122	1		T81	1		T253	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T23	1		T254	1		T255	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T158	1		T7	2		T256	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	16	1			T26	1		T23	1		T59	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	12	1			T35	1		T22	1		T257	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T82	1		T59	1		T258	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T259	1		T53	1		T9	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T260	1		T261	1		T202	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T50	1		T195	1		T190	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T73	1		T8	1		T240	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T192	1		T47	1		T262	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T2	1		T56	1		T263	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T35	1		T81	1		T85	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T96	1		T264	1		T265	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T47	1		T73	1		T59	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T191	1		T266	1		T267	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T81	1		T56	1		T58	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	16	1			T26	1		T82	1		T73	1
auto[2]	auto[StDisabled]	auto[OpGenId]	52	1			T123	1		T56	2		T57	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T124	1		T100	1		T56	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T4	1		T5	1		T35	2
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T49	1		T50	1		T60	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	8	1			T233	1		T235	1		T268	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T269	1		T270	1		T271	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T83	1		T235	1		T268	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T52	1		T55	1		T271	1
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T55	1		T230	3		T68	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	26	1			T187	2		T47	2		T236	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	43	1			T50	2		T122	1		T56	1
auto[3]	auto[StInit]	auto[OpAdvance]	11	1			T36	1		T123	1		T22	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T272	1		T273	1		T274	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	9	1			T50	1		T23	1		T128	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	30	1			T81	1		T275	1		T276	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T277	1		T278	1		T279	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T59	1		T64	1		T7	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T26	1		T230	1		T96	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T86	1		T56	1		T102	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T247	1		T47	1		T7	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T48	1		T53	1		T280	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T36	1		T50	1		T73	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T4	1		T195	1		T193	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T281	1		T282	2		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T230	1		T272	1		T159	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T47	1		T59	1		T48	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T102	1		T197	1		T58	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	24	1			T109	3		T59	1		T48	1
auto[3]	auto[StDisabled]	auto[OpGenId]	58	1			T109	1		T26	1		T56	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T192	1		T47	1		T59	4
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T5	1		T35	1		T86	2
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T158	1		T74	1		T283	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T80	1		T89	1		T284	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T16	1		T248	1		T285	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T3	2		T52	1		T90	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T52	1		T80	1		T233	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T123	1		T48	1		T286	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T56	1		T67	1		T68	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T35	1		T48	1		T287	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T220	1		T288	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T256	1		T289	1		T290	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T291	1		T292	1		T293	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	17	1			T56	1		T195	1		T197	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T48	1		T242	1		T230	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T26	1		T158	2		T242	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T7	2		T294	1		T295	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T197	1		T60	1		T296	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T238	2		T297	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T227	1		T47	2		T219	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T82	1		T298	1		T299	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T253	1		T300	1		T301	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T302	1		T303	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T17	1		T124	1		T241	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T304	1		T200	1		T305	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T82	1		T190	1		T237	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	6	1			T57	1		T8	1		T306	1
auto[4]	auto[StDisabled]	auto[OpGenId]	32	1			T2	1		T50	1		T140	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	39	1			T57	1		T190	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T26	1		T122	1		T56	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T307	1		T210	1		T308	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T309	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T39	1		T80	1		T55	2
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T233	1		T310	1		T286	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T37	1		T311	1		T312	1
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T129	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T49	1		T117	1		T313	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T314	1		T315	1		T161	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T128	1		T230	1		T287	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T316	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T53	1		T214	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T57	1		T59	1		T317	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T237	1		T158	1		T318	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T262	1		T200	1		T319	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T57	1		T129	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T47	1		T92	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T124	1		T246	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T57	1		T323	1		T214	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T236	1		T242	1		T324	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T325	1		T218	1		T326	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	14	1			T230	1		T327	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T329	1		T308	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T330	1		T331	1		T21	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T8	1		T314	1		T160	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T122	1		T246	1		T253	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T59	1		T53	1		T332	2
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T187	1		T333	1		T236	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T26	1		T57	1		T47	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T4	2		T122	3		T81	2
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T59	1		T242	1		T53	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T250	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T16	1		T39	1		T334	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T248	1		T286	1		T89	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T80	1		T268	1		T89	2
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T51	1		T117	1		T284	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	16	1			T22	1		T59	1		T335	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T16	1		T81	1		T158	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T59	1		T336	1		T337	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T230	1		T203	1		T338	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T47	1		T59	1		T339	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T34	1		T211	1		T340	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T56	1		T76	1		T203	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T242	1		T7	1		T273	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T194	1		T47	1		T341	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T342	1		T129	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T58	1		T48	1		T343	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T230	1		T53	1		T274	3
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T344	1		T287	1		T257	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T329	1		T338	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	12	1			T48	1		T7	1		T75	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T48	1		T345	1		T254	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T35	1		T346	1		T129	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T97	1		T7	1		T75	1
auto[6]	auto[StDisabled]	auto[OpGenId]	33	1			T57	1		T190	1		T58	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T26	1		T56	1		T47	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	94	1			T86	1		T195	1		T246	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T121	1		T347	1		T348	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T310	1		T349	1		T350	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T83	1		T248	1		T351	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T3	1		T52	1		T269	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T351	1		T352	1		T315	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T36	1		T158	1		T9	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T26	1		T59	1		T64	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	16	1			T122	2		T253	1		T55	1
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T159	1		T353	1		T350	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T187	1		T58	1		T354	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T253	1		T341	1		T314	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T146	1		T355	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T59	1		T241	1		T264	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T26	1		T53	2		T240	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T35	1		T81	1		T85	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T56	1		T356	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T123	1		T48	1		T357	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T358	1		T314	1		T120	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T86	1		T58	1		T60	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T203	1		T279	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T131	1		T117	1		T359	2
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T360	1		T361	1		T362	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T194	1		T333	1		T339	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T230	1		T314	1		T254	1
auto[7]	auto[StDisabled]	auto[OpGenId]	27	1			T51	1		T57	1		T187	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T82	1		T196	1		T57	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T85	1		T102	2		T246	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T73	1		T48	1		T53	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T83	1		T90	1		T249	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T55	1		T363	1		T315	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T234	1		T251	1		T364	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1418

1

T2

1

T3

1

T4

2

clear_one[1]

auto[0]

auto[0]

auto[0]

411

1

T35

1

T36

1

T49

1

clear_one[1]

auto[0]

auto[0]

auto[1]

134

1

T2

1

T4

1

T50

3

clear_one[1]

auto[0]

auto[1]

auto[0]

137

1

T5

1

T17

1

T26

1

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T48

1

T158

1

T230

1

clear_one[2]

auto[0]

auto[0]

auto[0]

389

1

T35

1

T36

1

T49

1

clear_one[2]

auto[0]

auto[0]

auto[1]

125

1

T2

1

T4

1

T86

1

clear_one[2]

auto[1]

auto[0]

auto[0]

119

1

T35

3

T26

1

T56

1

clear_one[2]

auto[1]

auto[0]

auto[1]

47

1

T5

1

T100

1

T227

1

clear_one[3]

auto[0]

auto[0]

auto[0]

446

1

T3

2

T4

1

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

149

1

T26

1

T81

1

T195

3

clear_one[3]

auto[1]

auto[0]

auto[0]

104

1

T35

1

T26

1

T56

1

clear_one[3]

auto[1]

auto[1]

auto[0]

51

1

T5

1

T109

6

T59

1

clear_none

auto[0]

auto[0]

auto[0]

1336

1

T3

2

T4

2

T5

1

clear_none

auto[0]

auto[0]

auto[1]

125

1

T2

1

T4

2

T26

1

clear_none

auto[0]

auto[1]

auto[0]

114

1

T56

2

T195

1

T246

1

clear_none

auto[0]

auto[1]

auto[1]

31

1

T48

1

T76

1

T330

2

clear_none

auto[1]

auto[0]

auto[0]

135

1

T36

3

T56

3

T193

4

clear_none

auto[1]

auto[0]

auto[1]

33

1

T5

1

T47

1

T158

2

clear_none

auto[1]

auto[1]

auto[0]

44

1

T48

2

T230

3

T10

1

clear_none

auto[1]

auto[1]

auto[1]

28

1

T47

1

T48

1

T88

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1324	1			T2	1		T3	1		T4	2
clear_all	auto[1]	94	1			T140	2		T129	3		T131	1
clear_one[1]	auto[0]	678	1			T2	1		T4	1		T5	1
clear_one[1]	auto[1]	40	1			T131	2		T359	3		T240	1
clear_one[2]	auto[0]	653	1			T2	1		T4	1		T5	1
clear_one[2]	auto[1]	27	1			T130	2		T314	1		T240	1
clear_one[3]	auto[0]	699	1			T3	2		T4	1		T5	1
clear_one[3]	auto[1]	51	1			T36	1		T109	3		T359	2
clear_none	auto[0]	1750	1			T2	1		T3	2		T4	4
clear_none	auto[1]	96	1			T36	4		T109	2		T130	2